Semiconductor components

Abstract

The present invention discloses a semiconductor element, comprising a substrate, a well region, a first groove, a second groove, a first field plate, a second lower field plate, a second upper field plate, a first base region, a first planar gate, and a first source doping region. The first groove and the second groove are arranged on the substrate and are laterally separated from each other. The first field plate is arranged in the first groove. The second lower field plate and the second upper field plate are arranged in the second groove, wherein the maximum width of the second lower field plate is less than the maximum width of the second upper field plate. The first base region is adjacent to the first groove and laterally separates the second groove. The first planar gate is arranged on the first base region and is located between the first groove and the second groove. The first source doping region is arranged in the first base region and is located between the first groove and the first planar gate.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and in particular to a semiconductor device including a trench power transistor and a manufacturing method thereof. Background Art

[0002] Power transistors are commonly used in power electronics technology. Power metal oxide semiconductor field effect transistors (power MOSFETs) are the most commonly used components in power conversion systems. They include lateral structures, such as laterally diffused metal oxide semiconductor (LDMOS) field effect transistors (FETs), and vertical structures, such as planar gate MOSFETs and trench gate MOSFETs. Trench gate MOSFETs have a gate disposed in a trench. Trench gate MOSFETs have advantages over planar gate MOSFETs in terms of reduced element unit size and reduced parasitic capacitance. However, in terms of on-state resistance (Ron) and breakdown voltage, conventional trench gate MOSFETs still cannot fully meet various requirements in power electronics applications. Summary of the invention

[0003] In view of this, the present invention proposes a semiconductor device including a trench power transistor to meet various requirements of the trench power transistor in power electronics applications, such as reducing on-resistance, reducing spreading resistance (Rsp), increasing or maintaining breakdown voltage, etc., to facilitate the needs of large current and low voltage components, so that it can be more efficiently applied to a battery management system (BMS).

[0004] According to one embodiment of the present invention, a semiconductor element is disclosed, comprising a substrate, a well region, a first trench, a second trench, a first field plate, a second lower field plate, a second upper field plate, a first base region, a first planar gate, and a first source doping region. The first trench and the second trench are arranged on the substrate and are laterally separated from each other. The first field plate is arranged in the first trench. The second lower field plate and the second upper field plate are arranged in the second trench, wherein the maximum width of the second lower field plate is less than the maximum width of the second upper field plate. The first base region is adjacent to the first trench and laterally separates the second trench. The first planar gate is arranged on the first base region and is located between the first trench and the second trench. The first source doping region is arranged in the first base region and is located between the first trench and the first planar gate.

[0005] According to one embodiment of the present invention, a semiconductor element is disclosed, including a substrate, a well region, a plurality of first trench structures, a plurality of second trench structures, a plurality of third trench structures, and a plurality of intermediate structures. The substrate has a first conductivity type. The well region has a first conductivity type and is arranged on the substrate. A plurality of first trench structures are arranged on the substrate, wherein each first trench structure) includes a first trench and a first field plate arranged in the first trench. A plurality of second trench structures are arranged on the substrate, wherein each second trench structure includes a second trench, a second lower field plate, and a second upper field plate. The second lower field plate and the second upper field plate are both arranged in the second trench, and the second lower field plate is arranged below the second upper field plate. A plurality of third trench structures are arranged on the substrate, wherein each third trench structure includes a third trench, a third lower field plate, and a third upper field plate. The third lower field plate and the third upper field plate are both arranged in the third trench, and the third lower field plate is arranged below the third upper field plate. A plurality of intermediate structures are arranged on the well region, each first trench structure is adjacent to at least one intermediate structure, and each intermediate structure includes a base region, a source doping region, and a planar gate. The base region is adjacent to the upper surface of the well region. The source doping region is arranged in the corresponding base region and adjacent to the upper surface of the base region. The first planar gate is arranged on the upper surface of the well region and partially overlaps with the corresponding base region. Among them, the plurality of second trench structures and the plurality of third trench structures are alternately arranged along an X direction, and each first trench structure is located between each adjacent second trench structure and each third trench structure, and each base region is adjacent to the X-direction sidewall of the first trench, but away from the X-direction sidewalls of the second trench and the third trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to when reading the present invention. Through the specific embodiments in this article and with reference to the corresponding drawings, the specific embodiments of the present invention are explained in detail and the working principles of the specific embodiments of the present invention are explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the size of some features in some drawings may be deliberately enlarged or reduced.

[0007] Figure 1 FIG. 4 is a cross-sectional view of a repeating unit of a semiconductor device according to an embodiment of the present invention.

[0008] Figure 2 FIG. 4 is a cross-sectional view of a local area of ​​a semiconductor device according to an embodiment of the present invention.

[0009] Figure 3 FIG. 4 is a cross-sectional view of a local area of ​​a semiconductor device according to an embodiment of the present invention.

[0010] Figure 4 and Figure 5 1 is a cross-sectional view and a top view of a semiconductor device according to an embodiment of the present invention.

[0011] Figure 6 FIG. 4 is a cross-sectional view of a repeating unit of a semiconductor device according to an embodiment of the present invention.

[0012] Figure 7 FIG. 4 is a cross-sectional view of a local area of ​​a semiconductor device according to a variant embodiment of the present invention.

[0013] Figure 8 FIG. 4 is a cross-sectional view of a local area of ​​a semiconductor device according to a variant embodiment of the present invention.

[0014] The reference numerals are described as follows:

[0015] 100: Semiconductor components

[0016] 100A: Cutaway

[0017] 100B: Looking down

[0018] 103: Well region

[0019] 105: Drain electrode

[0020] 107: Epitaxial layer

[0021] 108-1: First Groove

[0022] 108-2: Second Groove

[0023] 108-3: Third Groove

[0024] 109-1: First Upper Area

[0025] 109-2: Second Upper Area

[0026] 110-1: First board

[0027] 110-2a: Second lower field plate

[0028] 110-2b: Second upper field plate

[0029] 110-3a: The third lower field plate

[0030] 110-3b: Third upper field plate

[0031] 112-2a: Lower trench dielectric layer

[0032] 112-2b: Upper trench dielectric layer

[0033] 112-2c: Dielectric Isolation Section

[0034] 112-3a: Lower trench dielectric layer

[0035] 112-3b: Upper trench dielectric layer

[0036] 112-3c: Dielectric Isolation Section

[0037] 120: Planar gate

[0038] 120-1: First planar gate

[0039] 120-2: Second planar gate

[0040] 130: matrix area

[0041] 130-1: First matrix area

[0042] 130-1a: Bottom

[0043] 130-2: Second matrix area

[0044] 130-2a: Bottom

[0045] 140: Source doping region

[0046] 140-1: First source doping region

[0047] 140-2: Second source doping region

[0048] 150-1: First groove structure

[0049] 150-2: Second groove structure

[0050] 150-3: Third groove structure

[0051] 152: Intermediate structure

[0052] 152-1: Intermediate Structure

[0053] 152-2: Intermediate Structure

[0054] 170-1a: First source contact

[0055] 170-1b: Second source contact

[0056] 170-1c: First field plate contact

[0057] 170-2a: Second lower field plate contact

[0058] 170-2b: Second upper field plate contact

[0059] 170-3a: Third lower field plate contact

[0060] 170-3b: Third upper field plate contact

[0061] 172: Opening area

[0062] 176: Interlayer dielectric layer

[0063] 180-1: First conductive connection portion

[0064] 180-2: Second conductive connection portion

[0065] R1: Region

[0066] R2: Region

[0067] U1: Repeating unit

[0068] U2: Repeating unit

[0069] W21: horizontal width

[0070] W22: horizontal width DETAILED DESCRIPTION

[0071] The present invention provides several different embodiments that can be used to implement different features of the present invention. For the sake of simplicity of description, the present invention also describes examples of specific components and arrangements. The purpose of providing these embodiments is only for illustration, not for any limitation. For example, the description below for "a first feature is formed on or above a second feature" may refer to "the first feature is in direct contact with the second feature" or "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact. In addition, various embodiments of the present invention may use repeated reference symbols and / or text annotations. The use of these repeated reference symbols and annotations is to make the description more concise and clear, rather than to indicate the association between different embodiments and / or configurations.

[0072] In addition, for the spatially related descriptive words mentioned in the present invention, such as "under", "low", "down", "above", "on", "top", "bottom" and similar words, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings. In addition to the orientation shown in the drawings, these spatially related words are also used to describe the possible orientations of the semiconductor device during use and operation. As the orientation of the semiconductor device is different (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

[0073] Although the present invention uses the terms first, second, third, etc. to describe various elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish a certain element, component, region, layer, and / or block from another element, component, region, layer, and / or block, and they themselves do not imply or represent any previous ordinal number of the element, nor do they represent the arrangement order of a certain element and another element, or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or block discussed below can also be referred to as the second element, component, region, layer, or block.

[0074] The terms "about" or "substantially" mentioned in the present invention generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of a specific description of "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

[0075] The terms "coupled", "coupled", and "electrically connected" mentioned in the present invention include any direct and indirect electrical connection means. For example, if the text describes that a first component is coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

[0076] Although the invention of the present invention is described below by specific embodiments, the inventive principle of the present invention can also be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, certain details will be omitted, and these omitted details belong to the knowledge scope of those skilled in the art.

[0077] Figure 1 FIG. 1 is a cross-sectional view of a repeating unit of a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, the semiconductor device 100 includes at least one repeating unit U1 , and the number of the repeating units U1 may be any integer greater than 1, such as 2-100 or any number therebetween, which may be adjusted according to actual needs.

[0078] In one embodiment, the semiconductor device 100 includes a substrate 102, the substrate 102 has a first conductivity type, such as an n-type heavily doped substrate (N+substrate). An epitaxial layer 107 is disposed on the substrate 102, the epitaxial layer 107 has a first conductivity type, such as an n-type silicon epitaxial layer, and a well region 103 is formed in the epitaxial layer 107. According to an embodiment of the present invention, the substrate 102 can be used as a common drain region 110, and the well region 103 is used as a drift region. A drain electrode (or drain contact) 105 of the semiconductor device 100 is disposed on the bottom surface of the substrate 102, and the drain electrode 105 is electrically connected to the substrate 102.

[0079] In addition, the substrate 102 of the semiconductor device 100 further includes a plurality of trenches 108, such as a first trench 108-1, a second trench 108-2, and a third trench 108-3. The first trench 108-1, the second trench 108-2, and the third trench 108-3 are laterally separated from each other, for example, separated from each other in a first direction (e.g., an X direction). The first trench 108-1, the second trench 108-2, and the third trench 108-3 each extend along a second direction (e.g., a Y direction). Each of the trenches 108-1, 108-2, and 108-3 may have a similar cross-sectional profile and depth, but is not limited thereto.

[0080] As for the first trench 108-1, the first trench 108-1 is disposed in the well region 103, and the junction between the first trench 108-1 and the well region 103 is the inner wall of the first trench 108-1. The first trench 108-1 includes a central area where the first field plate 110-1 is disposed in the first trench 108-1, and the first trench dielectric layer 112-1 is disposed between the first field plate 110-1 and the inner wall of the first trench 108-1. The first field plate 110-1 extends along the second direction (for example, the Y direction), and the top surface of the first field plate 110-1 is lower than the uppermost opening of the first trench 108-1, so the first field plate 110-1 does not protrude upward from the first trench 108-1. The material of the first field plate 110-1 can be a conductive material, such as doped polysilicon or a conductive metal, but is not limited thereto. The material of the first trench dielectric layer 112-1 can be an insulating material, such as silicon oxide, but is not limited thereto.

[0081] Taking the second trench 108-2 as an example, the second trench 108-2 is arranged in the well region 103, and the junction between the second trench 108-2 and the well region 103 is the inner wall of the second trench 108-2. The second lower field plate 110-2a and the second upper field plate 110-2b are arranged in the central area of ​​the second trench 108-2. The second trench dielectric layer 112-2 is arranged along the inner wall of the second trench 108-2, so that the second lower field plate 110-2a and the second upper field plate 110-2b do not directly contact the inner wall of the second trench 108-2. The second lower field plate 110-2a and the second upper field plate 110-2b are separated from each other longitudinally (for example, in the Z direction), and both extend along the second direction (for example, in the Y direction), and are electrically connected to each other. The profile, size and material of the second lower field plate 110-2a are similar to the profile and size of the first field plate 110-1, so the two can be obtained through the same deposition and etching process. The width of the second upper field plate 110-2b is greater than the width of the second lower field plate 110-2a, so that the sidewall of the second upper field plate 110-2b can be closer to the inner wall of the second trench 108-2. Therefore, when the same bias is applied to the second upper field plate 110-2b and the second lower field plate 110-2a, the electric field generated by the second upper field plate 110-2b for the adjacent well region 103 is greater than the electric field generated by the second lower field plate 110-2a for the adjacent well region 103.

[0082] Taking the third trench 108-3 as an example, the components contained in the third trench 108-3 are substantially the same as the components contained in the second trench 108-2 in configuration and function, for example, both contain the lower field plate and the upper field plate, and are able to play similar functions, such as playing the function of regulating the electric field distribution. Specifically, the third lower field plate 110-3a and the third upper field plate 110-3b are arranged in the central area of ​​the third trench 108-3. The third trench dielectric layer 112-3 is arranged along the inner wall of the third trench 108-3, so that the third lower field plate 110-3a and the third upper field plate 110-3b do not directly contact the inner wall of the third trench 108-3. The third lower field plate 110-3a and the third upper field plate 110-3b are separated from each other longitudinally (for example, in the Z direction), and both extend along the second direction (for example, in the Y direction) and are electrically connected to each other. The profile, size and material of the third lower field plate 110-3a are similar to those of the first field plate 110-1, so both can be obtained through the same deposition and etching process. The width of the third upper field plate 110-3b is greater than the width of the third lower field plate 110-3a, so that the sidewall of the third upper field plate 110-3b can be closer to the inner wall of the third trench 108-3.

[0083] Continue reading Figure 1 In one embodiment, the semiconductor device 100 further includes a first body region 130-1 and a second body region 130-2, both of which are disposed in the epitaxial layer 107. The first body region 130-1 and the second body region 130-2 have a second conductivity type opposite to the aforementioned first conductivity type, for example, a p-type body region (p-body), and the p-type dopant concentration in the first body region 130-1 and the second body region 130-2 is higher than the n-type dopant concentration in the well region 107. The first body region 130-1 and the second body region 130-2 are respectively disposed on both sides of the first trench 108-1, and are separated from each other laterally (for example, in the X direction). The first body region 130-1 and the second body region 130-2 are adjacent to the first trench 108-1 and directly contact the first trench dielectric layer 112-1 in the first trench 108-1.

[0084] For the first base region 130-1, the bottom end 130-1a of the first base region 130-1 is adjacent to the first trench 108-1, and the first base region 130-1 is separated from the second trench 108-2 in the overall lateral direction (e.g., X direction). Therefore, there is still a doped region of the first conductivity type (e.g., n-type) between the first base region 130-1 and the second trench 108-2, such as the well region 103. In order to allow the first field plate 110-1 to regulate the electric field between the bottom end 130-1a of the first base region 130-1 and the well region 103 to reduce the concentration of the electric field, the top surface of the first field plate 110-1 is configured to be higher than the bottom end 130-1a of the first base region 130-1. In addition, in order to control the electric field distribution in the doping region between the first base region 130-1 and the second trench 108-2, the top surface of the second lower field plate 110-2a will be configured to be higher than the bottom end 130-1a of the first base region 130-1, and the bottom surface of the second upper field plate 110-2b will be configured to be higher than the bottom end 130-1a of the first base region 130-1.

[0085] Taking the second base region 130-2 as an example, the second base region 130-2 is roughly mirror-symmetrical with the first base region 130-1 in a certain plane (e.g., YZ plane) and has substantially the same function. Specifically, the bottom end 130-2a of the second base region 130-2 is adjacent to the first trench 108-1, and the second base region 130-2 is separated from the third trench 108-3 in the overall lateral direction (e.g., X direction). Therefore, there is still a doped region of the first conductivity type (e.g., n-type) between the second base region 130-2 and the third trench 108-3, such as the well region 103. In order to allow the first field plate 110-1 to regulate the electric field between the bottom end 130-2a of the second base region 130-2 and the well region 103 to reduce the concentration of the electric field, the top surface of the first field plate 110-1 is configured to be higher than the bottom end 130-2a of the second base region 130-2. In addition, in order to control the electric field distribution in the doping region between the second base region 130-2 and the third trench 108-3, the top surface of the third lower field plate 110-3a will be configured to be higher than the bottom end 130-2a of the second base region 130-2, and the bottom surface of the third upper field plate 110-3b will be configured to be higher than the bottom end 130-2a of the second base region 130-2.

[0086] In addition, the semiconductor device 100 further includes a first source doping region 140-1 and a second source doping region 140-2, which are adjacent to the first base region 130-1 and the second base region 130-2, respectively. Since the first source doping region 140-1 and the second source doping region 140-2 are formed by ion implantation into the first base region 130-1 and the second base region 130-2, the first source doping region 140-1 and the second source doping region 140-2 can also be regarded as being disposed in the first base region 130-1 and the second base region 130-2, respectively. The first source doping region 140-1 and the second source doping region 140-2 have a first conductivity type, for example, a heavily n-type doped region.

[0087] The semiconductor device 100 further includes a plurality of planar gates separated laterally from each other, such as a first planar gate 120-1 and a second planar gate 120-2, which are respectively disposed on the first source doping region 140-1 and the second source doping region 140-2, and overlap with the first source doping region 140-1 and the second source doping region 140-2, respectively. The first planar gate 120-1 and the second planar gate 120-2 can each extend along a second direction (e.g., the Y direction).

[0088] As for the first planar gate 120-1, the first planar gate 120-1 is located between the first trench 108-1 and the second trench 108-2. By applying an appropriate bias voltage to the first planar gate 120-1, a channel region can be formed on the surface of the first base doping region 130-1 below, so that current can flow through the channel region on the surface of the first base doping region 130-1 and reach the first source doping region 140-1. The material of the first planar gate 120-1 can be a conductive material, such as doped polysilicon or conductive metal, but is not limited thereto. According to an embodiment, the first planar gate 120-1 and the second upper field plate 110-2b can be formed together by photolithography and etching at the same time. Therefore, even if the first planar gate 120-1 and the second upper field plate 110-2b have misalignment with the underlying layer during the manufacturing process, resulting in the first planar gate 120-1 being closer to or farther away from the first trench 108-1 than expected, such misalignment will not change the lateral distance (e.g., distance in the X direction) between the first planar gate 120-1 and the second upper field plate 110-2b, so that the second upper field plate 110-2b can be closer to or farther away from the first trench 108-1 accordingly. In this way, the second upper field plate 110-2b can move laterally (e.g., in the X direction) in coordination with the position of the first planar gate 120-1, so that the second upper field plate 110-2b can still appropriately regulate the electric field distribution in the area between the first base region 130-1 and the second trench 108-2 even in the case of misalignment.

[0089] As for the second planar gate 120-2, the material and function of the second planar gate 120-2 are similar to those of the first planar gate 120-1. Specifically, the second planar gate 120-2 is located between the first trench 108-1 and the third trench 108-3. By applying an appropriate bias voltage to the second planar gate 120-2, a channel region can be formed on the surface of the second substrate doping region 130-2 below, so that current can flow through the channel region on the surface of the second substrate doping region 130-2 and reach the second source doping region 140-2. According to one embodiment, the second planar gate 120-2 can be formed together with the third upper field plate 110-3b by photolithography and etching at the same time. Therefore, even if the second planar gate 120-2 and the third upper field plate 110-3b have an alignment error with the underlying layer during the manufacturing process, the third upper field plate 110-3b can still move laterally (for example, in the X direction) in coordination with the position of the second planar gate 120-1, so that the third upper field plate 110-3b will not change the lateral distance (for example, the distance in the X direction) between the second planar gate 120-2 and the third upper field plate 110-3b even in the case of an alignment error, and the electric field distribution in the area between the second base region 130-2 and the third trench 108-3 can still be appropriately regulated.

[0090] The semiconductor device 100 further includes an interlayer dielectric layer 176 covering the epitaxial layer 107 , and the interlayer dielectric layer 176 covers the first source doping region 140 - 1 , the second source doping region 140 - 2 , the first planar gate 120 - 2 , the second planar gate 120 - 2 , and other components formed in the epitaxial layer 107 .

[0091] The semiconductor device 100 further includes a plurality of conductive contacts, such as a second upper field plate contact 170-2b, a third upper field plate contact 170-3b, a first source contact 170-1a, and a second source contact 170-1b. The second upper field plate contact 170-2b, the third upper field plate contact 170-3b, the first source contact 170-1a, and the second source contact 170-1b penetrate the interlayer dielectric layer 176 and are electrically connected to the second upper field plate 110-2b, the third upper field plate 110-3b, the first source doping region 140-1, and the second source doping region 140-2, respectively.

[0092] According to an embodiment of the present invention, the first base region 130-1 located directly below the first source contact 170-1a can have a higher dopant concentration, and the second base region 130-2 located directly below the second source contact 170-1b can also have a higher dopant concentration, so as to avoid the current directly passing through the well region 103 to the bottom of the first source contact 170-1a and the second source contact 170-1b.

[0093] Figure 2 is a cross-sectional view of a local area of ​​a semiconductor device according to an embodiment of the present invention, corresponding to Figure 2 Region R1. Figure 2 As shown, the maximum width W21 of the second lower field plate 110 - 2 a is smaller than the maximum width W22 of the second upper field plate 110 - 2 b .

[0094] The second trench dielectric layer 112-2 of the semiconductor device 100 can also be divided into a lower trench dielectric layer 112-2a, an upper trench dielectric layer 112-2b, and a dielectric isolation portion 112-2c. The lower trench dielectric layer 112-2a is disposed in the second trench 108-2 and is located between the second lower field plate 110-2a and the well region 103. The upper trench dielectric layer 112-2b is disposed in the second trench 108-2 and is located between the second upper field plate 110-2b and the well region 103. The maximum thickness of the lower trench dielectric layer 112-2a is greater than the maximum thickness of the upper trench dielectric layer 112-2b. The dielectric isolation portion 112 - 2 c is disposed between the second lower field plate 110 - 2 a and the second upper field plate 110 - 2 b such that the second lower field plate 110 - 2 a and the second upper field plate 110 - 2 b are longitudinally separated from each other.

[0095] The well region 103 of the semiconductor element 100 further includes a first upper region 109-1, which is located between the first body region 130-1 and the second trench 108-2 and is adjacent to the first body region 130-1 and the second trench 108-2. The first upper region 109-1 has a first conductivity type (n-type).

[0096] By providing a second upper field plate 110-2b with a wider width, the doping concentration of the first upper region 109-1 can be higher than the doping concentration of other regions of the well region 103, but it will not cause a significant increase in the local electric field. In addition, since the second upper field plate 110-2b is adjacent to the top surface of the well region 103, and the bottom surface of the second upper field plate 110-2b is lower than the top surface of the well region 103, the second upper field plate 110-2b can effectively reduce the electric field on the top surface of the well region 103, thereby avoiding electrical collapse on the top surface of the well region 103.

[0097] like Figure 2 , which represents the direction of current flow. Specifically, when the semiconductor device 100 is in the on state, the current flows from bottom to top in the well region 103 and flows to the first upper region 109-1. The current then flows horizontally through the channel region below the first planar gate 120-1 and finally reaches the first source contact 170-1a.

[0098] Figure 3 is a cross-sectional view of a local area of ​​a semiconductor device according to an embodiment of the present invention, corresponding to Figure 1 Region R2. Figure 3 As shown, similar Figure 2 In the structure shown, the third trench dielectric layer 112-3 of the semiconductor device 100 can also be divided into a lower trench dielectric layer 112-3a, an upper trench dielectric layer 112-3b, and a dielectric isolation portion 112-3c. The lower trench dielectric layer 112-3a is disposed in the third trench 108-3 and is located between the third lower field plate 110-3a and the well region 103. The upper trench dielectric layer 112-3b is disposed in the third trench 108-3 and is located between the third upper field plate 110-3b and the well region 103. The maximum thickness of the lower trench dielectric layer 112-3a is greater than the maximum thickness of the upper trench dielectric layer 112-3b. The dielectric isolation portion 112 - 3 c is disposed between the third lower field plate 110 - 3 a and the third upper field plate 110 - 3 b such that the third lower field plate 110 - 3 a and the third upper field plate 110 - 3 b are longitudinally separated from each other.

[0099] The well region 103 of the semiconductor element 100 further includes a second upper region 109-2, which is located between the second body region 130-2 and the third trench 108-3 and is adjacent to the second body region 130-2 and the third trench 108-3. The second upper region 109-2 has a first conductivity type (N type).

[0100] By providing a third upper field plate 110-3b with a wider width, the doping concentration of the second upper region 109-2 can be higher than the doping concentration of other regions of the well region 103, but it will not cause a significant increase in the local electric field. In addition, since the third upper field plate 110-3b is adjacent to the top surface of the well region 103, and the bottom surface of the third upper field plate 110-3b is lower than the top surface of the well region 103, the third upper field plate 110-3b can effectively reduce the electric field on the top surface of the well region 103, thereby avoiding electrical collapse on the top surface of the well region 103.

[0101] Figure 4 and Figure 5 1 is a cross-sectional view and a top view of a semiconductor device according to an embodiment of the present invention, wherein the cross-sectional view 100A corresponds to the AA′ cutting line of the top view 100B, and the cross-sectional view 100B corresponds to the BB′ cutting line of the top view 100A.

[0102] like Figure 4 As shown in the cross-sectional view 100A, its structure is similar to Figure 1 The semiconductor device 100 shown in the cross-section 100A includes a plurality of repeating units, such as a repeating unit U1 and a repeating unit U2. Since the structures and functions of the repeating units U1 and U2 are substantially the same, only the repeating unit U1 will be described below.

[0103] Also refer to Figure 4 In the cross-sectional view 100A and the top view 100B, the first trench 108-1, the second trench 108-2, the third trench 108-3, the first field plate 110-1, the second lower field plate 110-2a, the second upper field plate 110-2b, the third lower field plate 110-3a, the third upper field plate 110-3b, the first planar gate 120-1, and the second planar gate 120-2 extend in the same direction (e.g., the Y direction). The conductive contact 170 penetrates the interlayer dielectric layer 176.

[0104] Also refer to Figure 5 In the cross-sectional view 100B and the top view 100B of FIG. 100B , the second upper field plate 110-2b and the third upper field plate 110-3b each have a plurality of opening regions 172 separated from each other, so that the corresponding second lower field plate contact 170-2a and the third lower field plate contact 170-3a can penetrate the opening regions 172 and be electrically connected to the corresponding second lower field plate 110-2a and the third lower field plate 110-3a. In addition, if a conductive line layer is provided above the dielectric layer 176 to electrically connect the field plate contacts, the second lower field plate 110-2a and the second upper field plate 110-2b can be further electrically connected to the first source doping region 140-1, and the third lower field plate 170-3a and the third upper field plate 170-3b can be further electrically connected to the second source doping region 140-2. The first field plate 110 - 1 may be electrically connected to the first field plate contact 170 - 1 c , and electrically connected to the first source doping region 140 - 1 , and further electrically connected to an external circuit.

[0105] Figure 6 FIG. 4 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present invention. Figure 6 The structure shown and Figure 1 The structures shown are substantially the same, however Figure 6 The multiple components shown are further grouped to form multiple groove structures and multiple intermediate structures. Figure 1 and Figure 6 The same parts will not be described in detail.

[0106] like Figure 6 As shown, the semiconductor device 100 includes a substrate 102, a well region 103, at least one first trench structure 150-1, at least one second trench structure 150-2, at least one third trench structure 150-3, and at least one intermediate structure 152-1. For simplicity, Figure 6Only a single first trench structure 150-1, a single second trench structure 150-2, and a single third trench structure 150-3 are shown, however, the semiconductor device 100 may include a plurality of first trench structures 150-1, a plurality of second trench structures 150-2, and a plurality of third trench structures 150-3, wherein the plurality of second trench structures 150-2 and the third trench structures 150-3 are alternately arranged along the X direction, and each first trench structure 150-1 is located between each adjacent second trench structure 150-2 and each adjacent third trench structure 150-3.

[0107] The substrate 102 has a first conductivity type, such as an n-type. The well region 103 has a first conductivity type (n-type) and is disposed on the substrate.

[0108] A plurality of first trench structures 150 - 1 are disposed on the substrate, wherein each of the first trench structures 150 - 1 includes a first trench 108 - 1 and a first field plate 110 - 1 , and the first field plate 110 - 1 is disposed in the first trench 108 - 1 .

[0109] A plurality of second trench structures 150-2 are disposed on the substrate 102, wherein each second trench structure 150-2 includes a second trench 108-2, a second lower field plate 110-2a, and a second upper field plate 110-2b. The second lower field plate 110-2a and the second upper field plate 110-2b are both disposed in the second trench 108-2, and the second lower field plate 110-2a is disposed below the second upper field plate 110-2b.

[0110] A plurality of third trench structures 150-3 are disposed on the substrate 102, wherein each third trench structure 150-3 includes a third trench 108-3, a third lower field plate 110-3a, and a third upper field plate 110-3b. The third lower field plate 110-3a and the third upper field plate 110-3b are both disposed in the third trench 108-3, and the third lower field plate 110-3a is disposed below the third upper field plate 110-3b.

[0111] A plurality of intermediate structures 152-1 are disposed on the well region 103, each first trench structure 150-1 is adjacent to at least one intermediate structure 152-1, and each intermediate structure 152 includes a base region 130, a source doping region 140, and a planar gate 120. The base region 130 is adjacent to the upper surface of the well region 103. The source doping region 140 is disposed in the corresponding base region 130 and adjacent to the upper surface of the base region 130. The planar gate 120 is disposed on the upper surface of the well region 103 and partially overlaps with the corresponding base region 130. Each base region 130 is adjacent to the X-direction sidewall of the first trench 108-1, but is away from the X-direction sidewalls of the second trench 108-2 and the third trench 108-3.

[0112] For the intermediate structures 152-1 and 152-2, the plurality of intermediate structures 152-1 and 152-2 may appear in pairs, and each pair of intermediate structures 152-1 and 152-2 includes two base regions 130, two source doping regions 140, and two planar gates 120. The two base regions 130 are arranged adjacent to the upper surface of the well region 103, and are laterally separated from each other along the X direction, and are respectively adjacent to the two opposite side walls of the first trench 108-1 in the X direction. Each source doping region 140 is arranged in the corresponding base region 130 and adjacent to the upper surface of the base region 130. Each planar gate 120 is arranged on the upper surface of the well region 103 and partially overlaps with the corresponding base region 130.

[0113] For the second lower field plate 110-2a and the third lower field plate 110-3a, the second lower field plate 110-2a and the third lower field plate 110-3a extend substantially vertically (eg, in the Z direction), and the vertical lengths of the second lower field plate 110-2a and the third lower field plate 110-3a are greater than their horizontal widths.

[0114] Regarding the second upper field plate 110 - 2 b and the third upper field plate 110 - 3 b , the second upper field plate 110 - 2 b and the third upper field plate 110 - 3 b extend substantially horizontally, and the vertical lengths of the second upper field plate 110 - 2 b and the third upper field plate 110 - 3 b are smaller than their horizontal widths.

[0115] In addition, along the X direction, one of the plurality of base regions 130 is located between the adjacent first trench structure 150 - 1 and the second trench structure 150 - 2 , and one of the plurality of base regions 130 is located between the adjacent first trench structure 150 - 1 and the third trench structure 150 - 3 .

[0116] Figure 7 It is a cross-sectional view of a local area of ​​a semiconductor device according to a variant embodiment of the present invention. Figure 7 The structure is similar to Figure 1 The main difference between the two structures is that Figure 7 The structure shown further includes a first conductive connection portion 180-1 and a second conductive connection portion 180-2. The first conductive connection portion 180-1 is disposed in the second trench 108-2 and is located between the second lower field plate 110-2a and the second upper field plate 110-2b, so that the second lower field plate 110-2a is electrically connected to the second upper field plate 110-2b via the first conductive connection portion 180-1. Similarly, the second conductive connection portion 180-2 is disposed in the third trench 108-3 and is located between the third lower field plate 110-3a and the third upper field plate 110-3b, so that the third lower field plate 110-3a is electrically connected to the third upper field plate 110-3b via the second conductive connection portion 180-2.

[0117] Figure 8 It is a cross-sectional view of a local area of ​​a semiconductor device according to a variant embodiment of the present invention. Figure 8 The structure is similar to Figure 4 The main difference between the structure shown in the cross-sectional view 100A is that Figure 8 A planar gate, a substrate region, a source doping region, and a source contact are not disposed on one side of each first trench 108-1; that is, the intermediate structure 152-1 is disposed only on one side of the first trench 108-1 in the X direction, rather than on two opposite sides in the X direction; therefore, current does not flow through that side of each first trench 108-1.

[0118] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor element, characterized in that: include: a substrate having a first conductivity type; a well region having the first conductivity type and disposed on the substrate; a first groove and a second groove, disposed on the substrate and laterally separated from each other; a first field plate, disposed in the first trench; a second lower field plate and a second upper field plate, disposed in the second trench, wherein a maximum width of the second lower field plate is smaller than a maximum width of the second upper field plate; a first body region adjacent to the first trench and laterally separated from the second trench; a first planar gate, disposed on the first substrate region and located between the first trench and the second trench; as well as A first source doping region is disposed in the first base region and between the first trench and the first planar gate.

2. The semiconductor device according to claim 1, wherein: The first field plate is electrically connected to the first source doping region.

3. The semiconductor device according to claim 1, wherein: The second lower field plate and the second upper field plate are longitudinally separated from each other and electrically connected to each other.

4. The semiconductor device according to claim 1, wherein The second lower field plate and the second upper field plate are electrically connected to the first source doping region.

5. The semiconductor device according to claim 1, wherein: The top surface of the first field plate is higher than the bottom end of the first base region.

6. The semiconductor device according to claim 1, wherein: The top surface of the second lower field plate is higher than the bottom end of the first base region, and the bottom surface of the second upper field plate is higher than the bottom end of the first base region.

7. The semiconductor device according to claim 1, wherein: The well region includes a first upper region, the first upper region is located between the first base region and the second trench, and is adjacent to the first base region and the second trench, and the first upper region has the first conductivity type.

8. The semiconductor device according to claim 1, wherein: Also includes: a lower trench dielectric layer disposed in the second trench and between the second lower field plate and the well region; as well as an upper trench dielectric layer disposed in the second trench and between the second upper field plate and the well region, Wherein, the maximum thickness of the lower trench dielectric layer is greater than the maximum thickness of the upper trench dielectric layer.

9. The semiconductor device according to claim 1, wherein: The invention also includes a drain electrode, which is arranged under the substrate and electrically connected to the substrate.

10. The semiconductor device according to claim 1, wherein: In a top view, the first trench, the second trench, the first field plate, the second lower field plate, the second upper field plate, and the first planar gate extend along a same direction.

11. The semiconductor device according to claim 1, wherein Also includes: a third groove disposed on the substrate and laterally separated from the first groove and the second groove; a third lower field plate and a third upper field plate, disposed in the third trench and longitudinally separated from each other, wherein a maximum width of the third lower field plate is smaller than a maximum width of the third upper field plate; a second body region adjacent to the first trench and laterally separating the third trench; a second planar gate, disposed on the second substrate region and located between the first trench and the third trench; as well as A second source doping region is disposed in the second base region and between the first trench and the second planar gate.

12. The semiconductor device according to claim 11, wherein The third lower field plate and the third upper field plate are longitudinally separated from each other and electrically connected to each other.

13. The semiconductor device according to claim 11, wherein The third lower field plate and the third upper field plate are electrically connected to the second source doping region.

14. The semiconductor device according to claim 11, wherein A top surface of the first field plate is higher than a bottom end of the second base region.

15. The semiconductor device according to claim 11, wherein The top surface of the third lower field plate is higher than the bottom end of the second base region, and the bottom surface of the third upper field plate is higher than the bottom end of the second base region.

16. The semiconductor device according to claim 11, wherein The well region includes a second upper region, the second upper region is located between the second base region and the third trench, and is adjacent to the second base region and the third trench, and the second upper region has the first conductivity type.

17. The semiconductor device according to claim 11, wherein Also includes: a lower trench dielectric layer disposed in the third trench and between the third lower field plate and the well region; as well as an upper trench dielectric layer disposed in the third trench and between the third upper field plate and the well region, Wherein, the thickness of the lower trench dielectric layer is greater than the thickness of the upper trench dielectric layer.

18. The semiconductor device according to claim 1, wherein: In a top view, the first trench, the second trench, the third trench, the first field plate, the second lower field plate, the second upper field plate, the third lower field plate, the third upper field plate, the first planar gate, and the second planar gate extend along a same direction.

19. A semiconductor device, characterized in that: include: a substrate having a first conductivity type; a well region having the first conductivity type and disposed on the substrate; A plurality of first groove structures are disposed on the substrate, wherein each of the first groove structures comprises: a first groove; and a first field plate, disposed in the first trench; A plurality of second groove structures are disposed on the substrate, wherein each of the second groove structures comprises: a second groove; and a second lower field plate and a second upper field plate, both disposed in the second trench, the second lower field plate being disposed below the second upper field plate; A plurality of third groove structures are disposed on the substrate, wherein each of the third groove structures comprises: a third groove; and a third lower field plate and a third upper field plate, both disposed in the third trench, the third lower field plate being disposed below the third upper field plate; A plurality of intermediate structures are arranged on the well region, each of the first trench structures is adjacent to at least one of the intermediate structures, and each of the intermediate structures comprises: a substrate region adjacent to an upper surface of the well region; a source doping region, disposed in the corresponding base region and adjacent to an upper surface of the base region; and a planar gate, the planar gate being disposed on the upper surface of the well region and partially overlapping with the corresponding base region; The plurality of second trench structures and the plurality of third trench structures are alternately arranged along an X direction, and each of the first trench structures is located between each adjacent second trench structure and each adjacent third trench structure, and each of the base regions is adjacent to the X direction sidewall of the first trench but away from the X direction sidewalls of the second trench and the third trench.

20. The semiconductor device according to claim 19, wherein The plurality of intermediate structures appear in pairs, and the intermediate structure of each pair includes: The two base regions are arranged at the upper surface adjacent to the well region and are laterally separated from each other along the X direction, and are respectively adjacent to two opposite side walls of the first trench in the X direction; two source doping regions, each of which is disposed in a corresponding base region and adjacent to an upper surface of the base region; and The two planar gates are each arranged on the upper surface of the well region and partially overlapped with the corresponding base region.

21. The semiconductor device according to claim 19, wherein The second lower field plate and the third lower field plate extend vertically, and the vertical length of the second lower field plate and the third lower field plate is greater than the horizontal width thereof. The second upper field plate and the third upper field plate extend horizontally, and vertical lengths of the second upper field plate and the third upper field plate are smaller than horizontal widths thereof.

22. The semiconductor device according to claim 19, wherein: Along the X direction, one of the plurality of base regions is located between the adjacent first trench structure and the second trench structure, and one of the plurality of base regions is located between the adjacent first trench structure and the third trench structure.

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