High-voltage plane gate metal-oxide field effect transistor and manufacturing method thereof

Abstract

The invention relates to a high-voltage plane gate metal-oxide field effect transistor and a manufacturing method thereof, and belongs to the field of semiconductor devices, the high-voltage plane gate metal-oxide field effect transistor comprises a first metallization layer, a first semiconductor layer and a second semiconductor layer, a first semiconductor region and a second semiconductor region are formed on the second semiconductor layer, and a third semiconductor region is formed in the second semiconductor region; a fourth semiconductor region is arranged above the first semiconductor region; a gate oxide layer and a polycrystalline silicon gate are sequentially arranged above the second semiconductor region and the second semiconductor layer, and the gate oxide layer is adjacent to the fourth semiconductor region and is not overlapped with the fourth semiconductor region; an oxide dielectric layer is arranged above the polycrystalline silicon gate, an ohmic contact region is formed above the fourth semiconductor region, the second semiconductor region and the first semiconductor region, and a second metallization layer is arranged above the ohmic contact region and the oxide dielectric layer. According to the invention, high blocking voltage is maintained while the conduction channel length of the device is reduced, the gate leakage current is reduced, the tunneling effect of the oxide layer is weakened, and the reliability of the device is improved.

Description

Technical Field

[0001] The invention relates to a high-voltage planar gate metal-oxide field effect transistor (MOSFET) and a manufacturing method thereof, belonging to the technical field of semiconductor devices. Background Art

[0002] As power electronics technology continues to expand into renewable energy markets, smart grids, smart homes, transportation electrification, electric and hybrid vehicles, and other emerging industrial and medical applications, new wide bandgap (WBG) power semiconductor devices have gradually become the focus of current research. In the past few years, researchers have spent a lot of time understanding the advantages and disadvantages of these emerging power devices, such as reliability, cost, and availability. WBG power devices can be used in power converters to improve their efficiency and power density. High-efficiency and high-power-density power devices play an increasingly important role in power electronic systems. As the third-generation WBG power semiconductor devices, silicon carbide (SiC) devices show great potential in high-voltage, high-temperature, high-power, and high-frequency applications due to their excellent material properties.

[0003] Among the many SiC crystal forms, the most common ones include 3C-SiC, 4H-SiC, 6H-SiC and 15R-SiC. 4H-SiC is an ideal choice for power electronic devices due to its high electron mobility, low on-resistance and high current density. In fact, 4H-SiC is not only the third-generation semiconductor material with the best performance, the highest degree of commercialization and the most mature technology, but also the preferred material for the manufacture of power semiconductor devices under high voltage, high temperature and radiation resistance.

[0004] Silicon carbide (SiC) MOSFET is currently the core of electric vehicles (EV) as a switching device, located inside inverters and converters, making important contributions to the performance and long-term reliability of electric vehicles and promoting the development of electric vehicles. SiC MOSFET has received special attention due to its potential to replace existing silicon superjunction transistors and integrated gate bipolar transistor technologies. The main high-power silicon carbide MOSFETs on the market are mainly vertical lateral diffusion MOSFETs, and major device manufacturers have relatively mature planar MOSFET technology.

[0005] Fig. 9The figure shows a conventional planar MOSFET structure, including a semiconductor substrate 13, an N-type semiconductor epitaxial layer 14, a P-type semiconductor region 15, a high-doping concentration P-type semiconductor region 16, a high-doping concentration N-type semiconductor region 17, a gate oxide layer 6, a polysilicon gate 7, an oxide dielectric layer 9, a second metallization layer 11, and a first metallization layer 12. The gate oxide layer 6 is formed by an oxidation process, and an inversion layer conductive channel is formed near the gate oxide layer 6 in the P-type semiconductor region 15 by controlling the polysilicon gate 7, and the inversion layer conductive channel connects the high-doping concentration N-type semiconductor region 17 and the N-type semiconductor epitaxial layer 14. Silicon carbide material can grow an oxide layer on the surface by a thermal oxidation process, but due to the presence of a large number of trapped charges and interface charges at the interface of the P-type semiconductor region 15 / gate oxide layer 6 (i.e., at the SiC / SiO2 interface), the channel mobility of the SiC MOSFET is low, thereby increasing the on-resistance of the device. Fig. 9 The components of the on-resistance of the planar MOSFET structure are shown. The on-resistance consists of R1 (source resistance), R2 (channel resistance), R3 (JFET region resistance), R4 (drift region resistance), and R5 (substrate resistance). In low-voltage devices, R2 accounts for the largest proportion. As the applied voltage gradually increases, R4 becomes the part with the largest resistance value. However, the continuous increase in blocking voltage puts higher requirements on the channel length of the planar structure MOSFET. In order to avoid device breakdown in the channel, the channel length needs to be increased to enhance the blocking capability.

[0006] In addition to increasing the on-resistance of the device, the increase in the channel length also brings other problems. The threshold voltage hysteresis effect is the main problem faced in the application of SiC MOSFET. Threshold hysteresis depends on the charging and discharging of the interface charge. When the driving voltage is negative, the donor trap captures holes and the device is in the accumulation state. The lower the driving negative voltage, the more holes are captured. When the device changes from the accumulation state to the depletion state and then to the inversion state, the Fermi level quickly passes through almost the entire band gap of silicon carbide, which makes the interface state enter an unstable state, and the donor trap begins to discharge, resulting in a decrease in the threshold voltage, and then the gate charge also decreases. In addition, the lower the driving negative voltage, the more donor traps are discharged, and the smaller the threshold voltage. However, when the gate voltage is reduced from the strong inversion state to the threshold voltage, the change in the Fermi level is small, and the thermal equilibrium is quickly restored. Therefore, during the shutdown process, the threshold voltage remains almost unchanged. In addition, since the dynamic threshold hysteresis is closely related to the switching speed of the device, the influence of parasitic parameters cannot be ignored. Although the threshold hysteresis phenomenon can be recovered in the short term, due to the high switching speed of silicon carbide MOSFET, the transient threshold voltage change caused by hysteresis can be as high as several volts. Therefore, the threshold voltage hysteresis has a serious impact on the switching characteristics of SiC MOSFET devices.

[0007] As the device manufacturing process continues to improve, the thickness of the gate oxide layer continues to decrease, and the possibility of the gate oxide layer having a tunneling effect is higher. According to existing research, the vertical overlap portion of the polysilicon gate 7 and the high-doping concentration n-type semiconductor region 17 (such as Fig. 9 The electric field strength in the dashed box is the highest, and the possibility of tunneling is the greatest. Fig. 9 As shown, arrow A represents the gate leakage current and its direction. The gate leakage current seriously affects the reliability of the device. Summary of the invention

[0008] In view of the deficiencies in the prior art, the present invention provides a high-voltage planar gate metal-oxide field effect transistor and a method for manufacturing the same, which reduces the conduction channel length of the device while maintaining a high blocking voltage, reduces gate leakage current, and improves device reliability.

[0009] The present invention adopts the following technical solution: A high-voltage planar gate metal-oxide field effect transistor comprises, from bottom to top, a first metallization layer, a first semiconductor layer, and a second semiconductor layer, wherein a first semiconductor region and a second semiconductor region are formed on the second semiconductor layer by ion implantation, the first semiconductor region and the second semiconductor region are adjacent to each other, a third semiconductor region is formed in the second semiconductor region, a fourth semiconductor region is arranged above the third semiconductor region, the fourth semiconductor region is shorter than the third semiconductor region, and is connected to the third semiconductor region; a gate oxide layer and a polysilicon gate are arranged above the second semiconductor region and the second semiconductor layer, the gate oxide layer is adjacent to the fourth semiconductor region without overlapping; an oxide dielectric layer is arranged above the polysilicon gate, an ohmic contact region is formed above the fourth semiconductor region, the second semiconductor region, and the first semiconductor region, and a second metallization layer is arranged above the ohmic contact region and the oxide dielectric layer; The first semiconductor layer, the second semiconductor layer, the third semiconductor region, and the fourth semiconductor region are N-type, and the first semiconductor region and the second semiconductor region are P-type.

[0010] The present invention is a metal-oxide field effect transistor (MOSFET) with a planar gate structure. The fourth semiconductor region in the MOSFET structure is buried in the body, and the conduction channel length of the device is reduced while maintaining a high blocking voltage, thereby reducing the high on-resistance and threshold voltage hysteresis problems that come with it, and improving the reliability of the device. The self-alignment process eliminates the overlapping area of ​​the polysilicon gate and the high-doping concentration N-type source region, reducing the gate oxide layer tunneling and gate leakage current.

[0011] Preferably, the first semiconductor layer is an N-type semiconductor substrate made of silicon carbide with high-concentration impurities added, and is used as a substrate for semiconductor devices. The impurity concentration in the first semiconductor layer is 1×10 19 cm -3 .

[0012] Preferably, the thickness of the N-type semiconductor substrate is in the range of 300 μm to 350 μm.

[0013] Preferably, the second semiconductor layer is composed of silicon carbide with low concentration impurities added. The thickness and impurity concentration of the second semiconductor layer depend on the working voltage design of the semiconductor device. Generally, for a 4500V working voltage design, the thickness of the second semiconductor layer is 40 μm and the impurity concentration is about 1×10 16 cm -3 .

[0014] Preferably, the first semiconductor region is located within the second semiconductor layer and is formed by ion implantation, and the depth of the first semiconductor region is 0.3-0.5 μm; The impurity doping concentration of the first semiconductor region is not less than 1×10 18 cm -3 High doping.

[0015] Preferably, the second semiconductor region is located in the second semiconductor layer and is formed by ion implantation. A JFET region is formed between two sides of the second semiconductor region. The spacing between the JFET regions cannot be too small to prevent the device from failing to open normally. The width of the JFET region is greater than 1.5 μm. The doping concentration of the second semiconductor region is 5×10 17 cm -3 .

[0016] Preferably, the third semiconductor region is located within the second semiconductor region and is formed by ion implantation. The depth of the third semiconductor region is 0.3-0.5 μm. The impurity concentration of the third semiconductor region is not less than 1×10 18 cm -3 High doping.

[0017] Preferably, the fourth semiconductor region is located within the second semiconductor region and is formed by ion implantation, and the impurity concentration of the fourth semiconductor region is not less than 1×10 18 cm -3 High doping.

[0018] Preferably, the gate oxide layer is formed by thermal oxidation, and the thickness of the gate oxide layer is 40nm-200nm; The polysilicon gate is isolated from the second semiconductor layer and the second semiconductor region by a gate oxide layer; The oxide dielectric layer is formed by deposition and covers the polysilicon gate and the gate oxide layer, so that the polysilicon gate and the gate oxide layer are isolated from the second metallization layer; The ohmic contact region covers the exposed upper surface of the second semiconductor layer and is formed by depositing Ni and then performing rapid thermal annealing or laser annealing.

[0019] A method for manufacturing the above-mentioned high voltage planar gate metal-oxide field effect transistor comprises the following steps: S1: preparing an N-type semiconductor substrate made of silicon carbide (SiC), forming a first semiconductor layer, and forming a second semiconductor layer on the surface of the first semiconductor layer by epitaxial growth; S2: After forming a mask, impurity ions (P type) of aluminum or boron ions are implanted into the upper surface of the second semiconductor layer, thereby forming a first semiconductor region; S3: After forming a mask, impurity ions (P type) of aluminum or boron ions are implanted into the upper surface of the second semiconductor layer to form a second semiconductor region; S4: After forming a mask, high-concentration impurity ions of nitrogen or phosphorus ions (N-type) are implanted into the second semiconductor region to form a third semiconductor region. The implantation depth of the third semiconductor region is shallower and the length is narrower than that of the second semiconductor region. The upper surface of the third semiconductor region is 0.3-0.5 μm away from the upper surface of the second semiconductor region. S5: forming a gate oxide layer by a thermal oxidation process, depositing polysilicon on the gate oxide layer to form a polysilicon gate, and then removing excess polysilicon to the upper surface of the second semiconductor layer by plasma etching; S6: using a self-alignment process to implant high-concentration impurity ions of nitrogen or phosphorus ions (N-type) into the second semiconductor region to form a fourth semiconductor region, wherein the length of the fourth semiconductor region is smaller than that of the third semiconductor region, and the fourth semiconductor region is connected to the third semiconductor region from top to bottom; S7: Deposit oxide to form an oxide medium, form an ohmic contact area by dry etching, deposit a layer of metal to form the ohmic contact area and then form a second metallization layer, form a first metallization layer at the bottom of the first semiconductor layer, and the first metallization layer is formed on the opposite side of the second metallization layer and contacts the first semiconductor layer.

[0020] For any details not provided in the present invention, please refer to the prior art.

[0021] The beneficial effects of the present invention are: In the process of forming the fourth semiconductor region of the present invention, the conventional process requires the use of a mask for ion implantation, but the present invention does not require a mask, and the implantation of the fourth semiconductor region is achieved by aligning the gate oxide layer and the polysilicon gate. Through the self-alignment process, the overlapping area between the polysilicon gate and the fourth semiconductor region is eliminated (that is, there is no overlapping area between the polysilicon gate and the fourth semiconductor region), effectively weakening the oxide layer tunneling effect and reducing the gate leakage current.

[0022] In the forward conduction process, due to the low channel mobility and the presence of various complex interface states at the gate oxide interface, a shorter channel length is conducive to reducing the on-resistance and the threshold voltage hysteresis effect. In the reverse blocking process, since the length of the depletion region formed by the third semiconductor region in the second semiconductor region is greater than the forward conduction channel length, the present invention can maintain a larger blocking voltage, wherein the length of the depletion region refers to the right edge of the fourth semiconductor region to the right edge of the second semiconductor region, and the forward conduction length refers to the right edge of the third semiconductor region to the right edge of the second semiconductor region. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings in the specification, which constitute a part of the present application, are used to provide further understanding of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application.

[0024] Figure 1 A schematic diagram of the structure of a high-voltage planar gate metal-oxide field effect transistor formed in Example 1 of the present invention; Figure 2 is a cross-sectional schematic diagram of forming a second semiconductor layer on the first semiconductor layer; Figure 3 is a cross-sectional schematic diagram of forming a first semiconductor region by ion implantation; Figure 4 is a cross-sectional schematic diagram of forming a second semiconductor region by ion implantation; Figure 5 is a cross-sectional schematic diagram of forming a third semiconductor region in the second semiconductor region; Figure 6 A schematic cross-sectional view of forming a gate oxide layer and a polysilicon gate; Figure 7 is a cross-sectional schematic diagram of forming a fourth semiconductor region; Figure 8 A schematic cross-sectional view of forming an oxide medium; Fig. 9 It is a schematic diagram of the traditional planar MOSFET structure; Fig.10 It is a schematic diagram of the structure of a high voltage planar gate metal-oxide field effect transistor according to Example 2; In the figure, 1-first semiconductor layer, 2-second semiconductor layer, 3-first semiconductor region, 4-second semiconductor region, 5-third semiconductor region, 6-gate oxide layer, 7-polysilicon gate, 8-fourth semiconductor region, 9-oxide dielectric layer, 10-ohmic contact region, 11-second metallization layer, 12-first metallization layer, 13-semiconductor substrate, 14-N-type semiconductor epitaxial layer, 15-P-type semiconductor region, 16-high doping concentration P-type semiconductor region, 17-high doping concentration N-type semiconductor region. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of the present invention are clearly and completely described below in conjunction with the drawings in the implementation of this specification, but are not limited to this. Anything not fully described in the present invention shall be based on the conventional technology in the art.

[0026] Example 1 A high voltage planar gate metal-oxide field effect transistor, such as Figure 1 As shown, from bottom to top, it includes a first metallization layer 12, a first semiconductor layer 1, and a second semiconductor layer 2. A first semiconductor region 3 and a second semiconductor region 4 are formed on the second semiconductor layer 2 by ion implantation. The first semiconductor region 3 and the second semiconductor region 4 are adjacent to each other. A third semiconductor region 5 is formed in the second semiconductor region 4. A fourth semiconductor region 8 is arranged above the third semiconductor region 5. The fourth semiconductor region 8 is shorter than the third semiconductor region 5 and is connected to the third semiconductor region 5. A gate oxide layer 6 and a polysilicon gate 7 are arranged in sequence above the second semiconductor region 4 and the second semiconductor layer 2. The gate oxide layer 6 is adjacent to the fourth semiconductor region 8 without overlapping. An oxide dielectric layer 9 is arranged above the polysilicon gate 7. An ohmic contact region 10 is formed on one side of the oxide dielectric layer 9 above the fourth semiconductor region 8, the second semiconductor region 4, and the first semiconductor region 3. A second metallization layer 11 is arranged above the ohmic contact region 10 and the oxide dielectric layer 9. The first semiconductor layer 1 , the second semiconductor layer 2 , the third semiconductor region 5 , and the fourth semiconductor region 8 are of N-type, and the first semiconductor region 3 and the second semiconductor region 4 are of P-type.

[0027] This embodiment is a metal-oxide field effect transistor (MOSFET) with a planar gate structure. The fourth semiconductor region in the MOSFET structure is buried in the body, and the conduction channel length of the device is reduced while maintaining a high blocking voltage, thereby reducing the high on-resistance and threshold voltage hysteresis problems that come with it, and improving the reliability of the device. The self-aligned process eliminates the overlapping area of ​​the polysilicon gate and the high-doping concentration N-type source region, reducing the gate oxide layer tunneling and gate leakage current.

[0028] The first semiconductor layer 1 is an N-type semiconductor substrate made of silicon carbide with high concentration impurities added, and is used as a substrate for semiconductor devices. The impurity concentration in the first semiconductor layer is 1×10 19 cm -3 .

[0029] The thickness of the N-type semiconductor substrate is 320 μm.

[0030] The second semiconductor layer 2 is composed of silicon carbide with low concentration impurities added. The thickness and impurity concentration of the second semiconductor layer 2 depend on the working voltage design of the semiconductor device. Generally, for a 4500V working voltage design, the thickness of the second semiconductor layer is 40 μm and the impurity concentration is 1×10 16 cm -3 .

[0031] The first semiconductor region 3 is located in the second semiconductor layer 2 and is formed by ion implantation. The depth of the first semiconductor region 3 is 0.4 μm. The impurity doping concentration of the first semiconductor region 3 is 1×10 20 cm -3 .

[0032] The second semiconductor region 4 is located in the second semiconductor layer 2 and is formed by ion implantation. A JFET region is formed between the two sides of the second semiconductor region 4. The spacing between the JFET regions cannot be too small to prevent the device from being turned on normally. The width of the JFET region is greater than 1.5 μm. The doping concentration of the second semiconductor region is 5×10 17 cm -3 .

[0033] The third semiconductor region 5 is located within the second semiconductor region 4 and is formed by ion implantation. The depth of the third semiconductor region 5 is 0.4 μm. The impurity concentration of the third semiconductor region 5 is 1×10 20 cm -3 .

[0034] The fourth semiconductor region 8 is located within the second semiconductor region 4 and is formed by ion implantation. The impurity concentration of the fourth semiconductor region 8 is 1×10 20 cm -3 .

[0035] The gate oxide layer 6 is formed by thermal oxidation, and the thickness of the gate oxide layer 6 is 100 nm; The polysilicon gate 7 is isolated from the second semiconductor layer 2 and the second semiconductor region 4 by a gate oxide layer 6; The oxide dielectric layer 9 is formed by deposition and covers the polysilicon gate 7 and the gate oxide layer 6, so that the polysilicon gate 7 and the gate oxide layer 6 are isolated from the second metallization layer 11; The ohmic contact region 10 covers the exposed upper surface of the second semiconductor layer 2 and is formed by depositing Ni and then performing rapid thermal annealing or laser annealing.

[0036] Example 2 A high voltage planar gate metal-oxide field effect transistor, as described in Example 1, except that Fig.10As shown, during the process of etching polysilicon, the surface of the epitaxial layer is etched into the highly doped N-type source region, i.e., the third semiconductor region 5, due to over-etching, thereby achieving contact between the highly doped N-type source region and the second metallization layer 11, and the injection of the fourth semiconductor region 8 in Example 1 is omitted.

[0037] Example 3 A method for manufacturing a high voltage planar gate metal-oxide field effect transistor according to embodiment 1, as follows Figure 2-Figure 8 The steps include: S1: preparing an N-type semiconductor substrate made of silicon carbide (SiC), forming a first semiconductor layer 1, and forming a second semiconductor layer 2 on the surface of the first semiconductor layer 1 by epitaxial growth; S2: after forming a mask, impurity ions (P type) of boron ions are implanted into the upper surface of the second semiconductor layer 2, thereby forming a first semiconductor region 3; S3: after forming a mask, impurity ions (P type) of boron ions are implanted into the upper surface of the second semiconductor layer 2, thereby forming a second semiconductor region 4; S4: After forming a mask, impurity ions (N type) of high concentration nitrogen ions are implanted into the second semiconductor region 4 to form a third semiconductor region 5. The implantation depth of the third semiconductor region 5 is shallower and the length is narrower than that of the second semiconductor region 4. The upper surface of the third semiconductor region 5 is 0.4 μm away from the upper surface of the second semiconductor region 4. S5: forming a gate oxide layer 6 by a thermal oxidation process, depositing polysilicon on the gate oxide layer 6 to form a polysilicon gate 7, and then removing excess polysilicon to the upper surface of the second semiconductor layer 2 by plasma etching; S6: using a self-alignment process to implant impurity ions (N-type) of high-concentration nitrogen ions into the second semiconductor region 4 to form a fourth semiconductor region 8, wherein the length of the fourth semiconductor region 8 is less than that of the third semiconductor region 5, and the fourth semiconductor region 8 is connected to the third semiconductor region 5 from top to bottom; S7: Deposit oxide to form an oxide dielectric layer, form an ohmic contact area by dry etching, deposit a layer of metal to form the ohmic contact area and then form a second metallization layer 11, and form a first metallization layer 12 at the bottom of the first semiconductor layer 1. The first metallization layer 12 is formed on the opposite side of the second metallization layer 11 and contacts the first semiconductor layer 1.

[0038] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A high voltage planar gate metal-oxide field effect transistor, characterized in that: From bottom to top, it includes a first metallization layer, a first semiconductor layer, and a second semiconductor layer, a first semiconductor region and a second semiconductor region are formed on the second semiconductor layer by ion implantation, the first semiconductor region and the second semiconductor region are adjacent, a third semiconductor region is formed in the second semiconductor region, a fourth semiconductor region is arranged above the third semiconductor region, the fourth semiconductor region is shorter than the third semiconductor region, and is connected to the third semiconductor region; a gate oxide layer and a polysilicon gate are arranged above the second semiconductor region and the second semiconductor layer, the gate oxide layer is adjacent to the fourth semiconductor region without overlapping; an oxide dielectric layer is arranged above the polysilicon gate, an ohmic contact region is formed above the fourth semiconductor region, the second semiconductor region, and the first semiconductor region, and a second metallization layer is arranged above the ohmic contact region and the oxide dielectric layer; The first semiconductor layer, the second semiconductor layer, the third semiconductor region, and the fourth semiconductor region are N-type, and the first semiconductor region and the second semiconductor region are P-type.

2. The high voltage planar gate metal-oxide field effect transistor according to claim 1, characterized in that: The first semiconductor layer is an N-type semiconductor substrate made of silicon carbide and used as a substrate for semiconductor devices. The impurity concentration in the first semiconductor layer is 1×10 19 cm -3 .

3. The high voltage planar gate metal-oxide field effect transistor according to claim 2, characterized in that: The thickness of the N-type semiconductor substrate is in the range of 300 μm to 350 μm.

4. The high voltage planar gate metal-oxide field effect transistor according to claim 3, characterized in that: The second semiconductor layer is composed of silicon carbide. For the 4500V working voltage design, the thickness of the second semiconductor layer is 40μm and the impurity concentration is 1×10 16 cm -3 .

5. The high voltage planar gate metal-oxide field effect transistor according to claim 4, characterized in that: The first semiconductor region is located within the second semiconductor layer and is formed by ion implantation. The depth of the first semiconductor region is 0.3-0.5 μm. The impurity doping concentration of the first semiconductor region is not less than 1×10 18 cm -3 High doping.

6. The high voltage planar gate metal-oxide field effect transistor according to claim 5, characterized in that: The second semiconductor region is located in the second semiconductor layer and is formed by ion implantation. A JFET region is formed between two sides of the second semiconductor region. The width of the JFET region is greater than 1.5 μm. The doping concentration of the second semiconductor region is 5×10 17 cm -3 .

7. The high voltage planar gate metal-oxide field effect transistor according to claim 6, characterized in that: The third semiconductor region is located within the second semiconductor region and is formed by ion implantation. The depth of the third semiconductor region is 0.3-0.5 μm. The impurity concentration of the third semiconductor region is not less than 1×10 18 cm -3 High doping.

8. The high voltage planar gate metal-oxide field effect transistor according to claim 7, characterized in that: The fourth semiconductor region is located within the second semiconductor region and is formed by ion implantation. The impurity concentration of the fourth semiconductor region is not less than 1×10 18 cm -3 High doping.

9. The high voltage planar gate metal-oxide field effect transistor according to claim 8, characterized in that: The gate oxide layer is formed by thermal oxidation, and the thickness of the gate oxide layer is 40nm-200nm; The polysilicon gate is isolated from the second semiconductor layer and the second semiconductor region by a gate oxide layer; The oxide dielectric layer is formed by deposition, covering the polysilicon gate and the gate oxide layer; The ohmic contact region is formed by depositing Ni followed by rapid thermal annealing or laser annealing.

10. A method for manufacturing a high voltage planar gate metal-oxide field effect transistor according to claim 9, characterized in that: The steps include: S1: preparing an N-type semiconductor substrate made of silicon carbide, forming a first semiconductor layer, and forming a second semiconductor layer on the surface of the first semiconductor layer by epitaxial growth; S2: After forming a mask, impurity ions of aluminum or boron are implanted into the upper surface of the second semiconductor layer, thereby forming a first semiconductor region; S3: After forming a mask, impurity ions of aluminum or boron are implanted into the upper surface of the second semiconductor layer to form a second semiconductor region; S4: After forming a mask, high-concentration impurity ions of nitrogen or phosphorus ions are implanted into the second semiconductor region to form a third semiconductor region. The implantation depth of the third semiconductor region is shallower and the length is narrower than that of the second semiconductor region. The upper surface of the third semiconductor region is 0.3-0.5 μm away from the upper surface of the second semiconductor region. S5: forming a gate oxide layer by a thermal oxidation process, depositing polysilicon on the gate oxide layer to form a polysilicon gate, and then removing excess polysilicon to the upper surface of the second semiconductor layer by plasma etching; S6: using a self-aligned process to implant high-concentration impurity ions of nitrogen or phosphorus into the second semiconductor region to form a fourth semiconductor region, wherein the length of the fourth semiconductor region is shorter than that of the third semiconductor region, and the fourth semiconductor region is connected to the third semiconductor region from top to bottom; S7: depositing oxide to form an oxide dielectric layer, forming an ohmic contact region by dry etching, depositing a layer of metal to form an ohmic contact region and then forming a second metallization layer, and forming a first metallization layer at the bottom of the first semiconductor layer.

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