Thin film transistor and preparation method thereof, array substrate and display panel

Abstract

The invention discloses a thin film transistor and a preparation method thereof, an array substrate and a display panel, the thin film transistor provided by the invention comprises an active layer, the active layer comprises multiple sub-active layers, the multiple sub-active layers are stacked along a first direction, the sub-active layers comprise crystalline oxide materials, and the crystalline oxide materials are stacked along the first direction. And the atomic number proportions of indium elements in the adjacent sub active layers are different. According to the thin film transistor provided by the invention, both mobility and illumination stability can be realized, so that the comprehensive performance of the thin film transistor is improved.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and in particular relates to a thin film transistor and a preparation method thereof, an array substrate and a display panel. Background Art

[0002] With the development of display technology, the performance requirements for display devices are getting higher and higher. Display devices include a light-emitting layer and a driving circuit. The driving circuit is used to drive the light-emitting layer to emit light. The driving circuit includes a thin film transistor. The greater the mobility of the thin film transistor, the better the conductivity, the stronger the light stability of the thin film transistor, and the more stable the device performance. However, the thin film transistor in the related art cannot take into account both mobility and light stability, so its comprehensive performance is difficult to meet the requirements. Summary of the invention

[0003] The embodiments of the present application provide a thin film transistor and a method for manufacturing the same, an array substrate and a display panel, which can achieve a balance between mobility and light stability, thereby improving the overall performance of the thin film transistor.

[0004] An embodiment of the first aspect of the embodiments of the present application provides a thin film transistor, including an active layer, wherein the active layer includes a plurality of sub-active layers, the plurality of sub-active layers are stacked along a first direction, the sub-active layers include crystalline oxide materials, and the atomic number proportions of indium elements in adjacent sub-active layers are different.

[0005] According to an embodiment of the first aspect of the present invention, the crystalline oxide material includes indium gallium oxide, and the ratio of the total number of atoms in the indium gallium oxide to the total number of atoms in the crystalline oxide material is 70%-100%.

[0006] According to an implementation manner of the first aspect of the present invention, the multiple sub-active layers include at least one first sub-active layer and at least one second sub-active layer, the atomic number ratio of the indium element in the first sub-active layer is less than the atomic number ratio of the indium element in the second sub-active layer, and the atomic number ratio of the gallium element in the first sub-active layer is greater than the atomic number ratio of the gallium element in the second sub-active layer;

[0007] Preferably, the first sub-active layer and the second sub-active layer are alternately arranged along the first direction, the active layer comprises a first side and a second side, the first side and the second side are arranged along the first direction, one layer of the first sub-active layer is close to the first side, and one layer of the second sub-active layer is close to the second side;

[0008] Preferably, the indium element in the first sub-active layer is

[0009] The atomic number is a 1 , the number of atoms of gallium is b1 , k 1 =a 1 / (a 1 +b 1 ), k 2 =b 1 / (a 1 +b 1 ), where 50%≤k 1 ≤80%, 20%≤k 2 ≤50%;

[0010] Preferably,

[0011] The number of atoms of indium in the second active sub-layer is a 2 , the number of atoms of gallium is b 2 , k 3 =a 2 / (a 2 +b 2 ), k 4 =b 2 / (a 2 +b 2 ), where 80% ≤ k 3 ≤100%, 0≤k 4 ≤20%.

[0012] According to an embodiment of the first aspect of the present invention, the size of the active layer along the first direction is 3nm-50nm;

[0013] Preferably, the size of the first sub-active layer along the first direction is 1nm-10nm;

[0014] Preferably, a size of the second sub-active layer along the first direction is 0.5 nm-5 nm.

[0015] According to an embodiment of the first aspect of the present invention, in the active layer, the atomic number ratio of the indium element in the sub-active layer close to the first side and / or close to the second side is greater than or equal to the atomic number ratio of the indium element in any other sub-active layer.

[0016] According to an embodiment of the first aspect of the present invention, the active layer further comprises doping particles, and the ratio of the total number of atoms of the doping particles to the total number of atoms in the crystalline oxide material is greater than 0 and less than or equal to 30%;

[0017] Preferably, the doping particles include tin and / or germanium.

[0018] According to an embodiment of the first aspect of the present invention, the active layer includes a first side and a second side, the first side and the second side are arranged along the first direction, and the thin film transistor further includes:

[0019] a source-drain electrode layer, formed on the first side and connected to the active layer;

[0020] a gate, formed on the first side and / or the second side, and insulated from the active layer and the source-drain layer;

[0021] Preferably, the gate is formed on the first side, the gate is insulated from the active layer by a first insulating layer, and further comprises a second insulating layer, a light shielding layer, a buffer layer and a substrate which are formed on the second side and stacked in a direction away from the active layer, wherein the orthographic projection of the light shielding layer on the substrate covers the orthographic projection of the gate on the substrate; or,

[0022] The gate is formed on the second side, and the gate is insulated from the active layer by a first insulating layer.

[0023] The embodiment of the second aspect of the present application further provides a method for preparing a thin film transistor, comprising:

[0024] Crystalline oxide materials with different atomic ratios of indium are deposited successively to sequentially form multiple sub-active layers stacked along a first direction, wherein the atomic ratios of indium in adjacent sub-active layers are different, thereby forming an active layer.

[0025] According to an embodiment of the second aspect of the present invention, the active layer includes a first side and a second side, the first side and the second side are arranged along the first direction, and the preparation method also includes: forming a gate on the first side or the second side, the gate is insulated from the active layer; forming a source-drain layer on the first side, the source-drain layer is connected to the active layer and is insulated from the gate.

[0026] Preferably, the crystalline oxide material is deposited using an atomic layer deposition process.

[0027] An embodiment of the third aspect of the present application further provides an array substrate, comprising any one of the thin film transistors provided in the first aspect of the present application.

[0028] An embodiment of the fourth aspect of the present application further provides a display panel, comprising any array substrate provided by the third aspect of the present application.

[0029] The thin film transistor provided in the present application includes an active layer, the active layer includes multiple sub-active layers, the multiple sub-active layers are stacked along a first direction, the sub-active layers include crystalline oxide materials, and the atomic number ratios of indium elements in adjacent sub-active layers are different. On the one hand, using crystalline oxide materials as the material of the active layer can make the thin film transistor have high mobility and good light stability, and the better the crystallinity of the oxide material, the better the mobility and light stability of the thin film transistor, thereby achieving a balance between the mobility and light stability of the thin film transistor. On the other hand, the better the crystallinity of the oxide material, the more difficult it is to etch. The sub-active layer with a lower atomic number ratio of indium element is easy to be wet-etched, but the crystallinity is poor, and the mobility is lower than that of the sub-active layer with a higher atomic number ratio of indium element; the sub-active layer with a higher atomic number ratio of indium element has better crystallinity and higher mobility, but is not easy to be wet-etched; therefore, in the present application, by providing multiple sub-active layers and making the atomic number ratios of indium elements in adjacent sub-active layers different, the etching difficulty and crystallinity can be taken into account, so as to reduce the difficulty of patterning the active layer during the preparation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0031] Figure 1 is a top view of a thin film transistor provided in an embodiment of the present application;

[0032] Figure 2 yes Figure 1 Sectional view along P-P';

[0033] Figure 3 is a schematic structural diagram of an active layer in a thin film transistor provided in an embodiment of the present application;

[0034] Figure 4 is a schematic diagram of the structure of another thin film transistor provided in an embodiment of the present application;

[0035] Figure 5 is a schematic structural diagram of an active layer in another thin film transistor provided in an embodiment of the present application;

[0036] Figure 6 is a schematic structural diagram of an active layer in another thin film transistor provided in an embodiment of the present application;

[0037] Figure 7 is a schematic structural diagram of an active layer in another thin film transistor provided in an embodiment of the present application;

[0038] Figure 8 is a schematic structural diagram of an active layer in another thin film transistor provided in an embodiment of the present application;

[0039] Fig. 9 is a flow chart of a method for preparing a thin film transistor provided in an embodiment of the present application;

[0040] Fig.10 is a structural schematic diagram of an array substrate provided in an embodiment of the present application;

[0041] Fig.11 It is a structural schematic diagram of a display panel provided in an embodiment of the present application.

[0042] In the attached figure:

[0043] 1-thin film transistor; 11-active layer; 111-sub-active layer; 1111-first sub-active layer; 1112-second sub-active layer; x-first direction; A1-first side; A2-second side; 12-source and drain layer; 13-gate; 14-first insulating layer; 15-second insulating layer; 16-light shielding layer; 17-buffer layer; 18-substrate; 19-interlayer dielectric layer; 2-array substrate; 3-display panel. DETAILED DESCRIPTION

[0044] The features and exemplary embodiments of various aspects of the application will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the application. However, it is obvious to those skilled in the art that the application can be implemented when some details in these specific details are not needed. The following description of the embodiments is only to provide a better understanding of the application by illustrating the example of the application.

[0045] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0046] The inventors have found through research that the active layer of the thin film transistor in the related art is mainly composed of indium, gallium, zinc and doping elements. Among them, the mobility of the indium gallium zinc oxide active layer can be adjusted by adjusting the content of indium, gallium and zinc, but the mobility and the light stability of the thin film transistor in indium gallium zinc oxide are conflicting. The mobility is low and the light stability (NBTIS) is good, but the conductivity is poor; the mobility is high and the light stability is poor, so that the channel region of the thin film transistor is easily affected by light and affects its own performance. Therefore, it is difficult for the thin film transistor in the related art to achieve a balance between mobility and light stability, resulting in poor overall performance of the thin film transistor. Based on the research on the above problems, the inventors provide a thin film transistor and a preparation method thereof, an array substrate and a display panel to achieve a balance between mobility and light stability, thereby improving the overall performance of the thin film transistor.

[0047] In order to better understand this application, Figures 1 to 11 The thin film transistor and the manufacturing method thereof, the array substrate and the display panel according to the embodiments of the present application are described in detail.

[0048] See also Figure 1 , Figure 2 and Figure 3 The embodiment of the present application provides a thin film transistor 1, comprising an active layer 11. The active layer 11 comprises a plurality of sub-active layers 111, the plurality of sub-active layers 111 are stacked along a first direction x, the sub-active layers 111 comprise a crystalline oxide material, and the atomic number ratio of indium elements in adjacent sub-active layers 111 is different.

[0049] The thin film transistor 1 provided in the present application includes an active layer 11, the active layer 11 includes multiple sub-active layers 111, the multiple sub-active layers 111 are stacked along the first direction x, the sub-active layers 111 include crystalline oxide materials, and the atomic number ratios of indium elements in adjacent sub-active layers 111 are different. On the one hand, using crystalline oxide materials as the material of the active layer 11 can make the thin film transistor 1 have high mobility and good light stability, and the better the crystallinity of the oxide material, the better the mobility and light stability of the thin film transistor 1, so that the mobility and light stability of the thin film transistor 1 can be taken into account. On the other hand, the better the crystallinity of the oxide material, the more difficult it is to etch. The sub-active layer 111 with a lower atomic number ratio of indium element is easy to be wet-etched, but has poor crystallinity and lower mobility than the sub-active layer 111 with a higher atomic number ratio of indium element; the sub-active layer 111 with a higher atomic number ratio of indium element has good crystallinity and high mobility, but is not easy to be wet-etched; therefore, in the present application, by providing a plurality of sub-active layers 111 and making the atomic number ratios of indium element in adjacent sub-active layers 111 different, the etching difficulty and crystallinity can be taken into account, so as to reduce the difficulty of patterning the active layer 11 during the preparation process.

[0050] like Figure 2 and Figure 4 As shown, the thin film transistor 1 provided in the present application further includes a source-drain electrode layer 12 and a gate electrode 13, and the active layer 11 includes a first side A1 and a second side A2, and the first side A1 and the second side A2 are arranged along a first direction x. The source-drain electrode layer 12 is formed on the first side A1 and is connected to the active layer 11. The gate electrode 13 is formed on the first side A1 or the second side A2, and is insulated from the active layer 11 and the source-drain electrode layer 12. Specifically, the thin film transistor 1 may be a top gate structure or a bottom gate structure. When the gate electrode 13 is located on the first side A1, it is a top gate structure, and when the gate electrode 13 is located on the second side A2, it is a bottom gate structure. The present application does not specifically limit this.

[0051] In a possible implementation, Figure 2 As shown, the thin film transistor 1 has a top gate structure, a gate 13 is formed on the first side A1, the gate 13 is insulated from the active layer 11 by a first insulating layer 14, and also includes a second insulating layer 15, a shading layer 16, a buffer layer 17 and a substrate 18 formed on the second side A2 and stacked in a direction away from the active layer 11, and the projection of the shading layer 16 in the first direction x covers the projection of the gate 13 in the first direction x.

[0052] The light shielding layer 16 can be used to shield the channel region in the active layer 11 , reducing the influence of light on the channel region, so as to improve the stability of the thin film transistor 1 .

[0053] In another possible implementation, if Figure 4 As shown, the thin film transistor 1 has a bottom gate structure, the gate 13 is formed on the second side A2 , and the gate 13 is insulated from the active layer 11 by a first insulating layer 14 .

[0054] Specifically, the thin film transistor 1 may further include an interlayer dielectric layer 19 , and the source-drain electrode layer 12 includes source and drain electrodes, which are connected to the active layer 11 through via holes penetrating the interlayer dielectric layer 19 .

[0055] In other feasible embodiments, the thin film transistor 1 may also have a dual-gate structure (not shown in the figure), in which case the gate 13 is simultaneously formed on the first side A1 and the second side A2, and the gate 13 formed on the first side A1 and the gate formed on the second side A2 are insulated from the active layer 11 by the first insulating layer 14.

[0056] In a feasible implementation, the crystalline oxide material includes indium gallium oxide, and the ratio of the total number of atoms in the indium gallium oxide to the total number of atoms in the crystalline oxide material is 70%-100%.

[0057] In the above embodiment, the crystalline oxide material mainly includes indium gallium oxide, which can form a crystalline state and the higher the indium content, the better the crystallinity in the subsequent process and the higher the mobility of the thin film transistor 1, while the indium gallium zinc oxide material commonly used as the active layer 11 material cannot form a crystalline state.

[0058] The material of the sub-active layer 111 may only include crystalline oxide materials to enhance the balance between mobility and light stability.

[0059] Among them, the indium gallium oxide material includes indium gallium oxide, and the ratio of the total number of atoms in the indium gallium oxide to the total number of atoms in the crystalline oxide material is 70%-100%, specifically 70%, 72%, 79%, 80%, 85%, 90%, 92%, 94%, 97%, 100%, etc., and the present application does not make any special limitation on this. The higher the ratio of the total number of atoms in the indium gallium oxide to the total number of atoms in the crystalline oxide material, the better the mobility and light stability of the thin film transistor 1.

[0060] In a possible implementation, Figure 5 As shown, the multi-layer sub-active layer 111 includes at least one first sub-active layer 1111 and at least one second sub-active layer 1112, the atomic number ratio of the indium element in the first sub-active layer 1111 is smaller than the atomic number ratio of the indium element in the second sub-active layer 1112, and the atomic number ratio of the gallium element in the first sub-active layer 1111 is greater than the atomic number ratio of the gallium element in the second sub-active layer 1112.

[0061] In the above embodiment, the multi-layer sub-active layer 111 may include sub-active layers 111 with two atomic number ratios, namely, a first sub-active layer 1111 and a second sub-active layer 1112; or, the multi-layer sub-active layer 111 may include sub-active layers 111 with multiple atomic number ratios, such as three sub-active layers 111 or more seed active layers 111, which is not particularly limited in the present application.

[0062] Specifically, the atomic number ratio of the indium element in the first sub-active layer 1111 is less than the atomic number ratio of the indium element in the second sub-active layer 1112, and the atomic number ratio of the gallium element in the first sub-active layer 1111 is greater than the atomic number ratio of the gallium element in the second sub-active layer 1112. Since the atomic number ratio of the indium element is larger, the crystallinity is better in the subsequent process, and the mobility of the thin film transistor 1 is higher, but the better the crystallinity of the indium gallium oxide, the better the crystallization effect, which makes the wet etching more difficult. Therefore, the crystallinity of the first sub-active layer 1111 is weaker than that of the second sub-active layer 1112, but The etching difficulty is lower than that of the second sub-active layer 1112. The crystallinity of the second sub-active layer 1112 is stronger than that of the first sub-active layer 1111, so the mobility and light stability are better, but the etching difficulty is greater than that of the first sub-active layer 1111. Therefore, by setting the active layer 11 to include a first sub-active layer 1111 and a second sub-active layer 1112 arranged in a stacked manner, the etching difficulty of the active layer 11 can be reduced through the first sub-active layer 1111 to improve the feasibility of preparation, and the mobility and light stability can be improved through the second sub-active layer 1112, thereby achieving a comprehensive improvement in the performance of the thin film transistor 1 itself.

[0063] In a possible implementation, Figure 5 As shown, the first sub-active layer 1111 and the second sub-active layer 1112 are alternately arranged along the first direction x, the active layer 11 includes a first side A1 and a second side A2, the first side A1 and the second side A2 are arranged along the first direction x, wherein a layer of the first sub-active layer 1111 is close to the first side A1, and wherein a layer of the second sub-active layer 1112 is close to the second side A2.

[0064] In the above embodiment, one of the second sub-active layers 1112 is set to be close to the second side A2. The second sub-active layer 1112 can be prepared first during the preparation of the active layer 11. Since the atomic number ratio of the indium element in the second sub-active layer 1112 is greater than the atomic number ratio of the indium element in the first sub-active layer 1111, high mobility and high crystal quality can be provided for the thin film transistor 1. During the preparation process, when the first sub-active layer 1111 is prepared above the second sub-active layer 1112, the second sub-active layer 1112 can induce crystallization of the first sub-active layer 1111 in contact with the second sub-active layer 1112, thereby improving the crystallinity and mobility of the upper first sub-active layer 1111, while maintaining the low etching difficulty of the first sub-active layer 1111, thereby reducing the patterning difficulty of the active layer 11. The first sub-active layer 1111 can supplement oxygen atoms for the second sub-active layer 1112 , regulate the carrier concentration of the second sub-active layer 1112 , and have better crystallinity and mobility under the induction of the second sub-active layer 1112 during the film formation process.

[0065] Specifically, in the above embodiment, the number of the sub-active layers 111 can be odd or even. Figure 6 As shown, when the number of sub-active layers 111 is even, and when one of the second sub-active layers 1112 is close to the first side A1, one of the first sub-active layers 1111 is close to the second side A2; Figure 5 As shown, when one of the second sub-active layers 1112 is close to the second side A2, one of the first sub-active layers 1111 is close to the first side A1. Figure 7 As shown, when the number of the sub-active layers 111 is odd, and when one of the second sub-active layers 1112 is close to the first side A1, another second sub-active layer 1112 is close to the second side A2; Figure 8 As shown, when one layer of the second sub-active layer 1112 is close to the second side A2, another layer of the second sub-active layer 1112 is close to the first side A1.

[0066] In a feasible implementation manner, the number of atoms of the indium element in the first sub-active layer 1111 is a 1 , the number of atoms of gallium is b 1 , k 1 =a 1 / (a 1 +b 1 ), k 2 =b 1 / (a 1 +b 1 ), where 50%≤k 1 ≤80%, 20%≤k 2 ≤50%.

[0067] Specifically, k 1 It can be 50%, 55%, 57%, 63%, 68%, 70%, 72%, 79%, 80%, etc. 2 It can be 20%, 21%, 24%, 28%, 35%, 46%, 50%, etc. This application does not make any special limitation on this and can be selected according to actual needs.

[0068] Specifically, k can be set within the above numerical range in the first sub-active layer 1111. 1 Set to a smaller value, k 2 It is set to be larger to further reduce the difficulty of etching the active layer 11.

[0069] In a feasible implementation manner, the number of atoms of the indium element in the second sub-active layer 1112 is a 2 , the number of atoms of gallium is b 2 , k 3 =a 2 / (a 2 +b2 ), k 4 =b 2 / (a 2 +b 2 ), where 80% ≤ k 3 ≤100%, 0≤k 4 ≤20%.

[0070] Specifically, k in the second active sub-layer 1112 3 It can be 80%, 83%, 88%, 90%, 95%, 96%, 99%, 100%, etc. 4 It can be 5%, 8%, 10%, 11%, 15%, 18%, 20%, etc. This application does not make any special limitation on this and can be selected according to actual needs.

[0071] Specifically, within the above numerical range, a larger k 3 And choose a smaller k 4 , so as to further improve the mobility of the active layer 11.

[0072] In a possible implementation, Figure 8 As shown, the dimension D of the active layer 11 along the first direction x is 3 nm-50 nm.

[0073] In the above embodiment, the size of the active layer 11 along the first direction x may be 3nm, 5nm, 10nm, 13nm, 17nm, 20nm, 26nm, 28nm, 30nm, 35nm, 40nm, 43nm, 48nm, 50nm, etc., and the present application does not make any special limitation on this.

[0074] When the size of the active layer 11 along the first direction x is small, the risk of breakage is easily increased, and it is not easy to ensure the yield of the thin film transistor 1. When the size of the active layer 11 along the first direction x is large, the preparation cost is high and it is not easy to etch. Therefore, setting the size of the active layer 11 along the first direction x within the above range can simultaneously take into account the yield and manufacturing cost of the active layer 11.

[0075] In a possible implementation, Figure 8 As shown, the size of the first sub-active layer 1111 along the first direction x is 1 nm-10 nm.

[0076] Specifically, the size of the first sub-active layer 1111 along the first direction x may be 1 nm, 2 nm, 3 nm, 5 nm, 6 nm, 7 nm, 10 nm, etc., which is not particularly limited in the present application.

[0077] In a possible implementation, Figure 8As shown, the size of the second sub-active layer 1112 along the first direction x is 0.5 nm-5 nm.

[0078] Specifically, the size of the second sub-active layer 1112 along the first direction x may be 0.5 nm, 1 nm, 1.5 nm, 2 nm, 3 nm, 3.5 nm, 4.5 nm, 5 nm, etc., which is not particularly limited in the present application.

[0079] In a feasible implementation manner, the size of the first sub-active layer 1111 along the first direction x can be set to be larger than the size of the second sub-active layer 1112 along the first direction x, and the first sub-active layer 1111 plays a dominant role in the difficulty of etching the active layer 11. The thicker the first sub-active layer 1111 is and the greater the proportion of the thickness of the first sub-active layer 1111 in the active layer 11, the lower the difficulty of etching the active layer 11; the second sub-active layer 1112 plays a dominant role in the mobility and light reliability of the active layer 11. The thicker the second active layer 11 is and the greater the proportion of the second active layer 11 in the thickness of the active layer 11, the better the mobility and light reliability of the active layer 11. That is, the above-mentioned setting method can make the etching difficulty, mobility and light reliability of the active layer 11 meet the requirements.

[0080] Specifically, the thickness of each sub-active layer 111 may be adjusted according to the difference in etching selectivity and the mobility requirement of the thin film transistor 1 .

[0081] In a feasible implementation manner, in the active layer 11 , the atomic number ratio of the indium element in the sub-active layer 111 close to the first side A1 and / or close to the second side A2 is greater than or equal to the atomic number ratio of the indium element in any other sub-active layer 111 .

[0082] In the above embodiment, by making the atomic number ratio of the indium element in the sub-active layer 111 close to the first side A1 and / or close to the second side A2 greater than or equal to the atomic number ratio of the indium element in any other sub-active layer 111, the sub-active layer 111 having the largest atomic number ratio of the indium element in each sub-active layer 111 can be prepared first during the preparation process, and then the other sub-active layers 111 are prepared on the sub-active layer 111. Since the atomic number ratios of the indium element in two adjacent sub-active layers 111 are different, the atomic number ratio of the indium element in the sub-active layer 111 located above and adjacent to the sub-active layer 111 is relatively small, and the sub-active layer 111 can be induced to crystallize the other sub-active layers 111 above, thereby improving the crystallinity and mobility of the sub-active layer 111 above, and maintaining the easy etching property brought about by the low atomic number ratio of the indium element in the other sub-active layers 111 above.

[0083] In a feasible implementation manner, the active layer 11 further includes doping particles, and the ratio of the total number of atoms of the doping particles to the total number of atoms in the crystalline oxide material is greater than 0 and less than or equal to 30%.

[0084] In particular, the doping particles include tin and / or germanium.

[0085] In the above-mentioned embodiment, the active layer 11 includes a crystalline oxide material and doped particles. The doped particles can improve the diversity of the active layer 11. The doped particles that are easily available can be selected according to the actual preparation conditions. Under the premise of ensuring crystallinity, lower-cost crystalline particles can be selected to reduce the preparation cost of the active layer 11. Specifically, the doped particles include tin and / or germanium, and the ratio of the total number of atoms of the doped particles to the total number of atoms in the crystalline oxide material is greater than 0 and less than or equal to 30%, so that the main material in the active layer 11 can be ensured to be indium gallium oxide, thereby achieving a balance between mobility and light stability.

[0086] The present application also provides a method for preparing a thin film transistor 1, such as Fig. 9 As shown, including:

[0087] S200, crystalline oxide materials with different atomic ratios of indium are deposited successively to sequentially form a plurality of sub-active layers 111 stacked along a first direction x, wherein the atomic ratios of indium in adjacent sub-active layers 111 are different, thereby forming an active layer 11.

[0088] Specifically, the crystalline oxide material is deposited using an atomic layer deposition process.

[0089] In the method for preparing the thin film transistor 1 provided in the present application, the sub-active layer 111 is prepared by an atomic layer deposition process, so that the atomic number ratio of the film can be adjusted according to the requirements of the atomic number ratio, so that the sub-active layer 111 with a preset atomic number ratio can be accurately prepared. The preparation method is simple and has high accuracy.

[0090] Specifically, the active layer 11 includes a first side A1 and a second side A2, the first side A1 and the second side A2 are arranged along a first direction x, and the preparation method further includes:

[0091] S400 , forming a gate 13 on the first side A1 or the second side A2 , wherein the gate 13 and the active layer 11 are insulated from each other.

[0092] S600 , forming a source-drain electrode layer 12 on the first side A1 , wherein the source-drain electrode layer 12 is connected to the active layer 11 and is insulated from the gate 13 .

[0093] Before the above step S200, the process may further include S100: providing a substrate 18, and sequentially forming a buffer layer 17, a light shielding layer 16, and a second insulating layer 15 on the substrate 18; or providing a substrate 18, and sequentially forming a buffer layer 17, a gate 13, and a first insulating layer 14 on the substrate 18. This application does not specifically limit this.

[0094] The present application also provides an array substrate 2, such as Fig.10 As shown, it includes any one of the thin film transistors 1 provided in the above embodiments of the present application.

[0095] In the array substrate 2 provided by the present application, the mobility and light stability of the thin film transistor 1 are better, so the performance of the array substrate 2 is better. In addition, the preparation process of the thin film transistor 1 in the array substrate 2 provided by the present application is relatively simple, which takes into account the difficulty of etching while ensuring its own mobility and light stability, which helps to reduce the preparation cost.

[0096] The present application also provides a display panel 3, such as Fig.11 As shown, it includes the array substrate 2 provided in the above embodiment of the present application.

[0097] The array substrate 2 in the display panel 3 provided in the present application has better performance and better driving effect, thereby making the performance of the display panel 3 better.

[0098] According to the embodiments of the present application as above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A thin film transistor, characterized in that: An active layer is included, wherein the active layer includes a plurality of sub-active layers, the plurality of sub-active layers are stacked along a first direction, the sub-active layers include crystalline oxide materials, and the atomic number ratios of indium elements in adjacent sub-active layers are different.

2. The thin film transistor according to claim 1, characterized in that: The crystalline oxide material includes indium gallium oxide, and the ratio of the total number of atoms in the indium gallium oxide to the total number of atoms in the crystalline oxide material is 70%-100%.

3. The thin film transistor according to claim 2, characterized in that: The multiple sub-active layers include at least one first sub-active layer and at least one second sub-active layer, the atomic number ratio of indium element in the first sub-active layer is less than the atomic number ratio of indium element in the second sub-active layer, and the atomic number ratio of gallium element in the first sub-active layer is greater than the atomic number ratio of gallium element in the second sub-active layer; Preferably, the first sub-active layer and the second sub-active layer are alternately arranged along the first direction, the active layer comprises a first side and a second side, the first side and the second side are arranged along the first direction, one layer of the first sub-active layer is close to the first side, and one layer of the second sub-active layer is close to the second side; Preferably, the number of atoms of the indium element in the first active sub-layer is a1, the number of atoms of the gallium element is b1, k1=a1 / (a1+b1), k2=b1 / (a1+b1), wherein 50%≤k1≤80%, 20%≤k2≤50%; Preferably, the number of atoms of indium element in the second active sub-layer is a2, the number of atoms of gallium element is b2, k3=a2 / (a2+b2), k4=b2 / (a2+b2), wherein 80%≤k3≤100%, 0≤k4≤20%.

4. The thin film transistor according to claim 3, characterized in that: The size of the active layer along the first direction is 3nm-50nm; Preferably, the size of the first sub-active layer along the first direction is 1nm-10nm; Preferably, a size of the second sub-active layer along the first direction is 0.5 nm-5 nm.

5. The thin film transistor according to claim 1, characterized in that: In the active layer, the atomic number ratio of the indium element in the sub-active layer close to the first side and / or close to the second side is greater than or equal to the atomic number ratio of the indium element in any other sub-active layer.

6. The thin film transistor according to claim 1, characterized in that: The active layer further includes doping particles, and the ratio of the total number of atoms of the doping particles to the total number of atoms in the crystalline oxide material is greater than 0 and less than or equal to 30%; Preferably, the doping particles include tin and / or germanium.

7. The thin film transistor according to claim 1, characterized in that: The active layer includes a first side and a second side, the first side and the second side are arranged along the first direction, and the thin film transistor further includes: a source-drain electrode layer, formed on the first side and connected to the active layer; a gate, formed on the first side and / or the second side, and insulated from the active layer and the source and drain layer; Preferably, the gate is formed on the first side, the gate is insulated from the active layer by a first insulating layer, and further comprises a second insulating layer, a light shielding layer, a buffer layer and a substrate which are formed on the second side and stacked in a direction away from the active layer, wherein the orthographic projection of the light shielding layer on the substrate covers the orthographic projection of the gate on the substrate; or, The gate is formed on the second side, and the gate is insulated from the active layer by a first insulating layer.

8. A method for preparing a thin film transistor, characterized in that: include: Crystalline oxide materials with different atomic ratios of indium are deposited successively to sequentially form multiple sub-active layers stacked along a first direction, wherein the atomic ratios of indium in adjacent sub-active layers are different, thereby forming an active layer.

9. The preparation method according to claim 8, characterized in that: The active layer comprises a first side and a second side, the first side and the second side are arranged along the first direction, and the preparation method further comprises: forming a gate on the first side or the second side, the gate being insulated from the active layer; forming a source-drain electrode layer on the first side, the source-drain electrode layer being connected to the active layer and being insulated from the gate; Preferably, the crystalline oxide material is deposited using an atomic layer deposition process.

10. An array substrate, characterized in that: Comprising a thin film transistor as described in any one of claims 1 to 7.

11. A display panel, characterized in that: Comprising the array substrate as claimed in claim 10.

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