Semiconductor device and preparation method thereof, and electronic equipment

Abstract

The invention provides a semiconductor device, a preparation method thereof and electronic equipment, relates to the technical field of semiconductors, and aims to improve the reliability of the semiconductor device. The semiconductor device comprises a substrate, an epitaxial layer located on one side of the substrate, a channel part and a gate semiconductor layer which are located on the side, away from the substrate, of the epitaxial layer, a source electrode contact layer located on the side, away from the substrate, of the channel part, and a drain electrode located on the side, away from the epitaxial layer, of the substrate. The channel part comprises a first channel sub-part and a second channel sub-part which are connected, and the first channel sub-part is located between the epitaxial layer and the second channel sub-part. The gate semiconductor layer surrounds the first channel sub-portion. The source contact layer is located on the second channel sub-portion, and the second channel sub-portion separates the source contact layer from the gate semiconductor layer. The drain is located at one side of the substrate away from the epitaxial layer. The semiconductor device is applied to a power electronic device.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same, and an electronic device. Background Art

[0002] Junction field effect transistor (JFET) has the advantages of simple structure and reliable performance, and is widely used as an electrically controlled switch structure in electronic devices made of traditional silicon (Si) and wide bandgap semiconductors (such as silicon carbide (SiC), gallium nitride (GaN), etc.). JFET is a unipolar electronic device, that is, when the JFET is in the on state, there is basically only one type of carrier flowing in the channel of the JFET to form a conduction current between the source and the drain. The gate and channel of the JFET form a PN junction. In a normally-on JFET, by applying a voltage on the gate, the PN junction can be reverse biased to the channel pinch-off voltage to turn off the JFET.

[0003] JFET mainly includes vertical JFET, the channel of which extends along the thickness direction of the substrate, and the source and drain are located on the upper and lower sides of the channel, which is conducive to reducing the area of ​​the vertical JFET and improving the integration of devices used in the vertical JFET.

[0004] However, the vertical JFET has a problem of low breakdown voltage between the gate and the source, which reduces the reliability of the vertical JFET. Summary of the invention

[0005] Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, and an electronic device, aiming to improve the reliability of the semiconductor device.

[0006] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0007] In a first aspect, a semiconductor device is provided, comprising: a substrate, an epitaxial layer, a channel portion, a gate semiconductor layer, a source contact layer and a drain. The epitaxial layer is located on one side of the substrate. The channel portion is located on a side of the epitaxial layer away from the substrate, and the channel portion comprises a first channel sub-portion and a second channel sub-portion connected to each other, and the first channel sub-portion is located between the epitaxial layer and the second channel sub-portion. The gate semiconductor layer is located on a side of the epitaxial layer away from the substrate and surrounds the first channel sub-portion. The source contact layer is located on a side of the second channel sub-portion away from the substrate. The second channel sub-portion separates the source contact layer and the gate semiconductor layer. The drain is located on a side of the substrate away from the epitaxial layer.

[0008] The semiconductor device provided by some embodiments of the present disclosure divides the channel portion into a first channel sub-portion and a second channel sub-portion connected to each other, so that the first channel sub-portion is located between the epitaxial layer and the second channel sub-portion, and adjusts the arrangement between the gate semiconductor layer and the channel portion so that the gate semiconductor layer surrounds the first channel sub-portion, and the second channel sub-portion can be used to separate the gate semiconductor layer and the second channel sub-portion. That is, by adjusting the structure included in the semiconductor device itself, the distance between the gate semiconductor layer and the second channel sub-portion is increased. The adjustment of this structure is relatively clever, and can effectively improve the breakdown voltage between the gate and the source without adding additional structures, thereby enhancing the reliability of the semiconductor device.

[0009] In some embodiments, an orthographic projection of one end of the first channel subportion in contact with the second channel subportion on the substrate is located within a range of an orthographic projection of one end of the second channel subportion in contact with the first channel subportion on the substrate.

[0010] In some embodiments, the first channel sub-portion includes a first portion and a second portion connected to each other, the first portion is located between the epitaxial layer and the second portion, and an orthographic projection of the second portion on the substrate is located within the orthographic projection of the first portion on the substrate.

[0011] In some embodiments, a distance between an orthographic projection boundary of the second portion on the substrate and an orthographic projection boundary of the first portion on the substrate is in a range of 0.1 μm-1 μm.

[0012] In some embodiments, an orthographic projection of the second channel sub-portion on the substrate coincides with an orthographic projection of the first portion on the substrate.

[0013] In some embodiments, the semiconductor device further comprises: a current diffusion layer. The current diffusion layer is located between the epitaxial layer and the first channel sub-portion and contacts the first channel sub-portion. The orthographic projection of the first channel sub-portion on the substrate is located within the orthographic projection range of the current diffusion layer on the substrate.

[0014] In some embodiments, the current diffusion layer and the first channel sub-portion are in an integrated structure.

[0015] In some embodiments, there are multiple channel parts, and the gate semiconductor layer surrounds the first channel sub-parts of the multiple channel parts. A source contact layer is disposed on the side of the second channel sub-part of each channel part away from the substrate, and at least two source contact layers are electrically connected.

[0016] In some embodiments, the semiconductor device further comprises: a source electrode, a first ohmic contact layer, a gate electrode, and a second ohmic contact layer. The source electrode is located on a side of the source contact layer away from the substrate. The first ohmic contact layer is located between the source contact layer and the source electrode. The gate electrode is located on a side of the gate semiconductor layer away from the substrate. The second ohmic contact layer is located between the gate semiconductor layer and the gate electrode.

[0017] In some embodiments, the semiconductor device further comprises: a plurality of annular protrusions and a field limiting ring. The plurality of annular protrusions are located on a side of the epitaxial layer away from the substrate and are arranged in a ring-shaped manner in sequence, and the plurality of annular protrusions surround the channel portion and the gate semiconductor layer. The field limiting ring is located on a side of the epitaxial layer away from the substrate and is located between two adjacent annular protrusions.

[0018] In some embodiments, the gate semiconductor layer includes a first gate layer and a second gate layer connected to each other. The first gate layer surrounds the first channel sub-portion, and compared to the substrate, a side surface of the second gate layer away from the substrate is lower than a side surface of the first gate layer away from the substrate. The second gate layer is made of the same material as the field limiting ring and is disposed in the same layer.

[0019] In some embodiments, the annular protrusion includes a first annular sub-protrusion and a second annular sub-protrusion connected to each other, the first annular sub-protrusion is located between the epitaxial layer and the second annular sub-protrusion, the first annular sub-protrusion and the first channel sub-portion are arranged in the same layer, and the second annular sub-protrusion and the second channel sub-portion are made of the same material and arranged in the same layer.

[0020] In a second aspect, a method for preparing a semiconductor device is provided, the method comprising: providing a substrate. An epitaxial layer, a channel portion, a gate semiconductor layer and a source contact layer are formed on one side of the substrate; the channel portion is located on a side of the epitaxial layer away from the substrate; the channel portion comprises a first channel sub-portion and a second channel sub-portion connected to each other, the first channel sub-portion being located between the epitaxial layer and the second channel sub-portion; the gate semiconductor layer is located on a side of the epitaxial layer away from the substrate and surrounds the first channel sub-portion; the source contact layer is located on a side of the second channel sub-portion away from the substrate; the second channel sub-portion separates the source contact layer and the gate semiconductor layer. A drain is formed on a side of the substrate away from the epitaxial layer.

[0021] In some embodiments, an epitaxial layer, a channel portion, a gate semiconductor layer, and a source contact layer are formed on one side of a substrate, including: forming an epitaxial film on one side of the substrate. Performing a first ion implantation from a side of the epitaxial film away from the substrate to form a first doped region. Forming a first mask pattern on a side of the epitaxial film away from the substrate, the first mask pattern covers a portion of the first doped region and exposes another portion of the first doped region. Based on the first mask pattern, performing a second ion implantation from a side of the epitaxial film away from the substrate to form a second doped region; the portion of the first doped region opposite to the second doped region constitutes a second portion of the first channel sub-portion, and the second doped region is used to constitute a gate semiconductor layer. Forming a second channel sub-portion and a source contact layer on a side of the epitaxial film away from the substrate; the second channel sub-portion covers the first doped region and a portion of the second doped region.

[0022] In some embodiments, an epitaxial layer, a channel portion, a gate semiconductor layer and a source contact layer are formed on one side of the substrate, and also include: etching and thinning the second doped region based on the second channel sub-portion and the source contact layer; based on the second channel sub-portion and the source contact layer, performing a third ion implantation from a side of the epitaxial film away from the substrate to form a third doped region, the third doped region is connected to the second doped region to constitute a gate semiconductor layer.

[0023] In some embodiments, the epitaxial film has a termination region and an active region, and the termination region surrounds the active region; the channel portion and the gate semiconductor layer are located in the active region. In the process of forming the second channel sub-portion and the source contact layer on the side of the epitaxial film away from the substrate, a second annular sub-protrusion is also formed on the side of the epitaxial film away from the substrate; the second annular sub-protrusion is located in the termination region. In the process of etching and thinning the second doped region based on the second channel sub-portion and the source contact layer, the portion of the epitaxial film located in the termination region is thinned based on the second channel sub-portion and the source contact layer. In the process of forming the third doped region, the portion of the epitaxial film located in the termination region is also implanted with a third ion based on the second annular sub-protrusion to form a field limiting ring; the portion located between the second annular sub-protrusion and the substrate and in contact with the field limiting ring constitutes the first annular sub-protrusion.

[0024] In some embodiments, before forming the drain on the side of the substrate away from the epitaxial layer, the preparation method further includes: forming a first ohmic contact layer on the side of the source contact layer away from the substrate, and forming a second ohmic contact layer on the side of the gate semiconductor layer away from the substrate. Forming a dielectric layer covering the first ohmic contact layer and the second ohmic contact layer. Forming a source and a gate; the source penetrates the dielectric layer to the first ohmic contact layer, and the gate penetrates the dielectric layer to the second ohmic contact layer.

[0025] In a third aspect, an electronic device is provided, the electronic device comprising: a semiconductor device and a circuit board, wherein the circuit board is electrically connected to the semiconductor device. The semiconductor device is the semiconductor device as described in any one of the first aspects.

[0026] The technical effects brought about by any embodiment of the second aspect to the third aspect can refer to the technical effects brought about by different embodiments of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required for use in some embodiments of the present disclosure are briefly introduced below.

[0028] Figure 1 is a structural diagram of an electronic device according to some embodiments;

[0029] Figure 2 The structure of the semiconductor device according to some embodiments Figure 1 ;

[0030] Figure 3 The structure of the semiconductor device according to some embodiments Figure 2 ;

[0031] Figure 4 is a simulated electric field distribution diagram between a gate and a source of a semiconductor device according to some embodiments;

[0032] Figure 5 The simulated electric field strength of the semiconductor device according to some embodiments is Figure 4 The sampling line distribution curve diagram of the Y axis shown;

[0033] Figure 6 The structure of the semiconductor device according to some embodiments Figure 3 ;

[0034] Figure 7 The structure of the semiconductor device according to some embodiments Figure 4 ;

[0035] Figure 8 The structure of the semiconductor device according to some embodiments Figure 5 ;

[0036] Fig. 9 The structure of the semiconductor device according to some embodiments Figure 6 ;

[0037] Fig.10 is a flow chart of a method for preparing a semiconductor device according to some embodiments;

[0038] Figure 11a-11l The structures corresponding to the steps in the method for preparing a semiconductor device according to some embodiments are Figure 1 ;

[0039] Figure 12a-Figure 12c The structures corresponding to the steps in the method for preparing a semiconductor device according to some embodiments are Figure 2 ;

[0040] Fig.13a for Figure 2 A transfer characteristic curve diagram of a semiconductor device shown;

[0041] Fig.13b is a transfer characteristic curve diagram of a semiconductor device according to some embodiments;

[0042] Fig.14a for Figure 2 An off-state breakdown current-voltage curve diagram of the semiconductor device shown;

[0043] Fig.14bFIG. 4 is an off-state breakdown current-voltage curve diagram of a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0044] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0045] In the description of the present disclosure, unless the context requires otherwise, throughout the specification and claims, the term "including" is interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0046] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0047] When describing some embodiments, the term "connected" and its derivative expressions may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0048] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0049] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0050] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0051] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0052] In the context of the present disclosure, the meaning of “on the side away from…” should be interpreted in the broadest manner, so that “on the side away from…” not only means “directly on the side of something away from…” but also includes the meaning of “on the side of something away from…” with intermediate features or layers therebetween.

[0053] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0054] Some embodiments of the present application provide an electronic device. The electronic device may be a power electronic device, that is, a device with a power electronic device (also referred to as a semiconductor device or a power semiconductor device) as a main functional element. For example, the electronic device may be a converter, an electronic switch, an electronic AC power controller, a power factor correction (PFC) circuit, etc. Among them, the converter includes but is not limited to a DC chopper (DC / DC, or a DC to DC power supply), a rectifier (AC / DC, or an AC-DC converter), an inverter (DC / AC, or a DC-AC converter), etc., and the electronic switch includes but is not limited to a power switch power supply circuit, etc. The embodiments of the present application do not impose any special restrictions on the specific type of the electronic device.

[0055] Figure 1 The schematic diagram of the structure of an electronic device 1000 is shown. The electronic device 1000 comprises a semiconductor device 100 and a circuit board 200. The circuit board 200 and the semiconductor device 100 are electrically connected, and the circuit board 200 is used to provide the semiconductor device 100 with required electrical signals.

[0056] It is to be understood that the structure illustrated in the embodiment of the present application does not constitute a specific limitation on the electronic device 1000. In other embodiments of the present application, the electronic device 1000 may include more components than those shown in the figure, or combine certain components, or separate certain components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0057] Some embodiments of the present disclosure also provide a semiconductor device. The semiconductor device can be applied to the above-mentioned electronic device 1000. Optionally, the semiconductor device provided in the embodiment of the present application can be used as the semiconductor device in the above-mentioned electronic device 1000. Of course, the specific application scenarios of the above-mentioned semiconductor device are not limited thereto. It can be understood that any electronic device that needs to use a power semiconductor device belongs to the application scenario of the embodiment of the present application. Alternatively, the semiconductor device provided in the embodiment of the present application can be used alone.

[0058] Figure 2 A structural diagram of a semiconductor device is shown. In some examples, such as Figure 2 As shown, the semiconductor device may include a substrate 1, an epitaxial layer 2, a channel portion 3, a gate semiconductor layer 4, a source contact layer 5, a gate 6, a source 7, and a drain 8. The channel portion 3, the gate semiconductor layer 4, the source contact layer 5, the gate 6, the source 7, and the drain 8 may constitute a JFET.

[0059] Continue reading Figure 2 , the epitaxial layer 2 is located on one side of the substrate 1. Exemplarily, the materials of the substrate 1 and the epitaxial layer 2 both include wide bandgap semiconductor materials, which include but are not limited to silicon carbide, gallium nitride, diamond, etc. Optionally, the materials of the substrate 1 and the epitaxial layer 2 are the same, for example, the materials of the substrate 1 and the epitaxial layer 2 are both silicon carbide.

[0060] Exemplarily, the substrate 1 is an N+ substrate, that is, the substrate 1 is subjected to N-type high doping treatment (or heavy doping treatment), which can reduce the resistivity of the substrate 1. The epitaxial layer 2 is an N-epitaxial layer, that is, the epitaxial layer 2 is subjected to N-type light doping treatment. The epitaxial layer 2 can also be called an N-drift region.

[0061] The channel portion 3 and the gate semiconductor layer 4 are both located on the side of the epitaxial layer 2 away from the substrate 1, and the gate semiconductor layer 4 surrounds the channel portion 3. The source contact layer 5 is located on the side of the channel portion 3 away from the substrate 1 and is in contact with the channel portion 3. The gate 6 is located on the side of the gate semiconductor layer 4 away from the substrate 1 and is in contact with the gate semiconductor layer 4; the source 7 is located on the side of the source contact layer 5 away from the substrate 1 and is in contact with the source contact layer 5; the drain 8 is located on the side of the substrate 1 away from the epitaxial layer 2.

[0062] Exemplarily, the gate 6 and the source 7 are made of the same material. Optionally, the material of either the gate 6 or the source 7 includes, but is not limited to, metal materials such as titanium, aluminum, gold, silver, copper, and their alloy materials, or heavily doped polysilicon, titanium nitride, indium tin oxide, and other conductive materials. The material of the drain 8 includes, but is not limited to, metal materials such as nickel, aluminum, titanium, tungsten, and their alloy materials.

[0063] When the above-mentioned semiconductor device is in the on state, the gate 6 can receive a more appropriate voltage, which can be distributed on the gate semiconductor layer 4 to control the conduction of the semiconductor device. The current will flow out from the source 7 and conduct downward, passing through the source contact layer 5, the channel part 3, the epitaxial layer 2 and the substrate 1 in sequence to the drain 8.

[0064] In some possible implementations, the channel portion 3 is formed by ion implanting a semiconductor structure protruding from the epitaxial layer 2, the source contact layer 5 is formed by ion implanting the top of the channel portion 3, and the gate semiconductor layer 4 is formed by ion implanting the sidewall and bottom of the channel portion 3, and the channel portion 3 and the source contact layer 5 have the same doping type, and the doping type of the channel portion 3 is opposite to the doping type of the gate semiconductor layer 4. Optionally, the doping type of the channel portion 3 and the source contact layer 5 are both N-type, and the doping type of the gate semiconductor layer 4 is P-type.

[0065] In order to form the gate semiconductor layer 4, in the process of ion implantation into the sidewall and bottom of the channel portion 3, it is necessary to adopt an inclined ion implantation method, that is, to make the angle of ion implantation form a certain angle with the extension direction of the channel portion 3. This requires more precise control of the angle, depth, dose, etc. of ion implantation, which increases the difficulty of preparing semiconductor devices. Moreover, the use of an inclined ion implantation method to form the gate semiconductor layer 4 will result in a very small spacing between the gate semiconductor layer 4 and the source contact layer 5, which will in turn result in a low breakdown voltage between the gate 6 and the source 7, reducing the reliability of the semiconductor device.

[0066] Based on this, some embodiments of the present disclosure make improvements to the semiconductor device 100, wherein: Figure 3 A structural diagram of a semiconductor device is shown schematically.

[0067] In some embodiments, Figure 3 As shown, the semiconductor device 100 may include a substrate 1, an epitaxial layer 2, a channel portion 3, a gate semiconductor layer 4, a source contact layer 5, a gate 6, a source 7, and a drain 8. For the substrate 1, the epitaxial layer 2, the gate 6, the source 7, and the drain 8, reference may be made to the above related descriptions, which will not be repeated here.

[0068] In some examples, the channel portion 3 is located on a side of the epitaxial layer 2 away from the substrate 1. The channel portion 3 extends along the thickness direction of the substrate 1. The thickness direction of the substrate 1 refers to the stacking direction of the substrate 1, the epitaxial layer 2 and the channel portion 3.

[0069] Continue reading Figure 3 , wherein the channel portion 3 includes a first channel sub-portion 31 and a second channel sub-portion 32 connected to each other, and the first channel sub-portion 31 is located between the epitaxial layer 2 and the second channel sub-portion 32. The first channel sub-portion 31 and the second channel sub-portion 32 are in direct contact, for example, the first channel sub-portion 31 and the second channel sub-portion 32 are two independent structures, and there is a relatively obvious interface between the two.

[0070] In some examples, such as Figure 3 As shown, the gate semiconductor layer 4 is located on the side of the epitaxial layer 2 away from the substrate 1, and surrounds the first channel sub-portion 31. For example, relative to the substrate 1, the surface of the side of the gate semiconductor layer 4 away from the substrate 1 is flush with the surface of the side of the first channel sub-portion 31 away from the substrate 1. The gate semiconductor layer 4 does not surround the second channel sub-portion 32; in the direction perpendicular to the thickness direction of the substrate 1, the gate semiconductor layer 4 and the second channel sub-portion 32 do not overlap.

[0071] Exemplarily, the gate semiconductor layer 4 is in direct contact with the sidewall of the first channel sub-portion 31. For example, the first channel sub-portion 31 and the gate semiconductor layer 4 are both formed by doping a semiconductor material, and the doping type of the first channel sub-portion 31 is opposite to the doping type of the gate semiconductor layer 4. Optionally, the doping type of the first channel sub-portion 31 is N-type, and the doping type of the gate semiconductor layer 4 is P-type.

[0072] In some examples, such as Figure 3 As shown, the source contact layer 5 is located on the side of the second channel sub-portion 32 away from the substrate 1. The gate semiconductor layer 4 is located below the second channel sub-portion 32, and the second channel sub-portion 32 separates the source contact layer 5 and the gate semiconductor layer 4, and the source contact layer 5 and the gate semiconductor layer 4 are not in direct contact.

[0073] Accordingly, the distance between the source contact layer 5 and the gate semiconductor layer 4 increases, which can effectively improve the breakdown voltage between the gate 6 and the source 7 .

[0074] The embodiments of the present disclosure are respectively Figure 2 and Figure 3 The semiconductor device shown in the figure is simulated, and the simulation results are shown in Figure 4 As shown. Among them, Figure 4 (a) in Figure 2 The electric field distribution diagram between the gate 6 and the source 7 in the semiconductor device shown in FIG. Figure 4 (b) in Figure 3The electric field distribution between the gate 6 and the source 7 in the semiconductor device is shown. Figure 5 for Figure 2 and Figure 3 The simulated electric field strength of the semiconductor device shown is Figure 4 The sampling line distribution curve graph of the Y axis is shown.

[0075] like Figure 4 (a) and Figure 5 As shown, the voltage difference (V GS ) is -20V, the semiconductor device is turned off. Figure 2 In the semiconductor device shown, there is a high field (about 3.2 MV / cm) between the gate 6 and the source 7. This means that the PN junction formed between the gate 6 and the source 7 has been reversely broken down. GS Next, such as Figure 4 (b) and Figure 5 As shown, Figure 3 The electric field strength of the PN junction formed between the gate 6 and the source 7 in the semiconductor device shown is less than 1.5 MV / cm, which is less than the breakdown electric field. This means that Figure 3 The gate voltage range of the semiconductor device shown is improved, and the breakdown voltage range between the gate 6 and the source 7 is improved.

[0076] Therefore, the semiconductor device 100 provided by some embodiments of the present disclosure divides the channel portion 3 into the first channel sub-portion 31 and the second channel sub-portion 32 connected to each other, so that the first channel sub-portion 31 is located between the epitaxial layer 2 and the second channel sub-portion 32, and adjusts the arrangement between the gate semiconductor layer 4 and the channel portion 3 so that the gate semiconductor layer 4 surrounds the first channel sub-portion 31, and the second channel sub-portion 32 can be used to separate the gate semiconductor layer 4 and the second channel sub-portion 32. That is, by adjusting the structure included in the semiconductor device 100 itself, the distance between the gate semiconductor layer 4 and the second channel sub-portion 32 is increased. The adjustment of this structure is relatively clever, and can effectively improve the breakdown voltage between the gate 6 and the source 7 on the basis of avoiding the addition of additional structures, thereby enhancing the reliability of the semiconductor device 100.

[0077] Moreover, this can also make the semiconductor device 100 more suitable for high-voltage normally-on JFETs and cascode devices commonly used in high-voltage normally-on JFETs, and help reduce or even prevent the semiconductor device 100 from being damaged by transient gate voltage spikes when used in cascode devices.

[0078] In some embodiments, along the thickness direction of the substrate 1, the spacing between the source contact layer 5 and the gate semiconductor layer 4 is, for example, the same as the thickness of the second channel sub-portion 32. Accordingly, by adjusting the thickness of the second channel sub-portion 32, the breakdown voltage range between the gate 6 and the source 7 of the semiconductor device 100 can be adjusted, so that there is a more appropriate breakdown voltage between the gate 6 and the source 7. Here, the thickness of the second channel sub-portion 32 can be selected and set according to actual design requirements.

[0079] In some embodiments, Figure 3 and Figure 6 As shown, the orthographic projection of one end of the first channel sub-portion 31 in contact with the second channel sub-portion 32 on the substrate 1 is located within the orthographic projection range of one end of the second channel sub-portion 32 in contact with the first channel sub-portion 31 on the substrate 1. Accordingly, the orthographic projection area of ​​one end of the first channel sub-portion 31 in contact with the second channel sub-portion 32 on the substrate 1 is smaller than the orthographic projection area of ​​one end of the second channel sub-portion 32 in contact with the first channel sub-portion 31 on the substrate 1.

[0080] It can be understood that the semiconductor device 100 has a first direction, which is perpendicular to the thickness direction of the substrate 1. Accordingly, the first direction can be any direction parallel to the contact surface between the substrate 1 and the epitaxial layer 2. Figure 3 and Figure 6 As shown, along the first direction, one end of the first channel sub-portion 31 that contacts the second channel sub-portion 32 is retracted relative to one end of the second channel sub-portion 32 that contacts the first channel sub-portion 31 .

[0081] For example, Figure 6 As shown, along the first direction, the size of one end of the first channel sub-portion 31 in contact with the second channel sub-portion 32 is D1, and the size of one end of the second channel sub-portion 32 in contact with the first channel sub-portion 31 is D2, wherein D1<D2. The edge of one end of the second channel sub-portion 32 in contact with the first channel sub-portion 31 exceeds one end of the first channel sub-portion 31 in contact with the second channel sub-portion 32. One end of the second channel sub-portion 32 in contact with the first channel sub-portion 31 and one end of the first channel sub-portion 31 in contact with the second channel sub-portion 32 form a T-shaped structure.

[0082] In this way, the end of the gate semiconductor layer 4 away from the substrate 1 can be located below the surface of the second channel sub-portion 32 on the side close to the substrate 1, and in contact with the surface of the second channel sub-portion 32 on the side close to the substrate 1, ensuring that the second channel sub-portion 32 can cover the end of the gate semiconductor layer 4 away from the substrate 1, thereby ensuring that the second channel sub-portion 32 has a better spacing effect on the gate semiconductor layer 4 and the source contact layer 5, and effectively ensuring a higher breakdown voltage between the gate 6 and the source 7.

[0083] In some examples, such as Figure 3 and Figure 6 As shown, the first channel sub-portion 31 includes a first portion 311 and a second portion 312 connected to each other, for example, the first portion 311 and the second portion 312 are in an integral structure. The first portion 311 is located between the epitaxial layer 2 and the second portion 312. The second portion 312 is in contact with the second channel sub-portion 32. Accordingly, the orthographic projection of the second portion 312 on the substrate 1 is located within the orthographic projection range of the second channel sub-portion 32 on the substrate 1. Along the first direction, the second portion 312 is inwardly set relative to the end of the second channel sub-portion 32 in contact with the first channel sub-portion 31.

[0084] Furthermore, the orthographic projection of the second portion 312 on the substrate 1 is located within the orthographic projection range of the first portion 311 on the substrate 1. Along the first direction, the second portion 312 is set back relative to the first portion 311. For example, Figure 6 As shown, along the first direction, the size of the second portion 312 is D1, and the size of the first portion 311 is D3, wherein D1<D3. The edge of the first portion 311 exceeds the second portion 312. The first channel sub-portion 31 is in a step shape as a whole, and the channel portion 3 is in an "I" shape as a whole.

[0085] It is understandable that, in the process of turning off the JFET, the narrower position in the channel will be pinched off first. Accordingly, in the process of turning off the semiconductor device 100, the first channel sub-portion 31 in the channel portion 3 will be pinched off first, and further, the second portion 312 in the first channel sub-portion 31 will be pinched off first. The second portion 312 is relatively small in the first direction, which is easy to increase the channel resistance of the semiconductor device 100.

[0086] By dividing the first channel sub-portion 31 into two parts, and making the size of the first part 311 away from the first channel sub-portion 31 in the first direction larger than the size of the second part 312 in the first direction, the second part 312 can be used to reduce the channel resistance of the semiconductor device 100, thereby avoiding affecting or even improving the conduction characteristics of the semiconductor device 100.

[0087] Exemplarily, the distance between the orthographic projection boundary of the second portion 312 on the substrate 1 and the orthographic projection boundary of the first portion 311 on the substrate 1 is in the range of 0.1 μm-1 μm. That is, along the first direction, the minimum distance between the sidewall of the second portion 312 and the sidewall of the first portion 311 is in the range of 0.1 μm-1 μm; the difference between the dimension D3 of the first portion 311 and the dimension D1 of the second portion 312 is in the range of 0.2 μm-2 μm.

[0088] Optionally, the distance between the orthographic projection boundary of the second portion 312 on the substrate 1 and the orthographic projection boundary of the first portion 311 on the substrate 1 may be 0.1 μm, 0.2 μm, 0.4 μm, 0.6 μm, 0.8 μm or 1 μm, etc.

[0089] By adopting the above-mentioned size range, on the one hand, the difficulty of preparing the first part 311, the second part 312 and the gate semiconductor layer 4 can be reduced, and the gate parasitic resistance can be reduced; on the other hand, it can avoid the situation where the drain 8 cannot pinch off the first channel sub-portion 31 in the channel portion 3 under high pressure, thereby avoiding reducing the voltage resistance between the source 7 and the drain 8.

[0090] In some examples, such as Figure 3 and Figure 6 As shown, the orthographic projection of the second channel sub-portion 32 on the substrate 1 coincides with the orthographic projection of the first portion 311 of the first channel sub-portion 31 on the substrate 1. Accordingly, along the first direction, the size D2 of the second channel sub-portion 32 is equal to the size D3 of the first portion 311 of the first channel sub-portion 31. The orthographic projection area of ​​the second channel sub-portion 32 on the substrate 1 is equal to the orthographic projection area of ​​the first portion 311 of the first channel sub-portion 31 on the substrate 1.

[0091] This is beneficial to reducing the area occupied by the orthographic projection of the channel portion 3 on the substrate 1 , reducing the area occupied by the JFET in the semiconductor device 100 , and improving the integration of the semiconductor device 100 .

[0092] In some embodiments, Figure 7 As shown, in the semiconductor device 100, there are a plurality of channel portions 3 and a plurality of source contact layers 5, and the plurality of channel portions 3 and the plurality of source contact layers 5 are arranged one by one in correspondence, and a second channel sub-portion 32 of each channel portion 3 is provided with a source contact layer 5 on a side away from the substrate 1, for example. The plurality of channel portions 3 may be arranged at intervals along the first direction. Each channel portion 3, for example, corresponds to a JFET.

[0093] For example, see Figure 7 The gate semiconductor layer 4 surrounds the first channel sub-portion 31 of the plurality of channel portions 3, and at least two source contact layers 5 are electrically connected. Accordingly, the gates of the plurality of JFETs are electrically connected together, and the sources of at least two JFETs are electrically connected together, so that at least two JFETs can constitute a common-source and common-gate configuration device.

[0094] Here, at least two source contact layers 5 are electrically connected in various ways. Figure 7, the source electrodes 7 located on the side of the at least two source contact layers 5 away from the substrate 1 are connected, that is, the at least two source contact layers 5 are electrically connected together through the source electrodes 7. For example, the source electrodes 7 on the side of the at least two source contact layers 5 away from the substrate 1 are in an integrated structure.

[0095] It is understandable that the semiconductor device 100 may further include other structures, which are schematically described below with reference to the accompanying drawings.

[0096] In some embodiments, Figure 6 and Figure 7 As shown, the semiconductor device 100 may further include: a current diffusion layer 9. The current diffusion layer 9 is located between the epitaxial layer 2 and the first channel sub-portion 31, and is in contact with the first channel sub-portion 31. The orthographic projection of the first channel sub-portion 31 on the substrate 1 is located within the orthographic projection range of the current diffusion layer 9 on the substrate 1. Accordingly, along the first direction, the edge of the current diffusion layer 9 exceeds the first channel sub-portion 31.

[0097] For example, the orthographic projection area of ​​the first channel sub-portion 31 on the substrate 1 is smaller than the orthographic projection area of ​​the current diffusion layer 9 on the substrate 1. Along the first direction, the size of the first channel sub-portion 31 is smaller than the size of the current diffusion layer 9.

[0098] In this way, the current diffusion layer 9 can be used to further reduce the channel resistance of the semiconductor device 100 , thereby avoiding affecting or even improving the conduction characteristics of the semiconductor device 100 .

[0099] In some examples, the current diffusion layer 9 and the first channel sub-portion 31 are in an integrated structure, that is, the current diffusion layer 9 and the first channel sub-portion 31 are made of the same or substantially the same material, and are continuous and unbroken.

[0100] In this way, during the process of preparing and forming the semiconductor device 100 , the current diffusion layer 9 and the first channel sub-portion 31 can be prepared and formed simultaneously, which is beneficial to simplifying the preparation process of the semiconductor device 100 .

[0101] For example, Figure 6 and Figure 7 As shown, the current diffusion layer 9 may also be located between the gate semiconductor layer 4 and the epitaxial layer 2, and in contact with the surface of the gate semiconductor layer 4 on one side close to the substrate 1. Alternatively, the current diffusion layer 9 may be sunken into the gate semiconductor layer 4, that is, relative to the substrate 1, the surface of the gate semiconductor layer 4 on one side close to the substrate 1 is lower than the surface of the current diffusion layer 9 on one side close to the substrate 1.

[0102] In some embodiments, Figure 7 , Figure 8 and Fig. 9As shown, the semiconductor device 100 may further include: a first ohmic contact layer 10 and a second ohmic contact layer 11 .

[0103] The first ohmic contact layer 10 is located between the source contact layer 5 and the source electrode 7, and is in direct contact with the source contact layer 5 and the source electrode 7, respectively. This is beneficial to reducing the contact resistance between the source contact layer 5 and the source electrode 7, and the provision of the source contact layer 5 can further reduce the contact resistance between the channel portion 3 and the source electrode 7.

[0104] The second ohmic contact layer 11 is located between the gate semiconductor layer 4 and the gate electrode 6, and is in direct contact with the gate semiconductor layer 4 and the gate electrode 6, respectively. This is beneficial to reducing the contact resistance between the gate semiconductor layer 4 and the gate electrode 6.

[0105] In some embodiments, Figure 8 and Fig. 9 As shown, the semiconductor device 100 may further include: a plurality of annular protrusions 12 and a field limiting ring 13. The field limiting ring 13 may also be referred to as a terminal field limiting ring.

[0106] The above-mentioned multiple annular protrusions 12 are located on the side of the epitaxial layer 2 away from the substrate 1, and are arranged in a ring-shaped manner. Exemplarily, the orthographic projection shapes of the multiple annular protrusions 12 on the substrate 1 include but are not limited to circular rings, square rings, etc. The orthographic projection shapes of each annular protrusion 12 on the substrate 1 can be the same or different. For example, along the first direction, the inner diameters of the multiple annular protrusions 12 are different, and at least one annular protrusion 12 surrounds another annular protrusion 12. Optionally, the multiple annular protrusions 12 are concentric and spaced apart.

[0107] The field limiting ring 13 is located on the side of the epitaxial layer 2 away from the substrate 1 and between two adjacent annular protrusions 12. For example, along the first direction, the annular protrusions 12 and the field limiting rings 13 are alternately arranged. The number of the field limiting rings 13 can be one or more.

[0108] Furthermore, the plurality of annular protrusions 12 surround the channel portion 3 and the gate semiconductor layer 4. The channel portion 3 and the gate semiconductor layer 4, as well as the source contact layer 5 and the source electrode 7 located on the side of the channel portion 3 away from the substrate 1, are located in the area surrounded by the plurality of annular protrusions 12.

[0109] The annular protrusion 12 with the smallest inner diameter among the plurality of annular protrusions 12 , for example, contacts the gate semiconductor layer 4 , and separates the gate semiconductor layer 4 from the field limiting ring 13 with the smallest inner diameter.

[0110] By providing the field limiting ring 13 , the problem of electric field concentration at the edge of the semiconductor device 100 can be alleviated or even eliminated, and the breakdown voltage of the semiconductor device 100 can be further improved.

[0111] In some examples, such as Fig. 9 As shown, the gate semiconductor layer 4 includes a first gate layer 41 and a second gate layer 42 connected to each other. The first gate layer 41 surrounds the first channel sub-portion 31. Compared with the substrate 1, the side surface of the second gate layer 42 away from the substrate 1 is lower than the side surface of the first gate layer 41 away from the substrate 1. Accordingly, the cross-sectional figures of the first gate layer 41 and the second gate layer 42 are L-shaped.

[0112] Furthermore, the second gate layer 42 and the field limiting ring 13 are made of the same material and are disposed in the same layer.

[0113] In this article, "same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0114] In this way, the second gate layer 42 and the field limiting ring 13 can be simultaneously formed in the same manufacturing process, which can avoid adding process steps due to the provision of the field limiting ring 13 , and is conducive to simplifying the manufacturing process of the semiconductor device 100 .

[0115] In some examples, such as Fig. 9 As shown, the annular protrusion 12 includes a first annular sub-protrusion 121 and a second annular sub-protrusion 122 connected to each other, and the first annular sub-protrusion 121 is located between the epitaxial layer 2 and the second annular sub-protrusion 122. The first annular sub-protrusion 121 and the first channel sub-portion 31 are arranged in the same layer, and the second annular sub-protrusion 122 and the second channel sub-portion 32 are made of the same material and are arranged in the same layer.

[0116] In this way, the first annular sub-protrusion 121 and the first channel sub-portion 31 can be simultaneously formed in the same preparation process, and the second annular sub-protrusion 122 and the second channel sub-portion 32 can be simultaneously formed in the same preparation process. This can avoid adding process steps due to the setting of the annular protrusion 12, which is beneficial to simplifying the preparation process of the semiconductor device 100.

[0117] Some embodiments of the present application also provide a method for preparing a semiconductor device, which is used, for example, to prepare the semiconductor device 100 in some of the above embodiments. Fig.10 A flow chart of a method for preparing a semiconductor device is shown; Figure 11a-11l and Figure 12a-Figure 12c The structure diagrams corresponding to each step in a method for preparing a semiconductor device are shown respectively. It should be understood that Fig.10 The steps shown are not exclusive and can also be Fig.10Other steps may be performed before, after or between any of the steps shown. In addition, some of the steps may be performed simultaneously, or may be performed in different order. Fig.10 Executed in the order shown.

[0118] The following is a schematic illustration of a method for preparing a semiconductor device in conjunction with the accompanying drawings. Fig.10 As shown, the preparation method includes: S100-S300.

[0119] S100 , providing a substrate.

[0120] Regarding the substrate, please refer to the relevant description above and will not be repeated here.

[0121] S200, combined Figure 11a-Figure 11i , an epitaxial layer 2, a channel portion 3, a gate semiconductor layer 4 and a source contact layer 5 are formed on one side of the substrate 1. The channel portion 3 is located on the side of the epitaxial layer 2 away from the substrate 1. The channel portion 3 includes a first channel sub-portion 31 and a second channel sub-portion 32 connected to each other, and the first channel sub-portion 31 is located between the epitaxial layer 2 and the second channel sub-portion 32. The gate semiconductor layer 4 is located on the side of the epitaxial layer 2 away from the substrate 1 and surrounds the first channel sub-portion 31. The source contact layer 5 is located on the side of the second channel sub-portion 32 away from the substrate 1, and the second channel sub-portion 32 separates the source contact layer 5 and the gate semiconductor layer 4.

[0122] Illustratively, the embodiments of the present disclosure may adopt an epitaxial process, an ion implantation process, an etching process, etc. to prepare and form the epitaxial layer 2 , the channel portion 3 , the gate semiconductor layer 4 and the source contact layer 5 .

[0123] S300, such as Figure 11l As shown, a drain 8 is formed on a side of the substrate 1 away from the epitaxial layer 2 .

[0124] For example, the embodiment of the present disclosure may use a deposition process to deposit a conductive material on the side of the substrate 1 away from the epitaxial layer 2 to form a drain 8, and then use a high temperature annealing process to process the drain 8 so that the drain 8 forms an ohmic contact with the substrate 1. Optionally, the material of the drain 8 includes but is not limited to metal materials such as nickel, aluminum, titanium, tungsten, and alloy materials thereof. Along the thickness direction of the substrate 1, the thickness of the drain 8 ranges from 0.02 μm to 2 μm, for example.

[0125] In the method for preparing a semiconductor device provided by some embodiments of the present disclosure, during the process of preparing and forming an epitaxial layer 2, a channel portion 3, a gate semiconductor layer 4 and a source contact layer 5, the preparation processes of the four can be adjusted, so that the prepared channel portion 3 includes a first channel sub-portion 31 and a second channel sub-portion 32 that are connected to each other, and the first channel sub-portion 31 is located between the epitaxial layer 2 and the second channel sub-portion 32, and the gate semiconductor layer 4 surrounds the first channel sub-portion 31. In this way, the second channel sub-portion 32 can be used to separate the gate semiconductor layer 4 and the second channel sub-portion 32, thereby increasing the distance between the gate semiconductor layer 4 and the second channel sub-portion 32, thereby effectively improving the breakdown voltage between the gate 6 and the source 7 without adding additional structures, thereby enhancing the reliability of the prepared semiconductor device 100.

[0126] In some embodiments, in the above S200 , an epitaxial layer 2 , a channel portion 3 , a gate semiconductor layer 4 and a source contact layer 5 are formed on one side of the substrate 1 , including: S210 - S250 .

[0127] S210, such as Fig.11a As shown, an epitaxial thin film 2a is formed on one side of a substrate 1.

[0128] For example, the embodiment of the present disclosure may adopt an epitaxial process to grow an epitaxial film 2a. The thickness of the epitaxial film 2a may range from 1 μm to 100 μm. The epitaxial film 2a may be treated with N-type light doping, and the doping concentration may range from 1×10 14 cm -3 to 1×10 17 cm -3 .

[0129] The material of the epitaxial film 2a includes wide bandgap semiconductor materials, which include but are not limited to silicon carbide, gallium nitride, diamond and the like.

[0130] S220, such as Fig.11b As shown, a first ion implantation is performed from a side of the epitaxial film 2a away from the substrate 1 to form a first doping region A1.

[0131] For example, Fig.11b As shown, before the first ion implantation, a mask film can be formed on the side of the epitaxial film 2a away from the substrate 1, and then the mask film can be etched by photolithography to obtain a second mask layer M2, wherein the second mask layer M2 has a plurality of openings arranged at intervals, each of which exposes a portion of the epitaxial film 2a. The position of each opening corresponds to the position of the channel portion to be formed. Then, based on the second mask layer M2, the first ion implantation can be performed on the epitaxial film 2a to form a plurality of first doping regions A1. Afterwards, the second mask layer M2 can be removed.

[0132] For example, the implanted ions are N-type ions, including but not limited to nitrogen ions, phosphorus ions, etc. The depth range of the first doping region A1 is, for example, 0.1 μm-4 μm, and the doping concentration range of the first doping region A1 is, for example, 1×10 14 cm -3 -1×10 20 cm -3 .

[0135] S230, such as Fig.11c As shown, a first mask pattern 14 is formed on a side of the epitaxial film 2a away from the substrate 1, and the first mask pattern 14 covers a portion of the first doping region A1 and exposes another portion of the first doping region A1.

[0136] Exemplarily, dielectric materials such as silicon oxide (SiO2) and silicon nitride (SiNx) or photoresists can be used to form a mask film on the side of the epitaxial film 2a away from the substrate 1, and then the mask film is etched using a photolithography process to obtain a first mask layer M1. The first mask layer M1 includes a plurality of first mask patterns 14 spaced apart, and each first mask pattern 14 is in a block shape.

[0137] The first mask patterns 14 and the first doping regions A1 are arranged in a one-to-one correspondence, and each first mask pattern 14 covers a portion of the corresponding first doping region A1 and exposes another portion of the first doping region A1. The exposed portion of the first doping region A1 is, for example, ring-shaped.

[0138] S240, such as Fig.11c As shown, based on the first mask pattern 14, a second ion implantation is performed from the side of the epitaxial film 2a away from the substrate 1 to form a second doping region A2. The portion of the first doping region A1 opposite to the second doping region A2 constitutes the second portion of the first channel sub-portion 31, and the second doping region A2 is used to form a gate semiconductor layer.

[0139] Exemplarily, the second doping region A2 surrounds each first doping region A1. For example, the ions implanted in the second doping region A2 are P-type ions, including but not limited to aluminum ions, boron ions, etc. Accordingly, the second doping region A2 can also be called a P-type region. The depth range of the second doping region A2 is, for example, 0.1 μm-4 μm, and the doping concentration range of the second doping region A2 is, for example, 1×10 16 cm -3 -1×10 20 cm -3Along the first direction, a size range of a portion of the first doping region A1 opposite to the second doping region A2 (ie, the second portion of the first channel sub-portion 31 ) is, for example, 0.5 μm-5 μm.

[0140] The second ion implantation is, for example, vertical ion implantation, and the ion implantation direction is parallel or substantially parallel to the thickness direction of the substrate 1 .

[0141] Here, after forming the second doping region A2, the first mask layer M1 may be removed, and the surface of the epitaxial film 2a that is away from the substrate 1 may be cleaned.

[0142] S250, such as Fig.11e As shown, a second channel sub-portion 32 and a source contact layer 5 are formed on the side of the epitaxial film 2a away from the substrate 1. The second channel sub-portion 32 covers the first doping region A1 and a portion of the second doping region A2.

[0143] Exemplary, combined Fig.11d and Fig.11e The method for forming the second channel sub-portion 32 and the source contact layer 5 includes: using an epitaxial process to grow a channel film 32a on the side of the epitaxial film 2a away from the substrate 1, and then, epitaxially growing or ion implanting the side of the channel film 32a away from the substrate 1 to form a source contact film 5a; then, using a photolithography process to form a third mask layer M3 on the side of the source contact film 5a away from the substrate 1, the third mask layer M3 includes a plurality of second mask patterns in a block shape, and the plurality of second mask patterns and the plurality of first doping regions A1 are arranged one-to-one, and each second mask pattern covers the first doping region A1 and a portion of the second doping region A2; then, based on the third mask layer M3, a dry etching process can be used to etch the source contact film 5a and the channel film 3a to obtain a plurality of second channel sub-portions 32 and a plurality of source contact layers 5.

[0144] For example, the thickness of the channel film 32a is in the range of 0.2 μm to 2 μm. The channel film 32a is, for example, N-type doped, and the doping concentration thereof is, for example, in the range of 1×10 16 cm -3 -1×10 20 cm -3 The thickness of the source contact film 5a is, for example, in the range of 0.1 μm-0.5 μm. The source contact film 5a is, for example, heavily N-type doped, and the doping concentration thereof is, for example, in the range of 1×10 17 cm -3 -1×10 20 cm -3 Along the first direction, the size of the second channel sub-portion 32 is smaller than or equal to the size of a portion of the first doping region A1 that is not opposite to the second doping region A2.

[0145] It can be understood that the second channel sub-portion 32 and the source contact layer 5 are formed by etching in the same patterning process and are prepared by a preparation process independent of the first channel sub-portion 31. The second channel sub-portion 32 can be used to isolate the source contact layer 5 and the second doping area A2, and correspondingly, the source contact layer 5 and the gate semiconductor layer to be formed are isolated. The process is relatively simple and can effectively increase the breakdown voltage between the source and the gate of the semiconductor device.

[0146] Furthermore, in the above S200 , the epitaxial layer 2 , the channel portion 3 , the gate semiconductor layer 4 and the source contact layer 5 are formed on one side of the substrate 1 , and the following steps may be further included: S260 - S270 .

[0147] S260, such as Fig.11e As shown, based on the second channel sub-portion 32 and the source contact layer 5 , the second doping region A2 is etched and thinned.

[0148] Specifically, based on the third mask layer M3 located on the side of the second channel sub-portion 32 and the source contact layer 5 away from the substrate 1 , the second doping region A2 is etched and thinned.

[0149] Optionally, the etching of the source contact film 5a and the channel film 32a, and the etching of the second doping region A2 can be performed in the same etching process. Here, the etching depth ranges from 0.3 μm to 4.5 μm, for example.

[0150] S270, such as Fig.11f As shown, based on the second channel sub-portion 32 and the source contact layer 5 , a third ion implantation is performed from the side of the epitaxial film 2 a away from the substrate 1 to form a third doping region A3 , which is connected to the second doping region A2 to form a gate semiconductor layer 4 .

[0151] Specifically, the third ion implantation is performed based on the third mask layer M3 located on the side of the second channel sub-portion 32 and the source contact layer 5 away from the substrate 1. For example, the implanted ions are P-type ions, the depth range of the third doping region A3 is, for example, 0.1 μm-2 μm, and the doping concentration range of the third doping region A3 is, for example, 1×10 16 cm -3 -1×10 20 cm -3 Afterwards, the third mask layer M3 may be removed.

[0152] The portion of the first doping region A1 opposite to the third doping region A3 constitutes the first portion 311 of the first channel sub-portion 31. Fig.11f As shown, by controlling the depth of the third doping region A3, the bottom of the first doping region A1 can form a current diffusion layer 9.

[0153] Here, along the first direction, the distance between the edge of the third doping region A3 and the edge of the second doping region A2 is, for example, in the range of 0.1 μm-1 μm. In this way, on the one hand, it is possible to avoid the second doping region A2 being removed too much and making it difficult to control the overlay accuracy of the process, and to avoid increasing the gate parasitic resistance; on the other hand, it is possible to avoid the sidewall of the third doping region A3 being too large in the first direction, resulting in the failure to pinch off the first channel sub-portion 31 under the drain high voltage, thereby reducing the withstand voltage between the source and the drain of the semiconductor device.

[0154] It can be understood that in the channel portion 3, the second portion 312 has the smallest size in the first direction, and accordingly, the second ion implantation in S240 controls the threshold voltage of the channel portion 3. The third ion implantation in S270 and the formation of the second channel sub-portion 32 in S250 are not related to the size of the second portion 312 in the first direction and will not affect the size of the second portion 312 in the first direction.

[0155] exist Figure 2 In the semiconductor device shown, the material of the channel portion 3 includes a wide bandgap semiconductor material, and a dry etching process is usually required to etch the wide bandgap semiconductor material to form a groove, thereby obtaining the channel portion 3. However, etching a wide bandgap semiconductor material is relatively difficult, and a hard mask and a high-power etching device are required. It is difficult to accurately control the size of the etched channel portion 3 in the first direction, which results in poor uniformity of the size of different etched channel portions 3 in the first direction. The channel portion 3 has a relatively high carrier concentration, so the change in the size of the channel portion 3 etched in the first direction during the preparation process will lead to a huge change in the threshold voltage and withstand voltage capability of the final semiconductor device.

[0156] In the embodiment of the present disclosure, the threshold voltage of the semiconductor device is determined by the second part 312 of the channel portion 3. In the process of forming the second part 312, the first mask layer M1 used can also be called an ion implantation mask. The material of the ion implantation mask is usually easier to etch, and accordingly, the etching size is easy to control and the process uniformity is high. Accordingly, the dimensional accuracy of the first mask pattern 14 is high, and the dimensional accuracy of the prepared second part 312 is high. This avoids the adverse effects of directly etching the channel portion on the threshold voltage and the breakdown voltage between the source and the drain.

[0157] In addition, the third doping region A3 is formed by the third ion implantation, which can improve the voltage resistance of the semiconductor device and avoid affecting the threshold voltage of the semiconductor device.

[0158] The embodiments of the present disclosure are respectively Figure 2 and a semiconductor device (e.g. Figure 11l The transfer characteristic curve and off-state breakdown current-voltage curve (as shown in the figure) were simulated.

[0159] from Fig.13a and Fig.13b It can be seen that Figure 2 In the semiconductor device shown, when the size of the channel portion 3 in the first direction changes from 1.2μm to 1.6μm, the threshold voltage drifts greatly; while in the semiconductor device shown in the embodiment of the present disclosure, when the size of the second part 312 of the first channel sub-portion 31 in the first direction changes from 1.2μm to 1.6μm, the threshold voltage is stable and basically stable at around -9V.

[0160] from Fig.14a and Fig.14b It can be seen that Figure 2 In the semiconductor device shown, when the size of the channel portion 3 in the first direction changes from 1.2μm to 1.6μm, the off-state drain breakdown voltage is greatly degraded, and breakdown occurs before the rated voltage; while in the semiconductor device shown in the embodiment of the present disclosure, when the size of the second part 312 of the first channel sub-portion 31 in the first direction changes from 1.2μm to 1.6μm, the off-state drain breakdown voltage is not degraded.

[0161] That is to say, the preparation method of the channel portion 3 in the semiconductor device provided in the embodiment of the present disclosure can achieve the decoupling between the size of the second part 312 of the first channel sub-portion 31 in the first direction and the threshold voltage and the off-state drain breakdown voltage, and effectively improves the problems of threshold voltage drift and off-state drain breakdown voltage degradation caused by the change of the size of the second part 312 of the first channel sub-portion 31 in the first direction.

[0162] In some embodiments, before the above S300, the above preparation method also includes: S281-S283.

[0163] S281, such as Fig.11i As shown, a first ohmic contact layer 10 is formed on a side of the source contact layer 5 away from the substrate 1 , and a second ohmic contact layer 11 is formed on a side of the gate semiconductor layer 4 away from the substrate 1 .

[0164] For example, Figure 11g As shown, before forming the first ohmic contact layer 10 and the second ohmic contact layer 11, a dielectric material may be deposited on the side of the gate semiconductor layer 4 and the source contact layer 5 away from the substrate 1 to form a dielectric film 15a, and the dielectric film 15a also covers the sidewalls of the gate semiconductor layer 4, the sidewalls of the second channel sub-portion 32 and the sidewalls of the source contact layer 5; then, in combination with Figure 11g and Fig.11hFor example, an anisotropic dry etching process is used to etch the dielectric film 15a, and the portion of the dielectric film 15a located on the side of the gate semiconductor layer 4 and the source contact layer 5 away from the substrate 1 is removed, and the portion of the dielectric film 15a covering the sidewall of the gate semiconductor layer 4, the sidewall of the second channel sub-portion 32, and the sidewall of the source contact layer 5 is retained to form the sidewall 15. Then, as Fig.11i As shown, an ohmic metal material is deposited on the side of the gate semiconductor layer 4 and the source contact layer 5 away from the substrate 1 , and annealed by a high temperature annealing process to obtain a first ohmic contact layer 10 and a second ohmic contact layer 11 .

[0165] Optionally, the thickness of the dielectric film 15a may be in the range of 0.02 μm-2 μm, and the material of the dielectric film 15a includes but is not limited to dielectric materials such as silicon oxide and silicon nitride. The thickness of the first ohmic contact layer 10 and the second ohmic contact layer 11 are, for example, the same, and the thickness range is, for example, 0.02 μm-0.2 μm. The material of the first ohmic contact layer 10 and the second ohmic contact layer 11 is the same, for example, including but not limited to metal materials such as nickel, aluminum, titanium, tungsten and their alloy materials.

[0166] The first ohmic contact layer 10 and the second ohmic contact layer 11 are simultaneously prepared and formed in the same preparation process, which is beneficial to simplifying the preparation process of the semiconductor device.

[0167] S282, such as Fig.11j As shown, a dielectric layer 16 covering the first ohmic contact layer 10 and the second ohmic contact layer 11 is formed.

[0168] For example, a deposition process may be used to deposit dielectric material on the side of the first ohmic contact layer 10 and the second ohmic contact layer 11 away from the substrate 1 to form the dielectric layer 16 . The dielectric layer 16 also covers the sidewall spacer 15 .

[0169] S283, such as Figure 11k As shown, a source electrode 7 and a gate electrode 6 are formed. The source electrode 7 penetrates the dielectric layer 16 to the first ohmic contact layer 10 , and the gate electrode 6 penetrates the dielectric layer 16 to the second ohmic contact layer 11 .

[0170] Exemplarily, before forming the source 7 and the gate 6, a first via hole and a second via hole may be formed in the dielectric layer 16; the first via hole penetrates the dielectric layer 16 and exposes the first ohmic contact layer 10; the second via hole penetrates the dielectric layer 16 and exposes the second ohmic contact layer 11; then, a conductive material is deposited on the first via hole, the second via hole and the side of the dielectric layer 16 away from the substrate 1 to obtain the source 7 and the gate 6, the source 7 contacts the first ohmic contact layer 10 through the first via hole, and the gate 6 contacts the second ohmic contact layer 11 through the second via hole. There is a certain distance between the source 7 and the gate 6 to avoid leakage between the source 7 and the gate 6.

[0171] Regarding the materials of the source electrode 7 and the gate electrode 6 , please refer to the relevant description above and will not be repeated here.

[0172] In some embodiments, Figure 12a-Figure 12c As shown, the epitaxial film 2a has a termination region B1 and an active region B2. The termination region B1 is, for example, annular and surrounds the active region B2. The channel portion 3 and the gate semiconductor layer 4 are located in the active region B2. Furthermore, the source contact layer 5, the source electrode 7 on the side of the channel portion 3 away from the substrate 1, and the gate electrode 6 on the side of the gate semiconductor layer 4 away from the substrate 1 are also located in the active region B2.

[0173] In some examples, such as Fig.12a As shown, in the above S250, in the process of forming the second channel sub-portion 32 and the source contact layer 5 on the side of the epitaxial film 2a away from the substrate 1, a second annular sub-protrusion 122 is also formed on the side of the epitaxial film 2a away from the substrate 1, and the second annular sub-protrusion 122 is located in the termination area B1.

[0174] Specifically, the channel film 3a and the source contact film 5a are not only located in the active area B2, but also in the termination area B1; part of the second mask pattern in the third mask layer M3 is also located in the termination area B1, and part of the second mask pattern located in the termination area B1 is annular. In the process of etching the source contact film 5a and the part of the channel film 3a located in the active area B2 based on the third mask layer M3, the part of the source contact film 5a and the channel film 3a located in the termination area B1 is also etched to obtain the second annular sub-protrusion 122.

[0175] like Figure 12b As shown, in the above S260, based on the second channel sub-portion 32 and the source contact layer 5, during the etching and thinning of the second doping region A2, the portion of the epitaxial film 2a located in the termination region B1 is also thinned based on the second channel sub-portion 32 and the source contact layer 5.

[0176] Specifically, based on a portion of the second mask pattern in the third mask layer M3 located in the termination region B1 , the epitaxial thin film 2 a is etched and thinned.

[0177] like Fig.12c As shown, in the above S270, in the process of forming the third doping area A3, based on the second annular sub-protrusion 122, a third ion implantation is performed on the portion of the epitaxial film 2a located in the termination area B1 to form a field limiting ring 13; the portion located between the second annular sub-protrusion 122 and the substrate 1 and in contact with the field limiting ring 13 constitutes the first annular sub-protrusion 121. The first annular sub-protrusion 121 and the second annular sub-protrusion 122 constitute the annular protrusion 12.

[0178] Specifically, based on the portion of the second mask pattern located in the termination area B1 in the third mask layer M3, the epitaxial film 2a is subjected to a third ion implantation. Afterwards, in the process of removing the third mask layer M3, for example, a portion of the source contact film on the side of the second annular sub-protrusion 122 away from the substrate 1 is also removed. The subsequently formed dielectric layer 16 also covers the annular protrusion 12 and the field limiting ring 13.

[0179] By simultaneously forming the annular protrusion 12 and the field limiting ring 13 during the process of forming the second channel sub-portion 32 , the source contact layer 5 and the gate semiconductor layer 4 , it is beneficial to simplify the manufacturing process of the semiconductor device.

[0180] Of course, the annular protrusion 12 and the field limiting ring 13 may also be independently prepared and formed in the preparation process of the second channel sub-portion 32 , the source contact layer 5 and the gate semiconductor layer 4 , and the embodiment of the present disclosure is not limited to this.

[0181] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: substrate; an epitaxial layer, located on one side of the substrate; A channel portion, located at a side of the epitaxial layer away from the substrate; the channel portion includes a first channel sub-portion and a second channel sub-portion connected to each other, the first channel sub-portion being located between the epitaxial layer and the second channel sub-portion; a gate semiconductor layer, located on a side of the epitaxial layer away from the substrate and surrounding the first channel sub-portion; a source contact layer, located at a side of the second channel sub-portion away from the substrate; the second channel sub-portion separates the source contact layer and the gate semiconductor layer; The drain is located at a side of the substrate away from the epitaxial layer.

2. The semiconductor device according to claim 1, wherein: An orthographic projection of one end of the first channel sub-portion in contact with the second channel sub-portion on the substrate is located within the orthographic projection range of one end of the second channel sub-portion in contact with the first channel sub-portion on the substrate.

3. The semiconductor device according to claim 2, characterized in that The first channel sub-portion includes a first portion and a second portion connected to each other, the first portion being located between the epitaxial layer and the second portion; The orthographic projection of the second portion on the substrate is located within the orthographic projection range of the first portion on the substrate.

4. The semiconductor device according to claim 3, characterized in that The distance between the orthographic projection boundary of the second part on the substrate and the orthographic projection boundary of the first part on the substrate is in the range of 0.1 μm-1 μm.

5. The semiconductor device according to claim 3, characterized in that An orthographic projection of the second channel sub-portion on the substrate coincides with an orthographic projection of the first portion on the substrate.

6. The semiconductor device according to claim 1, wherein: The semiconductor device further includes: a current diffusion layer, the current diffusion layer being located between the epitaxial layer and the first channel sub-portion and in contact with the first channel sub-portion; The orthographic projection of the first channel sub-portion on the substrate is located within the orthographic projection range of the current diffusion layer on the substrate.

7. The semiconductor device according to claim 6, characterized in that The current diffusion layer and the first channel sub-portion are in an integrated structure.

8. The semiconductor device according to claim 1, wherein: There are multiple channel parts, and the gate semiconductor layer surrounds the first channel sub-parts of the multiple channel parts; The source contact layer is disposed on a side of the second channel sub-portion of each channel portion away from the substrate, and at least two source contact layers are electrically connected.

9. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: A source electrode, located at a side of the source contact layer away from the substrate; A first ohmic contact layer, located between the source contact layer and the source electrode; A gate electrode, located at a side of the gate semiconductor layer away from the substrate; The second ohmic contact layer is located between the gate semiconductor layer and the gate electrode.

10. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: A plurality of annular protrusions are located on a side of the epitaxial layer away from the substrate and are arranged in a ring-shaped manner in sequence; the plurality of annular protrusions surround the channel portion and the gate semiconductor layer; The field limiting ring is located on a side of the epitaxial layer away from the substrate and between two adjacent annular protrusions.

11. The semiconductor device according to claim 10, characterized in that The gate semiconductor layer comprises a first gate layer and a second gate layer connected to each other; the first gate layer surrounds the first channel sub-portion, and compared with the substrate, a side surface of the second gate layer away from the substrate is lower than a side surface of the first gate layer away from the substrate; The second gate layer and the field limiting ring are made of the same material and are disposed in the same layer.

12. The semiconductor device according to claim 10, characterized in that The annular protrusion includes a first annular sub-protrusion and a second annular sub-protrusion connected to each other, and the first annular sub-protrusion is located between the epitaxial layer and the second annular sub-protrusion; The first annular sub-protrusion and the first channel sub-portion are arranged in the same layer; The second annular sub-protrusion and the second channel sub-portion are made of the same material and are disposed in the same layer.

13. A method for preparing a semiconductor device, characterized in that: The preparation method comprises: providing a substrate; An epitaxial layer, a channel portion, a gate semiconductor layer and a source contact layer are formed on one side of the substrate; the channel portion is located on a side of the epitaxial layer away from the substrate; the channel portion includes a first channel sub-portion and a second channel sub-portion connected to each other, the first channel sub-portion is located between the epitaxial layer and the second channel sub-portion; the gate semiconductor layer is located on a side of the epitaxial layer away from the substrate and surrounds the first channel sub-portion; the source contact layer is located on a side of the second channel sub-portion away from the substrate; the second channel sub-portion separates the source contact layer and the gate semiconductor layer; A drain is formed on a side of the substrate away from the epitaxial layer.

14. The preparation method according to claim 13, characterized in that: The step of forming an epitaxial layer, a channel portion, a gate semiconductor layer and a source contact layer on one side of the substrate comprises: forming an epitaxial thin film on one side of the substrate; Performing a first ion implantation from a side of the epitaxial film away from the substrate to form a first doped region; forming a first mask pattern on a side of the epitaxial film away from the substrate, wherein the first mask pattern covers a portion of the first doped region and exposes another portion of the first doped region; Based on the first mask pattern, a second ion implantation is performed from a side of the epitaxial thin film away from the substrate to form a second doping region; a portion of the first doping region opposite to the second doping region constitutes a second portion of the first channel sub-portion, and the second doping region is used to constitute the gate semiconductor layer; The second channel sub-portion and the source contact layer are formed on a side of the epitaxial thin film away from the substrate; the second channel sub-portion covers the first doped region and a part of the second doped region.

15. The preparation method according to claim 14, characterized in that: The method of forming an epitaxial layer, a channel portion, a gate semiconductor layer and a source contact layer on one side of the substrate further includes: Based on the second channel sub-portion and the source contact layer, etching and thinning the second doped region; Based on the second channel sub-portion and the source contact layer, a third ion implantation is performed from a side of the epitaxial film away from the substrate to form a third doped region, and the third doped region is connected to the second doped region to constitute the gate semiconductor layer.

16. The preparation method according to claim 15, characterized in that: The epitaxial film has a termination region and an active region, wherein the termination region surrounds the active region; the channel portion and the gate semiconductor layer are located in the active region; In the process of forming the second channel sub-portion and the source contact layer on the side of the epitaxial film away from the substrate, a second annular sub-protrusion is also formed on the side of the epitaxial film away from the substrate; the second annular sub-protrusion is located in the termination area; In the process of etching and thinning the second doped region based on the second channel sub-portion and the source contact layer, thinning a portion of the epitaxial thin film located in the termination region based on the second channel sub-portion and the source contact layer; In the process of forming the third doped region, the third ion implantation is also performed on the portion of the epitaxial film located in the termination region based on the second annular sub-protrusion to form a field limiting ring; the portion located between the second annular sub-protrusion and the substrate and in contact with the field limiting ring constitutes the first annular sub-protrusion.

17. The preparation method according to claim 13, characterized in that: Before forming the drain on the side of the substrate away from the epitaxial layer, the preparation method further comprises: forming a first ohmic contact layer on a side of the source contact layer away from the substrate, and forming a second ohmic contact layer on a side of the gate semiconductor layer away from the substrate; forming a dielectric layer covering the first ohmic contact layer and the second ohmic contact layer; A source electrode and a gate electrode are formed; the source electrode penetrates the dielectric layer to the first ohmic contact layer, and the gate electrode penetrates the dielectric layer to the second ohmic contact layer.

18. An electronic device, characterized in that: The electronic device comprises: A semiconductor device, which is a semiconductor device as claimed in any one of claims 1 to 12; A circuit board is electrically connected to the semiconductor device.

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