Semiconductor device and current regulative diode circuit

Abstract

The invention relates to a semiconductor device and a current regulative diode circuit. A semiconductor device includes a drift layer, a plurality of first doped regions, a plurality of second doped regions, a plurality of third doped regions, a doped channel layer, a gate insulating layer, a gate contact and a source contact. The drift layer is arranged on a substrate, and the drift layer is provided with an upper surface. A junction field effect transistor region is defined between the adjacent first doped regions. The second doped region and the first doped region define a plurality of channel regions along the upper surface. The doped channel layer is disposed adjacent to the upper surface and extends across the drift layer between the second doped regions. The gate insulating layer is disposed on the upper surface. The gate contact contacts the gate insulating layer. The source contact contacts the plurality of second doped regions and the plurality of third doped regions.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a constant current diode circuit. Background Art

[0002] A constant current diode (CRD) is a semiconductor constant current element that can maintain a certain current value within a certain operating voltage range. Its output current is between a few milliamperes (mA) and tens of milliamperes. The output current can drive the load and has the advantages of simple circuit structure, good reliability, and small size. In addition, the constant current diode has a constant current with a large working range and a high dynamic resistance, which can enable the circuit structure to obtain a circuit characteristic of constant current, and obtain low power supply variation, low load variation, and low ripple voltage through a single diode. The inflection point voltage of a constant current diode refers to the voltage value at which the current begins to increase rapidly when the diode is forward biased.

[0003] However, the current constant current diode circuit still has problems such as high inflection point voltage, unstable current characteristics at high temperature, small operating current value range and difficulty in adjusting the positive and negative trends of the temperature coefficient. How to improve the above-mentioned shortcomings of the constant current diode circuit is a problem that technicians in this field want to solve. Summary of the invention

[0004] The main purpose of the present invention is to solve the problems of high inflection point voltage of constant current diode, unstable current characteristics at high temperature, small operating current value range and difficulty in adjusting the positive and negative trends of temperature coefficient.

[0005] The present invention discloses a semiconductor device, comprising a drift layer, a plurality of first doped regions, a plurality of second doped regions, a plurality of third doped regions, a doped channel layer, a gate insulating layer, a gate contact and a source contact. The drift layer is disposed on a substrate, and the drift layer has a first conductivity type and an upper surface. The first doped regions are disposed in the drift layer adjacent to the upper surface and are separated from each other, and the first doped regions have a second conductivity type opposite to the first conductivity type. The first doped regions and the drift layer form a plurality of first pn junctions, and a junction field effect transistor region is defined between adjacent first doped regions. The first doped regions have a depth ranging from 3 μm to 5 μm, a width ranging from 8e16 cm -3 With 2e15cm -3The second doping region is disposed in the first doping region, the second doping region has the first conductivity type, the second doping region and the first doping region form a plurality of second pn junctions, and a plurality of channel regions are defined between the first pn junction and the second pn junction along the upper surface, the second doping region has a depth ranging from 0.4 μm to 1 μm, a depth ranging from 2e19 cm -3 With 2e17cm -3 The third doping region is arranged in the second doping region, and the plurality of third doping regions have the second conductivity type. The doped channel layer is arranged adjacent to the upper surface and extends across the drift layer between the second doping regions, and the doped channel layer has a doping concentration between and The thickness ranges from 1e17cm to -3 With 1e16cm -3 The gate contact contacts the gate insulating layer. The source contact contacts the second doping regions and the third doping regions.

[0006] In one embodiment, a source contact is further included, contacting a bottom surface of the substrate.

[0007] In one embodiment, a knee voltage of the semiconductor device is adjusted as the thickness of the doped channel layer changes.

[0008] In one embodiment, a peak current of the semiconductor device is adjusted as the thickness of the doped channel layer changes.

[0009] In one embodiment, a temperature coefficient of the semiconductor device is adjusted as the thickness of the doped channel layer changes.

[0010] In one embodiment, the semiconductor device has a peak current greater than 500 mA.

[0011] In one embodiment, the semiconductor device has a temperature coefficient between -0.01% and +0.01%.

[0012] In one embodiment, the semiconductor device is configured as a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).

[0013] The invention also discloses a constant current diode circuit, comprising the semiconductor device as mentioned above. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 FIG. 4 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0015] Figure 2 It is the IV curve characteristic of the experimental example of the present invention.

[0016] Figure 3 It is the IV curve characteristic of the experimental example of the present invention.

[0017] Figure 4 1 and 2 are IV curve characteristics of the experimental examples of the present invention and the comparative examples.

[0018] Figure 5A It is the IV curve characteristic of the experimental example of the present invention.

[0019] Figure 5B This is the IV curve characteristic of the comparative example of the present invention. DETAILED DESCRIPTION

[0020] It should be understood that the thickness of each layer and each region is exaggerated for clarity. It should also be understood that when an element such as a layer, part, region or substrate is referred to as being "on", "covering" or "over" another element, it can be directly on, directly covering or directly over the element; or other elements may be present in between. Conversely, when an element is referred to as being "directly on", "directly covering" or "directly over" another element, there are no intervening elements. Similarly, when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements between them.

[0021] Relative terms such as "above", "below", "above", "below", "horizontally", "laterally" or "vertical" may be used herein to describe the relationship of one element, layer, portion or region in the drawings to another element, layer, portion or region. It should be understood that these terms and those described above are intended to cover different orientations of the elements in addition to the orientation depicted in the drawings. A number of embodiments will be described below, in which the same structural features are identified by the same or similar reference numerals. As used herein, "laterally" or "lateral direction" should be understood to mean a direction or extent extending substantially parallel to the lateral extent of a semiconductor element, and therefore extending substantially parallel to its surface or side. In contrast, the term "thickness direction" is understood to mean a direction extending substantially perpendicular to its surface or side and therefore perpendicular to the lateral direction.

[0022] In this article, the terms used in the description of various embodiments are only for the purpose of describing specific examples and are not intended to be limiting. Unless the context clearly indicates otherwise, or the number of elements is deliberately limited, the singular forms "one", "the" used in this article may also include plural forms. Further, the terms "including" and / or "comprising" when used in this article indicate the presence of the described features, elements and / or components, but do not exclude the addition or presence of one or more other features, elements, components and / or their groups. Indefinite and definite articles should include plural and singular, unless the contrary is clearly seen from the context.

[0023] The terms “first conductivity type” and “second conductivity type” refer to opposite conductivity types, such as n-type or p-type. However, the description and drawings of each embodiment herein also include its complementary embodiments, and the same numbers represent the same elements.

[0024] See also Figure 1The present invention discloses a semiconductor device 100, which includes a substrate 110, a drift layer 120, a plurality of first doped regions 130, a plurality of second doped regions 140, a plurality of third doped regions 150, a doped channel layer 160, a gate insulating layer 170, a gate contact 181, a source contact 182, and a source contact 183. In one example, the material of the substrate 110 is silicon (Si), and the first doped region 130 can be formed by epitaxial process, diffusion, ion implantation, or chemical vapor deposition (CVD) technology, for example, a p-type layer is directly grown on an n-type drift layer in a MOCVD reactor, or aluminum ions are implanted as dopants into the n-type drift layer by ion implantation technology to form a reverse doped p-type region adjacent to a main surface of the drift layer 120. Similarly, the second doping region 140 and the third doping region 150 can be formed by epitaxial process, diffusion method, ion implantation or gas phase doping.

[0025] The substrate 110 has a top surface 111 and a bottom surface 112 . The drift layer 120 is disposed on the top surface 111 of the substrate 110 and has a first conductivity type (eg, n-type). The drift layer 120 includes an upper surface 121 .

[0026] The first doping regions 130 are disposed in the drift layer 120 adjacent to the upper surface 121 and are spaced apart from each other. Specifically, the first doping regions 130 are doped downward from the upper surface 121 into the drift layer 120. The first doping regions 130 have a second conductivity type (e.g., p-type). The first doping regions 130 and the drift layer 120 form a plurality of first pn junctions PN1, and a junction field effect transistor region J is defined between adjacent first doping regions 130. In the present embodiment, the first doping regions 130 have a depth D1 between 3 μm and 5 μm, a depth D2 between 8 e16 cm -3 With 2e15cm -3 The doping concentration ranges between .

[0027] The second doping region 140 is disposed in the first doping region 130, the second doping region has the first conductivity type, the second doping region 140 and the first doping region 130 form a plurality of second pn junctions PN2, and the second doping region 140 and the first doping region 130 define a plurality of channel regions CH between the first pn junction PN1 and the second pn junction PN2 along the upper surface 121. In this embodiment, the second doping region 140 has a depth D2 ranging from 0.4 μm to 1 μm, a depth D3 ranging from 2e19 cm -3 With 2e17cm-3 The doping concentration ranges between .

[0028] The third doping region 150 is disposed in the second doping region 140 and contacts the first doping region 130 and the second doping region 140 . The third doping regions 150 have the second conductivity type.

[0029] The doped channel layer 160 is disposed adjacent to the upper surface 121 and extends across the drift layer 120 between the second doped regions 140. The doped channel layer 160 is doped downward from the upper surface 121 of the drift layer 120 to be formed between the second doped regions 140 and to cross the drift layer 120. In this embodiment, the doped channel layer 160 has a and The thickness ranges between T and 1e17cm -3 With 1e16cm -3 A doping concentration in the range between and a width W in the range between 1 μm and 6 μm.

[0030] The gate insulating layer 170 is disposed on the upper surface 121 of the drift layer 120 . The gate insulating layer 170 extends over and contacts the junction field effect transistor region J, the channel regions CH, and a portion of the second doping regions 140 .

[0031] In one example, the depth D1 of the first doped region 130 and the depth D2 of the second doped region 140 are the vertical distances from the upper surface 121 to the bottom of the first doped region 130 and the second doped region 140, the thickness T of the doped channel layer 160 is also the vertical distance from the upper surface 121 to the bottom of the doped channel layer 160, and the width W of the doped channel layer 160 is the horizontal distance between adjacent second doped regions 140.

[0032] The gate contact 181 contacts the gate insulating layer 170 and is a contact structure for connecting the gate (Gate) and an external circuit. The source contact 182 contacts the second doping regions 140 and the third doping regions 150 and is a contact structure for connecting the source (Source) and an external circuit. The source contact 183 contacts the bottom surface 112 of the substrate 110 and is a contact structure for connecting the source (Drain) and an external circuit. In one example, the gate contact 181, the source contact 182 and the source contact 183 can be made of metal or alloy materials, such as platinum (Platinum), nickel (Nickel), aluminum (Aluminum) or a combination thereof.

[0033] In the present invention, a knee voltage, a peak current and a temperature coefficient of the semiconductor device 100 are adjusted as the thickness T of the doped channel layer 160 changes. In one example, the peak current is greater than 500 mA, and in another example, the temperature coefficient is between -0.01% and +0.01%. In this embodiment, the semiconductor device 100 is configured as a metal-oxide-semiconductor field-effect transistor (MOSFET) and can be applied to a constant current diode circuit.

[0034] When applied to the constant current diode circuit, when bias is applied, current will flow through the doped channel layer 160, and when the bias rises to the channel cutoff voltage (Vk), a constant current state is reached (i.e., the current no longer increases with the increase of voltage, but is maintained at a constant value). In the present invention, by first setting the conditions of the doping concentration of the first doping region 130 and the second doping region 140, and under the conditions, finding the specific parameters of the structure and doping concentration of the doped channel layer 160, the following effects are achieved: the semiconductor device 100 can still maintain a constant current close to that at different operating temperatures; reducing the inflection point voltage of the semiconductor device 100 can save the consumption of the circuit's own components; increasing the range of the constant current value; and adjusting the positive and negative trends of the temperature coefficient of the semiconductor device 100. In one example, the semiconductor device 100 can have a constant current close to that at an operating temperature between 25°C and 150°C, and the constant current range of the semiconductor device 100 can be between 0.1mA and 500mA. Specifically, the doped channel layer 160 belongs to the back-end process and is less susceptible to the impact of other processes. Therefore, it has advantages in manufacturing, facilitates the control of the process range, and reduces the challenge of mass production.

[0035] Figure 2 The IV curve characteristics of different experimental examples are shown. The applied voltage is 5V, the operating temperature of the experimental example is 25°C, and the voltage with increasing current is Figure 2 In the experimental examples E1, E2, and E3, the depth D1 of the first doping region 130 is about 3.5 μm and the doping concentration is about 3e16 cm -3 The depth D2 of the second doping region 140 is about 0.5 μm and the doping concentration is about 5e18 cm -3 The width W of the doped channel layer 160 is about 5 μm and the doping concentration is about 5e16 cm -3 In addition, the thickness T of the doped channel layer 160 in Experimental Examples E1, E2, and E3 is respectively

[0036] The thickness T of the doped channel layer 160 is When the inflection point voltage of the experimental example E1 is 2.8V, the temperature coefficient is -0.07%; when the thickness T of the doped channel layer 160 is When the inflection point voltage of the experimental example E2 is 2.3V, the temperature coefficient is -0.05%; when the thickness T of the doped channel layer 160 is In experimental example E3, the inflection point voltage is 2.0 V and the temperature coefficient is 0.00%.

[0037] From the measurement of the peak current (constant current) of the semiconductor device 100 when the voltage value is 5V, it can be found that the thickness T of the doped channel layer 160 is When the peak current of the experimental example E1 is 119.87 mA, the thickness T of the doped channel layer 160 is When the peak current of the experimental example E2 is 71.82 mA, the thickness T of the doped channel layer 160 is , the peak current of Experimental Example E3 is 80.13 mA.

[0038] Depend on Figure 2 It can be seen from the IV curve that the inflection point voltage of the semiconductor device 100 can be adjusted by controlling the thickness T of the doped channel layer 160. The thickness T of the doped channel layer 160 is positively correlated with the inflection point voltage, that is, the thicker the thickness T, the higher the inflection point voltage; the thinner the thickness T, the lower the inflection point voltage; in addition, the positive and negative trends of the temperature coefficient can also be adjusted to meet the needs of the application.

[0039] Figure 3 The IV curve characteristics of different experimental examples are shown. The applied voltage is 10V, the operating temperature of the experimental example is 25°C, and the voltage with increasing current is Figure 3 The experimental examples E4, E5, and E6 are devices with the same structure as the experimental examples E1, E2, and E3, that is, the width, depth, and doping concentration of the first doping region 130, the second doping region 140, and the doped channel layer 160 are the same, and the thickness T of the doped channel layer 160 of the experimental examples E4, E5, and E6 is respectively

[0040] The inflection point voltages of the experimental examples E4, E5, and E6 are all 1.8 V, and the thickness T of the doped channel layer 160 is When the temperature coefficient of the experimental example E4 is -0.12%; when the thickness T of the doped channel layer 160 is When the temperature coefficient of the experimental example E2 is -0.09%; when the thickness T of the doped channel layer 160 is , the temperature coefficient of Experimental Example E3 is -0.06%.

[0041] Further measuring the current value of the peak current (constant current) of the semiconductor device 100 when the voltage value is 5V, the thickness T of the doped channel layer 160 is , the peak current of Experimental Example E4 is 556 mA, and the thickness T of the doped channel layer 160 is , the peak current of the experimental example E5 is 551 mA, and the thickness T of the doped channel layer 160 is When the peak current of the experimental example E6 is 490 mA, the semiconductor device 100 according to the embodiment of the present invention can obtain a high rated current higher than 500 mA.

[0042] Depend on Figure 3 It can be seen from the IV curve that when the inflection point voltage is a constant value, by controlling the thickness T of the doped channel layer 160, the peak current of the semiconductor device 100 can be adjusted. The thickness T of the doped channel layer 160 is positively correlated with the peak current, that is, the thicker the thickness T, the higher the peak current, and the thinner the thickness T, the lower the peak current. By increasing the thickness T of the doped channel layer 160, the current value of the peak current can be increased to more than 500mA, as shown in curves E4 and E5.

[0043] Figure 4 The IV curve characteristics of other experimental examples and comparative examples are shown. Experimental examples E7, E8, and E9 are tested at operating temperatures of 25°C, 75°C, and 125°C, respectively. Comparative examples C1, C2, and C3 are tested at operating temperatures of 25°C, 75°C, and 125°C, respectively. The voltages as the current increases are Figure 4 Curve E7, curve E8, curve E9, curve C1, curve C2, and curve C3.

[0044] It can be seen from Experimental Examples E7, E8, and E9 that the IV curves at different temperatures are close, that is, the temperature coefficient of the experimental examples is relatively low (that is, the relative change rate of the peak current at the operating temperature is small), about -0.021%. On the contrary, the temperature coefficients of Comparative Examples C1, C2, and C3 are relatively high, about -0.325%.

[0045] Figure 5A as well as Figure 5B The IV curve characteristics of other experimental examples E10 and E11 and comparative examples C4 and C5 are shown respectively. Figure 5A is a semiconductor device according to the present invention, Figure 5BIn the experimental examples E10 and E11, the depth D1 of the first doped region 130 is about 4 μm and the doping concentration is about 8e15 cm -3 The depth D2 of the second doping region 140 is about 0.7 μm and the doping concentration is about 5e18 cm -3 The width W of the doped channel layer 160 is about 5 μm and the doping concentration is about 5e16 cm -3 The thickness T of the doped channel layer 160 in the experimental examples E10 and E11 is divided into and The difference between the comparative examples C4 and C5 and the experimental examples E10 and E11 is that the thickness T of the doped channel layer 160 in the comparative examples C4 and C5 is divided into and

[0046] The inflection point voltages of the experimental examples E10 and E11 are 2.3V and 2.0V, respectively, and the temperature coefficients are -0.05% and 0.00%, respectively; the inflection point voltages of the comparative examples C4 and C5 are 6.0V and 5.5V, respectively, and the temperature coefficients are -0.17% and -0.14%, respectively.

[0047] In addition to the previous experiments and comparisons, in order to verify that the present invention has found that the channel cutoff voltage (Vk) of the constant current diode circuit can be appropriately adjusted by changing the width W of the doped channel layer 160, the constant current diode circuit with the same parameters but different width W of the doped channel layer 160 is further tested. The depth D1 of the first doped region 130 is about 4 μm and the doping concentration is about 9e15 cm -3 The depth D2 of the second doping region 140 is about 0.5 μm and the doping concentration is about 5e18 cm -3 The width W of the doped channel layer 160 is shown in Table 1, and the doping concentration is about 5e16cm -3 .

[0048] Table 1 shows the channel cutoff voltage (Vk) of different widths W of the doped channel layer 160. The width W of the doped channel layer 160 is in micrometers (μm), and the input current unit of the test is milliamperes (mA). In the experimental examples numbered #1 to #13, the temperature coefficient (TC) is in the range of 0.000% to -0.050%, showing good thermal stability; the channel cutoff voltage (Vk) decreases with the increase of the channel width, showing an inverse relationship.

[0049] It can be seen from the above that the semiconductor device according to the present invention has a low knee voltage and an excellent temperature coefficient.

[0050]

[0051]

Explanation of symbols

[0052] 100: Semiconductor devices

[0053] 110: Substrate

[0054] 111: Top

[0055] 112: Bottom surface

[0056] 120: Drift layer

[0057] 121: Upper surface

[0058] 130: First doping region

[0059] 140: Second doping region

[0060] 150: The third doping region

[0061] 160: Doped channel layer

[0062] 170: Gate insulation layer

[0063] 181: Gate contact

[0064] 182: Source contact

[0065] 183: Source contact

[0066] D1: Depth

[0067] D2: Depth

[0068] T: Thickness

[0069] W: Width

[0070] J: Junction field effect transistor region

[0071] CH: Channel region

[0072] PN1: First pn junction

[0073] PN2: Second pn junction

[0074] E1, E2, E3, E4, E5, E6, E7, E8, E9, E10, E11, C1, C2, C3, C4, C5: curves.

Claims

1. A semiconductor device, characterized in that: include: A drift layer is disposed on a substrate, the drift layer having a first conductivity type and an upper surface; A plurality of first doped regions are disposed in the drift layer adjacent to the upper surface and are spaced apart from each other, the first doped regions having a second conductivity type opposite to the first conductivity type, the first doped regions and the drift layer forming a plurality of first pn junctions, a junction field effect transistor region being defined between adjacent first doped regions, the first doped regions having a depth ranging between 3 microns and 5 microns, a thickness ranging between 8e16 cm -3 and 2e15 cm -3 Doping concentrations in the range between A plurality of second doped regions are disposed in the first doped region, the second doped regions have the first conductivity type, the second doped regions and the first doped regions form a plurality of second pn junctions, and a plurality of channel regions are defined between the first pn junctions and the second pn junctions along the upper surface, the second doped regions have a depth ranging from 0.4 micrometers to 1 micrometer, a depth ranging from 2e19 cm -3 and 2e17 cm -3 Doping concentrations in the range between A plurality of third doping regions are disposed in the second doping region, and the plurality of third doping regions have the second conductivity type; A doped channel layer disposed adjacent to the upper surface and extending across the drift layer between the second doped regions, the doped channel layer having a thickness ranging between 75 angstroms and 90 angstroms, a width ranging between 1e17 cm -3 and 1e16 cm -3 and a width ranging between 1 micron and 6 microns; a gate insulating layer disposed on the upper surface, the gate insulating layer extending over the junction field effect transistor region, the plurality of channel regions and a portion of the plurality of second doped regions; a gate contact contacting the gate insulating layer; as well as A source contact contacts the plurality of second doping regions and the plurality of third doping regions.

2. The semiconductor device according to claim 1, wherein: The invention also includes a source contact contacting a bottom surface of the substrate.

3. The semiconductor device according to claim 1, wherein: A knee voltage of the semiconductor device is adjusted as the thickness of the doped channel layer changes.

4. The semiconductor device according to claim 1, wherein: A peak current of the semiconductor device is adjusted as the thickness of the doped channel layer changes.

5. The semiconductor device according to claim 1, wherein: A temperature coefficient of the semiconductor device is adjusted as the thickness of the doped channel layer changes.

6. The semiconductor device according to claim 1, wherein: The semiconductor device has a peak current greater than 500 milliamperes.

7. The semiconductor device according to claim 1, wherein: The semiconductor device has a temperature coefficient between -0.01% and +0.01%.

8. The semiconductor device according to claim 1, wherein: The semiconductor device is configured as a metal oxide semiconductor field effect transistor.

9. A constant current diode circuit comprising a semiconductor device according to any one of claims 1 to 7.

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