Semiconductor device comprising a self-aligned dwell implant having a gate electrode with self-aligned dwell implant with inverse type

Abstract

The present disclosure is directed to a semiconductor device having a gate electrode with opposite types of doping at drain and source terminals including a self-aligned DWELL implant. Disclosed examples include a microelectronic device (200), such as an integrated circuit, including a source region (258) and a drain region (260) extending into a semiconductor substrate (208), the semiconductor substrate (208) having a second conductivity type, the source region (258) and the drain region (260) having an opposite first conductivity type. A channel region (239) having a second conductivity type extends between the source region (258) and the drain region (260). A gate electrode (228) over the channel region (239) has a first portion (286) and a second portion (246). The first portion (286) has a second conductivity type and a first dopant concentration. A second portion (246) extends from the first portion toward the source region and has a second conductivity type and a second higher dopant concentration. Self-aligned implantation is used to simultaneously implant dopants in the semiconductor substrate (208) proximate the source terminal of the gate electrode (228) and in the semiconductor substrate (208) proximate the source region (258).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is related to commonly owned U.S. patent application Ser. No. 18 / 459,065, filed on Aug. 31, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to the field of microelectronic devices. More particularly, but not exclusively, the present disclosure relates to gated devices such as MOS transistors. Background Art

[0004] Semiconductor components are continually improving to operate reliably with smaller feature sizes. There are various challenges in manufacturing semiconductor devices with increasingly higher performance while meeting reliability specifications. Summary of the invention

[0005] This summary is provided to present a brief overview of the disclosed concepts in a simplified form, which concepts are further described below in the detailed description including the provided figures. This summary is not intended to limit the scope of the disclosure or the claims.

[0006] Disclosed examples include microelectronic devices, such as integrated circuits. One example includes a microelectronic device, the microelectronic device including a source region and a drain region, the source region and the drain region having a first conductivity type, extending into a semiconductor substrate having an opposite second conductivity type. A channel region having the first conductivity type extends between the source region and the drain region to a surface of the substrate. A gate electrode over the channel region has a first portion and a second portion having the second conductivity type, the first portion having a first dopant concentration, and the second portion extending from the first portion toward the source region and having a second higher dopant concentration. The second higher dopant concentration increases from the first portion toward the source region.

[0007] Another example provides a method of forming a microelectronic device. A gate electrode is formed above a semiconductor substrate, the gate electrode having a source terminal and a drain terminal. A first portion of the gate electrode extends from the drain terminal toward the source terminal, a second portion of the gate electrode extends from the first portion toward the source terminal, and a third portion of the gate electrode extends from the second portion to the source terminal. A first dopant of a first conductivity type is simultaneously implanted into the third portion of the gate electrode and into the semiconductor substrate adjacent to the third portion. A second dopant of an opposite second conductivity type is simultaneously implanted into the third portion of the gate electrode and into the semiconductor substrate adjacent to the third portion. The gate electrode is annealed, thereby diffusing the dopant of the second conductivity type from the third portion of the gate electrode into the second portion of the gate electrode so that the second portion of the gate electrode has a horizontal dopant concentration gradient between the first portion and the third portion of the gate electrode.

[0008] Another example provides a method of forming a microelectronic device, the microelectronic device including a source region and a drain region extending into a semiconductor substrate, the source region and the drain region having a first conductivity type, and the semiconductor substrate having an opposite second conductivity type. A gate electrode having an opposite first end and a second end is formed above the semiconductor substrate, between the source region and the drain region. A first portion of the gate electrode extends from the first end toward the source region, and a second portion of the gate electrode extends from the second end toward the drain region. The first portion of the gate electrode is doped to have the second conductivity type. A dopant of the second conductivity type is implanted into the second portion at the second end of the gate electrode and implanted into the semiconductor substrate adjacent to the second end. The gate electrode is thermally annealed so that the dopant of the second conductivity type in the second portion of the gate electrode diffuses toward the first end, thereby providing a horizontal gradient of the dopant in the second portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1A to 1G is a cross section of an exemplary microelectronic device including a transistor having a gate electrode formed using an IARC layer, and a depletable resurf gate electrode formed using a self-aligned DWELL implant at various stages of formation.

[0010] FIG. 2A to FIG. 2H is a cross-section of an exemplary microelectronic device including a transistor and a depletable resurf gate electrode formed using a self-aligned DWELL implant at various stages of formation.

[0011] Figure 3Ais a graphical representation of an extended drain transistor with a depletable resurf gate electrode having source and drain potentials of 0V.

[0012] Figure 3B is a graphical representation of an extended drain transistor with a depletable resurf gate electrode having a source potential of 0 V and a drain potential greater than 0 V (in a blocking state), illustrating the depletable resurf effect of the depletable resurf gate electrode.

[0013] FIG. 4A to FIG. 4G is a cross section of an exemplary microelectronic device including a transistor and a depletable resurf gate electrode formed using a self-aligned light halo implant at various stages of formation. DETAILED DESCRIPTION

[0014] The present disclosure is described with reference to the accompanying drawings. The drawings are not drawn to scale and are provided only for illustrating the present disclosure. Several aspects of the present disclosure are described below with reference to exemplary applications for illustration. It should be understood that many specific details, relationships and methods are set forth to provide an understanding of the present disclosure. The present disclosure is not limited by the order of description of actions or events, because unless otherwise specified, some actions can occur in different orders and / or simultaneously with other actions or events. In addition, not all described actions or events are necessary to implement the methods according to the present disclosure.

[0015] In addition, although some of the examples described herein are shown in two-dimensional views of various regions having depth and width, it should be clearly understood that these regions are only illustrations of a portion of a device that is actually a three-dimensional structure. Therefore, when manufactured on an actual device, these regions will have three dimensions, including length, width, and depth. In addition, although the present disclosure may be described by examples directed to active devices, it is not intended that these descriptions limit the scope or applicability of the present disclosure. It is not intended that the active devices of the present disclosure be limited to the physical structures described. These structures are included to show the practicality and application of the present disclosure to various examples.

[0016] It should be noted that terms such as top, bottom, above, above, and below may be used in the present disclosure. These terms should not be understood to limit the position or orientation of structures or elements, but should be used to provide spatial relationships between structures or elements. The terms "lateral" and "laterally" refer to directions parallel to a plane corresponding to a surface of a layer (e.g., a top surface of a semiconductor substrate). In addition, the term "approximately" as used herein may refer to a ±5% to ±10% variation of a stated value in some cases. In other cases, the term "approximately" may refer to a ±10% to ±20% variation of a stated value.

[0017] Microelectronic devices are constantly being improved to operate reliably with higher performance and smaller feature sizes. There are ongoing challenges in manufacturing such microelectronic devices that meet area scaling and reliability requirements. Certain gated devices such as metal oxide semiconductor (MOS) transistors include features for supporting high voltage operation, such as where the voltage applied to their drain (or drain structure) is about 20V, 30V, 40V or even greater. Such MOS transistors may include a drain diffusion distribution (or drain junction distribution) designed to support a high voltage applied to the drain, such as having an extension portion to distribute the voltage drop across a greater distance. Therefore, such MOS transistors may be referred to as drain-extended MOS transistors, such as drain-extended n-channel MOS (DENMOS) transistors, drain-extended p-channel MOS (DEPMOS) transistors, lateral diffusion MOS (LDMOS) transistors, and DENMOS and DEPMOS transistor groups (which may be referred to as complementary drain-extended MOS or DECMOS transistors). Other gated microelectronic devices may include gated bipolar semiconductor devices, gated unipolar semiconductor devices, insulated gate bipolar transistors (IGBTs), MOS triggered SCRs, MOS controlled thyristors, and gated diodes.

[0018] Baseline field effect transistors typically have a gate electrode over a channel region, wherein the gate electrode is doped with the same conductivity type as the channel region, which in turn has the same conductivity type between the source region and the drain region. Thus, when the transistor is in the off state, the gate electrode has a majority carrier type opposite to the majority carrier type of the channel region. For example, a baseline n-type transistor, such as an n-channel MOSFET, has a p-type body region before channel inversion, and the gate electrode is typically heavily doped to obtain high conductivity. In the case of an extended drain (ED) transistor, the operating voltage may be limited by avalanche breakdown at the drain-body junction, which typically occurs at the silicon surface. In contrast, examples of the present disclosure include innovative identifications that the gate electrode may be depleted by the electric field generated by the drain at a high drain voltage by lightly doping the drain end of the gate electrode with majority charge carriers of the opposite doping type of the channel under inversion (e.g., electrons for an n-channel device). In this way, the gate electrode may act as a semiconductor "resurf" element, resurf refers to reducing the surface field. The gate electrode of the exemplary device may be referred to as a "depletable resurf gate electrode" because carriers in the gate electrode are depleted simultaneously with carriers in the drain drift region of the ED device example. Electrons and holes deplete each other due to the electric field of the junction reverse bias. This causes a reduction in the electric field in the gate oxide at the drain end of the gate electrode, which reduces aging in the microelectronic device by reducing failure mechanisms such as channel hot carriers (CHC) and gate oxide cracking. In this way, device reliability may be improved and / or device size may be reduced.

[0019] By way of additional background, the gate electrode of an operating ED transistor performs the important function of controlling the silicon surface potential in the channel region. The bottom of the portion of the gate electrode overlying the channel should enforce metal boundary conditions during gate switching in order to control the surface potential of the underlying channel silicon, thereby forcing the silicon surface carrier distribution to accumulate (transistor gate off-state), through depletion (subthreshold), and ultimately to a strong inversion (on-state) as the gate electrode changes from 0V to a positive on-state voltage (NMOS transistor) or a negative on-state voltage (PMOS transistor).

[0020] In order to achieve this channel surface potential control, the portion of the semiconductor gate electrode whose lower surface is located above the channel must have a high dopant concentration, because maintaining the metallic boundary condition requires that the vertical electric field in the gate dielectric be screened by free carriers to produce a zero electric field within the conductive interior of this portion of the gate electrode. Obtaining a sufficiently high concentration of free carriers requires a high concentration of majority carrier doping in the portion of the gate electrode that is located above the channel. In some examples, it is desirable that the dopant concentration in the channel is at least high enough to make the carrier distribution degenerate, or at least 1×10 19 cm -3 .

[0021] At the drain terminal of the gate electrode, the doping distribution of the drain region is below the gate electrode. In the transistor gate-off state, and specifically, when the drain region is maintained at a high reverse bias (commonly referred to as the blocking state), the majority carriers in this lower overlapping portion of the drain of the gate electrode will be depleted, thereby exposing the ionized majority carrier dopant. If the doping type of the gate electrode overlying the drain region is the same as the doping type of the drain, then the majority carriers will be attracted to the bottom of the gate electrode near and including its drain terminal and will form an accumulation layer that provides a metal boundary condition. This causes a high local high electric field in the gate dielectric near the drain terminal, and at the corner of the bottom of the gate electrode facing the drain, the electric field can be enhanced by the curvature of the gate electrode corner. This localized peak in the electric field can be high enough to cause transistor degradation mechanisms, such as CHC injection or dielectric failure in the gate dielectric, which can cause severe limitations on the use of transistors at elevated drain blocking voltages.

[0022] According to examples of the present disclosure, a doping having a conductivity type (e.g., P-type) opposite to the conductivity type (e.g., N-type) of the doping of the drain is provided in the drain terminal of the gate. In this configuration, the majority carriers in the drain terminal of the gate electrode can be depleted under the action of the electric field caused by the drain in a reverse bias state. In addition, in various examples, the majority carrier concentration in the drain terminal of the gate electrode can be low enough to be depleted without experiencing breakdown, such as by having a conductivity of less than 1×10 13 cm-2 The invention relates to a method for controlling the dopant dosage of the drain electrode to ensure the resurf condition of the dopant dosage of the gate electrode. A considerable portion of the gate (e.g., even wider than the gate electrode thickness) can be depleted during drain reverse bias, thereby turning this portion of the gate electrode into a charged dielectric region that balances the exposed charge in the underlying silicon due to the opposite doping sign. This charge balance alleviates the highest surface electric field peak across the overlap region between the drain doping profile and the gate electrode, thereby enabling drain-extended transistor operation at high blocking drain voltages without inducing the degradation effects of high local electric fields, especially when operating in pulsed mode. This mutual depletion effect between the drain carrier distribution and the carrier distribution in the drain-facing end of the gate electrode is similar to the mutual depletion of the n-layer and the p-layer in the resurf drift region, so we refer to the drain-extended transistor adopting this gate electrode doping profile as a depletable resurf gate electrode drain-extended transistor.

[0023] The extent of depletion of the gate electrode facing the drain end should be limited so that it does not extend to source end features such as silicide on the top surface of the gate electrode to avoid breakdown effects such as avalanche. To suppress this effect, in some examples, the doping concentration of the gate electrode is increased as it approaches any surface silicide or other features that may cause breakdown.

[0024] The present disclosure includes several examples of implants that are self-aligned to the source end of the gate electrode. The self-aligned DWELL implant provides an advantageous method to simultaneously implant a first type of dopant (the same type as the channel region before inversion) into the gate electrode, which forms a third portion of the gate electrode above the channel region; implant a second type of dopant (the opposite type as the channel region before inversion) into the gate electrode, which forms a second portion of the gate electrode above the drift region; and implant the first type and second type of dopant in silicon near the source side of the gate electrode, which forms a DWELL that provides a channel region and a body region. In addition, the self-aligned DWELL implant provides an advantageous method to implant the second type of dopant to form the second portion of the gate electrode while implanting silicon near the source side of the gate electrode.

[0025] Figures 1A to 1G 1 and 2 represent a first type of microelectronic device 100 to which the principles of the present disclosure may be advantageously applied. These figures show a cross section of an exemplary microelectronic device 100 (eg, a MOS transistor) including a depletable resurf gate electrode 128 (referred to herein as gate electrode 128). Figure 1B, and below). Without implicit limitation, in this example, the gate electrode 128 is implemented in a DENMOS transistor 102, which is shown in successive stages of an exemplary formation method. Other implementations of the gate electrode 128 for a DEPMOS transistor are within the scope of this example. In the exemplary DENMOS transistor 102, the dopant of the first conductivity type is an n-type dopant, and the dopant of the second conductivity type is a p-type dopant.

[0026] Figure 1A The microelectronic device 100 including the DENMOS transistor 102 is shown after forming the gate dielectric layer 118 and the gate layer 120. The structures and methods within the microelectronic device 100 formed before the gate dielectric layer 118 is formed can include an epitaxial layer 106 over a base wafer 104, which together are referred to as a substrate 108 having a top surface 110. For example, the base wafer 104 can be a 1×10 17 cm -3 to 1×10 19 cm -3 Alternatively, the base wafer 104 may be lightly doped, with an average dopant concentration of less than 1×10 16 cm -3 As an example, the epitaxial layer 106 may have a thickness of 1×10 15 cm -3 to 1×10 16 cm -3 The epitaxial layer 106 is optional, as in some examples, the DENMOS transistor 102 may be formed directly in the base wafer 104 .

[0027] The isolation layer for DENMOS transistor 102 may be formed by shallow trench isolation (STI) or local oxidation of silicon (LOCOS), either of which may be conventional, or formed by any future discovered method. The example shown includes an STI structure 112 .

[0028] The drift region 116 is formed in the substrate 108 in the epitaxial layer 106 and below a portion of the gate dielectric layer 118. One or more n-type implants are performed to form the drift region 116 (which may be referred to as an n-drift region) in the substrate 108. The n-type dopant that defines the n-drift region 116 may be implanted in one step or in multiple steps. For example, phosphorus may be implanted at 1×10 12 cm -2 With 1×10 13 cm -2A total dose implant of between 100 and 1000 Å is provided, which has an energy suitable for forming the n-drift region 116 with or without subsequent thermal cycling. Arsenic may also be implanted at a similar dose, with an energy relatively less than the phosphorus implant.

[0029] Although not limited to the above Figure 1A 102, but the gate dielectric layer 118 and the gate layer 120 are formed above the top surface 110. The gate dielectric layer 118 can be formed in a high temperature boiler operation or a rapid thermal process. Other methods of forming the gate dielectric layer 118 are within the scope of the present disclosure. The gate dielectric layer 118 can be any material and have any thickness suitable for the technical application. The gate layer 120 is formed on the gate dielectric layer 118 by conventional or future discovered methods. In the example shown, the gate layer 120 is formed by a deposition process of depositing polycrystalline silicon (polycrystalline silicon) (which may be referred to as polysilicon) using one or more silane-based precursors. In other examples, a replacement gate process can be used to form the gate layer 120. The gate layer 120 has a thickness that can be in the range of approximately 50nm to 300nm. The gate layer 120 can be undoped or in-situ doped when deposited. In this exemplary formation, the gate layer 120 is co-deposited with a p-type precursor (e.g., diborane, boron trichloride, tris(2,4-pentanedione)gallium(III)) such that the p-type dopant dose (e.g., the integration of the net p-type doping concentration through the thickness of the gate electrode) is between 1×10 12 cm -2 With 1×10 13 cm -2 The low doping concentration in the gate layer 120 provides a resurf region to be defined at a later stage of processing. The gate layer 120 may also be a polycrystalline SiGe layer, a polycrystalline Ge layer, a polycrystalline SiC layer, or another semiconductor that may be grown or deposited on the gate dielectric.

[0030] Figure 1B A cross section of the DENMOS transistor 102 is shown after an inorganic anti-reflective coating (IARC) 122 and a gate resist 124 have been formed and after a gate plasma etch 126. The gate plasma etch 126 removes the previously formed gate dielectric layer 118, the gate layer 120, and the IARC 122 in areas not covered by the gate resist 124. The area below the gate resist 124 defines a gate electrode 128 and the gate dielectric layer 118, the gate electrode 128 including the portion of the gate layer 120 remaining after the gate plasma etch 126. After the gate plasma etch 126 is completed, the gate resist 124 is removed and a wet or dry process may be used to clean the wafer surface.

[0031] refer to Figure 1C , forming a DWELL resist 130. A self-aligned DWELL implant 134 can implant p-type and n-type ions through the DWELL resist opening 132 to form several implant regions of the DENMOS transistor 102. The IARC 122 coincides with the vertical edge of the gate electrode 128. The presence of the IARC 122 on the gate electrode 128 can be advantageous because it can produce improved implant uniformity in the gate electrode 128 during the self-aligned DWELL implant 134. The self-aligned DWELL implant 134 can be composed of one or more p-type implants and one or more n-type implants. Some of the n-type implants and p-type implants can be tilted to up to 45 degrees to implant n-type ions and p-type ions into the vertical surface of the gate electrode 128. The p-type well region 136 and the p-type gate region 140 are implanted with p-type dopants that can include boron and / or indium. After thermal annealing, p-type well region 136 may have a thickness of at most 1×10 19 cm -3 or greater peak dopant density. The p-type gate region 140 may have a peak dopant density of 3×10 16 cm -3 With 1×10 19 cm -3 The p-type well region 136 (in some instances in conjunction with the epitaxial layer 106) may be referred to as the body region (eg, P-type body region) of the DENMOS transistor 102. After thermal annealing, the p-type gate region 140 forms a second portion 146 of the gate electrode 128 (at Figure 1D mentioned in ).

[0032] In addition, in substrate 108, self-aligned DWELL implant 134 forms an n-type well region 138. N-type well region 138 is doped with an n-type dopant that may include, for example, phosphorus or arsenic. After thermal annealing, n-type well region 138 may have a depth of at most 1×10 19 cm -3 or greater peak dopant density. The self-aligned DWELL implant 134 also implants n-type ions to form an n-type gate region 142. The n-type gate region 142 may have a peak dopant density of 3×10 16 cm -3 With 1×10 19 cm -3 After the self-aligned DWELL implant 134, the DWELL resist 130 and the IARC 122 are removed.

[0033] refer to Figure 1D, a thermal annealing step 144 may be used to activate the implant species and diffuse the implant species from the self-aligned DWELL implant 134 to form a DWELL 137. The DWELL 137 extends to the top surface 110 between the n-type well region 138 and the n-type drift region 116. A boiler or a rapid thermal annealing (RTA) process may be used as a heat source for the thermal annealing step 144. In the substrate 108, the thermal annealing provides a thermal budget for the p-type boron of the self-aligned DWELL implant 134 to diffuse in a lateral direction through the n-type well region 138 of the self-aligned DWELL implant 134 forming a channel distribution of the channel region 139. In the gate electrode 128, the thermal annealing step 144 takes advantage of the higher diffusion constant of p-type boron in the p-type gate region 140 compared to the n-type arsenic in the n-type gate region 142, thereby allowing the implanted species in the gate electrode 128 to be separated into a heavily p-type doped second portion 146 and an n-type gate region 142, referred to herein as a heavily n-type doped third portion 142, after thermal treatment.

[0034] exist Figure 1D In the remaining discussion of the gate electrode 128, Figure 1D The portions labeled 120, 146, and 142 in the figure may be referred to as first portion 120, second portion 146, and third portion 142, respectively. In first portion 120 (resurf region) of gate electrode 128, the p-type doping density is low enough to allow depletion during operation of DENMOS transistor 102 and to allow it to act as a resurf region. Second portion 146 of gate electrode 128 is heavily p-type doped (greater than 1×10 18 cm -3 ) until it is equivalent to the doping of the first portion 120 at the interface between the second portion 146 and the first portion 120. 18 cm -3 The heavily doped p-type doped gate region 140 of the second portion 146 of the gate electrode between the third portion 142 of the gate electrode 128 and the lightly p-type doped first portion 120 prevents the n-type dopant of the third portion 142 from back doping the p-type dopant of the first portion 120. Although the overall doping of the third portion 142 is heavy, it can also have a horizontal doping gradient with the heaviest doping at the source end of the gate electrode 128 and lighter doping at the interface between the third portion 142 and the second portion 146.

[0035] refer to Figure 1E, sidewall spacers 148 may be formed on the vertical surface of gate electrode 128 and may extend 50 nm to 200 nm from the lateral edge of gate electrode 128. After forming sidewall spacers 148, a first source / drain resist 150 is deposited and patterned. A first source / drain implant 156 implants n-type dopants into substrate 108 through source opening 152 and drain opening 154 to implant source region 158 and drain region 160. The first source / drain implant 156 may include one or more implantation steps, provided that the resulting dopant concentration of source region 158 and drain region 160 has a peak value of 1×10 19 cm -3 With 1×10 21 cm -3 . The source region 158 and the drain region 160 contain at least twice the average dopant density of the epitaxial layer 106, with a peak doping density between 0.15 μm and 0.5 μm from the top surface 110. The source / drain resist extension 161 extends the first source / drain resist 150 past the end of the gate electrode 128 toward the drain region 160. The source / drain resist extension 161 prevents n-type dopants from the first source / drain implant 156 from extending under the gate electrode 128 after a subsequent thermal annealing process. After forming the source region 158 and the drain region 160, the first source / drain resist 150 is removed and the wafer is thermally annealed (not specifically shown).

[0036] Figure 1F 1 is a cross-section of the DENMOS transistor 102 after a second source / drain implant resist 162 is deposited and patterned to form a second source / drain resist opening 164 for a second source / drain implant 166. The second source / drain implant 166 can implant dopants for a second source / drain region of a p-channel device (not specifically shown) for the microelectronic device 100. In addition, the second source / drain implant 166 implants p-type dopants through the second source / drain resist opening 164 to form a back gate region 168 of the DENMOS transistor 102.

[0037] As with the first source / drain implant 156, the second source / drain implant 166 may occur in one or more steps. The second source / drain implant 166 may implant a substance including boron (or indium) with a total dose and energy such that it provides degenerate doping, for example with greater than 1×10 19 cm -3 The active average dopant density is near the solubility limit of the dopant atoms in the back gate region 168. After the second source / drain implant 166, the second source / drain implant resist 162 is removed.

[0038] Figure 1GA cross section of the DENMOS transistor 102 is shown after the first level of interconnect 178 is completed. In some examples, a silicide blocking layer 170 may be formed over the first portion 120 of the gate electrode 128, extending partially over the second portion 146 of the gate electrode 128 and leaving areas of the second portion 146 and the third portion 142 not covered by the silicide blocking layer 170. The silicide blocking layer 170 may be formed by depositing one or more sub-layers of oxide, nitride, oxynitride, or any combination thereof over the entire wafer and patterning to open areas where silicide formation is desired. In some examples, a metal silicide layer 172 may be formed on the source region 158, the drain region 160, the back gate region 168, and the exposed portion of the gate electrode 128. The metal silicide layer 172 can provide an ohmic electrical connection to the source region 158 , the drain region 160 , the back gate region 168 , and the gate electrode 128 with lower resistance than a similar microelectronic device without the metal silicide layer 172 .

[0039] A pre-metal dielectric (PMD) layer 174 is formed above the top surface 110 of the substrate 108. The PMD layer 174 may include one or more dielectric layers, such as silicon nitride, silicon oxynitride, silicon dioxide, etc. In some examples, the PMD layer 174 includes a PMD liner and a main dielectric sublayer formed on the PMD liner. Subsequently, the PMD layer 174 may be planarized by a chemical mechanical polishing (CMP) process. Contacts 176 (such as tungsten plugs) are formed in the PMD layer 174 to provide electrical connections to the source region 158 and the drain region 160. An interconnect 178 electrically connected to the contact 176 is formed above the PMD layer 174 using any suitable metallization scheme and provides electrical contact between the DENMOS transistor 102 and other components of the microelectronic device 100.

[0040] FIG. 2A to FIG. 2H 200 (eg, a MOS transistor) including a depletable resurf gate electrode 228 (referred to herein as gate electrode 228). Figure 2B , and below). Without implicit limitation, in this example, gate electrode 228 is implemented in DENMOS transistor 202, which is shown in successive stages of an exemplary formation method. Other implementations of gate electrode 228 for PMOS transistors are within the scope of this example. In the exemplary DENMOS transistor 202, the dopant of the first conductivity type is an n-type dopant, and the dopant of the second conductivity type is a p-type dopant.

[0041] Figure 2AThe microelectronic device 200 including the DENMOS transistor 202 is shown after forming a gate dielectric layer 218 and a gate layer 220. The structures and methods within the microelectronic device 200 formed before the gate dielectric layer 218 is formed can include an epitaxial layer 206 over a base wafer 204, which together are referred to as a substrate 208 having a top surface 210. For example, the base wafer 204 can be a 1×10 17 cm -3 to 1×10 19 cm -3 Alternatively, the base wafer 204 may be lightly doped, with an average dopant concentration of less than 1×10 16 cm -3 As an example, the epitaxial layer 206 may have a thickness of 1×10 15 cm -3 to 1×10 16 cm -3 Epitaxial layer 206 is optional, as in some examples, DENMOS transistor 202 may be formed directly in base wafer 204 .

[0042] The isolation layer for the DENMOS transistor may be formed by STI or LOCOS, either of which may be conventional, or formed by any future discovered method. The example shown includes an STI structure 212 .

[0043] The field release dielectric layer 214 may be formed by a LOCOS process and may have a thickness in a range between 50 nm and 500 nm. The field release dielectric layer 214 may have a tapered edge along its perimeter where the field release dielectric layer 214 abuts the top surface 210 of the substrate 208. The tapered edge of the field release dielectric layer 214 may be referred to as a "bird's beak" region. Although Figures 2A to 2H The exemplary DENMOS transistor 202 shown in FIG. 1 includes an STI structure 212 and a field release dielectric layer 214, but any feature may be omitted in other examples within the scope of the present disclosure. For example, the field release dielectric layer 214 may be replaced by another STI structure. Similarly, the STI structure 212 may be replaced by another LOCOS structure, such as similar to the field release dielectric layer 214.

[0044] The drift region 216 is formed in the substrate 208 in the epitaxial layer 206 and below a portion of the gate dielectric layer 218. One or more n-type implants are performed to form the drift region 216 (which may be referred to as an n-drift region) in the substrate 208. The n-type dopant that defines the n-drift region 216 may be implanted in one step or in multiple steps. For example, phosphorus may be implanted at 1×10 12 cm -2 With 1×10 13cm -2 A total dose implant of between 100 and 1000 Å is provided, which has an energy suitable for forming the n-drift region 216 with or without subsequent thermal cycling. Arsenic may also be implanted at a similar dose, with an energy relatively less than the phosphorus implant.

[0045] Although not limited to the above Figure 2A , but the gate dielectric layer 218 and the gate layer 220 are formed above the top surface 210. The gate dielectric layer 218 can be formed in a high temperature boiler operation or a rapid thermal process. Other methods of forming the gate dielectric layer 218 are within the scope of the present disclosure. The gate dielectric layer 218 can be any material and have any thickness suitable for the technical application. The gate layer 220 is formed on the gate dielectric layer 218 by conventional or future discovered methods. In the example shown, the gate layer 220 is formed by a deposition process that deposits polycrystalline silicon (which may be referred to as polysilicon) using one or more silane-based precursors. In other examples, a replacement gate process can be used to form the gate layer 220. The gate layer 220 has a thickness that can range from approximately 50nm to 300nm. The gate layer 220 can be undoped or doped in situ when deposited. In Figure 2A In the example shown in FIG. 1 , the gate layer 220 is undoped. Figure 1A The gate layer 220 may also be a polycrystalline SiGe layer, a polycrystalline Ge layer, a polycrystalline SiC layer, or another semiconductor that may be grown or deposited on the gate dielectric.

[0046] Figure 2B A cross section of the DENMOS transistor 202 is shown after a gate resist 224 has been formed and after a gate plasma etch 226. The gate plasma etch 226 removes the previously formed gate dielectric layer 218 and gate layer 220 in areas not covered by the gate resist 224. The area under the gate resist 224 defines a gate electrode 228, a field plate 229, and the portion of the gate dielectric layer 218 that remains after the gate plasma etch 226. After the gate plasma etch 226 is completed, the gate resist 224 is removed and a wet or dry process may be used to clean the wafer surface.

[0047] refer to Figure 2C, forming a DWELL resist 230. A self-aligned DWELL implant 234 may implant p-type and n-type ions through the DWELL resist opening 232 to form several implant regions of the DENMOS transistor 202. The self-aligned DWELL implant 234 may include one or more p-type implants and one or more n-type implants. Some of the n-type implants and p-type implants may be tilted to up to 45 degrees to implant n-type ions and / or p-type ions into the vertical surface of the gate electrode 228. The p-type well region 236 and the p-type gate region 240 are implanted with p-type dopants that may include boron and / or indium. After thermal annealing, the p-type well region 236 may have a 1×10 19 cm -3 or greater peak dopant density. The p-type gate region 240 may have a peak dopant density of 1×10 19 cm -3 or greater peak dopant density. The p-type well region 236 (in some instances in conjunction with the epitaxial layer 206) may be referred to as the body region (e.g., P-type body region) of the DENMOS transistor 202. After thermal annealing, the p-type gate region 240 forms a second portion 246 of the gate electrode 228 (at Figure 2D mentioned in ).

[0048] In addition, in substrate 208, self-aligned DWELL implant 234 forms an n-type well region 238. N-type well region 238 is doped with an n-type dopant that may include, for example, phosphorus or arsenic. After thermal annealing, n-type well region 238 may have a 1×10 19 cm -3 or greater peak dopant density. The self-aligned DWELL implant 234 also implants n-type ions to form an n-type gate region 242. The n-type gate region 242 may have a 1×10 19 cm -3 or greater peak dopant density. The n-type gate region 242 may be referred to herein as a third portion 242 of the gate electrode. After the self-aligned DWELL implant 234, the DWELL resist 230 is removed.

[0049] Figure 2D The cross section is shown after depositing and patterning the resurf resist 280 through the resurf resist opening 282. The resurf implant 284 uses ion implantation to implant p-type dopants to form a first portion 286 of the gate electrode 228. The resurf implant 284 may have a 1×10 12 cm -2 to 1×10 13 cm -2After the resurf implant 284, the resurf resist 280 is removed.

[0050] refer to Figure 2E , a thermal annealing step 244 may be used to activate the implanted species and diffuse the implanted species from the self-aligned DWELL implant 234, thereby forming a DWELL 237. The DWELL 237 extends to the top surface 210 between the n-type well region 238 and the drift region 216, thereby providing a channel region 239 of the microelectronic device 200. A boiler or RTA process may be used as a heat source for the thermal annealing step 244. In the substrate 208, the thermal annealing provides a thermal budget for the dopants of the p-type well region 236 to diffuse through the n-type well region 238 to form a channel distribution in the lateral direction. In the gate electrode 228, the thermal annealing step 244 utilizes the higher diffusion constant of p-type boron in the p-type gate region 240 compared to the n-type arsenic in the n-type gate region 242, thereby allowing the implanted species in the gate electrode 228 to be separated into a heavily p-type doped second portion 246 and a heavily n-type doped n-type gate region 242 after the thermal treatment.

[0051] exist Figure 2E In the remaining discussion of the gate electrode 228, Figure 2E The portions shown as 286, 246, 242, and 229 in the figure may be referred to as the first portion 286, the second portion 246, the third portion 242, and the field plate 229, respectively. In the first portion 286 (resurf region) of the gate electrode 228, the p-type doping density is low enough to allow depletion during operation of the DENMOS transistor 202 and to allow it to act as a resurf region. The doping density of the field plate 229 may be equivalent to the doping density of the first portion 286. The second portion 246 of the gate electrode 228 is heavily p-type doped (greater than 1×10 18 cm -3 ) until it is equivalent to the doping of the first portion 286 at the interface between the second portion 246 and the first portion 286. 18 cm -3 The heavily doped p-type gate region 240 of the second portion 246 of the gate electrode between the third portion 242 of the gate electrode 228 and the lightly p-type doped first portion 286 prevents the n-type dopant of the third portion 242 from back-doping the p-type dopant of the first portion 286. Although the overall doping of the third portion 242 is heavy, it can also have a horizontal doping gradient with the heaviest doping at the source end of the gate electrode 228 and lighter doping at the interface between the third portion 242 and the second portion 246.

[0052] refer to Figure 2F , sidewall spacers 248 may be formed on the vertical surface of gate electrode 228 and may extend 50 nm to 200 nm from the lateral edge of gate electrode 228. After forming sidewall spacers 248, a first source / drain resist 250 is deposited and patterned. A first source / drain implant 256 implants n-type dopants into substrate 208 through source opening 252 and drain opening 254 to implant source region 258 and drain region 260. The first source / drain implant 256 may include one or more implantation steps, provided that the resulting dopant concentration of source region 258 and drain region 260 has a peak value of 1×10 19 cm -3 With 1×10 21 cm -3 The source region 258 and the drain region 260 contain at least twice the average dopant density of the epitaxial layer 206, wherein after thermal annealing, the peak doping density is between 0.15 μm and 0.5 μm from the top surface 210. After forming the source region 258 and the drain region 260, the source / drain resist 250 is removed and the wafer is thermally annealed (not specifically shown).

[0053] Figure 2G 2 is a cross-section of the DENMOS transistor 202 after a second source / drain implant resist 262 is deposited and patterned to form a second source / drain resist opening 264 for a second source / drain implant 266. The second source / drain implant 266 can implant dopants for a second source / drain region of a p-channel device (not specifically shown) for the microelectronic device 200. In addition, the second source / drain implant 266 implants p-type dopants through the second source / drain resist opening 264 to form a back gate region 268 of the DENMOS transistor 202.

[0054] As with the first source / drain implant 256, the second source / drain implant 266 may occur in one or more steps. The second source / drain implant 266 may implant a substance including boron (or indium) with a total dose and energy such that it provides degenerate doping, for example with greater than 1×10 19 cm -3 The active average dopant density is around the solubility limit of the dopant atoms in the back gate contact 268. After the second source / drain implant 266, the second source / drain implant resist 262 is removed.

[0055] Figure 2HA cross section of the DENMOS transistor 202 is shown after the first level of interconnect 278 is completed. In some examples, a silicide blocking layer 270 may be formed over the field plate 229 and the first portion 286 of the gate electrode 228, extending partially over the second portion 246 of the gate electrode 228 and leaving areas of the second portion 246 and the third portion 242 not covered by the silicide blocking layer 270. The silicide blocking layer 270 may be formed by depositing one or more sub-layers of oxide, nitride, oxynitride, or any combination thereof over the entire wafer and patterning to open areas where silicide formation is desired. In some examples, a metal silicide layer 272 may be formed over the source region 258, the drain region 260, and the exposed portion of the gate electrode 228. The metal silicide layer 272 may provide an ohmic electrical connection to the source region 258, the drain region 260, and the gate electrode 228 with a lower resistance than a similar microelectronic device without the metal silicide layer 272.

[0056] The PMD layer 274 is formed above the top surface 210 of the substrate 208. The PMD layer 274 may include one or more dielectric layers, such as silicon nitride, silicon oxynitride, silicon dioxide, etc. In some examples, the PMD layer 274 includes a PMD liner and a main dielectric sublayer formed on the PMD liner. Subsequently, the PMD layer 274 may be planarized by a CMP process. Contacts 276 (such as tungsten plugs) are formed in the PMD layer 274 to provide electrical connections to the source region 258 and the drain region 260. An interconnect 278 electrically connected to the contact 276 is formed above the PMD layer 274 using any suitable metallization scheme, and provides electrical contact between the DENMOS transistor 202 and other components of the microelectronic device 200.

[0057] Figure 3A and Figure 3B is a representation of an exemplary microelectronic device 300 including a DENMOS transistor 302 having different voltages applied to a drain region 360. Figure 3A , the DENMOS transistor 302 is in a state where the source region 358 is at zero applied voltage 392, the drain region 360 is at zero voltage 396, the gate electrode 328 is at zero voltage 394, and the body region 306 is at zero voltage 399. The source region 358, the drain region 360, and the gate electrode 328 are all connected in parallel to ground 390. There is a narrow depletion region with charge donor space 317 and acceptor charge space 363 at the interface between the n-drift region 316 and the body region 306. Other narrow depletion regions not shown for simplicity include a narrow depletion region between the source region 358 and the body region 306, and a narrow depletion region between the third portion 320 and the second portion 322. Figure 3A, each of the doped regions of the DENMOS transistor 302 has a dopant concentration when it is doped, such as the third portion 320 being heavily n-type doped, the second portion 322 being heavily p-type doped, and the first portion 324 being very lightly p-type doped. No potential is applied to the system that disturbs the carrier distribution in any doped region to deviate from the formed state. Figure 3A Other components of include interconnects 378 , contacts 376 , PMD layer 374 , silicide blocking layer 370 , silicide layer 372 , sidewalls 348 , top surface 310 , and gate dielectric layer 318 .

[0058] Figure 3B The DENMOS transistor 302 is shown in a blocking state, wherein the drain region 360 is held at a high reverse bias 398, wherein a zero voltage 392 is applied to the source region 358, a zero voltage 394 is applied to the gate electrode 328, and a zero voltage is applied to the body region 306, all of which are connected in parallel to ground 390. It may be advantageous in the DENMOS transistor 302 to have a first portion 324 that is a lightly doped resurf region of the opposite type to the drain region 360, in that in this configuration, the majority carriers in the drain end of the gate electrode may be depleted under the action of the electric field caused by the reverse bias state of the drain region 360. When the drain region 360 is at a high reverse bias 398, the lightly doped (less than 1×10 13 cm -2 The doping of the gate electrode 328 with a dose of 0.1 % (or 0.1 % of the dose) allows a substantial portion of the gate electrode 328 to be depleted, thereby turning the first portion 324 of the gate electrode 328 into a charged dielectric region that balances the exposed charge in the underlying silicon due to the opposite doping sign. The cylinder 331 resembles a Gaussian pillbox, where the charge of the portion of the cylinder 331 in the first portion 324 is equivalent to the charge in the portion of the cylinder 331 in the n-drift region 316. The high reverse bias 398 on the drain region forms an electron donor region 361 and a donor charge space 317. The first portion 324 and a portion of the body region 306 form acceptor charge spaces 326 and 363, respectively, balancing the donor charge space 317. The charge balance between the donor charge space 317 and the acceptor charge space 363 and the resurf region acceptor charge space 326 mitigates the high surface electric field over the entire overlap region between the drain doping distribution and the gate electrode 328, thereby enabling the DENMOS transistor 302 to operate at a high blocking drain voltage with a high reverse bias 398 on the drain region 360 without the degenerative effects of high local electric fields, especially when operating in a pulsed mode.

[0059] The mutual depletion between the donor charge space 317, the acceptor charge space 363 and the resurf region acceptor charge space 326 is similar to the mutual depletion of the n-type layer and the p-type layer in the resurf drift region, so that the DENMOS transistor 302 using the lightly doped first portion 324 is called a depletable resurf gate electrode drain extended transistor.

[0060] Figure 3B Other components of include interconnects 378 , contacts 376 , PMD layer 374 , silicide blocking layer 370 , silicide layer 372 , sidewalls 348 , and top surface 310 .

[0061] FIG. 4A to FIG. 4G 4 and 5. The third type of electronic device to which the principles of the present disclosure may be advantageously applied is represented by the figures. These figures show a cross section of an exemplary microelectronic device 400 (e.g., a MOS transistor) including a depletable resurf gate electrode 428 (referred to herein as gate electrode 428). Figure 4B , and below). Without implicit limitation, in this example, gate electrode 428 is implemented in DENMOS transistor 402, which is shown in successive stages of an exemplary formation method. Other implementations of gate electrode 428 for DEPMOS transistors are within the scope of this example. In the exemplary DENMOS transistor 402, the dopant of the first conductivity type is an n-type dopant, and the dopant of the second conductivity type is a p-type dopant. For DENMOS transistor 402, the halo implant is used as a self-aligned implant.

[0062] Figure 4A The microelectronic device 400 including the DENMOS transistor 402 is shown after forming a gate dielectric layer 418 and a gate layer 420. The structures and methods within the microelectronic device 400 formed before the gate dielectric layer 418 is formed can include an epitaxial layer 406 over a base wafer 404, which together are referred to as a substrate 408 having a top surface 410. For example, the base wafer 404 can be a 1×10 17 cm -3 to 1×10 19 cm -3 Alternatively, the base wafer 404 may be lightly doped, with an average dopant concentration of less than 1×10 16 cm -3 As an example, the epitaxial layer 406 may have a thickness of 1×10 15 cm -3 to 1×10 16 cm -3Epitaxial layer 406 is optional, as in some examples, DENMOS transistor 402 may be formed directly in base wafer 404 .

[0063] The isolation layer for DENMOS transistor 402 may be formed by STI or LOCOS, either of which may be conventional, or formed by any future discovered method. The example shown includes an STI structure 412 .

[0064] A drift region 416 is formed in the substrate 408 in the epitaxial layer 406 and below a portion of the gate dielectric layer 418. One or more n-type implants are performed to form the drift region 416 (which may be referred to as an n-drift region) in the substrate 408. The n-type dopant that defines the n-drift region 416 may be implanted in one step or in multiple steps. For example, phosphorus may be implanted at 1×10 12 cm -2 With 1×10 13 cm -2 A total dose implant of between 100 and 1000 Å has an energy suitable for forming n-drift region 416 with or without subsequent thermal cycling. Arsenic may also be implanted at a similar dose, with an energy relatively less than the phosphorus implant.

[0065] Although not limited to the above Figure 4A 408 of the DENMOS transistor 402 as discussed in the above, but the gate dielectric layer 418 and the gate layer 420 are formed above the top surface 410. The gate dielectric layer 418 can be formed in a high temperature boiler operation or a rapid thermal process. Other methods of forming the gate dielectric layer 418 are within the scope of the present disclosure. The gate dielectric layer 418 can be any material and have any thickness suitable for the technical application. The gate layer 420 is formed on the gate dielectric layer 418 by conventional or future discovered methods. In the example shown, the gate layer 420 is formed by a deposition process of depositing polycrystalline silicon (polycrystalline silicon) (which may be referred to as polysilicon) using one or more silane-based precursors. In other examples, a replacement gate process can be used to form the gate layer 420. The gate layer 420 has a thickness that can be in the range of approximately 50nm to 300nm. The gate layer 420 can be undoped or in-situ doped when deposited. In this exemplary formation, the gate layer 420 is co-deposited with a p-type precursor (e.g., diborane, boron trichloride, tris(2,4-pentanedione)gallium(III)) such that the p-type dopant dose (e.g., the integral of the net p-type doping concentration through the thickness of the gate electrode) is between 1×10 12 cm -2 With 1×10 13 cm -2The low doping concentration in the gate layer 420 provides a resurf region to be defined at a later stage of processing.

[0066] The gate layer 420 may also be a polycrystalline SiGe layer, a polycrystalline Ge layer, a polycrystalline SiC layer, or another semiconductor that may be grown or deposited on the gate dielectric.

[0067] Figure 4B A cross section of the DENMOS transistor 402 is shown after a gate resist 424 has been formed and after a gate plasma etch 426. The gate plasma etch 426 removes the previously formed gate dielectric layer 418 and gate layer 420 in areas not covered by the gate resist 424. The area below the gate resist 424 defines a gate electrode 428, which is the gate layer 420 and gate dielectric layer 418 remaining after the gate plasma etch 426. After the gate plasma etch 426 is completed, the gate resist 424 is removed and a wet or dry process may be used to clean the wafer surface.

[0068] refer to Figure 4C , forming a halo implant resist 430. Self-aligned halo implants 434 may implant p-type and n-type ions through halo resist openings 432 to form several implant regions of DENMOS transistor 402. Self-aligned halo implants 434 may consist of one or more p-type implants and one or more n-type implants. Some of the p-type implants may be tilted up to 45 degrees to implant p-type ions into the vertical surface of gate electrode 428. P-type halo regions 436 and p-type gate regions 440 are implanted with p-type dopants that may include boron and / or indium. After thermal annealing, p-type halo regions 436 may have a 1×10 19 cm -3 or greater peak dopant density. The p-type gate region 440 may have a peak dopant density of 3×10 16 cm -3 With 1×10 19 cm -3 The p-type halo region 436 (in some instances in conjunction with the epitaxial layer 406) may be referred to as the body region (eg, P-type body region) of the DENMOS transistor 402. After thermal annealing, the p-type gate region 440 forms a second portion 446 of the gate electrode 428 (at Figure 4D It may be advantageous to use the self-aligned halo implant 434 instead of the DWELL implant in the case where the microelectronic device 400 does not require the DWELL implant for other components (not specifically shown). Figures 1A to 1G Self-aligned DWELL implant 434 of the exemplary device described in.

[0069] Additionally, in substrate 408, self-aligned halo implant 434 forms an n-type implant for n-type lightly doped drain region 438. N-type lightly doped drain region 438 is doped with an n-type dopant that may include, for example, phosphorus or arsenic. N-type lightly doped drain region 438 may have a 3×10 16 cm -3 With 1×10 19 cm -3 After the self-aligned halo implant 434, the halo implant resist 430 is removed.

[0070] refer to Figure 4D , a thermal annealing step 444 may be used to activate the implant species and diffuse the implant species from the self-aligned halo implant 434 to form a DWELL 437. The DWELL 437 extends to the top surface 410 between the n-type well region 438 and the drift region 416, thereby providing a channel region 439 of the microelectronic device 400. A boiler or RTA process may be used as a heat source for the thermal annealing step 444. In the substrate 408, the thermal annealing provides a thermal budget for the p-type boron of the p-type lightly doped drain region 436 to diffuse through the n-type dopant of the n-type lightly doped drain region 438 to form a channel profile in the lateral direction. In the gate electrode 428, the thermal annealing step 444 utilizes the higher diffusion constant of the p-type boron in the p-type gate region 440, thereby remaining in the second portion 446 having the horizontal gradient of p-type doping and the heavily p-type doped p-type gate region 440 after the thermal treatment.

[0071] exist Figure 4D In the remaining discussion of the present invention, the portions 420, 446 of the gate electrode 428 may be referred to as the first portion 420 and the second portion 446, respectively. In the first portion 420 (resurf region) of the gate electrode 428, the p-type doping density is low enough to allow depletion during operation of the DENMOS transistor 402 and allow it to act as a resurf region. The second portion 446 of the gate electrode 428 is heavily p-type doped in the p-type gate region 440 with a horizontal gradient toward a lighter doping until it is equivalent to the doping of the first portion 420 at the interface between the second portion 446 and the first portion 420. The heavily doped p-type gate region 440 of the second portion 446 of the gate electrode is closest to the source and acts as a switching region for the DENMOS transistor 402.

[0072] refer to Figure 4E, sidewall spacers 448 may be formed on the vertical surface of gate electrode 428 and may extend 50 nm to 200 nm from the lateral edge of gate electrode 428. After forming sidewall spacers 448, a first source / drain resist 450 is deposited and patterned. A first source / drain implant 456 implants n-type dopants into substrate 408 through source opening 452 and drain opening 454 to implant source region 458 and drain region 460. The first source / drain implant 456 may include one or more implantation steps, provided that the resulting dopant concentration of source region 458 and drain region 460 has a peak value of 1×10 19 cm -3 With 1×10 21 cm -3 . The source region 458 and the drain region 460 contain at least twice the average dopant density of the epitaxial layer 406, with a peak doping density between 0.15 μm and 0.5 μm from the top surface 410. The source / drain resist extension 461 extends the first source / drain resist 450 past the end of the gate electrode 428 toward the drain region 460. The source / drain resist extension 461 prevents n-type dopants from the first source / drain implant 456 from extending under the gate electrode 428 after a subsequent thermal annealing process. After forming the source region 458 and the drain region 460, the source / drain resist 450 is removed and the wafer is thermally annealed (not specifically shown).

[0073] Figure 4F 4 is a cross-section of the DENMOS transistor 402 after the second source / drain implant resist 462 is deposited and patterned to form a second source / drain resist opening 464 for a second source / drain implant 466. The second source / drain implant 466 can implant dopants for a second source / drain region of a p-channel device (not specifically shown) for the microelectronic device 400. In addition, the second source / drain implant 466 implants p-type dopants through the second source / drain resist opening 464 to form a back gate region 468 of the DENMOS transistor 402. In addition, the second source / drain implant resist 462 can contain additional resist openings (not specifically shown) above the p-type gate region 440, which allows the second source / drain implant 466 to implant additional p-type dopants into the p-type gate region 440.

[0074] As with the first source / drain implant 456, the second source / drain implant 466 may occur in one or more steps. The second source / drain implant 466 may implant a substance including boron (or indium) with a total dose and energy such that it provides degenerate doping, for example with greater than 1×10 19 cm -3The active average dopant density is near the solubility limit of the dopant atoms in the back gate region 468. After the second source / drain implant 466, the second source / drain implant resist 462 is removed.

[0075] Figure 4G A cross section of a DENMOS transistor 402 is shown after the first level of interconnect 478 is completed. In some examples, a silicide blocking layer 470 may be formed over a first portion 420 of a gate electrode 428, extending partially over a second portion 446 of the gate electrode 428 and leaving an area of ​​the second portion 446 not covered by the silicide blocking layer 470. The silicide blocking layer 470 may be formed by depositing one or more sub-layers of oxide, nitride, oxynitride, or any combination thereof over the entire wafer and patterning to open areas where silicide formation is desired. In some examples, a metal silicide layer 472 may be formed over the source region 458, the drain region 460, the back gate region 468, and the exposed portion of the gate electrode 428. The metal silicide layer 472 may provide an ohmic electrical connection to the source region 458, the drain region 460, the back gate region 468, and the gate electrode 428 with a lower resistance than a similar microelectronic device without the metal silicide layer 472.

[0076] The PMD layer 474 is formed above the top surface 410 of the substrate 408. The PMD layer 474 may include one or more dielectric layers, such as silicon nitride, silicon oxynitride, silicon dioxide, etc. In some examples, the PMD layer 474 includes a PMD liner and a main dielectric sublayer formed on the PMD liner. Subsequently, the PMD layer 474 may be planarized by a CMP process. Contacts 476 (such as tungsten plugs) are formed in the PMD layer 474 to provide electrical connections to the source region 458 and the drain region 460. An interconnect 478 electrically connected to the contact 476 is formed above the PMD layer 474 using any suitable metallization scheme, and provides electrical contact between the DENMOS transistor 402 and other components of the microelectronic device 400.

[0077] Although various examples of the present disclosure have been described above, it should be understood that the examples have been presented only by way of example and not by way of limitation. Thus, although the aforementioned examples of using various resist layers (e.g., photoresists or photomask layers) to perform various process steps (e.g., implantation steps or etching steps) have been described, the present disclosure is not limited thereto. For example, one or more hard masks (comprising one or more layers) may be patterned to define various regions (e.g., regions for receiving dopant atoms, regions for blocking etchants) for subsequent process steps to be applied. In addition, in some examples, the resist layer may include a multilayer resist instead of a single layer resist. Without departing from the spirit or scope of the present disclosure, numerous changes may be made to the disclosed examples according to the disclosure herein. Therefore, the breadth and scope of the present disclosure should not be limited by any of the examples described above. In fact, the scope of the present disclosure should be defined according to the appended claims and their equivalents.

Claims

1. A microelectronic device comprising: source and drain regions having a first conductivity type extending into a semiconductor substrate having an opposite second conductivity type; a channel region having the first conductivity type extending between the source region and the drain region; as well as A gate electrode is above the channel region and has a first portion and a second portion having the second conductivity type, the first portion having a first dopant concentration, and the second portion extends from the first portion toward the source region and has a second higher dopant concentration, the second higher dopant concentration increasing from the first portion toward the source region.

2. The microelectronic device according to claim 1 further comprises a drain drift region of the first conductivity type, the drain drift region extending from the drain region toward the source region below the first portion, the drain drift region having an average dopant concentration smaller than an average dopant concentration of the drain region. The microelectronic device of claim 1 , wherein the channel region is a portion of a DWELL having the second conductivity type.

4. The microelectronic device according to claim 1, wherein the second portion has a thickness greater than 1×10 18 cm -3 The second dopant concentration of the first portion is less than 1×10 13 cm -2 A first dopant dose of .

5. The microelectronic device of claim 1, further comprising a silicide blocking layer over the first portion of the gate electrode. 6 . The microelectronic device of claim 1 , wherein a third portion of the gate electrode extends from the second portion toward the source region, the third portion having the first conductivity type.

7. A method of forming a microelectronic device, comprising: forming a gate electrode over a semiconductor substrate, the gate electrode having a source terminal and a drain terminal, a first portion of the gate electrode extending from the drain terminal toward the source terminal, a second portion extending from the first portion toward the source terminal, and a third portion extending from the second portion to the source terminal; simultaneously implanting a first dopant of a first conductivity type in the third portion of the gate electrode and in the semiconductor substrate adjacent to the source terminal of the gate electrode; Simultaneously implanting a second dopant of a second opposite conductivity type in the third portion of the gate electrode and in the semiconductor substrate adjacent to the source terminal of the gate electrode; as well as The gate electrode is thermally annealed to diffuse the dopant of the second conductivity type from the third portion of the gate electrode into the second portion, thereby causing the second portion of the gate electrode to have a horizontal dopant concentration gradient between the first and third portions of the gate electrode.

8. The method of claim 7, further comprising forming a source region of the first conductivity type spaced apart from the source end of the gate electrode, and a drain region of the first conductivity type spaced apart from the drain end of the gate electrode.

9. The method according to claim 8 further includes forming a drain drift region in the semiconductor substrate, wherein the drain drift region has the first conductivity type, extends from the drain region toward the source region and ends under the first portion of the gate electrode, and the drain drift region has an average dopant concentration that is smaller than the average dopant concentration of the drain region.

10. The method of claim 7, wherein a field plate extends from the drain end of the first portion of the gate electrode toward a drain region, and the method further comprises forming a field release dielectric layer between the field plate and a drain drift region, the field release dielectric layer having a thickness greater than a thickness of a gate dielectric layer.

11. The method according to claim 7, wherein the first dopant has a ratio of 10 13 cm -2 A small dopant dose is implanted, and the second portion of the gate electrode has a thickness greater than 10 18 cm -3 An average second dopant concentration of . 12 . The method of claim 7 , further comprising forming a silicide blocking layer over the first portion of the gate electrode.

13. The method of claim 7, further comprising forming an inorganic anti-reflective coating over the gate electrode.

14. A method of forming a microelectronic device, comprising: forming a source region and a drain region having a first conductivity type extending into a semiconductor substrate having an opposite second conductivity type; forming a gate electrode having opposing first and second ends above the semiconductor substrate between the source region and the drain region, wherein a first portion of the gate electrode extends from the first end toward the source region and a second portion of the gate electrode extends from the second end toward the drain region; doping the first portion of the gate electrode to have the second conductivity type; implanting a dopant of the second conductivity type into the second portion at the second end of the gate electrode and into the semiconductor substrate adjacent the second end; as well as The gate electrode is thermally annealed to diffuse the dopant of the second conductivity type in the second portion of the gate electrode toward the first end, thereby providing a horizontal gradient of the dopant in the second portion.

15. The method according to claim 14 further includes forming a drain drift region in the semiconductor substrate, wherein the drain drift region has the first conductivity type, extends from the drain region toward the source region, and extends below the first portion of the gate electrode, and the drain drift region has an average dopant concentration that is smaller than the average dopant concentration of the drain region.

16. The method of claim 14, wherein a field plate extends from the first portion of the gate electrode toward the drain region, and the method further comprises forming a field release dielectric layer between the field plate and a drain drift region, the field release dielectric layer having a thickness greater than that of a gate dielectric layer.

17. The method according to claim 14, wherein the second portion has a thickness greater than 1×10 18 cm -3 The average second dopant concentration of the first portion is less than 1×10 13 cm -2 An average first dopant dose of .

18. The method of claim 14, further comprising forming a silicide blocking layer over the first portion of the gate electrode.

19. The method of claim 14, further comprising implanting a dopant of the first conductivity type in the second portion of the gate electrode, thereby forming a doped region of the gate electrode having the first conductivity type extending from the second end toward the first end.

20. The method of claim 14, wherein the dopant is implanted through an inorganic anti-reflective coating.

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