Gallium oxide-based power device and preparation method thereof

Abstract

The invention discloses a gallium oxide-based power device and a preparation method thereof, and relates to the field of semiconductor devices.The device comprises a cathode layer, an n-type gallium oxide substrate and an n-type gallium oxide epitaxial layer which are sequentially stacked from bottom to top; the p-type semiconductor layer, the first field limiting ring and the second field limiting ring are sequentially arranged on the n-type gallium oxide epitaxial layer at intervals and respectively form PN junctions with the n-type gallium oxide epitaxial layer; the first dielectric layer is positioned on the n-type gallium oxide epitaxial layer, the second field limiting ring, the first field limiting ring and the p-type semiconductor layer; the first anode layer is positioned on the p-type semiconductor layer and the first dielectric layer; in the horizontal direction, the projection of the end part of one end, far away from the p-type semiconductor layer, of the first anode layer on the n-type gallium oxide epitaxial layer is located in the projection of the first field limiting ring on the n-type gallium oxide epitaxial layer; the second dielectric layer is positioned on the first dielectric layer and the first field plate; and the second anode layer is positioned on the first anode layer and the second medium. The device has relatively high breakdown voltage and relatively good voltage resistance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a gallium oxide-based power device and a preparation method thereof. Background Art

[0002] As a typical representative of the new generation of ultra-wide bandgap semiconductor materials, gallium oxide (Ga2O3) has an ultra-wide bandgap of about 4.8eV and an ultra-high critical breakdown field strength of about 8MV / cm. Therefore, in theory, gallium oxide-based power devices can obtain a Baliga figure of merit of more than 3000, which is 4 times that of gallium nitride (GaN)-based power devices and 10 times that of silicon carbide (SiC)-based power devices, and has the application prospects of ultra-high withstand voltage and ultra-high power density. At the same time, unlike SiC and GaN, two third-generation semiconductor substrate materials that can only be grown by vapor phase method, gallium oxide substrate materials can be grown by melt method, so it has both high quality and low cost application potential.

[0003] However, due to the lack of effective P-type doping in gallium oxide materials, the mature terminal technology in silicon (Si) or SiC-based power devices cannot be directly applied to gallium oxide-based power devices, resulting in significant electric field concentration in the device terminal area, which reduces the breakdown voltage of the device. Therefore, based on the unique material properties of gallium oxide, the development of terminal technology and preparation process suitable for gallium oxide-based power devices is of great significance to improving device performance.

[0004] Therefore, the prior art still needs to be improved and developed. Summary of the invention

[0005] Based on the above-mentioned deficiencies of the prior art, an object of the present invention is to provide a gallium oxide-based power device and a preparation method thereof, aiming to solve the problem that the breakdown voltage of the existing gallium oxide-based power devices still needs to be improved.

[0006] The technical solution of the present invention is as follows:

[0007] A first aspect of the present invention provides a gallium oxide-based power device, wherein the gallium oxide-based power device comprises a cathode layer, an n-type gallium oxide substrate and an n-type gallium oxide epitaxial layer stacked in sequence from bottom to top;

[0008] The gallium oxide-based power device further comprises:

[0009] A p-type semiconductor layer, a second field limiting ring, and a first field limiting ring located between the p-type semiconductor layer and the second field limiting ring, wherein the p-type semiconductor layer, the first field limiting ring, and the second field limiting ring are arranged on the n-type gallium oxide epitaxial layer at intervals and form PN junctions with the n-type gallium oxide epitaxial layer respectively;

[0010] A first dielectric layer is continuously disposed on a surface of the n-type gallium oxide epitaxial layer, a surface of the second field limiting ring, a surface of the first field limiting ring, and a portion of a surface of the p-type semiconductor layer;

[0011] A first anode layer is continuously located on the surface of the p-type semiconductor layer and on a portion of the surface of the first dielectric layer, and the portion of the first anode layer located on the portion of the surface of the first dielectric layer is a first field plate; in a horizontal direction, a projection of an end of the first field plate away from one end of the p-type semiconductor layer on the n-type gallium oxide epitaxial layer is located within a projection of the first field limiting ring on the n-type gallium oxide epitaxial layer;

[0012] A second dielectric layer is continuously disposed on the surface of the first dielectric layer and on a portion of the surface of the first field plate;

[0013] The second anode layer is continuously disposed on the surface of the first anode layer and on a portion of the surface of the second dielectric layer.

[0014] Optionally, a portion of the second anode layer located on the surface of a portion of the second dielectric layer is a second field plate; in the horizontal direction, a projection of an end of the second field plate away from one end of the p-type semiconductor layer on the n-type gallium oxide epitaxial layer is located within a projection of the second field limiting ring on the n-type gallium oxide epitaxial layer.

[0015] Optionally, the thickness of the n-type gallium oxide substrate is 50 to 650 μm;

[0016] The n-type gallium oxide substrate is a highly doped n-type gallium oxide substrate with a doping concentration of 10 18 ~10 20 cm -3 ;

[0017] The thickness of the n-type gallium oxide epitaxial layer is 2 to 20 μm;

[0018] The n-type gallium oxide epitaxial layer is a low-doped n-type gallium oxide epitaxial layer with a doping concentration of 10 15 ~10 17 cm -3 .

[0019] Optionally, the thickness of the p-type semiconductor layer is 100-1000 nm; the p-type semiconductor layer includes at least one of p-type nickel oxide, p-type diamond, p-type silicon carbide, p-type gallium nitride and p-type gallium oxide.

[0020] Optionally, the thickness of the first field limiting ring is 100-1000 nm; the first field limiting ring includes at least one of p-type nickel oxide, p-type diamond, p-type silicon carbide, p-type gallium nitride and p-type gallium oxide.

[0021] Optionally, the thickness of the second field limiting ring is 100-1000 nm; the second field limiting ring includes at least one of p-type nickel oxide, p-type diamond, p-type silicon carbide, p-type gallium nitride and p-type gallium oxide.

[0022] Optionally, the thickness of the first dielectric layer is 50 nm to 2 μm; and the first dielectric layer includes at least one of silicon oxide, silicon nitride, aluminum oxide and hafnium oxide.

[0023] Optionally, the thickness of the second dielectric layer is 50 nm to 2 μm; and the second dielectric layer includes at least one of silicon oxide, silicon nitride, aluminum oxide and hafnium oxide.

[0024] Optionally, the cathode layer includes at least one of Ti, Ni, Ag and Au;

[0025] The thickness of the first anode layer is 20 to 300 nm, and the first anode layer includes at least one of Ni, Al, Au, Mo and Pt;

[0026] The thickness of the second anode layer is 200 nm to 4 μm, and the second anode includes at least one of Ti, Al, Ag and Au.

[0027] A second aspect of the present invention provides a method for preparing the gallium oxide-based power device as described above, comprising the following steps:

[0028] Providing an n-type gallium oxide substrate;

[0029] forming an n-type gallium oxide epitaxial layer on the n-type gallium oxide substrate;

[0030] forming a cathode layer on a surface of the n-type gallium oxide substrate facing away from the n-type gallium oxide epitaxial layer;

[0031] Sequentially forming a p-type semiconductor layer, a first field limiting ring and a second field limiting ring which are spaced apart from each other on the surface of the n-type gallium oxide epitaxial layer;

[0032] Forming a first dielectric layer on the surface of the n-type gallium oxide epitaxial layer, on the surface of the second field limiting ring, on the surface of the first field limiting ring, and on a portion of the surface of the p-type semiconductor layer;

[0033] A first anode layer is formed on the surface of the p-type semiconductor layer and on a portion of the surface of the first dielectric layer; a portion of the first anode layer located on the portion of the surface of the first dielectric layer is a first field plate, and in a horizontal direction, a projection of an end of the first field plate away from an end of the p-type semiconductor layer on the n-type gallium oxide epitaxial layer is located within a projection of the first field limiting ring on the n-type gallium oxide epitaxial layer;

[0034] forming a second dielectric layer on the surface of the first dielectric layer and on a portion of the surface of the first field plate;

[0035] A second anode layer is formed on the surface of the first anode layer and on a portion of the surface of the second dielectric layer.

[0036] Beneficial effects: The arrangement of the p-type semiconductor layer, the first field limiting ring, and the second field limiting ring in the present invention can even out the electric field distribution in the terminal region of the device, that is, balance the surface electric field in the terminal region, increase the breakdown voltage of the device, and improve the withstand voltage performance of the device. In addition, the first field plate extends to the position on the first field limiting ring, which can flatten the electric field distribution between the p-type semiconductor layer and the first field limiting ring, further balance the electric field, further increase the breakdown voltage of the device, and further improve the withstand voltage performance of the device; at the same time, when the distance between the p-type semiconductor layer and the first field limiting ring is large, it can still play a role in optimizing the electric field, reducing the requirements for dimensional accuracy and processing difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 Schematic diagram of the structure of a gallium oxide-based power device in an embodiment of the present invention.

[0038] Figure 2 Schematic diagram of the preparation process of the gallium oxide power device in an embodiment of the present invention, wherein (a) is a schematic diagram of forming an n-type gallium oxide epitaxial layer and a cathode layer on both sides of an n-type gallium oxide substrate, respectively; (b) is a schematic diagram of sequentially forming a p-type semiconductor layer, a first field limiting ring and a second field limiting ring spaced apart on the surface of the n-type gallium oxide epitaxial layer; (c) is a schematic diagram of forming a first dielectric layer on the surface of the n-type gallium oxide epitaxial layer, on the surface of the first field limiting ring, on the surface of the second field limiting ring and on a portion of the surface of the p-type semiconductor layer; (d) is a schematic diagram of forming a first anode layer on the surface of the p-type semiconductor layer and on a portion of the surface of the first dielectric layer; (e) is a schematic diagram of forming a second dielectric layer on the surface of the first dielectric layer and on a portion of the surface of the first field plate; and (f) is a schematic diagram of forming a second anode layer on the surface of the first anode layer and on a portion of the surface of the second dielectric layer.

[0039] Figure 3 Schematic diagram of the structure of a gallium oxide-based power device with a field limiting ring.

[0040] Figure 4 Schematic diagram of the structure of a gallium oxide-based power device with double field plates.

[0041] Figure 5 The graphs are surface electric field distribution curves of a gallium oxide-based power device with a field limiting ring, a gallium oxide-based power device with a double field plate, and the gallium oxide-based power device in Example 1. Description of the drawings:

[0043] 1. cathode layer; 2. n-type gallium oxide substrate; 3. n-type gallium oxide epitaxial layer; 4. p-type semiconductor layer; 5. first field limiting ring; 6. second field limiting ring; 7. first dielectric layer; 8. first anode layer; 81. first field plate; 82. second part of the first anode layer; 9. second dielectric layer; 10. second anode layer; 101. second field plate; 102. second part of the second anode layer. DETAILED DESCRIPTION

[0044] The present invention provides a gallium oxide-based power device and a method for preparing the same. To make the purpose, technical solution and effect of the present invention clearer and more specific, the present invention is further described in detail below. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0045] Unless otherwise defined, all technical terms and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0046] The terms used herein such as “vertical”, “horizontal”, “upper”, “lower”, “left”, “right” and similar expressions are for illustrative purposes only and do not represent the only implementations.

[0047] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0048] If there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features.

[0049] An embodiment of the present invention provides a gallium oxide-based power device, wherein: Figure 1 As shown, the gallium oxide-based power device comprises a cathode layer 1, an n-type gallium oxide substrate 2 and an n-type gallium oxide epitaxial layer 3 which are stacked in sequence from bottom to top;

[0050] The gallium oxide-based power device further comprises:

[0051] A p-type semiconductor layer 4, a second field limiting ring 6, and a first field limiting ring 5 located between the p-type semiconductor layer 4 and the second field limiting ring 6, wherein the p-type semiconductor layer 4, the first field limiting ring 5, and the second field limiting ring 6 are arranged on the n-type gallium oxide epitaxial layer 3 at intervals and form PN junctions with the n-type gallium oxide epitaxial layer respectively;

[0052] A first dielectric layer 7 is continuously disposed on the surface of the n-type gallium oxide epitaxial layer 3, the surface of the second field limiting ring 6, the surface of the first field limiting ring 5, and a part of the surface of the p-type semiconductor layer 4 (the part of the surface mentioned in the present invention does not refer to the whole surface);

[0053] The first anode layer 8 is continuously located on the surface of the p-type semiconductor layer 4 and on a portion of the surface of the first dielectric layer 7. The portion of the first anode layer 8 located on the portion of the surface of the first dielectric layer 7 is the first field plate 81. Figure 1 ), the projection of the end (or end face) of the first field plate away from the p-type semiconductor layer on the n-type gallium oxide epitaxial layer is located in (or falls into) the projection of the first field limiting ring on the n-type gallium oxide epitaxial layer. That is, the rightmost end of the projection of the first field plate on the n-type gallium oxide epitaxial layer is located in the projection of the first field limiting ring on the n-type gallium oxide epitaxial layer;

[0054] A second dielectric layer 9 is continuously disposed on the surface of the first dielectric layer 7 and on a portion of the surface of the first field plate 81;

[0055] The second anode layer 10 is continuously disposed on the surface of the first anode layer 8 and on a portion of the surface of the second dielectric layer 9 .

[0056] In the embodiment of the present invention, the arrangement of the p-type semiconductor layer, the first field limiting ring, and the second field limiting ring can evenly distribute the electric field in the terminal region of the device, that is, balance the surface electric field in the terminal region, improve the breakdown voltage of the device, and improve the withstand voltage performance of the device. In addition, due to the advantage of the ultra-high critical breakdown field strength of gallium oxide, the electron concentration of the epitaxial layer of the gallium oxide-based power device is significantly higher than that of the Si or SiC-based power device at the same voltage level, so there is a more significant electric field curvature effect in the terminal region, which will require more precise size control of the field limiting ring to modulate the electric field distribution, greatly increasing the difficulty of regulation. In the embodiment of the present invention, extending the first field plate to the position above the first field limiting ring can not only flatten the electric field distribution between the p-type semiconductor layer and the first field limiting ring, further balance the electric field, further improve the breakdown voltage of the device, and further improve the withstand voltage performance of the device; at the same time, when the distance between the p-type semiconductor layer and the first field limiting ring is large, it can still play a role in optimizing the electric field, reducing the requirements for dimensional accuracy and processing difficulty.

[0057] In the embodiment of the present invention, the p-type semiconductor layer, the first field limiting ring and the second field limiting ring respectively form a PN junction with the n-type gallium oxide epitaxial layer, which is generally a heterogeneous PN junction, but can also be a homogeneous PN junction. The first anode layer includes two parts, namely a first part and a second part, wherein the first part of the first anode layer 8, namely the first field plate 81, is located on a partial surface of the first dielectric layer 7, and the second part 82 of the first anode layer is located on the p-type semiconductor layer 4. Specifically, in the horizontal direction, the second part 82 of the first anode layer is connected to the first dielectric layer 7. The first dielectric layer 7 is continuously located on the surface of the n-type gallium oxide epitaxial layer 3, the surface and side surface of the first field limiting ring 5, the surface and side surface of the second field limiting ring 6, and the side surface and partial surface of the p-type semiconductor layer 4.

[0058] In some embodiments, the portion of the second anode layer 10 located on the surface of the second dielectric layer 9 is the second field plate 101. Figure 1 ), the projection of the end (or end face) of the second field plate away from the p-type semiconductor layer on the n-type gallium oxide epitaxial layer is located in (or falls into) the projection of the second field limiting ring on the n-type gallium oxide epitaxial layer. That is, the rightmost end of the projection of the second field plate on the n-type gallium oxide epitaxial layer is located in the projection of the second field limiting ring on the n-type gallium oxide epitaxial layer.

[0059] In this embodiment, the second field plate extends to the position above the second field limiting ring, which can flatten the electric field distribution between the first field limiting ring and the second field limiting ring, further balance the electric field, further improve the breakdown electric field of the device, and further improve the voltage resistance performance of the device. At the same time, when the spacing between the first field limiting ring and the second field limiting ring is large, it can still play a role in optimizing the electric field, reducing the requirements for dimensional accuracy and the difficulty of processing. That is, the present invention simultaneously uses double field plates to balance the electric field between the junction field limiting rings, so that the different field limiting rings can still achieve high voltage resistance performance in the case of a larger size, reducing the difficulty of device preparation.

[0060] In this embodiment, the second anode layer includes two parts, namely a first part and a second part, wherein the first part of the second anode layer 10, namely the second field plate 101, is located on a partial surface of the second dielectric layer 9, and the second part 102 of the second anode layer is located on the surface of the first anode layer 8.

[0061] In some embodiments, the doping concentration (ie, electron concentration) of the n-type gallium oxide substrate is greater than that of the n-type gallium oxide epitaxial layer.

[0062] In some embodiments, the thickness of the n-type gallium oxide substrate is 50 to 650 μm (unless otherwise specified, the thickness referred to herein is as follows: Figure 1The thickness in the up-down direction shown) can be, for example, 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm or 650 μm, etc.

[0063] In some embodiments, the n-type gallium oxide substrate is a highly doped n-type gallium oxide substrate with a doping concentration (ie, electron concentration) of 10 18 ~10 20 cm -3 , for example, it can be 10 18 cm -3 , 5×10 18 cm -3 , 10 19 cm -3 , 5×10 19 cm -3 or 10 20 cm -3 In some specific embodiments, the highly doped n-type gallium oxide substrate includes n-type Si or Sn doped β-Ga2O3.

[0064] In some embodiments, the thickness of the n-type gallium oxide epitaxial layer is 2 to 20 μm, for example, 2 μm, 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, 18 μm or 20 μm.

[0065] In some embodiments, the n-type gallium oxide epitaxial layer is a low-doped n-type gallium oxide epitaxial layer, and the doping concentration (ie, electron concentration) is 10 15 ~10 17 cm -3 , for example, it can be 10 15 cm -3 , 5×10 15 cm -3 , 10 16 cm -3 , 5×10 16 cm -3 or 10 17 cm -3 In some specific embodiments, the low-doped n-type gallium oxide epitaxial layer includes n-type Si or Sn-doped β-Ga2O3.

[0066] In some embodiments, the thickness of the p-type semiconductor layer is 100 to 1000 nm, for example, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm or 1000 nm, etc.; the p-type semiconductor layer includes but is not limited to at least one of p-type nickel oxide, p-type diamond, p-type silicon carbide, p-type gallium nitride and p-type gallium oxide, and the doping concentration (i.e., hole concentration) is 10 16 ~10 19 cm -3 , for example, it can be 10 16 cm -3 , 5×10 16 cm -3 , 10 17 cm -3 , 5×10 17 cm -3 , 10 18 cm -3 , 5×10 18 cm -3 or 10 19 cm -3 wait.

[0067] In some embodiments, the thickness of the first field limiting ring is 100-1000 nm, for example, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm or 1000 nm, etc.; the first field limiting ring includes but is not limited to at least one of p-type nickel oxide, p-type diamond, p-type silicon carbide, p-type gallium nitride and p-type gallium oxide, and the doping concentration (i.e., hole concentration) is 10 16 ~10 19 cm -3 , for example, it can be 10 16 cm -3 , 5×10 16 cm -3 , 10 17 cm -3 , 5×10 17 cm -3 , 10 18 cm -3 , 5×10 18 cm -3 or 10 19 cm -3 wait.

[0068] In some embodiments, the thickness of the second field limiting ring is 100-1000 nm, for example, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm or 1000 nm, etc.; the second field limiting ring includes but is not limited to at least one of p-type nickel oxide, p-type diamond, p-type silicon carbide, p-type gallium nitride and p-type gallium oxide, and the doping concentration (i.e., hole concentration) is 10 16 ~10 19 cm -3 , for example, it can be 10 16 cm -3 , 5×10 16 cm -3 , 10 17 cm -3 , 5×10 17 cm -3 , 10 18 cm -3 , 5×10 18 cm -3 or 10 19 cm -3 wait.

[0069] In some embodiments, the thickness of the first dielectric layer is 50nm-2μm (that is, the thickness of all parts of the first dielectric layer is 50nm-2μm, the thickness of the part of the first dielectric layer located on the surface of the n-type gallium oxide epitaxial layer is 50nm-2μm, the thickness of the part of the first dielectric layer located on the surface of the second field limiting ring is 50nm-2μm, the thickness of the part of the first dielectric layer located on the side of the second field limiting ring in the left-right direction is 50nm-2μm, the thickness of the part of the first dielectric layer located on the surface of the first field limiting ring is 50nm-2μm, the thickness of the part of the first dielectric layer located on the side of the first field limiting ring in the left-right direction is 50nm-2μm, The thickness of a portion of the first dielectric layer located on the surface of the p-type semiconductor layer is 50nm~2μm, and the thickness of a portion of the first dielectric layer located on the side of the p-type semiconductor layer in the left-right direction is 50nm~2μm), for example, it can be 50nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 1.2μm, 1.5μm, 1.8μm or 2μm, etc.; the first dielectric layer includes at least one of silicon oxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3) and hafnium oxide (HfO2), but is not limited thereto.

[0070] In some embodiments, the thickness of the second dielectric layer is 50nm~2μm (that is, the thickness of all parts of the second dielectric layer is 50nm~2μm, the thickness of the part of the second dielectric layer located on the first dielectric layer is 50nm~2μm, and the thickness of the part of the second dielectric layer located on the first anode layer is 50nm~2μm), for example, it can be 50nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 1.2μm, 1.5μm, 1.8μm or 2μm, etc.; the second dielectric layer includes at least one of silicon oxide, silicon nitride, aluminum oxide and hafnium oxide, but is not limited thereto.

[0071] When the first dielectric layer and the second dielectric layer are made of the above materials, the electric field distribution on the surface of the device can be further uniformed, thereby improving the voltage resistance performance of the device.

[0072] In some embodiments, the thickness of the cathode layer is 150nm to 1.5μm, for example, it can be 150nm, 300nm, 500nm, 800nm, 1μm, 1.1μm, 1.2μm, 1.3μm, 1.4μm or 1.5μm, and the cathode layer includes at least one of Ti, Ni, Ag and Au, but is not limited thereto.

[0073] In some embodiments, the thickness of the first anode layer is 20 to 300 nm (i.e., the thickness of all parts of the first anode layer is 20 to 300 nm, the thickness of the part of the first anode layer located on the p-type semiconductor layer is 20 to 300 nm, and the thickness of the part of the first anode layer located on the first dielectric layer is 20 to 300 nm), for example, it can be 20 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm or 300 nm; the first anode layer includes at least one of Ni, Al, Au, Mo and Pt, but is not limited thereto.

[0074] In some embodiments, the thickness of the second anode layer is 200nm~4μm (that is, the thickness of all parts of the second anode layer is 200nm~4μm, the thickness of the part of the second anode layer located on the first anode layer is 200nm~4μm, and the thickness of the part of the second anode layer located on the second dielectric layer is 200nm~4μm), for example, it can be 200nm, 250nm, 300nm, 500nm, 700nm, 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm or 4μm, and the second anode includes at least one of Ti, Al, Ag and Au, but is not limited to this.

[0075] The embodiment of the present invention further provides a method for preparing a gallium oxide-based power device, which comprises the following steps:

[0076] S1, such as Figure 2 As shown in (a), an n-type gallium oxide substrate 2 is provided;

[0077] S2, such as Figure 2 As shown in (a), an n-type gallium oxide epitaxial layer 3 is formed on the n-type gallium oxide substrate 2;

[0078] S3, such as Figure 2 As shown in (a), a cathode layer 1 is formed on the surface of the n-type gallium oxide substrate 2 away from the n-type gallium oxide epitaxial layer 3;

[0079] S4, such as Figure 2 As shown in (b), a p-type semiconductor layer 4, a first field limiting ring 5 and a second field limiting ring 6 are sequentially formed on the surface of the n-type gallium oxide epitaxial layer 3;

[0080] S5, such as Figure 2 As shown in (c), a first dielectric layer 7 is formed on the surface of the n-type gallium oxide epitaxial layer 3, on the surface of the second field limiting ring 6, on the surface of the first field limiting ring 5, and on a part of the surface of the p-type semiconductor layer 4;

[0081] S6, such as Figure 2 As shown in (d), a first anode layer 8 is formed on the surface of the p-type semiconductor layer 4 and on a portion of the surface of the first dielectric layer 7; the portion of the first anode layer 8 located on the portion of the surface of the first dielectric layer 7 is a first field plate 81;

[0082] S7, such as Figure 2 As shown in (e), a second dielectric layer 9 is formed on the surface of the first dielectric layer 7 and on a portion of the surface of the first field plate 81;

[0083] S8, such as Figure 2 As shown in (f), a second anode layer 10 is formed on the surface of the first anode layer 8 and a portion of the surface of the second dielectric layer 9. The portion of the second anode layer 10 located on the portion of the surface of the second dielectric layer 9 is the second field plate 101.

[0084] In step S1 , the selection of the material and thickness of the n-type gallium oxide substrate is specifically described above and will not be repeated here.

[0085] In step S2, the selection of the material and thickness of the n-type gallium oxide epitaxial layer is specifically described above and will not be repeated here.

[0086] In step S3, the selection of the material and thickness of the cathode layer can be referred to the above description, which will not be repeated here. Specifically, the cathode layer is formed by deposition using electron beam evaporation or magnetron sputtering.

[0087] In step S4, a p-type semiconductor is deposited on the surface of the n-type gallium oxide epitaxial layer by magnetron sputtering, pulsed laser deposition, metal thermal oxidation, MOCVD (metal organic chemical vapor deposition), or Mist-CVD (ultrasonic atomization assisted chemical vapor deposition), and after patterning (patterning can be performed by dry-wet combination or wet etching), a p-type semiconductor layer, a first field limiting ring, and a second field limiting ring are obtained respectively.

[0088] In step S5, the first dielectric layer material (the first dielectric layer material includes but is not limited to at least one of silicon oxide, silicon nitride, aluminum oxide and hafnium oxide) can be deposited by PECVD (plasma enhanced chemical vapor deposition), ALD (atomic layer deposition), LPCVD (low pressure chemical vapor deposition), pulsed laser deposition, magnetron sputtering and the like, and then a hole is opened by a combination of dry and wet etching or wet etching to obtain the first dielectric layer.

[0089] In step S6, specifically, the first anode metal (the first anode metal includes but is not limited to at least one of Ni, Al, Au, Mo and Pt) is deposited by electron beam evaporation or magnetron sputtering, and then patterned by a lift-off process to form a first anode layer.

[0090] In step S7, the second dielectric layer material (the second dielectric layer material includes but is not limited to at least one of silicon oxide, silicon nitride, aluminum oxide and hafnium oxide) can be deposited by PECVD, ALD, LPCVD, pulsed laser deposition, magnetron sputtering and the like, and then holes are opened by a combination of dry and wet etching or wet etching to obtain the second dielectric layer.

[0091] In step S8, specifically, the second anode metal (the second anode metal includes but is not limited to at least one of Ti, Al, Ag and Au) is deposited by electron beam evaporation or magnetron sputtering, and then patterned by a lift-off process to form a second anode layer.

[0092] The present invention will be further described below by means of specific examples.

[0093] Example 1

[0094] This embodiment provides a gallium oxide-based power device, wherein: Figure 1 As shown, the gallium oxide-based power device comprises a cathode layer 1, an n-type gallium oxide substrate 2 and an n-type gallium oxide epitaxial layer 3 which are stacked in sequence from bottom to top; wherein the cathode layer comprises a Ti layer (100 nm thick), a Ni layer (300 nm thick) and an Ag layer (1 μm thick) which are stacked in sequence, and the Ti layer side is bonded to the n-type gallium oxide substrate; the thickness of the n-type gallium oxide substrate is 400 μm, specifically, an n-type Sn-doped β-Ga2O3 substrate, and the electron concentration is 10 20cm -3 The thickness of the n-type gallium oxide epitaxial layer is 10 μm, specifically, the n-type Si-doped β-Ga2O3 epitaxial layer, and the electron concentration is 10 16 cm -3 ;

[0095] The gallium oxide-based power device further comprises:

[0096] The p-type semiconductor layer 4, the second field limiting ring 6 and the first field limiting ring 5 located between the p-type semiconductor layer 4 and the second field limiting ring 6, the p-type semiconductor layer 4, the first field limiting ring 5 and the second field limiting ring 6 are arranged on the n-type gallium oxide epitaxial layer 3 at intervals, and form heterogeneous PN junctions with the n-type gallium oxide epitaxial layer 3 respectively; the thickness of the p-type semiconductor layer, the first field limiting ring and the second field limiting ring are all 500nm, the material thereof are all p-type nickel oxide, and the hole concentration is all 10 18 cm -3 ; In the left and right directions, the widths of the p-type semiconductor layer, the first field limiting ring, and the second field limiting ring are all 5μm, the gap between the p-type semiconductor layer and the first field limiting ring is 6μm, and the gap between the first field limiting ring and the second field limiting ring is 8μm. The overall width of the device (that is, the width of the n-type gallium oxide substrate) is 50μm;

[0097] A first dielectric layer 7 is continuously disposed on the surface of the n-type gallium oxide epitaxial layer 3, the surface of the second field limiting ring 6, the surface of the first field limiting ring 5, and a part of the surface of the p-type semiconductor layer 4; the first dielectric layer has a thickness of 1 μm and is made of SiO2;

[0098] The first anode layer 8 is continuously located on the surface of the p-type semiconductor layer 4 and on a portion of the surface of the first dielectric layer 7, and the portion of the first anode layer 8 located on the portion of the surface of the first dielectric layer 7 is the first field plate 81; the first anode layer is a Ni layer with a thickness of 100 nm; the rightmost end of the projection of the first field plate on the n-type gallium oxide epitaxial layer is located in the middle of the projection of the first field limiting ring on the n-type gallium oxide epitaxial layer.

[0099] A second dielectric layer 9 is continuously disposed on the surface of the first dielectric layer 7 and part of the surface of the first field plate 81; the second dielectric layer has a thickness of 1 μm and is made of Si3N4;

[0100] The second anode layer 10 is continuously located on the surface of the first anode layer 8 and on a partial surface of the second dielectric layer 9. The portion of the second anode layer 10 located on the partial surface of the second dielectric layer 9 is the second field plate 101. The second anode layer is an Al layer with a thickness of 1 μm. The rightmost end of the projection of the second field plate on the n-type gallium oxide epitaxial layer is located in the middle of the projection of the second field limiting ring on the n-type gallium oxide epitaxial layer.

[0101] In Example 1, a gallium oxide-based power device with a heterojunction field limiting ring and a double field plate and a gallium oxide-based power device with a field limiting ring (its structural schematic diagram is shown in FIG. Figure 3 As shown, it includes a cathode layer 1, an n-type gallium oxide substrate 2, and an n-type gallium oxide epitaxial layer 3 stacked in sequence from bottom to top; it also includes a p-type semiconductor layer 4, a first field limiting ring 5 and a second field limiting ring 6 sequentially spaced on the n-type gallium oxide epitaxial layer 3, a first dielectric layer 7 located on the surfaces of the n-type gallium oxide epitaxial layer 3, the second field limiting ring 6 and the first field limiting ring 5 and on a portion of the surface of the p-type semiconductor layer 4, a first anode layer 8 located on the surface of the p-type semiconductor layer 4 and on a portion of the surface of the first dielectric layer 7, and a second anode layer 10 located on the first anode layer 8, the rightmost end of the projection of the first anode layer 8 on the p-type semiconductor layer 4 is located in the p-type semiconductor layer 4, and the materials and thicknesses of the various layers are the same as those in Example 1), a gallium oxide-based power device with a double field plate (its structural schematic diagram is shown in Figure 4 As shown, it includes a cathode layer 1, an n-type gallium oxide substrate 2, and an n-type gallium oxide epitaxial layer 3 which are stacked in sequence from bottom to top; it also includes a p-type semiconductor layer 4 located on the n-type gallium oxide epitaxial layer 3, a first dielectric layer 7 located on the surface of the n-type gallium oxide epitaxial layer 3 and on a portion of the surface of the p-type semiconductor layer 4, a first anode layer 8 located on the surface of the p-type semiconductor layer 4 and on a portion of the surface of the first dielectric layer 7, a second dielectric layer 9 located on the surface of the first dielectric layer 7 and on a portion of the surface of the first anode layer 8, and a second anode layer 10 located on the surface of the first anode layer 8 and on a portion of the surface of the second dielectric layer 9, and the materials and thicknesses of the layers are the same as those in Example 1) as shown in the surface electric field distribution curve diagram as shown in Example 1 Figure 5 As shown, it can be seen that the electric field distribution of the gallium oxide-based power device with a field limiting ring and the gallium oxide-based power device with a double field plate is uneven, and the voltage resistance performance of the device is low. However, the terminal structure of the gallium oxide-based power device in Example 1 of the present invention can achieve a more uniform electric field distribution and has a higher breakdown voltage.

[0102] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A gallium oxide-based power device, characterized in that: The gallium oxide-based power device comprises a cathode layer, an n-type gallium oxide substrate and an n-type gallium oxide epitaxial layer which are stacked in sequence from bottom to top; The gallium oxide-based power device further comprises: A p-type semiconductor layer, a second field limiting ring, and a first field limiting ring located between the p-type semiconductor layer and the second field limiting ring, wherein the p-type semiconductor layer, the first field limiting ring, and the second field limiting ring are arranged on the n-type gallium oxide epitaxial layer at intervals and form PN junctions with the n-type gallium oxide epitaxial layer respectively; A first dielectric layer is continuously disposed on a surface of the n-type gallium oxide epitaxial layer, a surface of the second field limiting ring, a surface of the first field limiting ring, and a portion of a surface of the p-type semiconductor layer; A first anode layer is continuously located on the surface of the p-type semiconductor layer and on a portion of the surface of the first dielectric layer, and the portion of the first anode layer located on the portion of the surface of the first dielectric layer is a first field plate; in a horizontal direction, a projection of an end of the first field plate away from one end of the p-type semiconductor layer on the n-type gallium oxide epitaxial layer is located within a projection of the first field limiting ring on the n-type gallium oxide epitaxial layer; A second dielectric layer is continuously disposed on the surface of the first dielectric layer and on a portion of the surface of the first field plate; The second anode layer is continuously disposed on the surface of the first anode layer and on a portion of the surface of the second dielectric layer.

2. The gallium oxide-based power device according to claim 1, characterized in that: The portion of the second anode layer located on the surface of the second dielectric layer is the second field plate; in the horizontal direction, the projection of the end of the second field plate away from the p-type semiconductor layer on the n-type gallium oxide epitaxial layer is located in the projection of the second field limiting ring on the n-type gallium oxide epitaxial layer.

3. The gallium oxide-based power device according to claim 1, characterized in that: The thickness of the n-type gallium oxide substrate is 50 to 650 μm; The n-type gallium oxide substrate is a highly doped n-type gallium oxide substrate with a doping concentration of 10 18 ~10 20 cm -3 ; The thickness of the n-type gallium oxide epitaxial layer is 2 to 20 μm; The n-type gallium oxide epitaxial layer is a low-doped n-type gallium oxide epitaxial layer with a doping concentration of 10 15 ~10 17 cm -3 .

4. The gallium oxide-based power device according to claim 1, characterized in that: The thickness of the p-type semiconductor layer is 100-1000 nm; the p-type semiconductor layer includes at least one of p-type nickel oxide, p-type diamond, p-type silicon carbide, p-type gallium nitride and p-type gallium oxide.

5. The gallium oxide-based power device according to claim 1, characterized in that: The thickness of the first field limiting ring is 100-1000 nm; the first field limiting ring includes at least one of p-type nickel oxide, p-type diamond, p-type silicon carbide, p-type gallium nitride and p-type gallium oxide.

6. The gallium oxide-based power device according to claim 1, characterized in that: The thickness of the second field limiting ring is 100-1000 nm; the second field limiting ring includes at least one of p-type nickel oxide, p-type diamond, p-type silicon carbide, p-type gallium nitride and p-type gallium oxide.

7. The gallium oxide-based power device according to claim 1, characterized in that: The thickness of the first dielectric layer is 50 nm to 2 μm; the first dielectric layer includes at least one of silicon oxide, silicon nitride, aluminum oxide and hafnium oxide.

8. The gallium oxide-based power device according to claim 1, characterized in that: The thickness of the second dielectric layer is 50 nm to 2 μm; the second dielectric layer includes at least one of silicon oxide, silicon nitride, aluminum oxide and hafnium oxide.

9. The gallium oxide-based power device according to claim 1, characterized in that: The cathode layer includes at least one of Ti, Ni, Ag and Au; The thickness of the first anode layer is 20 to 300 nm, and the first anode layer includes at least one of Ni, Al, Au, Mo and Pt; The thickness of the second anode layer is 200 nm to 4 μm, and the second anode includes at least one of Ti, Al, Ag and Au.

10. A method for preparing a gallium oxide-based power device according to claim 1, characterized in that: The steps include: Providing an n-type gallium oxide substrate; forming an n-type gallium oxide epitaxial layer on the n-type gallium oxide substrate; forming a cathode layer on a surface of the n-type gallium oxide substrate facing away from the n-type gallium oxide epitaxial layer; Sequentially forming a p-type semiconductor layer, a first field limiting ring and a second field limiting ring which are spaced apart from each other on the surface of the n-type gallium oxide epitaxial layer; Forming a first dielectric layer on the surface of the n-type gallium oxide epitaxial layer, on the surface of the second field limiting ring, on the surface of the first field limiting ring, and on a portion of the surface of the p-type semiconductor layer; A first anode layer is formed on the surface of the p-type semiconductor layer and on a portion of the surface of the first dielectric layer; a portion of the first anode layer located on the portion of the surface of the first dielectric layer is a first field plate, and in a horizontal direction, a projection of an end of the first field plate away from an end of the p-type semiconductor layer on the n-type gallium oxide epitaxial layer is located within a projection of the first field limiting ring on the n-type gallium oxide epitaxial layer; forming a second dielectric layer on the surface of the first dielectric layer and on a portion of the surface of the first field plate; A second anode layer is formed on the surface of the first anode layer and on a portion of the surface of the second dielectric layer.

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