Interlayer dielectric film forming method, semiconductor structure and chip
By forming a step-shaped gate structure in the semiconductor structure and performing multiple etchings, a side wall structure with narrow upper end and wide lower end is formed, which solves the hole problem caused by the small spacing between adjacent polysilicon gates and improves the yield of static random access memory.
Patent Information
- Application Number
- CN202411772741.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-04
- Publication Date
- 2025-04-01
AI Technical Summary
At technical nodes below 55nm and below, the design distance between adjacent polysilicon gates is small, resulting in holes generated during the filling process of high-density plasma interlayer dielectric layer processes, affecting contact hole etching and tungsten filling, and reducing the yield of static random access memory.
By forming a plurality of step-like protruding gate structures on the substrate, and forming an initial side wall structure on both sides of each gate structure, multiple dry and wet etching are performed to form a side wall structure with a narrow upper end and wide lower end, increasing the spacing between the side walls of the adjacent two gate structures, thereby reducing the generation of holes in the filling process of the interlayer dielectric layer process.
The spacing between the side walls of the adjacent two gate structures is increased, and the generation of holes in the high-density plasma interlayer dielectric layer process is reduced during the filling process, ensuring contact hole etching, filling of side wall barrier layer and filling of tungsten, and improving the yield of static random access memory.
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Figure CN119743992A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming an interlayer dielectric film, a semiconductor structure and a chip. Background Art
[0002] The high-density plasma interlayer dielectric layer process is the only process with filling performance among all film deposition processes of the interlayer dielectric layer. The quality of the process directly affects the subsequent etching and filling of the contact holes, and further affects the yield of the static random access memory.
[0003] At 55nm and below technology nodes, the design distance between adjacent polysilicon gates is getting smaller and smaller, and the filling requirements are getting higher and higher. If the distance is too small, the high-density plasma interlayer dielectric layer process will produce holes during the filling process, affecting the contact hole etching, and even affecting the filling of the contact hole sidewall barrier layer and the filling of tungsten, causing tungsten leakage, which reduces the yield of static random access memory. Summary of the invention
[0004] Aiming at the technical problem that the spacing between adjacent gate structure side walls in the prior art is small, a high-density plasma interlayer dielectric layer process generates holes during the filling process, which affects the contact hole etching and even affects the filling of the contact hole side wall barrier layer and the filling of tungsten, causing tungsten leakage, and reducing the yield of a static random access memory, the present invention provides an interlayer dielectric film forming method, a semiconductor structure and a chip. The interlayer dielectric film forming method can increase the spacing between two adjacent gate structure side walls, reduce the holes generated in the filling process of the high-density plasma interlayer dielectric layer process, ensure the contact hole etching, ensure the filling of the contact hole side wall barrier layer and the filling of tungsten, and improve the yield of the static random access memory.
[0005] To achieve the above-mentioned purpose, the first aspect of the present invention provides a method for forming an interlayer dielectric film, which comprises: after forming a plurality of gate structures, forming initial sidewall structures on both sides of each gate structure respectively; wherein the gate structure protrudes from the upper surface of the substrate in a step-like manner; the initial sidewall structure is a configuration with the same thickness from top to bottom; etching the initial sidewall structure multiple times to form a sidewall structure with a narrow upper end and a wide lower end; wherein the multiple etchings include dry etching and wet etching; and forming an interlayer dielectric film on the surface of the substrate, the gate structure and the sidewall structure.
[0006] Furthermore, the sidewall structure is a configuration in which the oblique edges are concave toward the gate structure.
[0007] Furthermore, the etching the initial sidewall structure multiple times includes: performing multiple steps of dry etching on the initial sidewall structure to form an intermediate sidewall; and performing at least one step of wet etching on the intermediate sidewall to form the sidewall structure.
[0008] Furthermore, the dry etching step includes three steps.
[0009] Furthermore, the etching conditions of the first step of dry etching include: the etching gas is CH 2 F 2 CF 4 and He, the etching gas flow rate is between 15sccm-100sccm, the bias power is between 30W-60W, the etching pressure is between 60mTorr-80mTorr, and the etching time is between 10s-15s.
[0010] Furthermore, the etching conditions of the second step dry etching include: the etching gas is CH 2 F 2 , CHF 3 , O 2 and He, the etching gas flow rate is between 45sccm-100sccm, the bias power is between 30W-60W, the etching pressure is between 20mTorr-40mTorr, and the etching time is between 5s-12s.
[0011] Furthermore, the etching conditions of the third step of dry etching include: the etching gas is CH 2 F 2 , CHF 3 , O 2 and He, the etching gas flow rate is between 80sccm-130sccm, the bias voltage is between 60V-80V, the etching pressure is between 35mTorr-55mTorr, and the etching time is between 5s-15s.
[0012] Furthermore, the wet etching step includes one step; the etching conditions of the wet etching include: the etching solution includes one or a combination of hydrofluoric acid solution and ammonia solution, the reaction temperature is between 20°C-25°C, and the reaction time is between 2min-4min.
[0013] Furthermore, before etching the initial sidewall structure multiple times to form a sidewall structure with a narrow upper end and a wide lower end, the method also includes: forming a self-aligned silicide barrier layer on the initial sidewall structure, the gate structure and the substrate surface; and etching the initial sidewall structure while removing the self-aligned silicide barrier layer by multiple etchings to form a sidewall structure with a narrow upper end and a wide lower end.
[0014] Furthermore, before forming an interlayer dielectric film on the surfaces of the substrate, the gate structure and the sidewall structure, the method also includes: forming a metal silicide film in a designated area; wherein the designated area is located in an area where the self-aligned silicide barrier layer is removed and the sidewall structure is not formed; forming an etch stop layer on the surfaces of the substrate, the gate structure, the sidewall structure and the metal silicide film; and forming an interlayer dielectric film on the surface of the etch stop layer.
[0015] A second aspect of the present invention provides a semiconductor structure, comprising an interlayer dielectric film having tensile stress formed by the interlayer dielectric film forming method described above.
[0016] A third aspect of the present invention provides a chip, which includes the semiconductor structure described above.
[0017] Through the technical solution provided by the present invention, the present invention has at least the following technical effects:
[0018] The interlayer dielectric film forming method of the present invention first forms a plurality of step-shaped protruding gate structures on the upper surface of the substrate, and then forms initial sidewall structures on both sides of each gate structure. The initial sidewall structure is a configuration with the same thickness from top to bottom. The initial sidewall structure is etched multiple times to form a sidewall structure with a narrow upper end and a wide lower end. The multiple etchings include dry etching and wet etching. Finally, an interlayer dielectric film is formed on the surface of the substrate, the gate structure and the sidewall structure. The interlayer dielectric film forming method of the present invention can increase the distance between the sidewalls of two adjacent gate structures, reduce the holes generated in the filling process of the high-density plasma interlayer dielectric layer process, ensure the etching of the contact hole, ensure the filling of the contact hole sidewall barrier layer and the filling of tungsten, and improve the yield of the static random access memory.
[0019] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:
[0022] Figure 1 A flow chart of a method for forming an interlayer dielectric film provided by an embodiment of the present invention;
[0023] Figure 2 A schematic structural diagram of a gate structure and an initial sidewall structure formed in a method for forming an interlayer dielectric film provided in an embodiment of the present invention;
[0024] Figure 3A schematic structural diagram of a silicon oxide self-aligned silicide barrier layer and a silicon nitride self-aligned silicide barrier layer formed in the interlayer dielectric film forming method provided in an embodiment of the present invention;
[0025] Figure 4 A schematic structural diagram of a sidewall structure formed in a method for forming an interlayer dielectric film provided by an embodiment of the present invention;
[0026] Figure 5 A schematic structural diagram of a metal silicide film, an etch stop layer and an interlayer dielectric film formed in a method for forming an interlayer dielectric film provided in an embodiment of the present invention.
[0027] Description of Reference Numerals
[0028] 1-substrate; 2-gate structure; 3-silicon oxide initial sidewall structure; 4-silicon nitride initial sidewall structure; 5-silicon oxide initial sidewall structure; 6-silicon oxide self-aligned silicide barrier layer; 7-silicon nitride self-aligned silicide barrier layer; 8-metal silicide film; 9-etching stop layer; 10-interlayer dielectric film. DETAILED DESCRIPTION
[0029] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.
[0030] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.
[0031] In the present invention, unless otherwise specified, directional words such as "up, down, top, bottom" are usually used with reference to the directions shown in the drawings or are used to describe the relative positional relationships of components in the vertical, perpendicular or gravity direction.
[0032] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.
[0033] Please refer to Figure 1 A first aspect of an embodiment of the present invention provides a method for forming an interlayer dielectric film, the method comprising: S101: after forming a plurality of gate structures 2, forming initial sidewall structures on both sides of each gate structure 2; wherein the gate structure 2 protrudes from the upper surface of the substrate 1 in a step-like manner; the initial sidewall structure is a configuration with the same thickness from top to bottom; S102: etching the initial sidewall structure multiple times to form a sidewall structure with a narrow upper end and a wide lower end; wherein the multiple etchings include dry etching and wet etching; S103: forming an interlayer dielectric film on the surface of the substrate 1, the gate structure 2 and the sidewall structure.
[0034] Specifically, step S101 is first performed: after forming multiple gate structures 2, initial sidewall structures are formed on both sides of each gate structure 2; wherein the gate structure protrudes from the upper surface of the substrate 1 in a step-like manner; and the initial sidewall structure has the same thickness from top to bottom.
[0035] Specifically, in the embodiment of the present invention, Figure 2 As shown, a plurality of gate structures 2 are formed on the surface of the substrate 1, and the plurality of gate structures 2 protrude from the upper surface of the substrate 1 in a step-like manner. Then, an initial sidewall structure is formed on both sides of each gate structure 2. The initial sidewall structure includes at least one layer of layered sidewalls. In this embodiment, the initial sidewall structure includes, from the inside to the outside, a silicon oxide initial sidewall structure 3, a silicon nitride initial sidewall structure 4, and a silicon oxide initial sidewall structure 5, and the outermost layer may also be a silicon nitride initial sidewall structure. The initial sidewall structure formed using the prior art is a configuration of the same thickness from top to bottom. If the spacing between the initial sidewalls of the two gate structures 2 is too small, holes will be generated when the interlayer dielectric layer is filled later, thereby affecting the contact hole etching, and even affecting the filling of the contact hole sidewall barrier layer and the filling of tungsten, causing tungsten leakage. Therefore, the initial sidewall structure must be processed to reduce the thickness of the initial sidewall structure and increase the spacing between the sidewalls of the two gate structures 2.
[0036] Then, step S102 is performed: etching the initial sidewall structure multiple times to form a sidewall structure with a narrow upper end and a wide lower end; wherein the multiple etchings include dry etching and wet etching.
[0037] Furthermore, before etching the initial sidewall structure multiple times to form a sidewall structure with a narrow upper end and a wide lower end, the method also includes: forming a self-aligned silicide barrier layer on the initial sidewall structure, the gate structure 2 and the surface of the substrate 1; and etching the initial sidewall structure while removing the self-aligned silicide barrier layer by multiple etchings to form a sidewall structure with a narrow upper end and a wide lower end.
[0038] Furthermore, the sidewall structure is of a configuration with an oblique side concave toward the gate structure 2 .
[0039] Furthermore, the etching the initial sidewall structure multiple times includes: performing multiple steps of dry etching on the initial sidewall structure to form an intermediate sidewall; and performing at least one step of wet etching on the intermediate sidewall to form the sidewall structure.
[0040] Furthermore, the dry etching step includes three steps.
[0041] Furthermore, the etching conditions of the first step of dry etching include: the etching gas is CH 2 F 2 CF 4and He, the etching gas flow rate is between 15sccm-100sccm, the bias power is between 30W-60W, the etching pressure is between 60mTorr-80mTorr, and the etching time is between 10s-15s.
[0042] Furthermore, the etching conditions of the second step dry etching include: the etching gas is CH 2 F 2 , CHF 3 , O 2 and He, the etching gas flow rate is between 45sccm-100sccm, the bias power is between 30W-60W, the etching pressure is between 20mTorr-40mTorr, and the etching time is between 5s-12s.
[0043] Furthermore, the etching conditions of the third step of dry etching include: the etching gas is CH 2 F 2 , CHF 3 , O 2 and He, the etching gas flow rate is between 80sccm-130sccm, the bias voltage is between 60V-80V, the etching pressure is between 35mTorr-55mTorr, and the etching time is between 5s-15s.
[0044] Furthermore, the wet etching step includes one step; the etching conditions of the wet etching include: the etching solution includes one or a combination of hydrofluoric acid solution and ammonia solution, the reaction temperature is between 20°C-25°C, and the reaction time is between 2min-4min.
[0045] Specifically, in an embodiment of the present invention, after the initial sidewall structure is formed, a silicon oxide self-aligned silicide barrier layer 6 and a silicon nitride self-aligned silicide barrier layer 7 are deposited on the device surface as self-aligned silicide barrier layers. The self-aligned silicide barrier layers can prevent the formation of metal silicide in certain areas where metal silicide is not required to be formed.
[0046] like Figure 4 As shown, multiple etchings are then performed, including dry etching and wet etching. Dry etching is anisotropic and can control different etching rates in different directions to obtain a middle sidewall with a narrow upper end and a wide lower end. Then, wet etching is combined to etch away the self-aligned silicide barrier layer to obtain the final sidewall structure. By combining dry etching and wet etching, a sidewall structure with a configuration of a beveled concave gate structure is formed, which can increase the spacing between the sidewall structures of two adjacent gate structures 2, reduce the holes generated in the filling process of the high-density plasma interlayer dielectric layer process, ensure contact hole etching, ensure the filling of the contact hole sidewall barrier layer and the filling of tungsten, and improve the yield of the static random access memory.
[0047] In this embodiment, three steps of dry etching and one step of wet etching are performed. The etching conditions of the first step of dry etching include: the etching gas is CH 2 F 2 CF 4 and He, the etching gas flow rate is between 15sccm-100sccm, the bias power is between 30W-60W, the etching pressure is between 60mTorr-80mTorr, and the etching time is between 10s-15s. The etching conditions of the second step dry etching include: the etching gas is CH 2 F 2 , CHF 3 , O 2 and He, the etching gas flow rate is between 45sccm-100sccm, the bias power is between 30W-60W, the etching pressure is between 20mTorr-40mTorr, and the etching time is between 5s-12s. The etching conditions of the third step dry etching include: the etching gas is CH 2 F 2 , CHF 3 , O 2 and He, the etching gas flow rate is between 80sccm-130sccm, the bias voltage is between 60V-80V, the etching pressure is between 35mTorr-55mTorr, and the etching time is between 5s-15s. The etching conditions of wet etching include: the etching solution includes one or a combination of hydrofluoric acid solution and ammonia solution, the reaction temperature is between 20℃-25℃, and the reaction time is between 2min-4min.
[0048] Finally, step S103 is performed: forming an interlayer dielectric film on the surfaces of the substrate 1 , the gate structure 2 and the spacer structure.
[0049] Furthermore, before forming an interlayer dielectric film on the surfaces of the substrate 1, the gate structure 2 and the sidewall structure, the method also includes: forming a metal silicide film 8 in a designated area; wherein the designated area is located in an area where the self-aligned silicide barrier layer is removed and the sidewall structure is not formed; forming an etch stop layer 9 on the surfaces of the substrate 1, the gate structure 2, the sidewall structure and the metal silicide film 8; and forming an interlayer dielectric film 10 on the surface of the etch stop layer 9.
[0050] Specifically, in the embodiment of the present invention, Figure 5As shown, after the sidewall structure is formed, a metal silicide film 8 is formed in the designated area, and the designated area is located in the area where the self-aligned silicide barrier layer is removed and the sidewall structure is not formed. The metal silicide film 8 can reduce the series resistance of the circuit, thereby increasing the operating speed of the circuit and reducing power consumption, thereby increasing the operating speed of the transistor. Then, an etch stop layer 9 is formed on the surface of the substrate 1, the gate structure 2, the sidewall structure and the metal silicide film 8. The etch stop layer 9 can accurately control the etching depth of the subsequent contact hole etching, ensuring that the etching process stops when the etching stop layer 9 is reached, preventing excessive etching from causing device damage or performance degradation. Finally, an interlayer dielectric film 10 is formed on the surface of the etch stop layer 9.
[0051] A second aspect of the present invention provides a semiconductor structure, comprising an interlayer dielectric film formed by the interlayer dielectric film forming method described above.
[0052] A third aspect of the present invention provides a chip, which includes the semiconductor structure described above.
[0053] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.
[0054] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.
[0055] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.
Claims
1. A method for forming an interlayer dielectric film, characterized in that: The interlayer dielectric film forming method comprises: After forming a plurality of gate structures, initial spacer structures are formed on both sides of each gate structure; wherein the gate structure protrudes from the upper surface of the substrate in a step-like shape; and the initial spacer structures are configured with the same thickness from top to bottom; Etching the initial sidewall structure multiple times to form a sidewall structure with a narrow upper end and a wide lower end; wherein the multiple etchings include dry etching and wet etching; An interlayer dielectric film is formed on the surfaces of the substrate, the gate structure and the sidewall structure.
2. The interlayer dielectric film forming method according to claim 1, characterized in that: The sidewall structure is a configuration in which the oblique edges are concave toward the gate structure.
3. The interlayer dielectric film forming method according to claim 1, characterized in that: The etching of the initial sidewall structure multiple times includes: Performing multi-step dry etching on the initial sidewall structure to form an intermediate sidewall; The intermediate sidewall is subjected to at least one step of wet etching to form the sidewall structure.
4. The interlayer dielectric film forming method according to claim 3, characterized in that: The dry etching process includes three steps.
5. The interlayer dielectric film forming method according to claim 4, characterized in that: The etching conditions of the first step of dry etching include: The etching gas is one or more of CH2F2, CF4 and He, the etching gas flow rate is between 15sccm-100sccm, the bias power is between 30W-60W, the etching pressure is between 60mTorr-80mTorr, and the etching time is between 10s-15s.
6. The interlayer dielectric film forming method according to claim 4, characterized in that: The etching conditions of the second step dry etching include: The etching gas is one or more of CH2F2, CHF3, O2 and He, the etching gas flow rate is between 45sccm-100sccm, the bias power is between 30W-60W, the etching pressure is between 20mTorr-40mTorr, and the etching time is between 5s-12s.
7. The interlayer dielectric film forming method according to claim 4, characterized in that: The etching conditions of the third step dry etching include: The etching gas is one or more of CH2F2, CHF3, O2 and He, the etching gas flow rate is between 80sccm-130sccm, the bias voltage is between 60V-80V, the etching pressure is between 35mTorr-55mTorr, and the etching time is between 5s-15s.
8. The interlayer dielectric film forming method according to claim 3, characterized in that: The wet etching step includes the following steps: The etching conditions of the wet etching include: The etching solution includes one or a combination of hydrofluoric acid solution and ammonia solution, the reaction temperature is between 20° C. and 25° C., and the reaction time is between 2 min and 4 min.
9. The interlayer dielectric film forming method according to claim 1, characterized in that: Before etching the initial sidewall structure multiple times to form a sidewall structure with a narrow upper end and a wide lower end, the method further includes: forming a self-aligned silicide barrier layer on the initial sidewall structure, the gate structure and the substrate surface; The self-aligned silicide barrier layer is removed by etching multiple times while the initial sidewall structure is etched to form a sidewall structure with a narrow upper end and a wide lower end.
10. The interlayer dielectric film forming method according to claim 1, characterized in that: Before forming an interlayer dielectric film on the surfaces of the substrate, the gate structure and the sidewall structure, the method further comprises: forming a metal silicide film in a designated area; wherein the designated area is located in an area where the self-aligned silicide barrier layer is removed and a sidewall structure is not formed; forming an etching stop layer on the surface of the substrate, the gate structure, the sidewall structure and the metal silicide film; An interlayer dielectric film is formed on the surface of the etch stop layer.
11. A semiconductor structure, characterized in that: The semiconductor structure includes an interlayer dielectric film formed by the interlayer dielectric film forming method according to any one of claims 1 to 10.
12. A chip, characterized in that: The chip comprises the semiconductor structure according to claim 11.