High-voltage isolation ring structure

Abstract

This invention provides a high-voltage isolation ring structure. The high-voltage isolation ring is composed of a high-voltage diode and isolates a high-voltage circuit from a low-voltage circuit. An epitaxial layer doped with a first conductivity type is formed on a semiconductor substrate. A doped region of a second conductivity type is formed on the epitaxial layer. A heavily doped anode of the first conductivity type is connected to a high-level voltage. A heavily doped body contact region of the second conductivity type is connected to a low-level voltage. At least one pair of first and second heavily doped active regions of the first and second conductivity types are alternately formed in a selected area of ​​a first well region to form a parasitic transistor structure. Both the first and second active regions are connected to a low-level voltage. The gate structure is connected to a low-level voltage. This invention improves the electrostatic discharge capability of the isolation ring by inserting a transistor structure into the high-voltage diode, while maintaining the same chip area.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a high-voltage isolation ring structure. Background Technology

[0002] A typical high-voltage gate drive circuit (HVIC) consists of a high-side power transistor, a low-side power transistor, and control circuitry housed in a high-voltage floating basin. The high-voltage floating basin is surrounded by a high-voltage isolation ring to provide high withstand voltage (greater than 200V). Due to the withstand voltage requirements, it typically occupies a very large chip area. Because of the high operating voltage and the large size of the high-voltage isolation ring, a self-protection method is generally used to discharge ESD current. With the development of application scenarios, ESD performance requirements have gradually increased from 2KV HBM (Human Body Model) to 4KV. This places higher demands on the design of the high-voltage isolation ring.

[0003] The planar layout of the existing high-voltage isolation ring is as follows: Figure 1 As shown, the high-voltage isolation ring is a closed ring, consisting of an inner high-voltage floating basin, an outer high-voltage isolation ring, a level-shift region, and a P-type shielding ring that isolates the high-voltage isolation ring and the level-shift. The traditional high-voltage isolation ring cross-sectional structure AA' is as follows. Figure 2 As shown, from right to left, the high-voltage floating basin region and the high-voltage isolation ring structure are shown. The high-voltage floating basin region is formed by implanting an NBL region on the Psub substrate, followed by the growth of an N-type epitaxial layer, with an N+ active region formed on the epitaxial surface. The high-voltage isolation ring structure is similar to an LDMOS structure, with an N-type epitaxial layer grown on the Psub substrate. From right to left, it forms an N-type active region, a drift region field oxide, a polysilicon field plate near the N-type active region, a gate polysilicon, and a P-type active region. A P-type well and PBL are formed under the P-type active region, connected to the Psub substrate. The high-voltage floating basin N-type active region, the high-voltage isolation ring N-type active region, and the gate polysilicon field plate are connected together to a high potential. The gate polysilicon and the P-type active region are connected and grounded to achieve high voltage withstand capability. Two level-shift devices are formed on one side of the high-voltage isolation ring, and a P-type shielding ring isolates the level-shift devices from the high-voltage isolation ring.

[0004] Existing technologies utilize diodes with large areas to meet HBM requirements. However, the BV (breakdown voltage) distribution on the isolation ring is uneven, and the boundary between the isolation ring and the level-shift region is a weak point in BV, which limits the ability to discharge electrostatic current, allowing only 2KV of HBM to pass through.

[0005] To solve the above problems, a new type of high-voltage isolation ring structure needs to be proposed. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a high-voltage isolation ring structure to solve the problem that in the prior art, diodes with large areas are used to meet HBM requirements, but the BV (breakdown voltage) distribution on the isolation ring is uneven, and the boundary between the isolation ring and the level shifting device area is a weak point in breakdown voltage, which limits the ability to discharge electrostatic current.

[0007] To achieve the above and other related objectives, the present invention provides a high-voltage isolation ring structure, comprising:

[0008] The high-voltage isolation ring is composed of a high-voltage diode with a structure similar to LDMOS and is isolated between the high-voltage circuit and the low-voltage circuit. The operating voltage of the high-voltage circuit is greater than the operating voltage of the low-voltage circuit, and the operating voltage of the high-voltage diode is also greater than the operating voltage of the low-voltage circuit.

[0009] An epitaxial layer doped with a first conductivity type is formed on a semiconductor substrate;

[0010] A doped region of the second conductivity type is formed on the epitaxial layer, and the epitaxial layer of the first conductivity type between the doped region and the high voltage circuit forms a diode portion.

[0011] The high-voltage diode also includes:

[0012] A heavily doped anode of the first conductivity type is formed in the surface region of the epitaxial layer, the anode being located on the side close to the high voltage circuit and connected to a high voltage level;

[0013] A heavily doped body contact region of the second conductivity type is formed in a selected region of the doped region, and the body contact region is connected to a low level.

[0014] At least one pair of first active regions heavily doped with a first conductivity type and second active regions heavily doped with a second conductivity type are formed alternately in selected regions of the first well region to form a parasitic transistor structure, and both the first and second active regions are connected to a low level.

[0015] A gate structure covers the surface of the doped region and one side of the gate structure extends onto the epitaxial layer, and the gate structure is connected to a low level.

[0016] Preferably, the high-voltage circuit is located inside the high-voltage isolation ring.

[0017] Preferably, when viewed from above, the high-voltage isolation ring has a quadrilateral ring structure.

[0018] Preferably, the high-voltage diodes in a portion of the region constitute a level shifting device.

[0019] Preferably, the number of the level shifting devices is two and they are located on the same side.

[0020] Preferably, the high-voltage isolation ring structure is used on the other three sides besides the level shifting device.

[0021] Preferably, a shielding ring of the second conductivity type is provided around the level shifting device to achieve isolation between the level converter and the high-voltage diode and the high-voltage circuit devices outside the level converter.

[0022] Preferably, the doped region of the second conductivity type includes: a first buried layer, a first doped layer, and a first well region doped with the second conductivity type in sequence, wherein the first doped layer connects the first well region and the first buried layer; the first buried layer is formed in a selected region between the semiconductor substrate and the epitaxial layer; both the first doped layer and the first well region are formed in the epitaxial layer, and the bulk contact region of the second conductivity type is formed in the selected region of the first well region.

[0023] Preferably, the drift region of the LDMOS-like structure is composed of the epitaxial layer located between the first well region and the anode; a drift region field oxygen is formed on the surface of the drift region; a gate structure covers the surface of the doped region and one side of the gate structure extends onto the drift region field oxygen, and the gate structure is connected to a low level.

[0024] Preferably, the gate structure is formed by stacking a gate dielectric layer and a polysilicon gate.

[0025] Preferably, the gate dielectric layer is a gate oxide layer or a metal silicide.

[0026] Preferably, the top of the first trap region is covered with a field oxygen layer.

[0027] Preferably, the first conductivity type is N-type and the second conductivity type is P-type.

[0028] Preferably, the edges of the first and second active regions are in contact, and the first and second active regions are short-circuited through contact holes and the front metal layer.

[0029] Preferably, there is an undoped active region between the first and second active regions, and the first and second active regions are short-connected through a contact hole and a front metal layer.

[0030] Preferably, there is an undoped active region between the first and second active regions, and the undoped active region is covered with a self-aligned silicide barrier layer. The first and second active regions are shorted together through a contact hole and a front metal layer.

[0031] Preferably, the material of the self-aligned silicide barrier layer includes at least one of silicon-rich oxide, SiO2, SiON, and Si3N4.

[0032] Preferably, there is an undoped active region between the first and second active regions, and the undoped active region is covered with a polysilicon layer. The first and second active regions are shorted together through a contact hole and a front metal layer.

[0033] Preferably, the operating voltage of the high-voltage diode is not less than 150V.

[0034] As described above, the high-voltage isolation ring structure of the present invention has the following beneficial effects:

[0035] This invention can improve the ability of the isolation ring to discharge electrostatic current, while maintaining the same chip area. Attached Figure Description

[0036] Figure 1 The diagram shown is a schematic representation of a high-voltage isolation ring structure in the prior art.

[0037] Figure 2 Displayed as Figure 1 Schematic diagram of the cross-sectional structure at point A-A';

[0038] Figure 3 The diagram shown is a cross-sectional view of the high-voltage isolation ring according to the first embodiment of the present invention.

[0039] Figure 4 The diagram shown illustrates the formation of the parasitic BJT structure according to the present invention.

[0040] Figure 5 The diagram shown is a cross-sectional view of the high-voltage isolation ring according to the second embodiment of the present invention.

[0041] Figure 6 The diagram shown is a cross-sectional view of the high-voltage isolation ring according to the third embodiment of the present invention.

[0042] Figure 7 The diagram shown is a cross-sectional view of the high-voltage isolation ring according to the fourth embodiment of the present invention. Detailed Implementation

[0043] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] This invention provides a high-voltage isolation ring structure, comprising:

[0045] The high-voltage isolation ring is composed of a high-voltage diode and is isolated between the high-voltage circuit and the low-voltage circuit. The operating voltage of the high-voltage circuit is greater than that of the low-voltage circuit, and the operating voltage of the high-voltage diode is also greater than that of the low-voltage circuit. In the embodiments of the present invention, the operating voltage of the high-voltage diode is not less than 150V.

[0046] In some embodiments, the high-voltage circuit is located inside the high-voltage isolation ring.

[0047] In some embodiments, the high-voltage isolation ring has a quadrilateral ring structure when viewed from above.

[0048] An epitaxial layer 102 doped with a first conductivity type is formed on a semiconductor substrate 101;

[0049] A doped region of a second conductivity type is formed on the epitaxial layer 102, and the epitaxial layer 102 of the first conductivity type between it and the high voltage circuit forms a diode portion;

[0050] For example, the doped region of the second conductivity type includes a first buried layer 103, a first doped layer 104 and a first well region 105 of the second conductivity type doped in sequence, wherein the first doped layer 104 realizes the connection between the first well region 105 and the first buried layer 103.

[0051] The first buried layer 103 is formed in a selected region between the semiconductor substrate 101 and the epitaxial layer 102;

[0052] Both the first doped layer 104 and the first well region 105 are formed in the epitaxial layer 102;

[0053] In some embodiments, high-voltage diodes in a portion of the region constitute a level shifting device.

[0054] In some embodiments, the number of level shifting devices is two and they are located on the same side.

[0055] In some embodiments, the high-voltage isolation ring structure is used on the other three sides besides the level shifting device.

[0056] In some embodiments, a shielding ring of a second conductivity type is provided around the level shifting device to achieve isolation between the level shifter and the high-voltage diode and the high-voltage circuit devices outside the level shifter.

[0057] High-voltage diodes also include:

[0058] A heavily doped anode 112 of the first conductivity type is formed in the surface region of the epitaxial layer 102. The anode 112 is located on the side close to the high voltage circuit and is connected to a high voltage level.

[0059] The drift region, similar to the LDMOS structure, is composed of an epitaxial layer 102 located between the first well region 105 and the anode 112; a drift region field oxygen is formed on the surface of the drift region; the gate structure covers the surface of the doped region and one side of the gate structure extends onto the drift region field oxygen, and the gate structure is connected to a low level.

[0060] A second conductivity type heavily doped body contact region 110 is formed in a selected region of the doped region, such as a selected region of the first well region 105, and the body contact region 110 is connected to a low level.

[0061] At least one pair of first active regions 114 heavily doped with a first conductivity type and second active regions 113 heavily doped with a second conductivity type are alternately formed in a selected region of the first well region 105 to form a parasitic transistor structure. Both the first and second active regions are connected to a low level.

[0062] The drift region is composed of an epitaxial layer 102 located between the first well region 105 and the anode 112;

[0063] A drift region field oxygen 106 is formed on the surface of the drift region of the high voltage diode;

[0064] The gate structure covers the surface of the doped region and one side of the gate structure extends onto the epitaxial layer 102. The gate structure is connected to a low level.

[0065] In some embodiments, the gate structure covers the surface of the first well region 105 and the second side of the gate structure extends onto the drift region field oxygen, and the gate structure is connected to a low level.

[0066] In some embodiments, the gate structure is formed by stacking a gate dielectric layer 108 and a polysilicon gate 109.

[0067] In some embodiments, the gate dielectric layer 108 is a gate oxide layer or a metal silicide.

[0068] In some embodiments, the top of the first well region 105 is covered with a field oxygen layer 107, which is used to isolate the first and second active regions and the body contact region 110, as well as to isolate the body contact region 110 and other devices.

[0069] In an embodiment of the present invention, the first conductivity type is N-type and the second conductivity type is P-type.

[0070] In some embodiments, see Figure 3 The edges of the first and second active regions are in contact, and they are short-circuited through contact holes and the front metal layer. In the layout, the second active region 113 can be inserted into the first active region 114 at the source end using an interlocking method to achieve short-circuiting. Please refer to [link to relevant documentation]. Figure 4The first and second active regions are shorted together by a buttoning mechanism, thus constructing a parasitic BJT structure. Since the BJT structure has a higher current amplification factor than a diode, the current capability of the new structure is significantly improved compared to the traditional structure. The HBM capability of the isolation ring has been increased from 2KV to 4KV, while its chip area remains unchanged.

[0071] In some embodiments, see Figure 5 There is an undoped active region 115 between the first and second active regions, and the first and second active regions are shorted together through a contact hole and a front metal layer.

[0072] In some embodiments, see Figure 6 Between the first and second active regions is an undoped active region 115, which is covered by a self-aligned silicide barrier layer 116. The first and second active regions are shorted through contact holes and a front metal layer. Covering the undoped active region 115 with a self-aligned silicide barrier layer 116 can improve the immunity to latch-up (a low-impedance path in a CMOS chip caused by the interaction of parasitic PNP and NPN bipolar BJTs between power VDD and ground GND (VSS)).

[0073] In some embodiments, the material of the self-aligned silicide barrier layer 116 includes at least one of silicon-rich oxide, SiO2, SiON, and Si3N4.

[0074] In some embodiments, see Figure 7 An undoped active region 115 is located between the first and second active regions. A polysilicon layer 117 is covered on the undoped active region 115. The first and second active regions are shorted together through contact holes and a front metal layer. Covering the undoped active region 115 with a polysilicon layer 117 can improve latch-up immunity.

[0075] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0076] In summary, this invention improves the electrostatic discharge capability of the isolation ring while maintaining the same chip area. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0077] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A high-voltage isolation ring structure, characterized in that, include: The high-voltage isolation ring is composed of high-voltage diodes and is isolated between the high-voltage circuit and the low-voltage circuit. The operating voltage of the high-voltage circuit is greater than the operating voltage of the low-voltage circuit, and the operating voltage of the high-voltage diodes is also greater than the operating voltage of the low-voltage circuit. An epitaxial layer doped with a first conductivity type is formed on a semiconductor substrate; A doped region of a second conductivity type is formed on the epitaxial layer. The doped region of the second conductivity type includes a first well region. The first conductivity type doped epitaxial layer between the well region and the high voltage circuit forms a diode portion. The high-voltage diode also includes: A heavily doped anode of the first conductivity type is formed in the surface region of the epitaxial layer, the anode being located on the side close to the high voltage circuit and connected to a high voltage level; A heavily doped body contact region of the second conductivity type is formed in a selected region of the doped region, and the body contact region is connected to a low level. A first active region heavily doped with a first conductivity type and a second active region heavily doped with a second conductivity type are formed in a selected region of the first well region to form a parasitic transistor structure. Both the first active region and the second active region are connected to a low level. There is an undoped active region between the first active region and the second active region, and the first active region and the second active region are short-circuited through a contact hole and a front metal layer; A gate structure covers the surface of the epitaxial layer and one side of the gate structure extends onto the drift region field oxygen, and the gate structure is connected to a low level.

2. The high-voltage isolation ring structure according to claim 1, characterized in that: The high-voltage circuit is located inside the high-voltage isolation ring.

3. The high-voltage isolation ring structure according to claim 1, characterized in that: Viewed from above, the high-voltage isolation ring has a quadrilateral ring structure.

4. The high-voltage isolation ring structure according to claim 1, characterized in that: One of the high-voltage diodes in a certain area constitutes a level shifting device.

5. The high-voltage isolation ring structure according to claim 4, characterized in that: The number of level shifting devices is two, and they are located on the same side.

6. The high-voltage isolation ring structure according to claim 5, characterized in that: The high-voltage isolation ring structure is used on the other three sides except for the side where the level shifting device is located.

7. The high-voltage isolation ring structure according to claim 4, characterized in that: A shielding ring of a second conductivity type is provided around the level shifting device to achieve isolation between the level shifting device and the high-voltage diode and the high-voltage circuit components outside the level shifting device.

8. The high-voltage isolation ring structure according to claim 1, characterized in that: The second conductivity type doped region includes: a first buried layer, a first doped layer, and a first well region doped with the second conductivity type in sequence, wherein the first doped layer connects the first well region and the first buried layer; the first buried layer is formed in a selected region between the semiconductor substrate and the epitaxial layer; both the first doped layer and the first well region are formed in the epitaxial layer; and the second conductivity type heavily doped bulk contact region is formed in a selected region of the first well region.

9. The high-voltage isolation ring structure according to claim 1, characterized in that: The drift region of the high-voltage isolation ring is composed of the epitaxial layer located between the first well region and the anode; the drift region field oxygen is formed on the surface of the drift region.

10. The high-voltage isolation ring structure according to claim 1, characterized in that: The gate structure is composed of a gate dielectric layer and a polysilicon gate stacked together.

11. The high-voltage isolation ring structure according to claim 10, characterized in that: The gate dielectric layer is a gate oxide layer or a metal silicide.

12. The high-voltage isolation ring structure according to claim 8, characterized in that: The top of the first trap region is covered by a field oxygen layer.

13. The high-voltage isolation ring structure according to claim 1, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type.

14. The high-voltage isolation ring structure according to claim 1, characterized in that: The first active region and the second active region are connected by an undoped active region, which is covered by a self-aligned silicide barrier layer. The first active region and the second active region are short-circuited by a contact hole and a front metal layer.

15. The high-voltage isolation ring structure according to claim 14, characterized in that: The material of the self-aligned silicide barrier layer includes at least one of silicon-rich oxide, SiO2, SiON, and Si3N4.

16. The high-voltage isolation ring structure according to claim 1, characterized in that: The first active region and the second active region are connected by an undoped active region, which is covered by a polysilicon layer. The first active region and the second active region are short-circuited by a contact hole and a front metal layer.

17. The high-voltage isolation ring structure according to claim 1, characterized in that: The operating voltage of the high-voltage diode is not less than 150V.

Images