A high-efficiency perovskite-crystalline silicon stacked battery component and preparation method

Abstract

The present invention relates to a high-efficiency perovskite-crystalline silicon stacked cell assembly and a preparation method, and belongs to the technical field of solar cells. The crystalline silicon cell in the perovskite-crystalline silicon stacked cell assembly includes, from top to bottom, a front silver grid line, a first silicon nitride layer, an n-type emitter, a p-type monocrystalline silicon, an infrared reflection layer, an aluminum oxide passivation layer, a second silicon nitride layer, a p-type aluminum back field, and a back aluminum grid line; the infrared reflection layer is a stack of transition metal compound films and / or metal-doped transition metal compound films. The present invention achieves an improvement in the infrared band light absorption efficiency of the crystalline silicon assembly by adding one or more stacked transition metal compounds and metal layers to the crystalline silicon assembly structure, and the photoelectric conversion efficiency of the perovskite-crystalline silicon stacked cell assembly prepared by this method is significantly improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar cells, and in particular relates to a high-efficiency perovskite-crystalline silicon stacked cell assembly and a preparation method thereof. Background Art

[0002] With the rapid development of perovskite-crystalline silicon tandem photovoltaic technology, how to further reduce the efficiency loss of crystalline silicon components caused by light filtering by the top perovskite component has become an important research topic for improving the efficiency of perovskite-crystalline silicon tandem photovoltaic technology.

[0003] In order to enable existing crystalline silicon modules to make maximum use of incident light in the visible and near-infrared bands, the structural design of existing crystalline silicon modules will utilize both visible and infrared bands and maintain a balanced absorption rate for each band. However, once a stacked module is formed with a translucent perovskite module, the crystalline silicon cell will not be able to absorb the visible light before the 600nm band, and can only absorb the band after 600nm, which will cause the efficiency of the crystalline silicon module to drop sharply. Although the introduction of perovskite modules can further improve the efficiency of crystalline silicon modules, since the efficiency loss of crystalline silicon modules is also large, it is necessary to solve the problem of crystalline silicon efficiency loss and further improve the efficiency of crystalline silicon modules and stacked modules.

[0004] The main problems of the existing technology are: the existing crystalline silicon anti-reflection layer is designed for the full spectrum, without special treatment and optimization for infrared, the depth of the crystalline silicon PN junction is designed for the purpose of utilizing the full spectrum, and the carriers generated by near-infrared light are not effectively extracted and utilized in the perovskite-crystalline silicon stack structure, such as Figure 1 The spectral response index graph of crystalline silicon cells can clearly show that the spectral response of crystalline silicon cells decreases exponentially after 900-1200nm. Therefore, it is urgent to solve the problem of low near-infrared light utilization of crystalline silicon in the perovskite and crystalline silicon stacked structure. Summary of the invention

[0005] In view of the shortcomings of the prior art, the present invention proposes a method for improving the infrared band utilization rate of crystalline silicon cells in perovskite-crystalline silicon stacked cell components by using multi-layer thin film technology, which includes the following technical solutions:

[0006] In a first aspect, the present invention provides a crystalline silicon cell, which comprises, from top to bottom, a front silver grid line 1, a first silicon nitride layer 2, an n-type emitter 3, a p-type single crystal silicon 4, an infrared reflection layer 5, an aluminum oxide passivation layer 6, a second silicon nitride layer 7, a p-type aluminum back field 8, and a back aluminum grid line 9.

[0007] Furthermore, the infrared reflection layer is formed by stacking transition metal compound films and / or metal-doped transition metal compound films;

[0008] Furthermore, the thickness of a single layer of the transition metal compound film is 100 nm-1 μm; preferably, the thickness is 100-800 nm, and more preferably, the thickness is 200-600 nm, for example, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm or 600 nm.

[0009] Furthermore, the single-layer thickness of the metal-doped transition metal compound film is 100nm-1μm; preferably, the thickness is 100-600nm, for example, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm, 550nm or 600nm.

[0010] Furthermore, the total number of stacked layers of transition metal compound films and / or metal-doped transition metal compound films in the infrared reflective layer is in the range of 1-5 layers.

[0011] For example, the infrared reflection layer is formed by stacking a layer of transition metal compound film and a layer of metal-doped transition metal compound film;

[0012] For example, the infrared reflection layer is formed by stacking two layers of transition metal compound films and two layers of metal-doped transition metal compound films;

[0013] For example, the infrared reflection layer is formed by stacking two layers of transition metal compound films and three layers of metal-doped transition metal compound films;

[0014] For example, the infrared reflection layer is formed by stacking 1 layer, 2 layers, 3 layers, 4 layers or 5 layers of transition metal compound thin films;

[0015] For example, the infrared reflection layer is formed by stacking 1 layer, 2 layers, 3 layers, 4 layers or 5 layers of metal-doped transition metal compound thin films.

[0016] Furthermore, the transition metal compound is a compound formed by a transition metal element and a non-metal element;

[0017] Furthermore, the non-metallic element is any one of boron (B), carbon (C) and nitrogen (N).

[0018] Furthermore, the transition metal element is one or more of titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), and tungsten (W).

[0019] Furthermore, the metal in the metal-doped transition metal compound film includes gold (Au), silver (Ag), copper (Cu) and aluminum (Al);

[0020] The inventors have found that by doping metal elements into the transition metal compound film, the infrared reflectivity of the infrared reflective layer can be further improved.

[0021] In a second aspect, the present invention provides a method for preparing a crystalline silicon battery, comprising: selecting a piece of p-type single crystal silicon 4 and texturing it on both sides, preparing an n-type emitter 3 on the front side of the p-type single crystal silicon 4, preparing a first silicon nitride layer 2 on the n-type emitter 3, preparing an infrared reflection layer 5 on the back side of the p-type single crystal silicon 4, preparing an aluminum oxide passivation layer 6 on the infrared reflection layer 5, preparing a second silicon nitride layer 7 on the aluminum oxide passivation layer 6, preparing a p-type aluminum back field 8 on the second silicon nitride layer 7, preparing a back aluminum grid line 9 on the p-type aluminum back field 8, and preparing a front silver grid line 1 on the first silicon nitride layer 2 to obtain a crystalline silicon battery.

[0022] Furthermore, the preparation of the infrared reflection layer on the back side of the p-type monocrystalline silicon includes: stacking a transition metal compound film and / or a metal-doped transition metal compound film on the back side of the p-type monocrystalline silicon to form an infrared reflection layer; the total number of stacked layers is 1-5 layers.

[0023] Furthermore, the infrared reflection layer is prepared by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0024] Furthermore, the stoichiometric ratio of the transition metal element to the non-metal element in the transition metal compound is (0.5-2):1;

[0025] Further, in the metal-doped transition metal compound, the metal doping amount accounts for 0.2%-10% of the transition metal compound, for example, 0.2%, 0.5%, 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, 5%, 5.5%, 6%, 6.5%, 7%, 7.5%, 8%, 8.5%, 9%, 9.5% or 10%;

[0026] The inventors have found that doping metal elements into transition metal compound films can further improve the infrared reflectivity of the infrared reflective layer.

[0027] Wherein, a piece of p-type single crystal silicon is selected and double-sided texturing is performed, and a p-type single crystal silicon wafer with a crystal orientation of (100), a thickness of 150-300μm (for example, 150μm, 180μm, 200μm, 230μm, 250μm, 280μm, 300μm), and a resistivity of 1-5Ω·cm is used, and potassium hydroxide solution or sodium hydroxide solution is used for texturing at 70-75°C for 5-7 minutes.

[0028] Wherein, an n-type emitter is prepared on the front side of p-type single crystal silicon, and a phosphorus source is diffused at 700-900° C. (for example, 700° C., 750° C., 800° C., 850° C., 900° C.) to form a phosphorus-doped n-type emitter layer on the front side of the p-type single crystal silicon; the phosphorus source includes phosphoric acid, phosphorus oxychloride, and ammonium dihydrogen phosphate;

[0029] Afterwards, the phosphorus-doped region on the back of the p-type monocrystalline silicon needs to be removed, for example, by wet etching the phosphorus-doped region on the back of the p-type monocrystalline silicon using an etching solution composed of 40% nitric acid, 4% hydrofluoric acid and 66% deionized water.

[0030] Among them, an aluminum oxide passivation layer is prepared on the infrared reflection layer, and a second silicon nitride layer is prepared on the aluminum oxide passivation layer. The aluminum oxide passivation layer with a thickness of 5-10nm and the second silicon nitride layer with a thickness of 50-100nm are sequentially deposited on the infrared reflection layer using a PECVD process.

[0031] Optionally, the thickness of the aluminum oxide passivation layer is 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm; the thickness of the second silicon nitride layer is 50 nm, 60 nm, 70 nm, 80 nm, 90 nm or 100 nm.

[0032] Among them, a p-type aluminum back field is prepared on the second silicon nitride layer, including: etching the aluminum back field by laser ablation technology, setting the laser parameters to a wavelength of 532-1064nm, a pulse width of 15ps, a pulse repetition frequency of 200-1000kHz (for example, 200kHz, 300kHz, 400kHz, 500kHz, 600kHz, 700kHz, 800kHz, 900kHz, 1000kHz), etching a pattern of gate line distribution, a line width of 25-30μm, and a spacing between adjacent gate lines of 1.6mm.

[0033] Among them, preparing the back aluminum grid line on the p-type aluminum back field includes: printing aluminum paste in the etched grid line groove, sending the silicon wafer printed with aluminum paste into a sintering furnace for sintering treatment, sending the silicon wafer printed with aluminum paste into a sintering furnace for sintering treatment to form an aluminum back field and a metal-semiconductor ohmic contact, wherein the sintering temperature is 700-900°C, the sintering time is 5-10s, and the atmosphere is compressed air.

[0034] Wherein, a first silicon nitride layer is prepared on the n-type emitter using a PECVD process, and the thickness of the first silicon nitride layer is 50-100nm. Optionally, the thickness of the first silicon nitride layer is 50nm, 60nm, 70nm, 80nm, 90nm or 100nm. Wherein, preparing the front silver grid line on the first silicon nitride layer includes: using screen printing technology, printing the silver paste on the first silicon nitride layer according to the designed pattern, and then sending the silicon wafer printed with the silver grid line into the preheating zone of the sintering furnace for preheating, the preheating time is 5-10min, the preheating temperature is 150℃-250℃, and then sending the silicon wafer into the sintering zone for sintering, the sintering temperature is 700℃-900℃, and the sintering time is 5-15min.

[0035] In a third aspect, the present invention provides a perovskite-crystalline silicon stacked cell assembly, comprising a perovskite cell and the crystalline silicon cell prepared as described above arranged in sequence; the perovskite cell comprises, from top to bottom,: a first transparent electrode, a hole transport layer, a perovskite light absorption layer, an electron transport layer, and a second transparent electrode.

[0036] In a fourth aspect, the present invention provides a method for preparing a perovskite-crystalline silicon stacked battery assembly, comprising:

[0037] Prepare crystalline silicon cells; prepare perovskite cells; and obtain perovskite-crystalline silicon laminated cell components by laminating and assembling the perovskite cells and crystalline silicon cells.

[0038] Among them, preparing the perovskite top cell includes: providing a first transparent electrode, preparing a hole transport layer on the first transparent electrode, preparing a perovskite absorption layer on the hole transport layer, preparing an electron transport layer on the perovskite absorption layer, and preparing a second transparent electrode on the electron transport layer.

[0039] Furthermore, the thickness of the first transparent electrode is 100-500 nm (for example, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm); and the first transparent electrode is indium tin oxide (ITO).

[0040] Further, the preparation of the hole transport layer on the first transparent electrode comprises: coating the hole transport layer on the first transparent electrode by a coating or spin coating method, wherein the hole transport layer has a thickness of 5-20 nm, for example, 5 nm, 8 nm, 10 nm, 12 nm, 15 nm, 18 nm or 20 nm;

[0041] Optionally, the hole transport layer is nickel oxide; preferably, the concentration of nickel oxide is 5-20 mg / mL.

[0042] Further, the preparation of the perovskite absorption layer on the hole transport layer includes: preparing the perovskite absorption layer on the hole transport layer by evaporation or coating, the thickness of the perovskite absorption layer is 300-800nm ​​(for example, 300nm, 350nm, 400nm, 450nm, 500nm, 550nm, 600nm, 650nm, 700nm, 750nm, 800nm); the general structure formula of the perovskite absorption layer is ABX3, wherein A is a methylamine ion (MA + ), formamidinium ion (FA + ), cesium ion (Cs + ) one or more; B is lead ion (Pb 2+ ), tin ions (Sn 2+ ), germanium ion (Ge 2+ ) in one or more; X is an iodide ion (I - ), bromide ion (Br - ), chloride ion (Cl - )

[0043] Furthermore, the preparation of the electron transport layer on the perovskite absorption layer includes: coating a layer of electron transport layer on the surface of the perovskite absorption layer by a coating method, and performing thermal annealing treatment, the annealing temperature is 70-120°C, and the annealing time is 1-10min; the thickness of the electron transport layer is 5-50nm (for example, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm); the electron transport layer is PCBM ([6,6]-phenyl-C61-butyric acid methyl ester); preferably, the electron transport layer is prepared by coating a PCBM solution with a concentration of 10-20mg / mL.

[0044] Furthermore, the step of preparing a second transparent electrode on the electron transport layer comprises: sputtering a layer of the second transparent electrode on the electron transport layer with a vacuum degree of 1*10 -5 -2*10 -5 Pa, sputtering power, atmosphere is pure argon, gas flow rate is 30-60sccm, and sputtering time is 8min; the thickness of the second transparent electrode is 80-500nm (for example, 80nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm); the second transparent electrode is an ITO transparent electrode.

[0045] Furthermore, the lamination assembly is to connect the perovskite cell with the crystalline silicon cell through an adhesive film, wherein the lamination temperature is 100-120°C, the time is 10-15min, and the pressure is 60-90kPa. The adhesive film is a POE adhesive film, an EVA adhesive film or an EPE adhesive film.

[0046] Compared with the prior art, the present invention has the following beneficial effects:

[0047] By adding one or more stacked transition metal compounds and metal layers to the structure of the crystalline silicon module, the absorption efficiency of infrared light in the crystalline silicon module is improved. By preparing compounds containing transition metal elements Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, W and non-metallic elements B, C, and N, and adjusting the stoichiometric ratio of the compounds, multiple layers of thin films with different refractive indices are prepared. Among them, different metal elements Au, Ag, Cu, Al, etc. can also be doped in the formed compounds to further improve the reflectivity of the infrared band, and form a multi-layer stacked layer with high infrared reflection in combination with transition metal compounds. The method of making the multi-layer stacked layer adopts methods such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). The introduction of multi-layer thin films changes the optical properties of crystalline silicon modules. With the increase in the number of thin film layers and the optimization of the thickness of each layer, the absorption capacity of crystalline silicon modules for infrared light is gradually enhanced. At the same time, the changes in the refractive index and extinction coefficient of the multi-layer thin film also have a positive effect on light absorption. The present invention achieves further improvement in reflectivity by optimizing the structure of the multi-layer stack, significantly improving the light absorption efficiency in the infrared band, and the photoelectric conversion efficiency of the perovskite-crystalline silicon stacked cell assembly prepared by this method is significantly improved.

[0048] Other features and advantages of the present invention will be described in the following description, and partly become obvious from the description, or be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the specific embodiments pointed out in the description. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 It is a spectral response index diagram of a crystalline silicon cell in the prior art;

[0050] Figure 2 It is a schematic diagram of the structure of the crystalline silicon battery of the present invention;

[0051] Figure 3 This is a reflectivity detection diagram of the infrared reflection layer prepared in Example 1 of the present invention;

[0052] Figure 4 This is a schematic diagram of the structure of a perovskite battery prepared in Example 2 of the present invention;

[0053] Figure 5 This is a schematic structural diagram of a perovskite-crystalline silicon stacked battery assembly prepared in Example 3 of the present invention;

[0054] Reference numerals: front silver grid line 1, first silicon nitride layer 2, n-type emitter 3, p-type single crystal silicon 4, infrared reflection layer 5, aluminum oxide passivation layer 6, second silicon nitride layer 7, p-type aluminum back field 8, back aluminum grid line 9. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical scheme and advantages of the present invention clearer, the implementation scheme of the present application will be described in detail below in conjunction with specific examples. The technical terms and scientific terms used in the present invention have the meanings generally understood by those of ordinary skill in the art to which the present invention belongs, without other definitions. Without departing from the concept of the present invention, those skilled in the art may make various improvements and changes to the specific implementation methods of the present invention specification, which all belong to the protection scope of the present invention. The raw materials used in the present invention are all commercially available unless otherwise specified.

[0056] Example 1

[0057] A crystalline silicon battery, such as Figure 2 As shown, the crystalline silicon cell includes, from top to bottom, a front silver grid line 1, a first silicon nitride layer 2, an n-type emitter 3, a p-type single crystal silicon 4, an infrared reflection layer 5, an aluminum oxide passivation layer 6, a second silicon nitride layer 7, a p-type aluminum back field 8, and a back aluminum grid line 9.

[0058] A method for preparing a crystalline silicon battery comprises: selecting a piece of p-type single crystal silicon 4 and texturing both sides thereof, preparing an n-type emitter 3 on the front surface of the p-type single crystal silicon 4, preparing a first silicon nitride layer 2 on the n-type emitter 3, preparing an infrared reflection layer 5 on the back surface of the p-type single crystal silicon 4, preparing an aluminum oxide passivation layer 6 on the infrared reflection layer 5, preparing a second silicon nitride layer 7 on the aluminum oxide passivation layer 6, preparing a p-type aluminum back surface field 8 on the second silicon nitride layer 7, preparing a back aluminum grid line 9 on the p-type aluminum back surface field 8, and preparing a front silver grid line 1 on the first silicon nitride layer 2, so as to obtain a crystalline silicon battery.

[0059] In a specific embodiment, it includes:

[0060] (1) Substrate preparation: A p-type single-crystalline silicon wafer with a size of 182 mm x 182 mm, a crystal orientation of (100), a thickness of 180 μm, and a resistivity of 1 Ω·cm was selected.

[0061] (2) Preparation of velvet: 3% potassium hydroxide solution was used to make velvet at 75° C. for 5 minutes to form a random pyramid-shaped velvet.

[0062] (3) Preparation of n-type emitter: Phosphorus ion implantation and furnace annealing are used to form a phosphorus-doped emitter layer on the front of p-type single crystal silicon. The phosphorus implantation energy is 10 keV and the dose is 10 15 cm 2The annealing temperature is 850°C, the time is 30 minutes, and it is completed in a nitrogen atmosphere.

[0063] (4) Wet etching: The phosphorus-doped area on the back of the p-type single crystal silicon is wet-etched with an etching solution to remove the phosphorus-doped area on the back. The etching solution is composed of 40% nitric acid, 4% hydrofluoric acid and 66% deionized water, and is treated at a temperature of 7°C for 20 seconds to form an acid polished surface.

[0064] (5) Preparation of infrared reflective layer: Chemical vapor deposition (CVD) was used to deposit two 100 nm hafnium nitride (HfN) stacked films on the back of p-type single crystal silicon. Argon and nitrogen were used as carrier gases. A pure hafnium target was selected as the cathode. A mixture of nitrogen and argon was used as the discharge gas. The flow ratio of nitrogen and nitrogen to argon was increased from 10% to 100%, and the vacuum degree was 4*10 -4 Pa, controlling the stoichiometric ratio of the hafnium nitride film from 1.1 to 1.5.

[0065] Then two layers of 100nm copper-doped hafnium nitride films were prepared by sputtering the hafnium target and the copper target simultaneously in a mixture of nitrogen and argon. The power applied to the copper target was 50W to control the copper doping amount to 1%. The power applied to the hafnium target: 100W; substrate bias: -80V; substrate temperature: 150℃. Argon flow rate: 100sccm; nitrogen flow rate: 10sccm.

[0066] Figure 3 This is a reflectivity detection diagram of the infrared reflective layer, from which it can be seen that the reflectivity is stably maintained at more than 90% at a wavelength of 1000-2000nm, and although the reflectivity decreases at 2500nm, it is still 70%.

[0067] (6) Preparation of aluminum oxide passivation layer and second silicon nitride layer: using PECVD process to sequentially deposit an aluminum oxide passivation layer with a thickness of 5 nm and a silicon nitride layer with a thickness of 100 nm on the infrared reflection layer;

[0068] (7) Preparing a p-type aluminum back surface field on the second silicon nitride layer:

[0069] Laser ablation technology is used to etch the aluminum back surface field. The laser parameters are set to a wavelength of 1064nm, a pulse width of 15ps, and a pulse repetition frequency of 500kHz. A pattern of grid line distribution is etched with a line width of 25μm and a spacing of 1.6mm between adjacent grid lines.

[0070] (8) Preparing back aluminum grid lines on the p-type aluminum back field:

[0071] Subsequently, aluminum paste is printed in the etched gate line grooves, and the silicon wafer printed with aluminum paste is sent to a sintering furnace for sintering treatment, wherein the sintering temperature is 750°C, the sintering time is 5s, and the atmosphere is compressed air.

[0072] (9) Preparing a first silicon nitride layer on the n-type emitter: using a PECVD process, the thickness of the first silicon nitride layer is 80 nm.

[0073] (10) Preparing front silver grid lines on the first silicon nitride layer:

[0074] Using screen printing technology, silver paste is printed on the first silicon nitride layer according to the designed pattern, and then the silicon wafer printed with silver grid lines is sent to the preheating zone of the sintering furnace for preheating. The preheating time is 10 minutes and the preheating temperature is 150°C. Then the silicon wafer is sent to the sintering zone for sintering. The sintering temperature is 900°C and the sintering time is 8 minutes.

[0075] After completing the above steps, the crystalline silicon cells are laser-isolated at the edges to achieve electrical insulation, the component electrodes and the back substrate layer are prepared, and they are welded according to the 6*12 array standard consisting of 72 cells to form a crystalline silicon component for standby use.

[0076] Example 2

[0077] like Figure 4 As shown, a perovskite battery includes, from top to bottom, a first transparent electrode, a hole transport layer, a perovskite light absorption layer, an electron transport layer, and a second transparent electrode.

[0078] The preparation of perovskite cells includes:

[0079] (1) The first transparent electrode is made of indium tin oxide (ITO) glass with a square resistance of 15Ω / □ and a transmittance of more than 92%. The thickness of the first transparent electrode ITO is 350nm.

[0080] (2) The method of preparing a hole transport layer on the first transparent electrode comprises: after cleaning the ITO glass, coating a nickel oxide nano-dispersion on the ITO glass substrate by a coating or spin coating method, wherein the concentration of nickel oxide is 15 mg / mL, and the thickness of the hole transport layer is 10 nm.

[0081] (3) The method of preparing a perovskite absorption layer on the hole transport layer comprises: using an evaporation method to evaporate a lead iodide (PbI2) thin film on the surface of the hole transport layer, and the vacuum degree of the cavity is 1*10 -6 mbar. The deposition rate is The deposition thickness is 300 nm, and then a layer of 50 mg / mL methylamine iodine isopropanol solution is coated on PbI2 at a rate of 600 mm / min by a coating method and then heated at 100°C for 20 minutes to obtain MAPbI3 perovskite, and the thickness of the perovskite absorption layer is 400 nm.

[0082] (4) The preparation of the electron transport layer on the perovskite absorption layer includes: coating a layer of PCBM ([6,6]-phenyl-C61-butyric acid methyl ester) solution with a concentration of 20 mg / mL at a rate of 800 mm / min by a coating method, and then annealing at 100° C. for 10 minutes to form a PCBM electron transport layer with a thickness of 20 nm.

[0083] (5) The second transparent electrode is prepared on the electron transport layer, including: sputtering a layer of ITO transparent electrode on the top of the PCBM electron transport layer, with a vacuum degree of 1x10 -5 Pa, the sputtering pressure is 1 Pa, the atmosphere is pure argon, the gas flow rate is 60 sccm, and the sputtering time is 8 min; the thickness of the second transparent electrode ITO is 200 nm.

[0084] The final result is a semi-transparent perovskite cell.

[0085] Example 3

[0086] A perovskite-crystalline silicon stacked cell assembly, comprising a perovskite cell and a crystalline silicon cell arranged in sequence; the perovskite cell prepared in Example 2 and the crystalline silicon cell prepared in Example 1 are laminated and assembled to obtain a perovskite-crystalline silicon stacked cell assembly. Among them, KPF glass with a water permeability of <2.0gsm / d and a thickness of 2mm is selected as the backplane glass, and a POE film is first applied on the backplane glass, and then a crystalline silicon cell string is applied on the film, and then a layer of POE film is applied on the string, and then a conductive glass containing a semi-transparent perovskite component is applied, and then it enters a laminator for lamination, and the lamination temperature is 120°C, the time is 15min, and the pressure is 90kPa. Figure 5 Shown is a schematic diagram of the structure of the perovskite-crystalline silicon stacked battery assembly prepared in Example 3.

[0087] Comparative Example 1

[0088] A crystalline silicon cell without an infrared reflection layer is prepared.

[0089] Comparative Example 2

[0090] The crystalline silicon cell without the infrared reflection layer prepared in Comparative Example 1 and the perovskite cell prepared in Example 2 are laminated and assembled to obtain the result.

[0091] The crystalline silicon cells, perovskite cells, and perovskite-crystalline silicon stacked cell assemblies prepared in the examples and comparative examples were tested to obtain the electrical performance parameters of the cells shown in Table 1:

[0092] Table 1. Battery electrical performance parameters

[0093]

[0094] Among them, open circuit voltage (Voc), short circuit current density (Jsc), fill factor (FF), and photoelectric conversion efficiency (PCE).

[0095] Among them, the various electrical performance parameters of the crystalline silicon cell in the perovskite-crystalline silicon tandem cell refer to the electrical performance parameters generated after a part of the sunlight is absorbed by the perovskite cell and the remaining sunlight passes through the perovskite cell and acts on the crystalline silicon cell. The test is the electrical performance parameters of the crystalline silicon cell alone after the perovskite cell filters the light. The PCE of the perovskite-crystalline silicon tandem cell is the sum of the PCE of the perovskite cell and the PCE of the crystalline silicon cell.

[0096] By comparing the crystalline silicon cell prepared in Example 1 and the crystalline silicon cell prepared in Comparative Example 1, it can be seen that the crystalline silicon cell containing an infrared reflection layer has a higher PCE. At the same time, the perovskite-crystalline silicon stacked cell in Example 3 also has a higher PCE than that in Comparative Example 2.

[0097] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A crystalline silicon battery, characterized in that: The crystalline silicon cell comprises, from top to bottom, a front silver grid line (1), a first silicon nitride layer (2), an n-type emitter (3), a p-type single crystal silicon (4), an infrared reflection layer (5), an aluminum oxide passivation layer (6), a second silicon nitride layer (7), a p-type aluminum back field (8), and a back aluminum grid line (9); The infrared reflection layer (5) is formed by stacking transition metal compound films and / or metal-doped transition metal compound films.

2. The crystalline silicon cell according to claim 1, characterized in that: The thickness of a single layer of the transition metal compound film is 100 nm-1 μm.

3. The crystalline silicon cell according to claim 1, characterized in that: The thickness of a single layer of the metal-doped transition metal compound film is 100 nm-1 μm.

4. The crystalline silicon cell according to claim 1, characterized in that: The total number of stacked layers of transition metal compound films and / or metal-doped transition metal compound films in the infrared reflection layer ranges from 1 to 5 layers.

5. The crystalline silicon cell according to claim 1, characterized in that: The transition metal compound is a compound formed by a transition metal element and a non-metal element; The non-metallic element is any one of boron, carbon and nitrogen; The transition metal element is one or more of titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum and tungsten.

6. The crystalline silicon cell according to claim 1, characterized in that: The metals in the metal-doped transition metal compound film include gold, silver, copper and aluminum.

7. A method for preparing a crystalline silicon cell as claimed in claim 1, characterized in that: include: An n-type emitter (3) is prepared on the front surface of a p-type single crystal silicon (4), a first silicon nitride layer (2) is prepared on the n-type emitter (3), an infrared reflection layer (5) is prepared on the back surface of the p-type single crystal silicon (4), an aluminum oxide passivation layer (6) is prepared on the infrared reflection layer (5), a second silicon nitride layer (7) is prepared on the aluminum oxide passivation layer (6), a p-type aluminum back field (8) is prepared on the second silicon nitride layer (7), a back aluminum grid line (9) is prepared on the p-type aluminum back field (8), and a front silver grid line (1) is prepared on the first silicon nitride layer (2), to obtain a crystalline silicon battery; The method of preparing the infrared reflection layer on the back side of the p-type single crystal silicon comprises: stacking a transition metal compound film and / or a metal-doped transition metal compound film on the back side of the p-type single crystal silicon to form the infrared reflection layer.

8. The preparation method according to claim 7, characterized in that: The total number of layers of the stacked transition metal compound thin films and / or metal-doped transition metal compound thin films is 1-5 layers.

9. A perovskite-crystalline silicon stacked battery assembly, characterized in that: The invention comprises a perovskite cell and a crystalline silicon cell prepared according to claim 7 which are arranged in sequence.

10. A method for preparing a perovskite-crystalline silicon stacked battery assembly as claimed in claim 9, characterized in that: include: Preparation of crystalline silicon cells; Preparation of perovskite top cells; The perovskite cell and the crystalline silicon cell are laminated and assembled to obtain a perovskite-crystalline silicon laminated cell assembly.

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