A structure for improving the brightness of LED chips

Abstract

The present invention discloses a structure for improving the brightness of an LED chip, and relates to the field of LED chips, and in particular to a technical solution for enhancing light extraction efficiency and reducing light loss by gridding an optical isolation layer and combining a DBR with the gridded optical isolation layer. The structure comprises: a quantum well layer in an LED chip; a transparent conductive layer and an optical isolation layer located above the quantum well layer; a distributed Bragg reflector located on the optical isolation layer; wherein the optical isolation layer is gridded to form a regular grating structure to reduce light absorption; and the reflection area is increased by combining the grating structure with the DBR. Compared with the existing structure, the present invention achieves effective suppression of light absorption and improvement of light reflection efficiency.

Description

Technical Field

[0001] The present invention relates to the field of LED chips, and in particular to a structure for improving the brightness of LED chips, which enhances light extraction efficiency and reduces light loss by combining a gridded optical isolation layer and a DBR with the gridded optical isolation layer. Background Art

[0002] As a semiconductor light-emitting device, the brightness improvement of LED chips has always been the focus of research. In the existing technology, both flip-chip LEDs and face-mounted LEDs have certain light loss problems, especially the absorption of light by the transparent conductive layer and the optical isolation layer, as well as the limitation of the reflection efficiency of the distributed Bragg reflector (DBR), resulting in low overall light extraction efficiency.

[0003] Conventional flip-chip LEDs use a method of directly depositing a transparent conductive layer and an optical isolation layer on top of the quantum well layer, and achieve current distribution and light extraction through the current injection layer and the optical isolation layer. However, due to the high light absorption rate of the transparent conductive layer and the optical isolation layer, and the limited reflection area of ​​the DBR layer, part of the light propagating downward is absorbed or scattered, affecting the overall brightness.

[0004] In order to solve the above problems, the present invention provides an improved LED chip brightness enhancement structure. Summary of the invention

[0005] The invention aims to provide a structure for improving the brightness of LED chips. By gridding the optical isolation layer and combining it with an efficient DBR design, it can reduce light absorption and increase the reflection area, thereby improving the chip's luminous brightness and light extraction efficiency.

[0006] The technical solution adopted by the present invention is:

[0007] A structure for improving the brightness of an LED chip, comprising:

[0008] Quantum well layers in LED chips;

[0009] a transparent conductive layer and an optical isolation layer located above the quantum well layer;

[0010] a distributed Bragg reflector (DBR) located on the transparent conductive layer and the optical isolation layer;

[0011] The transparent conductive layer and the optical isolation layer are subjected to a gridding process to form a regular grating structure to reduce light absorption and increase the reflection area.

[0012] The transparent conductive layer is ITO or ZnO, and the optical isolation layer is SiO 2 or Al 2 O 3 .

[0013] Preferably, the transparent conductive layer is ITO, and the optical isolation layer is SiO 2 .

[0014] The thickness of the transparent conductive layer is 20-200 nm, and the thickness of the optical isolation layer is 60-2400 nm.

[0015] Preferably, the thickness of the transparent conductive layer is 50-120 nm, and the thickness of the optical isolation layer is 300-2400 nm.

[0016] The thickness of the optical isolation layer is generally 3 to 20 times that of the transparent conductive layer: the larger thickness of the optical isolation layer helps to reduce the absorption of light by the transparent conductive layer and improve the light extraction efficiency of the grating structure; the transparent conductive layer is thinner to maintain good conductivity while avoiding excessive absorption of light.

[0017] The grid holes are blind holes with circular or square openings, and the inner walls of the grid holes gradually narrow downward from the openings to form a linearly descending slope structure.

[0018] Preferably, the minimum characteristic size of the grid hole opening is in the range of 3-12μm; preferably, the depth of the grid hole is the thickness of the optical isolation layer × a, where a is between 0.3-0.8. Increasing the aperture helps reduce the absorption of the light-efficiency isolation layer, but it also reduces the light-emitting surface of the side slope, so the aperture is generally preferably between 3-12μm; increasing the a value helps increase the roughness and increase the light-emitting efficiency, but in view of the stability of the ICP etching machine, it is generally better to be between 0.3-0.8. At the same time, a between 0.3-0.8 can also avoid the etching depth exceeding the optical isolation layer and damaging the integrity and function of the transparent conductive layer.

[0019] The distributed Bragg reflector (DBR) is formed by alternately stacking high refractive index materials and low refractive index materials, and the thickness of each layer ranges from 50 to 150 nm.

[0020] The gridding process is completed by an ICP dry etching process.

[0021] The grid structure can adjust the grid hole size and spacing according to product requirements to optimize light extraction efficiency.

[0022] The principle of rasterization is to form a regular grating structure on the optical isolation layer through photolithography and etching technology, thereby reducing the light absorption area of ​​the optical isolation layer; at the same time, the setting of the grid holes increases the effective reflection area of ​​the DBR by increasing the coverage area of ​​the DBR inside and outside the grid holes; on the other hand, the inclined structure of the grid holes causes part of the obliquely propagating light to be reflected multiple times between the DBR layer and the inner wall of the grid holes, thereby reducing light loss and further improving light extraction efficiency.

[0023] Through this innovative design, the technical progress and beneficial effects achieved by the present invention include:

[0024] 1. The grid-processed optical isolation layer effectively reduces light absorption and improves light extraction efficiency;

[0025] 2. The DBR reflection area is increased and the light reflection efficiency is improved;

[0026] 3. The grid size, spacing and DBR material can be adjusted according to different product requirements.

[0027] In summary, the present invention realizes effective suppression of light absorption and improvement of light reflection efficiency by performing a gridding process on the optical isolation layer of the LED chip in combination with a distributed Bragg reflector (DBR). BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 : Schematic diagram of the LED chip brightness enhancement structure of the present invention.

[0029] Figure 2 : Mask design drawings of embodiments 1-6 of the present invention.

[0030] Figure 3 : Schematic diagram of the effect of rasterization processing on light extraction efficiency. DETAILED DESCRIPTION

[0031] Preferred embodiments of the present invention are given below in conjunction with the accompanying drawings to illustrate the technical solutions of the present invention in detail.

[0032] Embodiment 1:

[0033] like Figure 1 As shown, an ITO transparent conductive layer 200 with a thickness of 50 nm is deposited on the epitaxial layer 100 containing the quantum well layer; and SiO is deposited on the ITO layer. 2 The optical isolation layer 300 has a thickness of 300 nm.

[0034] Using the process of photolithography (control the photolithography thickness to 8um, uniformity to within 5%), photolithography (Stepper exposure machine control the energy to 100mj) and ICP dry etching, carbon tetrafluoride (CF 4 ) The air flow rate is 100sccm, the upper electrode power is 150W, and the lower electrode power is 200W. 2 The optical isolation layer is rasterized and the mask design is pressed Figure 2 As shown in A, a regular grating structure with a grid hole opening diameter of 4 um and a depth of 100 nm is formed.

[0035] After gridding, SiO 2The DBR 400 is deposited on the optical isolation layer and is composed of alternately stacked Ti 3 O 5 (high refractive index material, thickness 120nm) and SiO 2 (low refractive index material, thickness 100nm) is formed, and the number of stacked layers is 8 pairs.

[0036] Solder the chip to the substrate to complete the production of the LED chip.

[0037] Embodiment 2:

[0038] The difference between this embodiment and embodiment 1 is that the mask design is based on Figure 2 As shown in B, a regular grating structure with a grid hole opening diameter of 4 um and a depth of 100 nm is formed.

[0039] Embodiment 3:

[0040] The difference between this embodiment and embodiment 1 is that the mask design is based on Figure 2 As shown in C, a regular grating structure with a grid hole opening size of 4×15um and a depth of 100nm is formed.

[0041] Embodiment 4:

[0042] The difference between this embodiment and embodiment 1 is that the mask design is based on Figure 2 As shown in D, a regular grating structure is formed with a circular grid hole opening diameter of 4um, a square grid hole opening size of 4×15um, and a depth of 100nm.

[0043] Embodiment 5:

[0044] The difference between this embodiment and embodiment 1 is that the thickness of the ITO transparent conductive layer is 100 nm; SiO is deposited on the ITO layer. 2 The thickness of the optical isolation layer is 1200nm. Using the process of photolithography (the thickness of the photolithography is controlled at 8um and the uniformity is within 5%), photolithography (the energy of the Stepper exposure machine is controlled at 150mj) and ICP dry etching, CF 4 Air flow rate 150sccm, upper electrode power 150W, lower electrode power 300W, mask design according to Figure 2 As shown in B, a regular grating structure with a grid hole opening diameter of 6 um and a depth of 700 nm is formed.

[0045] Embodiment 6:

[0046] The difference between this embodiment and embodiment 1 is that the thickness of the ITO transparent conductive layer is 120nm; SiO is deposited on the ITO layer. 2The thickness of the optical isolation layer is 2400nm. Using the process of photolithography (the thickness of the photolithography is controlled at 8um and the uniformity is within 5%), photolithography (the energy of the Stepper exposure machine is controlled at 250mj) and ICP dry etching, CF 4 The air flow rate is 200sccm, the upper electrode power is 200W, the lower electrode power is 300W, and the mask design is based on Figure 2 As shown in D, a regular grating structure is formed with a circular grid hole opening diameter of 4um, a square grid hole opening size of 4×15um, and a depth of 1900nm.

[0047] Comparative Examples 1-6:

[0048] Comparative Examples 1-6 correspond to Examples 1-6 respectively, with the only difference being that the comparative examples use the existing design structure, and the transparent conductive layer and the optical isolation layer are not subjected to grid processing.

[0049] Figure 3 The brightness comparison between Examples 1-6 and Comparative Examples 1-6 shows the effect of the gridding process on the light extraction efficiency. It can be seen that the structure of the present invention has a significant brightness improvement effect and higher stability compared to the existing structure, indicating that the improved solution is successful in improving the brightness of the LED chip.

Claims

1. A structure for improving the brightness of an LED chip, comprising: Quantum well layers in LED chips; a transparent conductive layer located above the quantum well layer; an optical isolation layer located above the transparent conductive layer; a distributed Bragg reflector located on the optical isolation layer; It is characterized in that the optical isolation layer is gridded to form a grid structure including a plurality of regular grid holes, and the distributed Bragg reflector is deposited on the optical isolation layer so that the DBR covers the inner surface of the grid hole, thereby increasing the reflection area and improving the light reflection efficiency.

2. The structure according to claim 1, characterized in that The transparent conductive layer is ITO or ZnO, and the optical isolation layer is SiO2 or Al2O3.

3. The structure according to claim 2, characterized in that The transparent conductive layer is ITO, and the optical isolation layer is SiO2.

4. The structure according to claim 1, characterized in that The thickness of the transparent conductive layer is 20-200 nm, and the thickness of the optical isolation layer is 60-2400 nm.

5. The structure according to claim 4, characterized in that The thickness of the transparent conductive layer is 50-120 nm, and the thickness of the optical isolation layer is 300-2400 nm.

6. The structure according to claim 4, characterized in that The thickness of the optical isolation layer is 3 to 20 times the thickness of the transparent conductive layer.

7. The structure according to claim 1, characterized in that The grid holes are blind holes with circular or square openings, and the inner walls of the grid holes gradually narrow downward from the openings to form a linearly descending slope structure.

8. The structure according to claim 7, characterized in that The minimum feature size of the grid hole openings is in the range of 3-12 μm.

9. The structure according to claim 7, characterized in that The depth of the grid holes is the thickness of the optical isolation layer×a, where a is between 0.3 and 0.8.

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