Display device and mother substrate for display device

Abstract

The invention provides a display device and a mother substrate for the display device. According to one embodiment, a display device includes a lower electrode, a rib layer, a first partition wall, an organic layer, an upper electrode, and a second partition wall. The lower electrode is arranged in the display area. The rib layer is disposed in the display area and the peripheral area, and has a pixel opening overlapping the lower electrode. The first partition wall is disposed above the rib layer in the display region. The organic layer is in contact with the lower electrode through the pixel opening. The upper electrode covers the organic layer and is in contact with the first partition wall. The second partition wall is disposed above the rib layer in the peripheral region. Each of the first partition wall and the second partition wall includes a lower portion disposed above the rib layer, and an upper portion having an end portion protruding from a side surface of the lower portion. The second partition wall includes a plurality of segments separated from each other, and each of the plurality of segments has a plurality of openings.

Description

[0001] Cross-references of related applications

[0002] This application claims priority based on Japanese Patent Application No. 2023-170053 filed on September 29, 2023, and cites all the contents described in the Japanese Patent Application. Technical Field

[0003] Embodiments of the present invention relate to a display device and a mother substrate for a display device. Background Art

[0004] In recent years, display devices using organic light emitting diodes (OLEDs) as display elements have been put into practical use. In such display devices, a technology capable of improving the yield is required. Summary of the invention

[0005] Generally speaking, according to an embodiment, a display device includes a lower electrode, a rib layer, a first partition wall, an organic layer, an upper electrode and a second partition wall. The lower electrode is arranged in a display area for displaying an image. The rib layer is arranged in the display area and a peripheral area around the display area, and has a pixel opening overlapping with the lower electrode. The first partition wall is arranged above the rib layer in the display area. The organic layer contacts the lower electrode through the pixel opening and emits light according to the application of voltage. The upper electrode covers the organic layer and contacts the first partition wall. The second partition wall is arranged above the rib layer in the peripheral area. The first partition wall and the second partition wall each include a lower portion arranged above the rib layer and an upper portion having an end protruding from the side of the lower portion. Moreover, the second partition wall includes a plurality of segments separated from each other, and each of the plurality of segments has a plurality of openings.

[0006] In addition, according to an embodiment, a mother substrate for a display device includes a plurality of panel parts, a blank area around the plurality of panel parts, a lower electrode, a rib layer, a first partition wall, an organic layer, an upper electrode and a second partition wall. The plurality of panel parts include a display area and a peripheral area around the display area, respectively. The lower electrode is disposed in the display area. The rib layer has a pixel opening overlapping with the lower electrode. The first partition wall is disposed above the rib layer in the display area. The organic layer contacts the lower electrode through the pixel opening and emits light according to the application of voltage. The upper electrode covers the organic layer and contacts the first partition wall. The second partition wall is disposed above the rib layer in at least one of the peripheral area and the blank area. The first partition wall and the second partition wall each include a lower portion disposed above the rib layer and an upper portion having an end protruding from the side of the lower portion. Moreover, the second partition wall includes a plurality of sections separated from each other, and each of the plurality of sections has a plurality of openings.

[0007] According to these structures, the yield of the display device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a diagram showing a configuration example of a display device according to the first embodiment.

[0009] Figure 2 It is a schematic plan view showing an example of the layout of sub-pixels.

[0010] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display panel taken along line III-III in FIG.

[0011] Figure 4 This is a schematic plan view of the mother substrate according to the first embodiment.

[0012] Figure 5 This is a schematic plan view of a portion of the mother substrate according to the first embodiment.

[0013] Figure 6 It is a schematic plan view showing an example of the partition wall (second partition wall) according to the first embodiment.

[0014] Figure 7 It is along Figure 6 A schematic cross-sectional view of the mother substrate taken along line VII-VII in FIG.

[0015] Fig. 8A It is a schematic cross-sectional view showing a process of forming a panel portion on a mother substrate.

[0016] Figure 8B It means next Fig. 8AA schematic cross-sectional view of the process.

[0017] Figure 8C It means next Figure 8B A schematic cross-sectional view of the process.

[0018] Fig.8D It means next Figure 8C A schematic cross-sectional view of the process.

[0019] Fig. 8E It means next Fig.8D A schematic cross-sectional view of the process.

[0020] Fig.8F It means next Fig. 8E A schematic cross-sectional view of the process.

[0021] Figure 8G It means next Fig.8F A schematic cross-sectional view of the process.

[0022] Fig. 9 This is a schematic plan view of a plurality of sections according to the second embodiment.

[0023] Fig.10 This is a schematic plan view of a plurality of sections according to the third embodiment.

[0024] Fig.11 This is a schematic plan view of a plurality of sections according to the fourth embodiment.

[0025] Fig.12 This is a schematic plan view of multiple sections of the fifth embodiment.

[0026] Fig.13 This is a schematic plan view of multiple sections of the sixth embodiment.

[0027] Fig.14 This is a schematic plan view of multiple sections of the seventh embodiment.

[0028] Fig.15 This is a schematic plan view of multiple sections of the eighth embodiment.

[0029] Fig.16 It is a schematic plan view showing another example of the configuration pattern of multiple segments in the eighth embodiment.

[0030] Fig.17 This is a schematic plan view showing yet another example of the configuration pattern of multiple segments in the eighth embodiment. DETAILED DESCRIPTION

[0031] Please refer to the attached Figure 1 Several implementation modes are described.

[0032] The disclosed content is only an example, and appropriate changes that can be easily thought of by those skilled in the art while maintaining the main idea of ​​the invention are of course included in the scope of the present invention. In addition, in order to make the description clearer, there are cases where the width, thickness, shape, etc. of each part are schematically shown in the drawings compared with the actual state, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, the same figure mark is sometimes used for the structural elements that play the same or similar functions as the aforementioned structural elements with respect to the already appeared figures, and repeated detailed descriptions are appropriately omitted.

[0033] In addition, in the drawings, mutually orthogonal X-axis, Y-axis and Z-axis are recorded as needed for easy understanding. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction of the plane including the X-direction and the Y-direction. In addition, the situation of viewing various elements parallel to the Z-direction is called plane observation.

[0034] The display device of each embodiment is an organic electroluminescent display device having an organic light emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, vehicle-mounted equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0035] [First embodiment]

[0036] Figure 1 1 is a diagram showing a configuration example of a display device DSP according to the first embodiment. The display device DSP includes a display panel PNL including an insulating substrate 10. The display panel PNL includes a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be glass or a flexible resin film.

[0037] In the present embodiment, the shape of the substrate 10 when viewed from above is a rectangle, but the shape of the substrate 10 when viewed from above is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0038] The display area DA includes a plurality of pixels PX arranged in a matrix in the X direction and the Y direction. The pixel PX includes a plurality of sub-pixels SP that display different colors. In the present embodiment, it is assumed that the pixel PX includes a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. However, the pixel PX may include a sub-pixel SP of another color such as white together with the sub-pixels SP1, SP2, and SP3, or instead of one of the sub-pixels SP1, SP2, and SP3.

[0039] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements formed of, for example, thin film transistors.

[0040] In the display area DA, a plurality of scanning lines GL for supplying scanning signals to the pixel circuits 1 of the sub-pixels SP, a plurality of signal lines SL for supplying video signals to the pixel circuits 1 of the sub-pixels SP, and a plurality of power supply lines PL are arranged. Figure 1 In the example of FIG. 5 , the scanning lines GL and the power lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0041] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and the drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the driving transistor 3 and the capacitor 4. In the driving transistor 3, one of the source electrode and the drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0042] In addition, the structure of the pixel circuit 1 is not limited to the example shown in the figure. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0043] Figure 2 1 is a schematic plan view showing an example of the layout of sub-pixels SP1, SP2, and SP3. Figure 2 In the example of FIG. 1 , the sub-pixels SP2 and SP3 are arranged in the X direction with the sub-pixel SP1 . Furthermore, the sub-pixel SP2 and the sub-pixel SP3 are arranged in the Y direction.

[0044] When the sub-pixels SP1, SP2, and SP3 are arranged in this way, columns in which the sub-pixels SP2 and SP3 are alternately arranged in the Y direction and columns in which a plurality of sub-pixels SP1 are repeatedly arranged in the Y direction are formed in the display area DA. These columns are alternately arranged in the X direction. In addition, the layout of the sub-pixels SP1, SP2, and SP3 is not limited to Figure 2 Example.

[0045] The rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. Figure 2 In the example, the pixel opening AP1 is larger than the pixel opening AP2, and the pixel opening AP2 is larger than the pixel opening AP3. That is, among the sub-pixels SP1, SP2, and SP3, the sub-pixel SP1 has the largest aperture ratio, and the sub-pixel SP3 has the smallest aperture ratio.

[0046] The sub-pixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 respectively overlapping with the pixel opening AP1. The sub-pixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 respectively overlapping with the pixel opening AP2. The sub-pixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 respectively overlapping with the pixel opening AP3.

[0047] The lower electrode LE1, the upper electrode UE1, and the portion of the organic layer OR1 that overlaps with the pixel opening AP1 constitute the display element DE1 of the sub-pixel SP1. The lower electrode LE2, the upper electrode UE2, and the portion of the organic layer OR2 that overlaps with the pixel opening AP2 constitute the display element DE2 of the sub-pixel SP2. The lower electrode LE3, the upper electrode UE3, and the portion of the organic layer OR3 that overlaps with the pixel opening AP3 constitute the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may also include an overlying layer described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0048] A conductive partition wall 6A (first partition wall) is disposed above the rib layer 5. The partition wall 6A overlaps the rib layer 5 as a whole and has the same planar shape as the rib layer 5. That is, the partition wall 6A has openings in the sub-pixels SP1, SP2, and SP3, respectively. From another point of view, the rib layer 5 and the partition wall 6A are lattice-shaped when viewed in a plan view, and surround the display elements DE1, DE2, and DE3, respectively. The partition wall 6A has the function of serving as a wiring for supplying a common voltage to the upper electrodes UE1, UE2, and UE3.

[0049] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display panel PNL taken along line III-III in FIG. A circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes Figure 1 The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that planarizes the unevenness generated by the circuit layer 11.

[0050] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Figure 3 Although not shown in the cross section of FIG. 1 , the lower electrodes LE1 , LE2 , and LE3 are connected to the pixel circuit 1 of the circuit layer 11 through contact holes provided in the organic insulating layer 12 .

[0051] The partition wall 6A includes a conductive lower portion 61 disposed on the rib layer 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a greater width than the lower portion 61. Thus, both ends of the upper portion 62 protrude from the side surfaces of the lower portion 61. Such a shape of the partition wall 6A is called an overhang.

[0052] exist Figure 3 In the example of , the lower portion 61 has a bottom layer 63 disposed on the rib layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. Figure 3 In the example, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64 .

[0053] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and is opposite to the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and is opposite to the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and is opposite to the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side of the lower portion 61 of the partition wall 6A.

[0054] The display element DE1 includes an upper cover layer CP1 covering the upper electrode UE1. The display element DE2 includes an upper cover layer CP2 covering the upper electrode UE2. The display element DE3 includes an upper cover layer CP3 covering the upper electrode UE3. The upper cover layers CP1, CP2, and CP3 respectively have the function of improving the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3 as optical adjustment layers.

[0055] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1 and the upper covering layer CP1 is referred to as the stacked film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2 and the upper covering layer CP2 is referred to as the stacked film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3 and the upper covering layer CP3 is referred to as the stacked film FL3.

[0056] A portion of the laminate film FL1 is located above the upper portion 62. This portion is separated from the portion of the laminate film FL1 located around the partition wall 6A (the portion constituting the display element DE1). Similarly, a portion of the laminate film FL2 is located above the upper portion 62, and this portion is separated from the portion of the laminate film FL2 located around the partition wall 6A (the portion constituting the display element DE2). Furthermore, a portion of the laminate film FL3 is located above the upper portion 62, and this portion is separated from the portion of the laminate film FL3 located around the partition wall 6A (the portion constituting the display element DE3).

[0057] Seal layers SE11, SE12, and SE13 are respectively provided in sub-pixels SP1, SP2, and SP3. Seal layer SE11 continuously covers the overcoat layer CP1 and the partition wall 6A around the sub-pixel SP1. Seal layer SE12 continuously covers the overcoat layer CP2 and the partition wall 6A around the sub-pixel SP2. Seal layer SE13 continuously covers the overcoat layer CP3 and the partition wall 6A around the sub-pixel SP3.

[0058] exist Figure 3 In the example, the laminated film FL1 and the sealing layer SE11 on the partition wall 6A between the sub-pixels SP1 and SP2 are separated from the laminated film FL2 and the sealing layer SE12 on the partition wall 6A. In addition, the laminated film FL1 and the sealing layer SE11 on the partition wall 6A between the sub-pixels SP1 and SP3 are separated from the laminated film FL3 and the sealing layer SE13 on the partition wall 6A.

[0059] The sealing layers SE11, SE12, and SE13 are covered by the resin layer RS1. The resin layer RS1 is covered by the sealing layer SE2. The sealing layer SE2 is covered by the resin layer RS2. The resin layers RS1, RS2, and the sealing layer SE2 are continuously provided at least in the entire display area DA, and a part of them also reaches the peripheral area SA.

[0060] A cover member such as a polarizing plate, a touch panel, a protective film or a cover glass may be further disposed on the resin layer RS2. Such a cover member may be bonded to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0061] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, SE2 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0062] The lower electrodes LE1, LE2, and LE3 include a reflective layer formed of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. Each conductive oxide layer can be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0063] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg), etc. For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0064] The organic layers OR1, OR2, and OR3 are composed of a plurality of thin films including a light-emitting layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in order along the Z direction. However, the organic layers OR1, OR2, and OR3 may also have other structures such as a so-called column structure including a plurality of light-emitting layers.

[0065] The overlying layers CP1, CP2, and CP3 have a stacked structure formed by overlapping multiple transparent layers. These transparent layers can include layers formed by inorganic materials and layers formed by organic materials. In addition, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the refractive indices of the sealing layers SE11, SE12, and SE13. In addition, at least one of the overlying layers CP1, CP2, and CP3 may be omitted.

[0066] The bottom layer 63 and the shaft layer 64 of the partition wall 6A are formed of metal materials. As the metal material of the bottom layer 63, for example, molybdenum, titanium, titanium nitride (TiN), molybdenum-tungsten alloy (MoW) or molybdenum-niobium alloy (MoNb) can be used. As the metal material of the shaft layer 64, for example, aluminum, aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY) or aluminum-silicon alloy (AlSi) can be used. In addition, the shaft layer 64 can also be formed of an insulating material.

[0067] For example, the upper portion 62 of the partition wall 6A has a laminated structure of a lower layer formed of a metal material and an upper layer formed of a conductive oxide. As the metal material forming the lower layer, for example, titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy or molybdenum-niobium alloy can be used. As the conductive oxide forming the upper layer, for example, ITO or IZO can be used. In addition, the upper portion 62 may also have a single-layer structure of a metal material. Moreover, the upper portion 62 may also include a layer formed of an insulating material.

[0068] A common voltage is supplied to the partition wall 6A. The common voltage is supplied to the upper electrodes UE1, UE2, UE3 in contact with the side surface of the lower portion 61. Pixel voltages corresponding to the image signals of the signal lines SL are supplied to the lower electrodes LE1, LE2, LE3 through the pixel circuits 1 of the sub-pixels SP1, SP2, SP3, respectively.

[0069] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, if a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in a blue wavelength region. If a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in a green wavelength region. If a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in a red wavelength region.

[0070] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (for example, white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layer into light of a color corresponding to the sub-pixels SP1, SP2, and SP3. In addition, the display device DSP may also include a layer including quantum dots that are excited by the light emitted by the light-emitting layer to generate light of a color corresponding to the sub-pixels SP1, SP2, and SP3.

[0071] When manufacturing the display device DSP, a large mother substrate is produced on which a plurality of regions (panel portions) each corresponding to the display panel PNL are formed. A structure applicable to the mother substrate will be described below.

[0072] Figure 4 This is a schematic plan view of the mother substrate MB (mother substrate for display device) of this embodiment. The mother substrate MB is rectangular, for example, as shown in the figure, but can also be other shapes such as a circle. The mother substrate MB has a plurality of panel parts PP arranged in a matrix and a blank area BA around these panel parts PP.

[0073] Figure 5 It is a schematic plan view of a part of the mother substrate MB. The outer shape of each panel unit PP corresponds to the cutting line CL1 for cutting the panel unit PP from the mother substrate MB.

[0074] Each panel portion PP includes the display area DA and the peripheral area SA described above. In addition, each panel portion PP includes an inspection area TA. An inspection pad for inspecting the operation of the display panel PNL is arranged in the inspection area TA.

[0075] A cutting line CL2 is formed between the peripheral area SA and the inspection area TA. When manufacturing the display device DSP, the panel portion PP is first cut out from the mother substrate MB along the cutting line CL1. Then, the cut panel portion PP is subjected to the above-mentioned inspection. After the inspection, the inspection area TA is cut out from the panel portion PP along the cutting line CL2.

[0076] In this embodiment, the partition wall 6B (second partition wall) is arranged in the blank area BA, the peripheral area SA, and the inspection area TA. Figure 5In FIG. 1 , a lattice-shaped pattern is indicated in the arrangement region of the partition wall 6B. In addition, the lattice-shaped pattern does not represent the shape of the partition wall 6B itself.

[0077] From the viewpoint of efficiently cutting out the panel portion PP, it is preferable not to provide the partition wall 6B on the cutting line CL1. Similarly, it is preferable not to provide the partition wall 6B on the cutting line CL2.

[0078] Figure 6 1 is a schematic plan view showing an example of a partition wall 6B. The partition wall 6B has a plurality of segments SG separated from each other. Figure 6 In the example of , these segments SG have the same shape and are arranged in the X direction and the Y direction. The segment SG is a quadrilateral (rectangle or square) having two sides extending in the X direction and two sides extending in the Y direction.

[0079] The segment SG has three openings APa, APb, and APc. The openings APa, APb, and APc are arranged in the same layout as the pixel openings AP1, AP2, and AP3, for example. Figure 6 In the example, the openings APb and APc are arranged in the X direction with the opening APa. Moreover, the openings APb and APc are arranged in the Y direction. In addition, the openings APb and APc are smaller than the opening APa. The sizes of the openings APb and APc are, for example, the same, but may be different from each other.

[0080] A gap G is formed between adjacent segments SG. Figure 6 In the example of FIG. 1 , the gap G is in a lattice shape including a portion extending in the X direction and a portion extending in the Y direction.

[0081] The segment SG has a width Wx in the X direction and a width Wy in the Y direction. The gap G has a uniform width Wg as a whole. However, the gap G may also vary locally.

[0082] The widths Wx and Wy are, for example, respectively greater than the width in the X direction and the width in the Y direction of the pixel PX, but are not limited to this example. The widths Wx and Wy may be the same or different from each other. The width Wg is, for example, smaller than the widths Wx and Wy (Wg<Wx, Wy). Preferably, the width Wg is less than 40 μm (Wg≦40 μm). As a result, the effect of suppressing peeling of the laminated films FL1, FL2, and FL3 is improved as described later.

[0083] In addition, it is not necessary to arrange the blank area BA, the surrounding area SA, and the inspection area TA as a whole. Figure 6 Segments SG of other shapes may be arranged in at least a part of the blank area BA, the peripheral area SA, and the inspection area TA.

[0084] In addition, the shape of the segment SG is not limited to Figure 6 The quadrilateral shown in FIG. 1 may be other polygonal shapes or may be a shape including a curved outline. The number and shape of the openings in the segment SG are also not limited to Figure 6 Example.

[0085] Figure 7 It is along Figure 6 A schematic cross-sectional view of the mother substrate MB taken along line VII-VII in FIG. The partition wall 6B is arranged on the rib layer 5 in the same manner as the partition wall 6A. Figure 7 In the example of FIG. 1 , the circuit layer 11 and the organic insulating layer 12 are disposed between the rib layer 5 and the substrate 10. The circuit layer 11 and the organic insulating layer 12 may not be disposed in at least a portion of the blank area BA, the peripheral area SA, and the inspection area TA.

[0086] The partition wall 6B includes a lower portion 61 and an upper portion 62 similarly to the partition wall 6A. The lower portion 61 of the partition wall 6B includes a bottom layer 63 and an axial layer 64. In the partition wall 6B as well, the end of the upper portion 62 protrudes from the side surface of the lower portion 61 (axial layer 64).

[0087] The rib layer 5 is exposed from the partition wall 6B in the openings APa, APb, APc and the gap G. The width Wg of the gap G described above corresponds to the distance between the upper portions 62 of the segments SG adjacent to each other with the gap G therebetween.

[0088] Next, an example of a method for manufacturing the display device DSP will be described. FIG. 8A to FIG. 8G 2 is a schematic cross-sectional view showing a process of forming the panel portion PP on the mother substrate MB. FIG. 8A to FIG. 8G In FIG. 1 , the focus is mainly on the display area DA and the elements below the organic insulating layer 12 are omitted.

[0089] When forming the panel portion PP, first, a circuit layer 11 and an organic insulating layer 12 are formed on the substrate 10 of the mother substrate MB. Fig. 8A As shown, lower electrodes LE1 , LE2 , and LE3 are formed on the organic insulating layer 12 .

[0090] Then, if Figure 8B As shown, the rib layer 5 and the partition wall 6A are formed. The pixel openings AP1, AP2, and AP3 of the rib layer 5 can be provided after the partition wall 6A is formed, or can be provided before the partition wall 6A is formed. Figure 7 The partition wall 6B shown is formed in the same process as the partition wall 6A.

[0091] After the rib layer 5 and the partition walls 6A and 6B are formed, a process for forming the display elements DE1, DE2, and DE3 is performed. In this embodiment, it is assumed that the display element DE1 is formed first, the display element DE2 is formed next, and the display element DE3 is formed last. However, the order of forming the display elements DE1, DE2, and DE3 is not limited to this example.

[0092] When forming the display element DE1, first Figure 8C As shown in FIG. 1 , a laminate film FL1 and a sealing layer SE11 are formed. Figure 3 As shown, it includes an organic layer OR1 contacting the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and an overlying layer CP1 covering the upper electrode UE1.

[0093] The organic layer OR1, the upper electrode UE1, and the upper cover layer CP1 are formed by evaporation. In addition, the sealing layer SE11 is formed by CVD (Chemical Vapor Deposition).

[0094] The laminate film FL1 and the sealing layer SE11 are not formed only in the display area DA of each panel part PP, but are formed on the entire mother substrate MB including the peripheral area SA, the inspection area TA and the blank area BA. The laminate film FL1 is divided into a plurality of parts by the overhanging partition walls 6A and 6B. The sealing layer SE11 continuously covers the divided parts of the laminate film FL1 and the partition walls 6A and 6B.

[0095] Next, the laminate film FL1 and the sealing layer SE11 are patterned. Fig.8D As shown, a resist R is disposed on the sealing layer SE11. The resist R covers the sub-pixel SP1 and a part of the partition wall 6A around it.

[0096] Then, by etching with the resist R as a mask, as Fig. 8E As shown, the portions of the laminate film FL1 and the sealing layer SE11 exposed from the resist R are removed. In other words, the portions of the laminate film FL1 and the sealing layer SE11 that overlap with the lower electrode LE1 remain, and the other portions are removed. Thus, a display element DE1 is formed in the sub-pixel SP1. For example, in the peripheral area SA, the inspection area TA, and the blank area BA, the laminate film FL1 and the sealing layer SE11 are removed by the etching. The etching can include wet etching and dry etching performed sequentially on the sealing layer SE11, the overlying layer CP1, the upper electrode UE1, and the organic layer OR1. After these etchings, the resist R is removed.

[0097] The display element DE2 is formed in the same order as the display element DE1. That is, when forming the display element DE2, the laminated film FL2 and the sealing layer SE12 are formed on the entire mother substrate MB. Figure 3 As shown, it includes an organic layer OR2 contacting the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and an overlying layer CP2 covering the upper electrode UE2.

[0098] The organic layer OR2, the upper electrode UE2 and the upper cover layer CP2 are formed by evaporation. In addition, the sealing layer SE12 is formed by CVD. The laminate film FL2 is divided into a plurality of parts by the overhanging partition walls 6A and 6B. The sealing layer SE12 continuously covers the divided parts of the laminate film FL2 and the partition walls 6A and 6B. By patterning such a laminate film FL2 and the sealing layer SE2, as shown in FIG. Fig.8F As shown, the display element DE2 is formed in the sub-pixel SP2. For example, in the peripheral area SA, the inspection area TA, and the blank area BA, the laminated film FL2 and the sealing layer SE12 are removed by etching during the patterning.

[0099] The display element DE3 is formed in the same order as the display elements DE1 and DE2. That is, when forming the display element DE3, the laminated film FL3 and the sealing layer SE13 are formed on the entire mother substrate MB. Figure 3 As shown, it includes an organic layer OR3 contacting the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and an overlying layer CP3 covering the upper electrode UE3.

[0100] The organic layer OR3, the upper electrode UE3 and the upper cover layer CP3 are formed by evaporation. In addition, the sealing layer SE13 is formed by CVD. The laminate film FL3 is divided into a plurality of parts by the overhanging partition walls 6A and 6B. The sealing layer SE13 continuously covers the divided parts of the laminate film FL3 and the partition walls 6A and 6B. By patterning such a laminate film FL3 and the sealing layer SE13, as shown in FIG. Figure 8G As shown, the display element DE3 is formed in the sub-pixel SP3. For example, in the peripheral area SA, the inspection area TA, and the blank area BA, the laminated film FL3 and the sealing layer SE13 are removed by etching during the patterning.

[0101] After forming display elements DE1, DE2, and DE3, Figure 3 The resin layer RS1, the sealing layer SE2 and the resin layer RS2 are shown. Then, each panel portion PP is cut out from the mother substrate MB along the cutting line CL1.

[0102] Then, each panel unit PP is inspected. This inspection includes lighting inspection of each display element DE1, DE2, DE3 using the inspection pads arranged in the inspection area TA. After the inspection, the inspection area TA is cut along the cutting line CL2. Thus, the display panel PNL is completed.

[0103] In addition, in the peripheral area SA, the inspection area TA, and the blank area BA, at least one of the laminated films FL1, FL2, and FL3 may not be removed but may remain.

[0104] Here, some effects of this embodiment are described. When forming the display elements DE1, DE2, and DE3, the laminated films FL1, FL2, and FL3 are formed on the entire mother substrate MB. The laminated films FL1, FL2, and FL3 formed by evaporation have weak adhesion to the substrate, so there is a possibility of peeling off from the substrate during the manufacture of the display device DSP. If the peeling is extended, the laminated films FL1, FL2, and FL3 and the sealing layers SE11, SE12, and SE13 thereon will peel off, and undesirable particles may be generated.

[0105] In the display area DA, the laminated films FL1, FL2, and FL3 are divided into small pieces by the grid-shaped partition walls 6A. Therefore, the laminated films FL1, FL2, and FL3 are difficult to peel off from the substrate. In addition, in the present embodiment, the partition walls 6B are arranged in the peripheral area SA, the inspection area TA, and the blank area BA. Therefore, the peeling of the laminated films FL1, FL2, and FL3 is also suppressed in the peripheral area SA, the inspection area TA, and the blank area BA.

[0106] In this embodiment, if Figure 6 As shown, the partition wall 6B includes a plurality of sections SG, and each section SG has a plurality of openings APa, APb, and APc. With such a structure, the laminated films FL1, FL2, and FL3 are divided into small pieces in the peripheral area SA, the inspection area TA, and the blank area BA, thereby improving the effect of suppressing the laminated films FL1, FL2, and FL3 from peeling off.

[0107] In addition, if the partition wall 6B is not divided into a plurality of segments SG and is arranged without gaps in a wide range, the partition wall 6B forms a relatively large conductor. In this case, electrostatic discharge (ESD) caused by the partition wall 6B is likely to occur. If electrostatic discharge occurs, there is a possibility that the partition wall 6B and the surrounding elements will be damaged.

[0108] In addition, when the partition wall 6B is not divided into a plurality of segments SG, there is a possibility that the resist (for example, the resist used to pattern the rib layer 5) disposed behind the partition wall 6B may be poorly formed. That is, the diffusion of the resist is suppressed by the partition wall 6B, and the resist may not be fully filled to the portion below the upper portion 62 of the partition wall 6B. In this case, when the resist is dried in a reduced pressure environment, there is a possibility that the space where the resist is not disposed expands and breaks.

[0109] When the partition wall 6B is composed of a plurality of segments SG separated by gaps G as in the present embodiment, the electrostatic discharge described above is less likely to occur because the partition wall 6B as a conductor is subdivided. In addition, the resist easily spreads through the gaps G, so resist shape defects can also be suppressed.

[0110] If the width Wg is too large, the effect of suppressing the peeling of the laminated films FL1, FL2, and FL3 may be reduced. In this regard, the inventors have verified that if the width Wg is 40 μm or less as described above, the peeling of the laminated films FL1, FL2, and FL3 can be suppressed well.

[0111] As described above, according to the structure of this embodiment, it is possible to suppress peeling of the laminated films FL1, FL2, and FL3, electrostatic discharge, or resist shape defects, thereby improving the yield rate during the manufacture of the display device DSP and the mother substrate MB.

[0112] The shape and arrangement of the segments SG constituting the partition wall 6B are not limited to Figure 6 In the following second to eighth embodiments, other examples applicable to the segment SG are disclosed.

[0113] [Second embodiment]

[0114] Fig. 9 FIG. 2 is a schematic plan view of a plurality of segments SG according to the second embodiment. In this embodiment, segments SG adjacent to each other in the Y direction are offset in the X direction. Specifically, Fig. 9 In the example, a first column RW1 including a plurality of segments SG1 (first segment) arranged along the X direction (first direction) and a second column RW2 including a plurality of segments SG2 (second segment) arranged along the X direction are formed. In the Y direction (second direction), the first column RW1 and the second column RW2 are alternately arranged.

[0115] The segment SG1 and the segment SG2 are offset from each other in the X direction. Thus, for example, a gap G between the segments SG1 and SG2 is formed in a T-shape as shown in a portion surrounded by a dotted circle C1.

[0116] When the laminated films FL1, FL2, and FL3 described above peel off in the gap G, if the gap G is linear, the peeling tends to progress over a wide range. On the other hand, if the gap G is T-shaped, for example, the peeling direction Fig. 9 When the peeling progresses in the direction indicated by the arrow A in FIG. 1 , further expansion of the peeling is suppressed by the segment SG2 located in the direction of the progress.

[0117] In addition, Fig. 9 2 shows an example in which the segments SG adjacent to each other in the Y direction are offset in the X direction. As another example, the segments SG adjacent to each other in the X direction may be offset in the Y direction.

[0118] [Third Embodiment]

[0119] Fig.10 It is a schematic plan view of a plurality of segments SG (hereinafter referred to as segments SG3) according to the third embodiment. The segments SG3 have a stepped (sawtooth) planar shape.

[0120] The segment SG3 has a plurality of openings APa, APb, and APc. In addition, the segment SG3 is a polygonal shape having an internal angle θ greater than 180°. Fig.10 In the example, the interior angle θ is 270°.

[0121] A step-shaped gap G is formed between adjacent segments SG3. That is, as shown by a portion surrounded by a dotted circle C2, the gap G is bent in an L-shape. Even with such a structure, expansion of peeling of the laminated films FL1, FL2, and FL3 along the gap G can be suppressed.

[0122] The gap G has, for example, a uniform width Wg as a whole. The width Wg is preferably 40 μm or less, similarly to the first embodiment. The width Wg may be partially different.

[0123] [Fourth embodiment]

[0124] Fig.11 This is a schematic plan view of a plurality of segments SG (hereinafter referred to as segment SG4) of the fourth embodiment. Segment SG4 has a V-shaped planar shape. Specifically, segment SG4 has a first portion P4a, a second portion P4b, and a third portion P4c connecting the first portion P4a and the second portion P4b. The first portion P4a and the second portion P4b extend in different directions. The directions in which the first portion P4a and the second portion P4b extend, for example, intersect with the X direction and the Y direction.

[0125] Part 1 P4a and Part 2 P4b and Fig.10The segment SG3 shown is also stepped. The first portion P4a, the second portion P4b and the third portion P4c have a plurality of openings APa, APb, APc.

[0126] The plurality of segments SG4 are arranged such that the first portions P4a are arranged in the X direction, the second portions P4b are arranged in the X direction, and the third portions P4c are arranged in the X direction. A gap G is formed in a step shape between the first portions P4a of adjacent segments SG4 and between the second portions P4b of adjacent segments SG4.

[0127] exist Fig.11 In the example, the width of the gap G is increased in the region Ga of the third part P4c of the adjacent segment SG4. In one example, the width Wg of the gap G is 40 μm or less except for the region Ga. However, the shape of each segment SG4 may be determined so that the width Wg is substantially uniform throughout the gap G.

[0128] [Fifth embodiment]

[0129] Fig.12 FIG. 1 is a schematic plan view of a plurality of segments SG according to the fifth embodiment. Fig.12 In the example of , a plurality of segments SG51 to SG57 having different shapes are arranged. Each segment SG51 to SG57 has a plurality of openings APa, APb, and APc.

[0130] Segment SG51 has a complex planar shape with multiple arms protruding from a rectangular central portion. Segment SG52 is a rectangular shape that is long in the Y direction. Segment SG53 is a rectangular shape that is long in the X direction. Segment SG54 is an L-shape having a portion extending in the X direction and a portion extending in the Y direction. Segment SG55 is an L-shape obtained by rotating segment SG54 90° clockwise. Segment SG56 is an L-shape obtained by rotating segment SG55 90° clockwise. Segment SG57 is an L-shape obtained by rotating segment SG56 90° clockwise. Segments SG51, SG54 to SG57 are polygonal shapes having at least one internal angle greater than 180°, specifically, an internal angle of 270°, similar to segment SG3.

[0131] As an example of the plurality of arms included in the segment SG51, attention will be paid to the first arm P51a and the second arm P51b extending in the Y direction. Fig.12 In the embodiment, the segment SG52 is disposed between the first arm portion P51a and the second arm portion P51b. Thus, a U-shaped gap G is formed as shown in the portion surrounded by the dotted circle C3.

[0132] Here, not only the portion of interest, but also a plurality of such U-shaped gaps G are formed around the segment SG51. Fig.12In the example of , L-shaped gaps G are also formed in various locations as in the portion surrounded by the dotted circle C2. In the U-shaped gaps G as well, similarly to the L-shaped and T-shaped gaps G, the progress of peeling of the laminated films FL1, FL2, and FL3 is suppressed.

[0133] In the present embodiment as well, it is preferable that the width Wg of the gap G formed between two adjacent segments SG51 to SG57 is 40 μm or less. The width Wg may be uniform throughout the gap G or may vary partially.

[0134] [Sixth embodiment]

[0135] Fig.13 1 is a schematic plan view of a plurality of segments SG (hereinafter referred to as segment SG6) according to the sixth embodiment. Fig.10 The section SG3 shown has a short stepped plan view.

[0136] The segment SG6 has a plurality of openings APa, APb, and APc. In addition, the segment SG6 is a polygonal shape having a plurality of internal angles greater than 180°, specifically, a plurality of internal angles of 270°, similarly to the segment SG3 and the like.

[0137] exist Fig.13 In the example, a T-shaped gap G is formed at the portion where three segments SG6 are adjacent, as shown in the portion surrounded by the dotted circle C1. In addition, an L-shaped gap G is formed between two adjacent segments SG6, as shown in the portion surrounded by the dotted circle C2. In the present embodiment, the width Wg of the gap G is preferably 40 μm or less. The width Wg may be uniform throughout the gap G or may be partially different.

[0138] [Seventh embodiment]

[0139] Fig.14 This is a schematic plan view of a plurality of segments SG (hereinafter referred to as segments SG7) according to the seventh embodiment. The segments SG7 have a cross-shaped planar shape. Adjacent segments SG7 are offset in both the X direction and the Y direction.

[0140] The segment SG7 has a plurality of openings APa, APb, and APc. Also, similarly to the segment SG3, the segment SG7 is a polygonal shape having a plurality of internal angles greater than 180°, specifically, a plurality of internal angles of 270°.

[0141] exist Fig.14 In the example of FIG. 1 , as shown in the portion surrounded by the dotted circle C2 , an L-shaped gap G is formed between adjacent segments SG7 . In the present embodiment as well, the width Wg of the gap G is preferably 40 μm or less. The width Wg may be uniform throughout the gap G or may vary locally.

[0142] [Eighth embodiment]

[0143] Fig.15 1 is a schematic plan view of a plurality of segments SG (hereinafter referred to as segments SG8) according to the eighth embodiment. The segment SG8 has a so-called swastika-shaped plan view. Specifically, the segment SG8 has four arm portions P81 to P84 extending in different directions.

[0144] The arm portion P81 is L-shaped and has a straight portion L1 extending in the X direction and a straight portion L2 extending in the Y direction. Fig.15 In the example, the lengths of the straight portions L1 and L2 are equal. The arm portion P82 is an L-shaped portion obtained by rotating the arm portion P81 clockwise by 90°. The arm portion P83 is an L-shaped portion obtained by rotating the arm portion P82 clockwise by 90°. The arm portion P84 is an L-shaped portion obtained by rotating the arm portion P83 clockwise by 90°. Adjacent segments SG8 are offset in both the X direction and the Y direction.

[0145] The segment SG8 has a plurality of openings APa, APb, and APc. In addition, the segment SG8 is a polygonal shape having a plurality of internal angles greater than 180°, specifically, a plurality of internal angles of 270°, similarly to the segment SG3 and the like.

[0146] A portion of the arm P84 of another segment SG8 is located between the arms P81 and P82 of each segment SG8. In addition, a portion of the arm P82 of another segment SG8 is located between the arms P83 and P84 of each segment SG8. Thus, a U-shaped gap G is formed as shown in the portion surrounded by the dotted circle C3.

[0147] On the other hand, Fig.15 In the example of , the other segment SG8 is not located between the arms P81 and P84 of each segment SG8. The other segment SG8 is not located between the arms P82 and P83 of each segment SG8 either.

[0148] exist Fig.15 In the example, the gap G is composed of a plurality of portions having different widths. That is, in the region Gb between the arms P81 and P84 of each segment SG8, ​​the region Gc between the arms P82 and P83 of each segment SG8, ​​and the region Gd surrounded by the arms P81 to P84 of each different segment SG8, ​​the width of the gap G is larger than that of the portion surrounded by the dotted circle C3.

[0149] It is preferable that the width Wg of the gap G is 40 μm or less in most parts. In one example, the width Wg of the gap G except for the regions Gb, Gc, and Gd may be 40 μm or less.

[0150] Fig.16This is a schematic plan view showing another example of the configuration of the segment SG8. The shape of the segment SG8 shown in this figure is similar to Fig.15 However, in Fig.16 In the example, Fig.15 The regions Gb and Gc shown disappear, and each segment SG8 is arranged in such a way that the region Gd is reduced.

[0151] That is, in Fig.16 In the example, a portion of the arm P83 of the other segment SG8 is located between the arm P81 and the arm P84 of each segment SG8. In addition, a portion of the arm P81 of the other segment SG8 is located between the arm P82 and the arm P83 of each segment SG8.

[0152] By eliminating the regions Gb and Gc in this manner, it is possible to increase the portion forming a U-shape in the gap G. As a result, even if peeling of the laminated films FL1 , FL2 , and FL3 occurs in the gap G, the progress of the peeling can be easily suppressed.

[0153] Fig.17 1 is a schematic plan view showing another example of the configuration of the segment SG8. Fig.15 and Fig.16 Compared with the shape of the segments shown in FIG. 1 , the straight line portion L2 of each of the arm portions P81 to P84 is different in that it is shorter than the straight line portion L1 .

[0154] exist Fig.17 In the example, Fig.15 Each segment SG8 is arranged so that the regions Gb, Gc, and Gd shown in the figure disappear. Thereby, the width Wg of the gap G can be uniformed as a whole.

[0155] In addition to the first to eighth embodiments, various shapes and arrangement patterns can be applied to the segments SG. Two or more of the segments SG disclosed in each embodiment may be arranged in at least a portion of the peripheral area SA, the inspection area TA, and the margin area BA.

[0156] In each embodiment, it is assumed that the partition wall 6B (segment SG) is disposed in the peripheral area SA, the inspection area TA, and the blank area BA. As another example, the partition wall 6B may not be disposed in any one of the peripheral area SA, the inspection area TA, and the blank area BA. In the case where the partition wall 6B is not disposed in the peripheral area SA, the display panel PNL and the display device DSP without the partition wall 6B are manufactured.

[0157] Based on the display devices, mother substrates and manufacturing methods disclosed in the above embodiments, all display devices, mother substrates and manufacturing methods that can be implemented by technicians in this field by making appropriate design changes also fall within the scope of the present invention as long as they include the essence of the present invention.

[0158] In the scope of the concept of the present invention, those skilled in the art can think of various variations, and these variations are also interpreted as belonging to the scope of the present invention. For example, for the above-mentioned embodiments, those skilled in the art appropriately add, delete or design changes the structural elements to obtain the scheme, or add, omit or change the conditions of the process to obtain the scheme, as long as they have the gist of the present invention, they are included in the scope of the present invention.

[0159] In addition, other effects brought about by the solutions described in the above embodiments are of course interpreted as being brought about by the present invention if they are clear from the description of this specification or can be appropriately imagined by those skilled in the art.

Claims

1. A display device, characterized in that: have: A lower electrode, which is arranged in a display area for displaying an image; a rib layer, which is disposed in the display area and a peripheral area around the display area and has a pixel opening overlapping with the lower electrode; a first partition wall disposed above the rib layer in the display region; an organic layer, which contacts the lower electrode through the pixel opening and emits light according to the application of voltage; an upper electrode covering the organic layer and contacting the first partition wall; and a second partition wall disposed above the rib layer in the peripheral region, The first partition wall and the second partition wall each include a lower portion disposed above the rib layer and an upper portion having an end portion protruding from a side surface of the lower portion. The second partition wall includes a plurality of sections separated from each other, The plurality of sections each have a plurality of openings.

2. The display device according to claim 1, characterized in that At least a portion of the gaps formed between the plurality of segments has a width of 40 μm or less.

3. The display device according to claim 1, characterized in that At least one of the plurality of sections has a plurality of openings of different sizes.

4. The display device according to claim 1, characterized in that The plurality of sections include: a first column including a plurality of first segments arranged along a first direction; and a second column adjacent to the first column in a second direction intersecting the first direction and including a plurality of second segments arranged along the first direction, The plurality of first segments and the plurality of second segments are offset in the first direction.

5. The display device according to claim 1, characterized in that At least one of the plurality of segments is polygonal in shape having an internal angle greater than 180°.

6. The display device according to claim 1, characterized in that: At least one of the plurality of sections is stepped.

7. The display device according to claim 1, characterized in that: At least one of the plurality of sections is cross-shaped.

8. The display device according to claim 1, characterized in that: At least one of the plurality of sections includes a first arm and a second arm, A part of the other segment is arranged between the first arm portion and the second arm portion.

9. The display device according to claim 1, characterized in that: At least one of the plurality of sections has a plurality of arms extending in different directions.

10. The display device according to claim 1, characterized in that: The gaps formed between the plurality of sections include T-shaped, L-shaped or U-shaped portions.

11. A mother substrate for a display device, characterized in that: have: A plurality of panel parts, each of which includes a display area and a peripheral area around the display area; A blank area around the plurality of panel portions; A lower electrode, which is disposed in the display area; a rib layer having a pixel opening overlapping the lower electrode; a first partition wall disposed above the rib layer in the display region; an organic layer, which contacts the lower electrode through the pixel opening and emits light according to the application of voltage; an upper electrode covering the organic layer and contacting the first partition wall; and a second partition wall disposed above the rib layer in at least one of the peripheral region and the blank region, The first partition wall and the second partition wall each include a lower portion disposed above the rib layer and an upper portion having an end portion protruding from a side surface of the lower portion. The second partition wall includes a plurality of sections separated from each other, The plurality of sections each have a plurality of openings.

12. The mother substrate for a display device according to claim 11, characterized in that: At least a portion of the gaps formed between the plurality of segments has a width of 40 μm or less.

13. The mother substrate for a display device according to claim 11, wherein: At least one of the plurality of sections has a plurality of openings of different sizes.

14. The mother substrate for a display device according to claim 11, wherein: The plurality of sections include: a first column including a plurality of first sections arranged along a first direction; and a second column adjacent to the first column in a second direction intersecting the first direction and including a plurality of second segments arranged along the first direction, The plurality of first segments and the plurality of second segments are offset in the first direction.

15. The mother substrate for a display device according to claim 11, wherein: At least one of the plurality of segments is polygonal in shape having an internal angle greater than 180°.

16. The mother substrate for a display device according to claim 11, wherein: At least one of the plurality of sections is stepped.

17. The mother substrate for a display device according to claim 11, wherein: At least one of the plurality of sections is cross-shaped.

18. The mother substrate for a display device according to claim 11, wherein: At least one of the plurality of sections includes a first arm and a second arm, A part of the other segment is arranged between the first arm portion and the second arm portion.

19. The mother substrate for a display device according to claim 11, wherein: At least one of the plurality of sections has a plurality of arms extending in different directions.

20. The mother substrate for a display device according to claim 11, characterized in that: The gaps formed between the plurality of sections include T-shaped, L-shaped or U-shaped portions.

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