Heterojunction memristor based on two-dimensional material and preparation method thereof
By growing a two-dimensional material layer in situ on the metal capping layer and combining with heterostructure, the problems of difficult manufacturing and poor performance of two-dimensional material memristors are solved, and efficient and low-cost large-area two-dimensional material growth and excellent electrical performance are achieved.
Patent Information
- Application Number
- CN202411865412.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-18
- Publication Date
- 2025-04-01
AI Technical Summary
The existing two-dimensional material memristors are difficult to manufacture and poorly perform. Especially when building vertical structures, they are prone to introduce organic impurities and damage the material. The metal bottom electrodes are prone to dehumidification at high temperatures, resulting in film rupture and performance damage.
A heteromemory resistor structure based on two-dimensional materials is adopted, including a substrate, a bottom electrode layer, a metal capping layer, a two-dimensional material layer, a silicon layer, an oxide layer and a top electrode layer. The two-dimensional material layer is grown in situ on the metal capping layer by chemical vapor deposition method, avoiding dehumidification at high temperatures, and improving electrical properties through the heterostructure.
It achieves uniform and undamaged large-area in-situ growth of two-dimensional materials, avoids impurity pollution and dehumidification problems, improves the electrical performance of the device, and has lower operating voltage, energy consumption, and better stability and durability.
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Figure CN119744114A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor devices and process technologies, and in particular to a heterojunction memristor based on two-dimensional materials and a preparation method thereof. Background Art
[0002] Memristors have become an important component in neuromorphic computing applications due to their high integration, multi-value data storage capabilities, and simple structure. In particular, memristors made of two-dimensional materials such as transition metal chalcogenides and hexagonal boron nitride have faster switching speeds and lower power consumption than traditional metal oxide memristors, making them particularly suitable for neuromorphic computing and have received extensive research attention.
[0003] However, it is not easy to construct vertical structure memristors using two-dimensional materials. Two-dimensional materials represented by transition metal chalcogenides are usually synthesized by chemical vapor deposition. In a high temperature and sulfur vapor environment, even inert bottom electrode materials such as platinum will react with sulfur, so it is usually necessary to transfer the grown two-dimensional materials to the target substrate before manufacturing the device. The surface of two-dimensional materials lacks dangling bonds, and they can be transferred and adsorbed to any substrate through van der Waals forces. This process requires a series of tedious steps such as spin coating the support layer, soaking in alkaline or acidic solutions, and degumming. However, these transfer steps inevitably introduce organic impurities, and alkaline or acidic solutions may damage the two-dimensional materials. In addition, when the film is placed on the target substrate mechanically or manually, it is easy to cause film wrinkles and bubbles, which ultimately leads to damage to device performance.
[0004] The metal bottom electrode of the vertical memristor is usually a metal film with a thickness of tens to hundreds of nanometers. It is very difficult to prepare two-dimensional materials directly on the metal bottom electrode. Chemical vapor deposition synthesis of two-dimensional materials requires a high temperature (usually 600-1000°C). At such a high temperature, the metal film may dewet. After the metal film is deposited on the substrate, due to factors such as temperature, surface energy or stress, the film begins to crack and form a discontinuous state, such as droplets or holes. This phenomenon usually occurs when the film is subjected to thermal stress or other mechanical stress, causing the film to retreat or split from the substrate. The driving force for dewetting is the minimization of the total energy of the system. When the adhesion between the metal film and the substrate is weak, the film is prone to dewetting, reducing the contact area to reduce the surface energy. Summary of the invention
[0005] The purpose of the present invention is to provide a heterojunction memristor based on two-dimensional materials and a preparation method thereof, aiming to solve the problems of difficulty in manufacturing and poor performance of existing two-dimensional material memristors.
[0006] To achieve the above-mentioned objectives, the present invention provides a heterojunction memristor based on two-dimensional materials, the structure of which includes a substrate, a bottom electrode layer, a metal capping layer, a two-dimensional material layer, a silicon layer, an oxide layer and a top electrode layer from bottom to top; wherein the resistive functional layer is a heterostructure composed of the two-dimensional material layer, the silicon layer and the oxide layer, and is connected to the bottom electrode layer through the metal capping layer; wherein the two-dimensional material layer is directly grown in situ on the metal capping layer.
[0007] Wherein, the metal capping layer is a transition metal with a melting point greater than 1500° C. and a thickness of 1-200 nm.
[0008] Wherein, the substrate is a silicon-based substrate;
[0009] The bottom electrode layer is any one of gold and graphene, with a thickness of 1-100 nm;
[0010] The two-dimensional material layer is any one of transition metal chalcogenides, and has a thickness of 1-200 nm;
[0011] The silicon layer has a thickness of 1-100 nm;
[0012] The oxide layer is any one of zinc oxide, zirconium oxide and hafnium oxide, and has a thickness of 1-200 nm;
[0013] The top electrode layer is any one of silver, copper and titanium, and has a thickness of 1-200 nm.
[0014] The present invention also proposes a method for preparing a heterojunction memristor based on a two-dimensional material, which is used to prepare the heterojunction memristor based on a two-dimensional material, and comprises the following steps:
[0015] Step 1: depositing the bottom electrode layer, the metal capping layer and the precursor metal layer on the substrate in sequence;
[0016] Step 2: placing a sample containing the substrate, the bottom electrode layer, the metal capping layer and the precursor metal layer into a chemical vapor deposition reactor, reacting with reactants to convert the precursor metal layer into a two-dimensional material layer, and during the reaction, silicon will migrate from the silicon-based substrate to the surface of the two-dimensional material layer;
[0017] Step 3: depositing an oxide layer on the silicon layer by magnetron sputtering;
[0018] Step 4: Deposit the top electrode layer by sputtering or evaporation using a mask or photolithography process.
[0019] Wherein, an adhesion layer may be deposited between the substrate and the bottom electrode layer, and the adhesion layer is any one of titanium, chromium and nickel, and has a thickness of 1-20 nm.
[0020] Wherein, the precursor metal layer is the precursor metal required for synthesizing the two-dimensional material layer.
[0021] Wherein, the metal capping layer and the precursor metal layer may be made of the same metal.
[0022] Wherein, the reactant is any one of sulfur and selenium.
[0023] Beneficial effects of the present invention:
[0024] 1. It can achieve uniform, large-area, damage-free and low-cost in-situ growth of two-dimensional materials, avoiding a series of cumbersome steps and impurity contamination problems caused by the transfer method. By depositing the metal capping layer on the bottom electrode layer, the bottom electrode layer is prevented from dehumidifying due to the high temperature during the chemical vapor deposition process. In general, metal films with lower melting points are more likely to dehumidify at high temperatures. This is because during the heating process of low-melting-point metals, the bonding force between atoms is weaker, and the interface force between the film and the substrate is relatively low, which makes the film more likely to break or fall off. High-melting-point metals require higher temperatures to reach dehumidification conditions. Transition metals such as molybdenum, tungsten and platinum have relatively high melting points and can be used as materials for the metal capping layer.
[0025] 2. A method for preparing a heterojunction memristor based on two-dimensional materials is proposed, which is universal and easy to operate. The metal capping layer and the precursor metal layer can be of the same metal. By depositing a thicker metal capping layer, it serves as both a metal capping layer for the bottom electrode layer and a precursor for synthesizing a two-dimensional material layer, thereby simplifying the process steps. In addition, the silicon layer migrates from the substrate to the surface of the two-dimensional material during the chemical vapor deposition process, without the need for deposition by other means.
[0026] 3. The present invention introduces a novel heterostructure consisting of a two-dimensional material layer, a silicon layer and an oxide layer as the resistive switching functional layer of the memristor. The different ion migration rates of the two-dimensional material layer, the silicon layer and the oxide layer are utilized to guide the formation and fusing of the conductive filaments to be localized near the interface between the two-dimensional material layer and the silicon layer, so that the memristor has better electrical properties, lower operating voltage and lower energy consumption, as well as better stability and durability.
[0027] 4. This invention proposes a heterojunction memristor based on two-dimensional materials, which can effectively simulate the characteristics of neural synapses. It is expected to be applied to the research and development of storage-computing integrated structures and high-performance neuromorphic computing, and promote the progress and development of highly integrated and miniaturized brain-like chips. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0029] Figure 1 It is a schematic diagram of the device structure of a heterojunction memristor based on two-dimensional materials of the present invention.
[0030] Figure 2 This is a TEM cross-sectional image of the device prepared in specific embodiment 1 of the present invention, with a scale of 50 nm.
[0031] Figure 3 This is a transmission electron microscope photograph of the growth of the MoS2 layer of the sample prepared in specific embodiment 1 of the present invention, with a scale of 10 nm.
[0032] Figure 4 This is a schematic diagram of the IV curve of the memristor prepared in specific embodiment 1 of the present invention.
[0033] Figure 5 This is a characteristic diagram of simulating synaptic long-term potentiation and long-term depression of the heterojunction memristor prepared in specific embodiment 1 of the present invention.
[0034] Figure 6 This is a schematic diagram of the heterojunction memristor prepared in specific embodiment 1 of the present invention simulating synaptic excitatory postsynaptic current.
[0035] Figure 7 This is a schematic diagram of the response of the heterojunction memristor prepared in specific embodiment 1 of the present invention to simulated synapse responses to continuous pulses. DETAILED DESCRIPTION
[0036] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.
[0037] See also Figure 1 The present invention provides a heterojunction memristor based on two-dimensional materials, the structure of which includes a substrate, a bottom electrode layer, a metal capping layer, a two-dimensional material layer, a silicon layer, an oxide layer and a top electrode layer from bottom to top; wherein the resistive functional layer is a heterostructure composed of the two-dimensional material layer, the silicon layer and the oxide layer, and is connected to the bottom electrode layer through the metal capping layer; wherein the two-dimensional material layer is directly grown in situ on the metal capping layer.
[0038] The metal capping layer is a transition metal with a melting point greater than 1500° C. and a thickness of 1-200 nm.
[0039] The substrate is a silicon-based substrate;
[0040] The bottom electrode layer is any one of gold and graphene, with a thickness of 1-100 nm;
[0041] The two-dimensional material layer is any one of transition metal chalcogenides, and has a thickness of 1-200 nm;
[0042] The silicon layer has a thickness of 1-100 nm;
[0043] The oxide layer is any one of zinc oxide, zirconium oxide and hafnium oxide, and has a thickness of 1-200 nm;
[0044] The top electrode layer is any one of silver, copper and titanium, and has a thickness of 1-200 nm.
[0045] Furthermore, the present invention also proposes a method for preparing a heterojunction memristor based on a two-dimensional material, which is used to prepare the heterojunction memristor based on a two-dimensional material, comprising the following steps:
[0046] Step 1: depositing the bottom electrode layer, the metal capping layer and the precursor metal layer on the substrate in sequence;
[0047] Step 2: placing a sample containing the substrate, the bottom electrode layer, the metal capping layer and the precursor metal layer into a chemical vapor deposition reactor, reacting with reactants to convert the precursor metal layer into a two-dimensional material layer, and during the reaction, silicon will migrate from the silicon-based substrate to the surface of the two-dimensional material layer;
[0048] Step 3: depositing an oxide layer on the silicon layer by magnetron sputtering;
[0049] Step 4: Deposit the top electrode layer by sputtering or evaporation using a mask or photolithography process.
[0050] An adhesion layer may be deposited between the substrate and the bottom electrode layer. The adhesion layer is any one of titanium, chromium and nickel, and has a thickness of 1-20 nm.
[0051] The precursor metal layer is a precursor metal required for synthesizing a two-dimensional material layer.
[0052] The metal capping layer and the precursor metal layer may be made of the same metal.
[0053] The reactant is any one of sulfur and selenium.
[0054] The following two specific embodiments further illustrate the heterojunction memristor based on two-dimensional materials and the preparation method thereof. Figures 2 to 7 .
[0055] Example 1
[0056] In the heterojunction memristor and the preparation method thereof of the present embodiment, the metal capping layer and the precursor metal layer are the same metal molybdenum, which are deposited simultaneously through one process step. In addition, an adhesion layer of chromium is deposited between the substrate and the bottom electrode layer, including the following steps:
[0057] 1) SiO2 / Si was used as the substrate of the device, wherein the thickness of the SiO2 layer was about 300 nm, and was successively cleaned with acetone, ethanol, and deionized water ultrasonically and then dried;
[0058] 2) Using magnetron sputtering, an adhesion layer of chromium is deposited on the substrate. The sputtering parameters can be as follows: chromium is used as the sputtering target, argon is used as the sputtering atmosphere, the argon flow rate is 40 sccm, and the sputtering pressure is 2.1×10 -6 Torr, substrate temperature was room temperature, sputtering power was 100 W, and time was 30 s.
[0059] 3) Using magnetron sputtering, deposit gold as the bottom electrode layer on the adhesion layer. The sputtering parameters can be as follows: gold is used as the sputtering target, argon is used as the sputtering atmosphere, the argon flow rate is 40 sccm, and the sputtering pressure is 2.1×10 -6 Torr, substrate temperature was room temperature, sputtering power was 100 W, and time was 3 min.
[0060] 4) Using magnetron sputtering, a metal capping layer and a precursor metal layer are deposited on the bottom electrode layer simultaneously. The sputtering parameters can be as follows: molybdenum is used as the sputtering target, argon is used as the sputtering atmosphere, the argon flow rate is 40 sccm, and the sputtering pressure is 2.1×10 -6 Torr, substrate temperature was room temperature, sputtering power was 100 W, and time was 20 min.
[0061] 5) Chemical vapor deposition is used to react the precursor metal layer to generate MoS2. In order to facilitate temperature control, a quartz boat containing 50 mg of sulfur powder and the sample to be reacted are placed in different tube furnaces for heating; within 30 minutes, the sulfur powder is heated from room temperature to 160°C, and the sample is heated from room temperature to 800°C; then within 40 minutes, the sulfur powder is raised from 160°C to 200°C, while the sample temperature is maintained at 800°C. During the entire sulfurization process, a 100 sccm argon gas flow is introduced and the gas pressure is maintained at around 5 Torr; finally, the furnace is allowed to cool naturally to room temperature. In this step, the upper part of the molybdenum layer deposited in step 4 is converted into a two-dimensional material layer, and the remaining part can be regarded as the actual metal capping layer. In addition, silicon will migrate from the SiO2 / Si substrate to the surface of the two-dimensional material layer.
[0062] 6) Using magnetron sputtering method, zinc oxide is deposited on the silicon layer. The sputtering parameters can be as follows: zinc oxide is used as the sputtering target, argon gas is used as the sputtering atmosphere, the argon flow rate is 40 sccm, the oxygen flow rate is 5 sccm, and the sputtering pressure is 2.1×10 - 6 Torr, substrate temperature was room temperature, sputtering power was 150 W, and time was 2 min.
[0063] 7) Using a metal mask and thermal evaporation to deposit a silver top electrode layer with a thickness of about 70 nm, the heterojunction memristor is prepared.
[0064] The TEM characterization of the device structure of the heterojunction memristor prepared in Example 1 is as follows Figure 2 As shown; further, higher magnification Figure 3 Shows the growth status of two-dimensional MoS2; IV curve of the test memristor is as follows Figure 4 As shown, it can be seen that the device has small threshold voltages of approximately 0.4V and -0.2V.
[0065] Figure 5 This reflects the long-term potentiation and long-term depression characteristics of the heterojunction memristor simulating artificial synapses. First, 100 consecutive positive pulses were applied to the device, and the device's conductance increased with the increase in the number of pulses, simulating the long-term potentiation characteristics of biological synapses; then 100 consecutive negative pulses were applied to the device, and the device's conductance decreased with the increase in the number of pulses, simulating the long-term depression characteristics of biological synapses. Figure 6 The artificial synaptic device simulated excitatory postsynaptic currents, and the current enhancement caused by a single pulse stimulation lasted for more than 200 seconds; Figure 7 This is the response of the artificial synaptic device to continuous pulses. It can be seen that the latter pulse brings a larger response current than the previous pulse.
[0066] Example 2
[0067] The metal capping layer and the precursor metal layer of this embodiment are the same metal tungsten, which are deposited simultaneously by electron beam evaporation, and the metal capping layer and the precursor metal layer are 80 nm thick in total. Other specific implementations of the sample to be reacted are the same as those in Example 1.
[0068] Furthermore, chemical vapor deposition was used to react the precursor metal layer to generate WS2. In order to facilitate temperature control, a quartz boat containing 100 mg of sulfur powder and the sample to be reacted were placed in different tube furnaces for heating; within 40 minutes, the sulfur powder was heated from room temperature to 160°C, and the sample was heated from room temperature to 900°C; then within 40 minutes, the sulfur powder was heated from 160°C to 200°C, while the sample temperature was maintained at 900°C. During the entire sulfurization process, 100 sccm of argon gas flow was introduced and the gas pressure was maintained at around 5 Torr; finally, the furnace was allowed to cool naturally to room temperature; in addition, silicon will migrate from the SiO2 / Si substrate to the surface of the two-dimensional material layer.
[0069] Furthermore, hafnium oxide is deposited on the silicon layer by magnetron sputtering. The sputtering parameters can be as follows: hafnium is used as the sputtering target, argon and oxygen are used as the sputtering atmosphere, the argon flow rate is 40 sccm, the oxygen flow rate is 40 sccm, and the sputtering pressure is 2.1×10 -6 Torr, substrate temperature was room temperature, sputtering power was 100 W, and time was 3 min.
[0070] Finally, a copper top electrode layer with a thickness of about 100 nm was deposited by thermal evaporation using a metal mask.
[0071] What is disclosed above is only a preferred embodiment of the present invention, which certainly cannot be used to limit the scope of rights of the present invention. A person skilled in the art can understand that all or part of the processes of the above embodiments and equivalent changes made according to the claims of the present invention still fall within the scope of the invention.
Claims
1. A heterojunction memristor based on two-dimensional materials, characterized in that: The structure includes, from bottom to top, a substrate, a bottom electrode layer, a metal capping layer, a two-dimensional material layer, a silicon layer, an oxide layer and a top electrode layer; wherein the resistive functional layer is a heterogeneous structure composed of the two-dimensional material layer, the silicon layer and the oxide layer, and is connected to the bottom electrode layer through the metal capping layer; wherein the two-dimensional material layer is directly grown in situ on the metal capping layer.
2. The heterojunction memristor based on two-dimensional materials according to claim 1, characterized in that: The metal capping layer is a transition metal with a melting point greater than 1500° C. and a thickness of 1-200 nm.
3. The heterojunction memristor based on two-dimensional materials according to claim 1, characterized in that: The substrate is a silicon-based substrate; The bottom electrode layer is any one of gold and graphene, with a thickness of 1-100 nm; The two-dimensional material layer is any one of transition metal chalcogenides, and has a thickness of 1-200 nm; The silicon layer has a thickness of 1-100 nm; The oxide layer is any one of zinc oxide, zirconium oxide and hafnium oxide, and has a thickness of 1-200 nm; The top electrode layer is any one of silver, copper and titanium, and has a thickness of 1-200 nm.
4. A method for preparing a heterojunction memristor based on a two-dimensional material, used to prepare the heterojunction memristor based on a two-dimensional material as claimed in claim 1, characterized in that: The following steps are involved: Step 1: depositing the bottom electrode layer, the metal capping layer and the precursor metal layer on the substrate in sequence; Step 2: placing a sample containing the substrate, the bottom electrode layer, the metal capping layer and the precursor metal layer into a chemical vapor deposition reactor, reacting with reactants to convert the precursor metal layer into a two-dimensional material layer, and during the reaction, silicon will migrate from the silicon-based substrate to the surface of the two-dimensional material layer; Step 3: depositing an oxide layer on the silicon layer by magnetron sputtering; Step 4: Deposit the top electrode layer by sputtering or evaporation using a mask or photolithography process.
5. The method for preparing a heterojunction memristor based on two-dimensional materials according to claim 4, characterized in that: An adhesion layer may be deposited between the substrate and the bottom electrode layer. The adhesion layer is any one of titanium, chromium and nickel, and has a thickness of 1-20 nm.
6. The method for preparing a heterojunction memristor based on two-dimensional materials according to claim 4, characterized in that: The precursor metal layer is a precursor metal required for synthesizing a two-dimensional material layer.
7. The method for preparing a heterojunction memristor based on two-dimensional materials according to claim 4, characterized in that: The metal capping layer and the precursor metal layer may be made of the same metal.
8. The method for preparing a heterojunction memristor based on two-dimensional materials according to claim 4, characterized in that: The reactant is any one of sulfur and selenium.