A method and device for generating compressed test vectors

CN119744383APending Publication Date: 2025-04-01HUAWEI TECH CO LTD
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Patent Information

Application Number
CN202280099436.3
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2022-09-30
Publication Date
2025-04-01

AI Technical Summary

Technical Problem

During the chip testing process, the existing technology is inefficient in generating compressed test vectors, resulting in high software power consumption and a reduced success rate of test vector merging. Especially when Gaussian elimination technology calculates the implicit value of irrelevant bits, subsequent merging is increased. and compression risk.

Method used

By obtaining the decompression matrix of the chip under test, the first linear correlation matrix and the maximum irrelevant group are obtained, and the implicit values ​​in the background vector are filled to generate the second background vector, thereby updating the background vector to avoid subsequent merging and compression conflicts. Improve the merging success rate and generation efficiency of test vectors.

Benefits of technology

It significantly reduces the software power consumption of test vector generation, improves the merging success rate and generation efficiency of compressed test vectors, and avoids conflict problems caused by undetermined implicit values.

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Abstract

A method for generating a compressed test vector comprises: obtaining a first linear correlation matrix and a first maximally irrelevant group according to a decompression matrix corresponding to a chip to be tested, wherein the decompression matrix is ​​a matrix corresponding to a decompression circuit structure of the chip to be tested (S301); filling an implicit value into a first target bit in a first background vector according to the first linear correlation matrix and / or the first maximally irrelevant group to obtain a second background vector, wherein the first target bit includes all or part of the irrelevant bits in the first background vector (S302); and generating a compressed test vector according to the second background vector (S303).
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