Light detection element and electronic device

Abstract

[Problem] To provide a light detection element that can minimize deterioration in signal processing performance while avoiding an increase in the size of a circuit used in digital conversion processing of an analog pixel signal. [Solution] A light detection element according to the present disclosure includes a plurality of pixels arranged in a matrix. The plurality of pixels have: a photoelectric conversion circuit that photoelectrically converts incident light and outputs an analog pixel signal; a comparator outputting a comparison result of the analog pixel signal and a reference signal; a storage circuit storing data of an output signal from the comparator; and a switching circuit that switches between output destinations of the analog pixel signal or the output signal such that the memory circuit can be shared between the plurality of pixels.

Description

Technical Field

[0001] The present disclosure relates to a light detecting element and an electronic device. Background Art

[0002] The light detection element used in the CMOS image sensor is provided with an AD converter that digitally converts the analog pixel signal. In the AD converter, the comparator compares the analog pixel generated by the photoelectric conversion of the photodiode with the ramp signal. In addition, the latch circuit (storage circuit) stores the result of the comparison by the comparator.

[0003] The number of latch circuits is determined according to the operation mode of the light detection element. For example, in the image plane phase difference AF processing, three latch circuits are required for each pixel. When the number of latch circuits increases, the size of the circuit of the AD converter increases, and thus one AD converter may not fit in the area of ​​one pixel. In this case, measures are taken for sharing one AD converter by multiple pixels.

[0004] However, since a plurality of pixels sharing a latch circuit are driven by a rolling shutter system, a global shutter cannot be used. Therefore, there is a concern of adverse effects such as the occurrence of focal plane distortion and degradation of signal processing speed, which may lead to performance degradation.

[0005] Reference List

[0006] Patent Literature

[0007] Patent Document 1: WO 2016 / 009832 A Summary of the invention

[0008] Problems to be solved by the present invention

[0009] The present disclosure provides a light detection element and an electronic device capable of minimizing performance degradation in signal processing while avoiding an increase in the size of a circuit for digital conversion processing of an analog pixel signal.

[0010] Solution to the problem

[0011] The light detection element of the present disclosure includes a plurality of pixels arranged in a matrix. The plurality of pixels include: a photoelectric conversion circuit that photoelectrically converts incident light to output an analog pixel signal; a comparator that outputs a result of comparing the analog pixel signal with a reference signal; a storage circuit that stores data of the output signal of the comparator; and a switching circuit that switches the output destination of the analog pixel signal or the output signal to share the storage circuit among the plurality of pixels.

[0012] A switching circuit may be connected to the output of the comparator.

[0013] The switching circuit may be arranged on the input terminal side of the comparator.

[0014] The photoelectric conversion circuit may include a first photodiode and a second photodiode connected to an input terminal of the comparator,

[0015] The comparator may output a first output signal when the photoelectric conversion circuit is in a reset state, output a second output signal indicating a comparison result between the analog pixel signal and the reference signal when the first photodiode photoelectrically converts the incident light, and output a third output signal indicating a comparison result between the analog pixel signal and the reference signal when the first photodiode and the second photodiode photoelectrically convert the incident light,

[0016] The storage circuit may include a plurality of latch circuits, and

[0017] The switching circuit may switch output destinations of the first output signal, the second output signal, and the third output signal to different latch circuits, respectively.

[0018] The photoelectric conversion circuit may include: a first photodiode connected to an input terminal of the comparator;

[0019] The comparator may output a first output signal when the photoelectric conversion circuit is in a reset state, and output a second output signal indicating a comparison result between an analog pixel signal and the reference signal a plurality of times when the first photodiode photoelectrically converts the incident light,

[0020] The storage circuit may include a plurality of latch circuits, and

[0021] The switching circuit may switch the output destinations of the first output signal and the second output signal to different latch circuits respectively each time.

[0022] The comparator may output the second output signal a plurality of times by performing a plurality of AD conversion processes on the analog pixel signal once transmitted to the floating diffusion layer.

[0023] The comparator may output a second output signal under different conditions each time.

[0024] The comparator may output the second output signal under the condition that a gain of at least one of the analog pixel signal or the reference signal is changed.

[0025] The switching circuit may switch an output destination of an analog pixel signal or an output signal so that mutually adjacent pixels among a plurality of pixels share the storage circuit.

[0026] Multiple pixels can receive light beams of multiple colors individually, and

[0027] Memory circuits may be shared by pixels receiving the same color of light.

[0028] The plurality of pixels may include a first pixel and a second pixel adjacent to the first pixel,

[0029] The storage circuit may include a first latch circuit and a second latch circuit, and

[0030] The switching circuit may select the first latch circuit of the first pixel as an output destination of the first output signal, select the second latch circuit of the first pixel as an output destination of the second output signal, and select the first latch circuit of the second pixel as an output destination of the third output signal.

[0031] The plurality of pixels may include a first pixel and a second pixel adjacent to the first pixel,

[0032] The comparator can output the second output signal twice,

[0033] The storage circuit may include a first latch circuit and a second latch circuit, and

[0034] The switching circuit can select the first latch circuit of the first pixel as the output destination of the first output signal, select the second latch circuit of the first pixel as the output destination of the second output signal at the first time, and select the first latch circuit of the second pixel as the output destination of the second output signal at the second time.

[0035] The plurality of pixels may include first to fourth pixels arranged close to each other,

[0036] The storage circuit may include a first latch circuit, and

[0037] Among the first to fourth pixels, the number of pixels sharing the first latch circuit may be variable.

[0038] It may also include:

[0039] a first chip in which a plurality of photoelectric conversion circuits are arranged; and

[0040] a second chip in which a plurality of comparators, a plurality of storage circuits, a plurality of switching circuits, and a repeater for reading data from the storage circuits are arranged; and

[0041] The repeater may be arranged at a position facing the center of the plurality of photoelectric conversion circuits, and the plurality of comparators, the plurality of storage circuits, and the plurality of switching circuits may be symmetrically arranged with the repeater interposed therebetween.

[0042] The storage circuit may be arranged on both sides of the repeater, the comparator may be arranged on one side of the storage circuit, and the switching circuit may be arranged on one side of the comparator.

[0043] The switching circuit may include a multiplexer.

[0044] The switching circuit may include:

[0045] a first switch element, switching whether to output the analog pixel signal to a first pixel among the plurality of pixels; and

[0046] The second switch element switches whether to output the analog pixel signal to a second pixel different from the first pixel.

[0047] The photoelectric conversion circuit may include a selection transistor of a comparator that switches whether to output an analog pixel signal to a first pixel among the plurality of pixels, and

[0048] The switching circuit may include a first switching element that switches whether to output the analog pixel signal to a comparator of a second pixel different from the first pixel.

[0049] The photoelectric conversion circuit may include a transfer transistor that switches whether to transfer charges obtained by photoelectrically converting incident light to a floating diffusion layer of a first pixel among the plurality of pixels, and

[0050] The switching circuit may include a first switching element that switches whether to transfer the charges to a floating diffusion layer of a second pixel different from the first pixel.

[0051] The electronic device of the present disclosure includes a plurality of pixels arranged in a matrix. The plurality of pixels include: a photoelectric conversion circuit that photoelectrically converts incident light to output an analog pixel signal; a comparator that outputs a result of comparing the analog pixel signal with a reference signal; a storage circuit that stores data of the output signal of the comparator; and a switching circuit that switches the output destination of the analog pixel signal or the output signal to share the storage circuit among the plurality of pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 is a block diagram showing the configuration of a light detecting element according to the first embodiment.

[0053] Figure 2 is a block diagram showing an example of a circuit configuration of a pixel according to the first embodiment.

[0054] Figure 3 is a block diagram showing an example of a circuit configuration of a selection circuit.

[0055] Figure 4 is a diagram showing an example of a stacked structure of the light detecting element 1 according to the first embodiment.

[0056] Figure 5 is a diagram showing a layout example of pixels according to the first embodiment.

[0057] Figure 6 is a diagram showing another layout example of pixels according to the first embodiment.

[0058] Figure 7 is a block diagram showing a circuit configuration of a pixel according to Comparative Example 1.

[0059] Figure 8 is a block diagram showing a circuit configuration of a pixel according to Comparative Example 2.

[0060] Fig. 9 : is a timing chart for explaining the operation mode of the image plane phase difference AF of the pixel according to the first embodiment.

[0061] Fig.10 : is a timing chart for explaining an operation mode in which the image plane phase difference AF process of the pixel according to the first embodiment is not performed.

[0062] Fig.11 is a block diagram showing an example of a circuit configuration of a pixel according to the second embodiment.

[0063] Fig.12 : is a timing chart for explaining the multi-channel AD processing of the pixel according to the second embodiment.

[0064] Fig.13 : is a timing chart for explaining an operation mode in which the multi-channel AD processing of the pixel according to the second embodiment is not performed.

[0065] Fig.14 is a block diagram showing a circuit configuration of a pixel according to Comparative Example 3.

[0066] Fig.15 is a timing chart for explaining an operation mode in which the multi-AD processing of the pixel according to Comparative Example 3 is not performed.

[0067] Fig.16 1 is a timing chart for explaining the bit extension process performed by the pixel according to the fourth embodiment.

[0068] Fig.17 is a block diagram showing an example of a circuit configuration of a pixel according to a fifth embodiment.

[0069] Fig.18 is a block diagram showing an example of a circuit configuration of a pixel according to a sixth embodiment.

[0070] Fig.19 is a block diagram showing an example of a circuit configuration of a pixel according to a seventh embodiment.

[0071] Fig. 20is a block diagram showing an example of a circuit configuration of a pixel according to an eighth embodiment.

[0072] Fig.21 is a diagram showing a layout example of pixels according to the eighth embodiment.

[0073] Fig. 22 is a timing chart for explaining an operation mode when the number of pixels sharing the first latch circuit is set to zero.

[0074] Fig.23 is a timing chart for explaining an operation mode when the number of pixels sharing the first latch circuit is set to 2.

[0075] Fig.24 : is a timing chart for explaining the operation mode of the image plane phase difference AF processing when the number of pixels sharing the first latch circuit is set to four.

[0076] Fig.25 is a block diagram showing an example of a circuit configuration of a pixel according to a ninth embodiment.

[0077] Fig.26 is a diagram showing a layout example of pixels according to a ninth embodiment.

[0078] Fig. 27 is a block diagram showing an example of a circuit configuration of a pixel according to a tenth embodiment.

[0079] Fig.28 is a block diagram showing an example of a circuit configuration of a pixel according to an eleventh embodiment.

[0080] Fig.29 is a block diagram showing an example of a circuit configuration of a pixel according to a twelfth embodiment.

[0081] Fig.30 is a diagram showing an example of a color pattern of a pixel according to a thirteenth embodiment.

[0082] Fig.31 is a diagram showing another example of a color pattern of a pixel according to the thirteenth embodiment.

[0083] Fig.32 is a diagram showing still another example of a color pattern of a pixel according to the thirteenth embodiment.

[0084] Fig.33 It is shown that Fig.31 0 is a block diagram of an embodiment of a circuit configuration of a pixel arranged in a color pattern as shown in FIG.

[0085] Fig.34 It shows that the Fig.33FIG. 1 is a diagram showing an example of a layout of gate wiring of a transfer transistor in a photoelectric conversion circuit.

[0086] Fig.35 is a diagram showing a layout example of gate wiring of a transfer transistor when the number of shared photoelectric conversion circuits increases.

[0087] Fig.36 is a block diagram showing a schematic configuration of an electronic device according to a fourteenth embodiment.

[0088] Fig.37 This is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0089] Fig.38 It is an explanatory diagram showing an example of the installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0090] (First Embodiment)

[0091] Figure 1 is a block diagram showing the configuration of a light detecting element according to the first embodiment. Figure 1 The light detection element 1 shown in FIG. 1 includes a pixel array unit 22 , a pixel driving circuit 23 , a digital-to-analog converter (DAC) 24 , a vertical driving circuit 25 , a repeater 26 , an output unit 27 , and a timing generating circuit 28 .

[0092] In the pixel array unit 22, a plurality of pixels 21 are arranged in a matrix. The circuit configuration of each pixel 21 will be described later. The pixel driving circuit 23 drives each pixel 21 in the pixel array unit 22. The DAC 24 generates a ramp signal RAMP, which is a ramp signal whose level (voltage) changes over time, and supplies the ramp signal RAMP to each pixel 21. The vertical driving circuit 25 outputs the digital pixel signal generated in the pixel 21 to the repeater 26 in a predetermined order based on the timing signal provided from the timing generation circuit 28. The repeater 26 reads the data of the digital pixel signal from the pixel 21 and transmits the data to the output unit 27. The output unit 27 performs predetermined digital processing, such as a black level correction process or a correlated double sampling (CDS) process for correcting a black level. The timing generation circuit 28 includes a timing generator that generates various timing signals, etc., and provides the generated various timing signals to the pixel driving circuit 23, the DAC 24, the vertical driving circuit 25, etc.

[0093] Figure 2 is a block diagram showing an example of a circuit configuration of a pixel according to the first embodiment. Figure 2The pixel 21a (first pixel) and the pixel 21b (second pixel) shown in each include a photoelectric conversion circuit 211, a comparator 212, a selection circuit 213 and a storage circuit 214. The pixel 21a and the pixel 21b have a relationship of sharing each storage circuit 214, and are arranged adjacent to each other. In addition, the comparator 212 and the storage circuit 214 are configured as an analog-to-digital converter (ADC) for digitally converting the analog pixel signal SIG output from the photoelectric conversion circuit 211. In addition, the selection circuit 213 of the pixel 21a and the pixel 21b is each configured as a switching circuit 215, which switches the output destination of the analog pixel signal SIG to the storage circuit 214 of the pixel 21a or the storage circuit 214 of the pixel 21b.

[0094] The photoelectric conversion circuit 211 includes a first photodiode PD1, a second photodiode PD2, a first transfer transistor M1, and a second transfer transistor M2. In this embodiment, in order to perform image plane phase difference autofocus (AF) processing, the pixels 21a and 21b are divided by the first photodiode PD1 and the second photodiode PD2, respectively.

[0095] The first photodiode PD1 and the second photodiode PD2 are examples of photoelectric conversion elements that perform photoelectric conversion on incident light. The anode of the first photodiode PD1 is grounded, and the cathode is connected to the first input terminal of the comparator 212 through the first transfer transistor M1. At the same time, the anode of the second photodiode PD2 is also grounded, and the cathode is connected to the first input terminal of the comparator 212 through the second transfer transistor M2.

[0096] For example, the first transfer transistor M1 and the second transfer transistor M2 each include an N-channel MOS transistor. The drain of the first transfer transistor M1 is connected to the cathode of the first photodiode PD1, and the source is connected to the first input terminal of the comparator 212. Meanwhile, the drain of the second transfer transistor M2 is connected to the cathode of the second photodiode PD2, and the source is connected to the first input terminal of the comparator 212.

[0097] A transmission signal is input from the pixel driving circuit 23 to the gate of each of the first transfer transistor M1 and the second transfer transistor M2. The first transfer transistor M1 and the second transfer transistor M2 perform a switching operation based on the transmission signal. When the first transfer transistor M1 is turned on, the charge accumulated by the photoelectric conversion of the first photodiode PD1 is transferred to the floating diffusion layer FD. In addition, when the second transfer transistor M2 is turned on, the charge accumulated by the photoelectric conversion of the second photodiode PD2 is transferred to the floating diffusion layer FD. In the floating diffusion layer FD, a voltage signal is generated as an analog pixel signal SIG according to the charge amount. The analog pixel signal SIG is input to the first input terminal of the comparator 212.

[0098] Note that the circuit configuration of the photoelectric conversion circuit 211 is not limited to Figure 2 The photoelectric conversion circuit 211 may be provided with various pixel transistors such as a reset transistor for resetting the potential of the floating diffusion layer FD.

[0099] The comparator 212 compares the analog pixel signal SIG input to the first input terminal with the ramp signal RAMP input to the second input terminal as a reference signal. In addition, the comparator 212 outputs an output signal VCO indicating the comparison result from the output terminal. At this time, when the voltage of the ramp signal RAMP becomes the same as the voltage of the analog pixel signal SIG, the voltage level of the output signal VCO is reversed.

[0100] The selection circuit 213 selects the output destination of the output signal VCO according to the control of the pixel driving circuit 23. The selection circuit 213 includes, for example, a multiplexer. Figure 3 An embodiment of the circuit configuration of the selection circuit 213 is described.

[0101] Figure 3 is a block diagram showing an example of a circuit configuration of the selection circuit 213 . Figure 3 The selection circuit 213 shown includes a first AND circuit 301 , a second AND circuit 302 , an inverter circuit 303 , and an OR circuit 304 .

[0102] The first AND circuit 301 performs a positive logic operation (AND operation) on the output signal VCO input to the input terminal IN0 from the pixel driving circuit 23 and the selection signal input to the selection terminal SEL. The operation result of the first AND circuit 301 is input to the OR circuit 304.

[0103] The second AND circuit 302 performs a positive logic operation (AND operation) on the output signal VCO input to the input terminal IN1 and the selection signal input to the selection terminal SEL and inverted by the inverter circuit 303. The operation result of the second AND circuit 302 is input to the OR circuit 304.

[0104] The OR circuit 304 performs a negative logical operation (OR operation) on the operation result of the first AND circuit 301 and the operation result of the second AND circuit 302. The storage circuit 214 as the output destination of the output signal VCO is selected according to the operation result of the OR circuit 304.

[0105] like Figure 2As shown, the storage circuit 214 includes a first latch circuit 214a and a second latch circuit 214b. The first latch circuit 214a and the second latch circuit 214b respectively store the digital pixel signal selected by the selection circuit 213. The first latch circuit 214a and the second latch circuit 214b have the same circuit configuration. The time code indicating the time at this time sent from the time code generating unit (not shown) is input to each latch circuit. Then, in each latch circuit, the inversion code Coln when the output signal VCO of the comparator 212 is inverted is stored in the first latch circuit 214a and the second latch circuit 214b. In this way, the digital value obtained by digitizing the analog pixel signal SIG to N (N is a positive number) bits is read by the repeater 26.

[0106] Figure 4 is a diagram showing an example of a stacked structure of a light detecting element 1 according to a first embodiment. The light detecting element 1 according to the present embodiment includes a sensor chip 110 (first chip) and a logic chip 120 (second chip) stacked on the lower side of the sensor chip 110. The sensor chip 110 and the logic chip 120 are electrically connected together by, for example, so-called Cu-Cu bonding, in which copper pads formed on the respective chips are bonded to each other. Note that in addition to the Cu-Cu bonding, the chips may also be connected together by vias or bumps.

[0107] The sensor chip 110 includes an upper pixel region 111. A photoelectric conversion circuit 211 is arranged in the upper pixel region 111. Meanwhile, the logic chip 120 includes a lower pixel region 121. A comparator 212, a selection circuit 213, and a storage circuit 214 are arranged in the lower pixel region 121. Figure 4 Not shown in the figure, the pixel driving circuit 23 , the DAC 24 , the vertical driving circuit 25 , the repeater 26 , the output unit 27 , and the timing generating circuit 28 may be arranged around the lower pixel region 121 .

[0108] Note that the stacking structure of the sensor chip 110 and the logic chip 120 is not limited to Figure 3 The two-layer structure shown in the figure can be, for example, a three-layer structure. For example, the comparator 212 is arranged on another chip stacked between the sensor chip 110 and the logic chip 120. In this case, the circuit area can be reduced, and smaller pixels can be supported or the number of shared comparators can be reduced.

[0109] Figure 5 1 is a diagram showing an example of a layout of pixels according to the first embodiment. Figure 5As shown, in the sensor chip 110, eight photoelectric conversion circuits 211 are arranged along the row direction X. In the logic chip 120 stacked with the sensor chip 110, the repeater 26 is arranged at a position facing the center of the eight photoelectric conversion circuits 211. Regarding the repeater 26, one repeater 26 is shared by a pixel group including four groups of pixels 21a and 21b.

[0110] The comparator 212, the switching circuit 215, and the storage circuit 214 are arranged symmetrically with the repeater 26 inserted in the row direction X. On each of the two sides of the repeater 26 in the row direction X, four storage circuits 214 are arranged in the column direction Y. On one side in the row direction X of the storage circuit group including the four storage circuits 214, two switching circuits 215 are arranged in the column direction Y. On one side in the row direction X of the switching circuit group including the two switching circuits 215, four comparators 212 are arranged in the column direction Y. The four comparators 212 are individually connected to the photoelectric conversion circuit 211 through wirings 300a to 300d.

[0111] Figure 6 is a diagram showing another layout example of pixels according to the first embodiment. Figure 6 The layout shown is similar to Figure 5 The illustrated layout differs in the layout of the wiring 300 .

[0112] exist Figure 5 , the wiring 300b is formed so as to connect the photoelectric conversion circuit 211 arranged second from the left and the photoelectric conversion circuit 211 arranged second from the right to the comparator 212 arranged second from the top. In addition, the wiring 300c is formed so as to connect the photoelectric conversion circuit 211 arranged third from the left and the photoelectric conversion circuit 211 arranged third from the right to the comparator 212 arranged third from the top.

[0113] On the other hand, Figure 6 , the wiring 300b is formed to connect the photoelectric conversion circuit 211 arranged second from the left and the photoelectric conversion circuit 211 arranged second from the right to the comparator 212 arranged third from the top. In addition, the wiring 300c is formed to connect the photoelectric conversion circuit 211 arranged third from the left and the photoelectric conversion circuit 211 arranged third from the right to the comparator 212 arranged second from the top. As described above, the pixels sharing the memory circuit 214 can be easily changed by rearranging the wirings 300a to 300d.

[0114] Here, a description will be given of Comparative Examples 1 and 2 compared with the pixel according to the present embodiment described above.

[0115] Figure 7 is a block diagram showing a circuit configuration of a pixel according to Comparative Example 1. Figure 7 , circuit elements similar to those of the pixel 21 a and the pixel 21 b according to the first embodiment are denoted by the same reference symbols, and a detailed description thereof will be omitted.

[0116] Figure 7 The pixel 210a and the pixel 210b described in the figure do not include the selection circuit 213. At the same time, the storage circuit 214 of each pixel includes a third latch circuit 214c in addition to the first latch circuit 214a and the second latch circuit 214b. In the pixel 210a and the pixel 210b, three latch circuits are required for one photoelectric conversion circuit 211 in order to perform the image plane phase difference AF processing. As described above, in the pixel according to the present comparative example, the number of latch circuits is greater than the number of pixels according to the present embodiment. Therefore, it is very likely that a space for forming the storage circuit 214 cannot be ensured in the lower pixel area 121 of the logic chip 120.

[0117] Figure 8 is a block diagram showing a circuit configuration of a pixel according to Comparative Example 2. Figure 8 , circuit elements similar to those of the pixel according to the first embodiment are denoted by the same reference symbols, and a detailed description thereof will be omitted.

[0118] Figure 8 The pixel 220 shown in FIG. 1 is provided with two photoelectric conversion circuits 211. In addition, the pixel 220 does not include a selection circuit 213. In addition, the storage circuit 214 includes a third latch circuit 214c in addition to the first latch circuit 214a and the second latch circuit 214b. However, in the pixel 220, the comparator 212 and the storage circuit 214 are shared by the two photoelectric conversion circuits 211. Therefore, compared with Comparative Example 1, the number of comparators 212 and storage circuits 214 per pixel is reduced. Therefore, sufficient space for forming the storage circuit 214 can be ensured in the lower pixel area 121 of the logic chip 120.

[0119] However, in this comparative example, since the comparator 212 and the storage circuit 214 are shared, the number of digital conversions of the analog pixel signal SIG increases compared to Comparative Example 1. As a result, the signal processing speed decreases, focal plane distortion occurs, and the global shutter cannot be used. In addition, even when the image plane phase difference AF processing is unnecessary, operation under the premise of sharing the comparator 212 and the storage circuit 214 is required.

[0120] On the other hand, the switching circuit 215 is provided in the pixel 21a and the pixel 21b according to the present embodiment. The switching circuit 215 can select the storage circuit 214 of both the pixel 21a and the pixel 21b, instead of selecting the storage circuit 214 of only one of the pixel 21a and the pixel 21b as the output destination of the output signal VCO of the comparator 212. Thus, even if the storage circuit 214 of each pixel does not include three latch circuits, the image plane phase difference AF processing can be performed. In the following, referring to Fig. 9 , a description will be given of an operation mode for performing image plane phase difference AF processing.

[0121] Fig. 9 1 is a timing chart for explaining the operation mode of the image plane phase difference AF of the pixel 21 according to the first embodiment.

[0122] First, in the reset operation period R of the first pixel, a reset transistor (not shown) provided in the photoelectric conversion circuit 211 of the pixel 21a is turned on based on a reset signal from the pixel driving circuit 23. As a result, the potential of the floating diffusion layer FD of the photoelectric conversion circuit 211 is reset.

[0123] Next, in the reset period (P phase), the first output signal VCO1 when the potential of the above-mentioned floating diffusion layer FD is in the reset state is output from the comparator 212 of the pixel 21a. Subsequently, the selection circuit 213 of the pixel 21a selects the first latch circuit 214a as the output destination of the first output signal VCO1 based on the selection signal from the pixel driving circuit 23. As a result, the first data Coln1 of the first output signal VCO1 is written to the first latch circuit 214a (P phase W). Thereafter, when the above-mentioned reset transistor is turned off based on the above-mentioned reset signal, the reset state of the floating diffusion layer FD is released.

[0124] Next, in the charge transfer period (FD transfer), only the first photodiode PD1 of the pixel 21a performs photoelectric conversion on the incident light. Subsequently, based on the transfer signal from the pixel driving circuit 23, the first transfer transistor M1 of the pixel 21a is turned on. Therefore, the charge accumulated in the first photodiode PD1 of the pixel 21a is transferred to the floating diffusion layer FD. Thereafter, an analog pixel signal SIG according to the amount of charge is generated in the floating diffusion layer FD.

[0125] Next, in the first data acquisition cycle (D1 phase), the comparator 212 of the pixel 21a compares the analog pixel signal SIG based on the light reception of the first photodiode PD1 with the ramp signal RAMP, and outputs the second output signal VCO2. Subsequently, the selection circuit 213 of each pixel selects the second latch circuit 214b as the output destination of the second output signal VCO2 based on the selection signal from the pixel driving circuit 23. As a result, the second data Coln2 of the second output signal VCO2 is written into the second latch circuit 214b (D1 phase W).

[0126] Next, in the charge transfer period (FD transfer), both the first photodiode PD1 and the second photodiode PD2 of the pixel 21a photoelectrically convert the incident light. Subsequently, based on the transfer signal from the pixel driving circuit 23, the first transfer transistor M1 and the second transfer transistor M2 of the pixel 21a are turned on at the same time. As a result, the charges accumulated in the first photodiode PD1 and the second photodiode PD2 are transferred to the floating diffusion layer FD. Thereafter, an analog pixel signal SIG according to the amount of charge is generated in the floating diffusion layer FD.

[0127] Next, in the second data acquisition cycle (D2 phase), the comparator 212 of the pixel 21a compares the analog pixel signal SIG based on the light reception of the first photodiode PD1 and the second photodiode PD2 with the ramp signal RAMP, and outputs the third output signal VCO3. Subsequently, the selection circuit 213 of each pixel selects the first latch circuit 214a of the pixel 21b as the output destination of the third output signal VCO3 based on the selection signal from the pixel driving circuit 23. As a result, the third data Coln3 of the third output signal VCO3 is written to the first latch circuit 214a of the pixel 21b (D2 phase W).

[0128] Next, in the logic transfer cycle, the first data Coln1 stored in the first latch circuit 214a is read by the repeater 26 (P phase R) and written to the repeater 26 (P phase W). The first data Coln1 written to the repeater 26 is read out to the output unit 27 (P phase R).

[0129] Subsequently, the second data Coln2 stored in the second latch circuit 214b is read by the repeater 26 (D1 phase R) and written to the repeater 26 (D1 phase W). The second data Coln2 written to the repeater 26 is read out to the output unit 27 (D1 phase R).

[0130] Subsequently, the third data Coln3 stored in the first latch circuit 214a of the pixel 21b is read by the repeater 26 (D2 phase R) and written to the repeater 26 (D2 phase W). The third data Coln3 written to the repeater 26 is read out to the output unit 27 (D2 phase R). As a result, the image plane phase difference AF processing for the pixel 21a is completed. Thereafter, in the pixel 21b of the second pixel, the same operation as the above-mentioned pixel 21a is performed. In this case, the third data Coln3 of the third output signal VCO3 outputted from the comparator 212 of the pixel 21b is written to the first latch circuit 214a of the pixel 21a through the selection circuit 213 of the pixel 21a and the pixel 21b.

[0131] Next, refer to Fig.10 , a description will be given of an operation mode in which image plane phase difference AF processing is not performed.

[0132] Fig.10 1 is a timing chart for explaining an operation mode in which the image plane phase difference AF processing by the pixel 21 according to the first embodiment is not performed.

[0133] First, in the reset operation period R, a reset transistor (not shown) provided in each of the photoelectric conversion circuits 211 of all pixels including the pixel 21a and the pixel 21b is turned on based on a reset signal from the pixel driving circuit 23. Thereby, the potential of the floating diffusion layer FD is reset.

[0134] Next, in the reset period (P phase), the first output signal VCO1 when the potential of the floating diffusion layer FD is in the reset state is output from the comparators 212 of all the pixels. Subsequently, the selection circuits 213 of all the pixels each select the first latch circuit 214a as the output destination of the first output signal VCO1 based on the selection signal from the pixel driving circuit 23. As a result, the first data Coln1 of the first output signal VCO1 of all the pixels is each written into the first latch circuit 214a (P phase W). Thereafter, when the reset transistor is turned off based on the reset signal, the reset state of the floating diffusion layer FD is released.

[0135] Next, in the charge transfer period (FD transfer), both the first photodiode PD1 and the second photodiode PD2 of the pixel 21a photoelectrically convert the incident light. Subsequently, based on the transfer signal from the pixel driving circuit 23, the first transfer transistor M1 and the second transfer transistor M2 of the pixel 21a are turned on. As a result, the charges accumulated in the first photodiode PD1 and the second photodiode PD2 are transferred to the floating diffusion layer FD. Thereafter, an analog pixel signal SIG according to the charge amount is generated in the floating diffusion layer FD.

[0136] Next, in the data acquisition period (D phase), the comparators 212 of all pixels compare the analog pixel signal SIG based on the light reception of the first photodiode PD1 and the second photodiode PD2 with the ramp signal RAMP, and output the third output signal VCO3. Subsequently, the selection circuits 213 of all pixels each select the second latch circuit 214b as the output destination of the third output signal VCO3 based on the selection signal from the pixel driving circuit 23. As a result, the third data Coln3 of the third output signal VCO3 is written to the second latch circuit 214b (D phase W).

[0137] Next, in the logic transfer cycle, the first data Coln1 stored in the first latch circuit 214a is read by the repeater 26 (P phase R) and written to the repeater 26 (P phase W). The first data Coln1 written to the repeater 26 is read out to the output unit 27 (P phase R).

[0138] Subsequently, the third data Coln3 stored in the second latch circuit 214b is read by the repeater 26 (D phase R) and written to the repeater 26 (D phase W). The third data Coln3 written to the repeater 26 is read out to the output unit 27 (D phase R).

[0139] According to the light detection element 1 according to the present embodiment configured as described above, since the latch circuits of the adjacent pixels are used in the operation mode of performing the image plane phase difference AF processing, it is not necessary to provide three latch circuits for each pixel. Therefore, since a sufficient space for forming the memory circuit 214 can be ensured in the lower pixel region 121 of the logic chip 120, an increase in the size of the memory circuit 214 can be suppressed.

[0140] In addition, in an operation mode in which the image plane phase difference AF processing is not performed, the comparator 212 and the storage circuit 214 are not shared between the pixel 21a and the pixel 21b, so that a decrease in the signal processing speed can be suppressed. It should be noted that when the image plane phase difference AF processing is performed, the repeater 26 thins the pixels from which the output signal VCO is read, so that a decrease in the signal processing speed can be suppressed.

[0141] (Second Embodiment)

[0142] Fig.11 is a block diagram showing an example of a circuit configuration of a pixel according to the second embodiment. Fig.11 In the present invention, the same circuit elements as those of the pixel in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

[0143] This embodiment differs from the first embodiment in the configuration of the photoelectric conversion circuit 211. Specifically, the photoelectric conversion circuit 211 is provided with a first photodiode PD1 and a first transfer transistor M1, but is not provided with a second photodiode PD2 or a second transfer transistor M2. Note that the configurations of the comparator 212, the selection circuit 213, and the storage circuit 214 are the same as those of the first embodiment.

[0144] The pixel 21 a and the pixel 21 b according to the present embodiment can perform a multi-channel AD process of continuously performing the AD conversion process of the analog pixel signal once transmitted to the floating diffusion layer FD a plurality of times in the reset period and the data acquisition period according to the illuminance of the light detection target area.

[0145] In the following, reference Fig.12 , a description will be given of an operation mode of performing multiplexed AD processing by pixels according to the present embodiment. Fig.12 : is a timing chart for explaining the multi-channel AD processing of the pixel according to the second embodiment.

[0146] First, in the reset operation period R, a reset transistor (not shown) provided in the photoelectric conversion circuit 211 of the pixel 21a is turned on based on a reset signal from the pixel driving circuit 23. Thereby, the potential of the floating diffusion layer FD is reset.

[0147] Next, in the first reset period (P1 phase), the first output signal VCO1a when the potential of the floating diffusion layer FD is in the reset state is output from the comparator 212 of the pixel 21a. Based on the control of the pixel driving circuit 23, the first latch circuit 214a of the pixel 21a is selected as the output destination of the first output signal VCO1a by the operation of the selection circuit 213 of the pixel 21a and the pixel 21b. As a result, the first data Coln1a of the first output signal VCO1a is written to the first latch circuit 214a of the pixel 21a (P1 phase W).

[0148] Next, in the second reset period (P2 phase), after the first output signal VCO1a, the first output signal VCO1b when the potential of the floating diffusion layer FD is in the reset state is output from the comparator 212 of the pixel 21a. Based on the control of the pixel driving circuit 23, the first latch circuit 214a of the pixel 21b adjacent to the pixel 21a is selected as the output destination of the first output signal VCO1b by the operation of the selection circuit 213 of the pixel 21a and the pixel 21b. As a result, the first data Coln1b of the first output signal VCO1b is written to the first latch circuit 214a of the pixel 21b (P2 phase W). Thereafter, when the reset transistor of the pixel 21a is turned off based on the above reset signal, the reset state of the floating diffusion layer FD is released.

[0149] Next, in the charge transfer period (FD transfer), the first photodiode PD1 of the pixel 21a performs photoelectric conversion on the incident light. Subsequently, based on the transfer signal from the pixel driving circuit 23, the first transfer transistor M1 of the pixel 21a is turned on. When the first transfer transistor M1 is turned on, the charge accumulated in the first photodiode PD1 is transferred to the floating diffusion layer FD, and in the floating diffusion layer FD, an analog pixel signal SIG is generated according to the amount of charge accumulated in the first photodiode PD1.

[0150] Next, in the first data acquisition cycle (D1 phase), the comparator 212 compares the analog pixel signal SIG based on the first light received by the first photodiode PD1 of the photoelectric conversion circuit 211 with the ramp signal RAMP, and outputs the second output signal VCO2a. Based on the control of the pixel driving circuit 23, the second latch circuit 214b of the pixel 21a is selected as the output destination of the second output signal VCO2a by the operation of the selection circuit 213 of the pixel 21a and the pixel 21b. As a result, the second data Coln2a of the second output signal VCO2a is written to the second latch circuit 214b of the pixel 21a (D1 phase W).

[0151] Next, in the second data acquisition cycle (D2 phase), the comparator 212 compares the analog pixel signal SIG based on the second light reception after the first light reception by the first photodiode PD1 of the photoelectric conversion circuit 211 with the ramp signal RAMP, and outputs the second output signal VCO2b. Based on the control of the pixel driving circuit 23, the second latch circuit 214b of the pixel 21b is selected as the output destination of the second output signal VCO2b by the operation of the selection circuit 213 of the pixel 21a and the pixel 21b. As a result, the second data Coln2b of the second output signal VCO2b is written to the second latch circuit 214b of the pixel 21b (D2 phase W).

[0152] Next, in the logic transfer cycle, the first data Coln1a stored in the first latch circuit 214a of the pixel 21a is read by the repeater 26 (P1 phase R) and written to the repeater 26 (P phase W). The first data Coln1a written to the repeater 26 is read out to the output unit 27 (P1 phase R).

[0153] Subsequently, the second data Coln2a stored in the second latch circuit 214b of the pixel 21a is read by the repeater 26 (D1 phase R) and written to the repeater 26 (D1 phase W). The second data Coln2a written to the repeater 26 is read out to the output unit 27 (D1 phase R).

[0154] Subsequently, the first data Coln1b stored in the first latch circuit 214a of the pixel 21b is read by the repeater 26 (P2 phase R) and written to the repeater 26 (P2 phase W). The first data Coln1b written to the repeater 26 is read out to the output unit 27 (P2 phase R).

[0155] Subsequently, the second data Coln2b stored in the second latch circuit 214b of the pixel 21b is read by the repeater 26 (D2 phase R) and written to the repeater 26 (D2 phase W). The second data Coln2b written to the repeater 26 is read out to the output unit 27 (D2 phase R). As a result, the multi-channel AD processing of the pixel 21a is completed. Thereafter, in the pixel 21b, the same operation as the above-mentioned pixel 21a is performed. In this case, the first data Coln1a, the first data Coln1b, the second data Coln2a and the second data Coln2b of the pixel 21b are written into the first latch circuit 214a of the pixel 21b, the first latch circuit 214a of the pixel 21a, the second latch circuit 214b of the pixel 21b and the second latch circuit 214b of the pixel 21a by the selection circuit 213 of the pixel 21a and the pixel 21b, respectively.

[0156] Next, refer to Fig.13 , a description will be given of an operation mode in which multi-channel AD processing is not performed. Fig.13 : is a timing chart for explaining an operation mode in which the multi-channel AD processing of the pixel according to the second embodiment is not performed.

[0157] First, in the reset operation period R, reset transistors (not shown) provided in the photoelectric conversion circuits 211 of the pixels 21a and 21b are turned on based on a reset signal from the pixel driving circuit 23. As a result, the potentials of the floating diffusion layers FD of the pixels are reset simultaneously.

[0158] Next, in the reset period (P phase), the first output signal VCO1 when the potential of the floating diffusion layer FD is in the reset state is simultaneously output from the comparators 212 of the pixel 21a and the pixel 21b. The first data Coln1 of the first output signal VCO1 output from the pixel 21a is written into the first latch circuit 214a of the pixel 21a, and the first data Coln1 of the first output signal VCO1 output from the pixel 21b is written into the first latch circuit 214a of the pixel 21b (P phase W). Thereafter, when the above-mentioned reset transistor is turned off based on the above-mentioned reset signal, the reset state of the floating diffusion layer FD is released.

[0159] Next, in the charge transfer period (FD transfer), the first photodiodes PD1 of the pixels 21a and 21b each photoelectrically convert the incident light. Subsequently, based on the transfer signal from the pixel driving circuit 23, the first transfer transistors M1 of the corresponding pixels are turned on at the same time. Therefore, the charges accumulated in the first photodiodes PD1 are simultaneously transferred to the floating diffusion layers FD of the corresponding pixels. Thereafter, in each floating diffusion layer FD, an analog pixel signal SIG is generated according to the amount of charge accumulated in the first photodiode PD1.

[0160] Next, in the data acquisition period (D phase), the comparator 212 of each pixel compares the analog pixel signal SIG with the ramp signal RAMP based on the light reception by the first photodiode PD1, and outputs the second output signal VCO2. Through the selection circuit 213 of each pixel, the second data Coln2 of the second output signal VCO2 output from the pixel 21a is written into the second latch circuit 214b of the pixel 21a, and the second data Coln2 of the second output signal VCO2 output from the pixel 21b is written into the second latch circuit 214b of the pixel 21b (D phase W).

[0161] Next, in the logic transfer cycle, the first data Coln1 stored in the first latch circuit 214a of the pixel 21a is read by the repeater 26 (P phase R) and written to the repeater 26 (P phase W). The first data Coln1 written to the repeater 26 is read out to the output unit 27 (P1 phase R).

[0162] Subsequently, the second data Coln2 stored in the second latch circuit 214b of the pixel 21a is read by the repeater 26 (D phase R) and written to the repeater 26 (D phase W). The second data Coln2 written to the repeater 26 is read out to the output unit 27 (D phase R). Thereafter, as in the pixel 21a, the first data Coln1 and the second data Coln2 respectively stored in the first latch circuit 214a and the second latch circuit 214b of the pixel 21b are read out to the output unit 27 via the repeater 26. As a result, the operation mode in which the multiplex AD processing is not performed ends.

[0163] Here, Comparative Example 3 to be compared with the second embodiment will be described.

[0164] Fig.14 is a block diagram showing a circuit configuration of a pixel according to Comparative Example 3. Fig.14 , circuit elements similar to those of the pixel according to the present embodiment described above are denoted by the same reference symbols, and a detailed description thereof will be omitted.

[0165] Fig.14The pixel 230 shown is provided with a photoelectric conversion circuit 211a and a photoelectric conversion circuit 211b. Each photoelectric conversion circuit includes a first photodiode PD1 and a first transfer transistor M1. In addition, the pixel 230 does not include a selection circuit 213. In addition, the storage circuit 214 includes a first latch circuit 214a, a second latch circuit 214b, a third latch circuit 214c and a fourth latch circuit 214d for performing multiple AD processing. The comparator 212 and the storage circuit 214 are shared by the photoelectric conversion circuit 211a and the photoelectric conversion circuit 211b. Hereinafter, a description will be given of an operation mode in which the pixel 230 according to this comparative example performs multiple AD processing.

[0166] First, in the reset operation period R, a reset transistor (not shown) provided in the photoelectric conversion circuit 211a is turned on based on a reset signal from the pixel driving circuit 23. Thereby, the potential of the floating diffusion layer FD is reset.

[0167] Next, in the first reset period (P1 phase), the first output signal VCO1a when the potential of the floating diffusion layer FD is in a reset state is output from the comparator 212. The first data Coln1a of the first output signal VCO1a is written to the first latch circuit 214a (P1 phase W).

[0168] Next, in the second reset period (P2 phase), as in the first reset period, the first output signal VCO1b when the potential of the floating diffusion layer FD is in the reset state is output from the comparator 212. The first data Coln1b of the first output signal VCO1b is written into the third latch circuit 214c (P2 phase W). Thereafter, when the reset transistor is turned off based on the reset signal, the reset state of the floating diffusion layer FD is released.

[0169] Next, in the charge transfer period (FD transfer), the first photodiode PD1 of the photoelectric conversion circuit 211a performs photoelectric conversion on the incident light multiple times. Subsequently, each time the first photodiode PD1 performs photoelectric conversion, the first transfer transistor M1 of the photoelectric conversion circuit 211a is turned on based on the transfer signal from the pixel driving circuit 23. Each time the first transfer transistor M1 is turned on, the charge accumulated in the first photodiode PD1 of the photoelectric conversion circuit 211a is transferred to the floating diffusion layer FD and converted into an analog pixel signal SIG according to the amount of charge.

[0170] Next, in the first data acquisition cycle (D1 phase), the comparator 212 compares the first analog pixel signal SIG1 generated based on the first light reception by the first photodiode PD1 of the photoelectric conversion circuit 211a with the ramp signal RAMP, and outputs a second output signal VCO2a. The second data Coln2a of the second output signal VCO2a is written into the second latch circuit 214b (D1 phase W).

[0171] Next, in the second data acquisition cycle (D2 phase), the comparator 212 compares the second analog pixel signal SIG2 generated based on the second light reception by the first photodiode PD1 of the photoelectric conversion circuit 211a with the ramp signal RAMP, and outputs a second output signal VCO2b. The second data Coln2b of the second output signal VCO2b is written into the fourth latch circuit 214d (D2 phase W).

[0172] Next, in the logic transfer cycle, the first data Coln1a stored in the first latch circuit 214a is read by the repeater 26 (P1 phase R) and written to the repeater 26 (P phase W). The first data Coln1a written to the repeater 26 is read out to the output unit 27 (P1 phase R).

[0173] Next, the second data Coln2a stored in the second latch circuit 214b is read by the repeater 26 (D1 phase R) and written to the repeater 26 (D1 phase W). The second data Coln2a written to the repeater 26 is read out to the output unit 27 (D1 phase R).

[0174] Subsequently, the first data Coln1b stored in the third latch circuit 214c is read by the repeater 26 (P2 phase R) and written to the repeater 26 (P2 phase W). The first data Coln1b written to the repeater 26 is read out to the output unit 27 (P2 phase R).

[0175] Next, the second data Coln2b stored in the fourth latch circuit 214d is read by the repeater 26 (D2 phase R), and is written to the repeater 26 (D2 phase W). The second data Coln2b written to the repeater 26 is read out to the output unit 27 (D2 phase R). As a result, the multiplex AD processing of the photoelectric conversion circuit 211a is completed. Thereafter, the same operation as that of the above-mentioned photoelectric conversion circuit 211a is performed in the photoelectric conversion circuit 211b.

[0176] Next, refer to Fig.15 , a description will be given of an operation mode in which multi-channel AD processing is not performed. Fig.15 is a timing chart for explaining an operation mode in which the multi-AD processing of the pixel according to Comparative Example 3 is not performed.

[0177] First, in the reset operation period R, as in the operation mode in which multiplexed AD processing is performed, a reset transistor (not shown) provided in the photoelectric conversion circuit 211a is turned on based on a reset signal from the pixel driving circuit 23. Thereby, the potential of the floating diffusion layer FD is reset.

[0178] Next, in the reset period (P phase), the first output signal VCO1a when the potential of the floating diffusion layer FD is in the reset state is output from the comparator 212. The first data Coln1a of the first output signal VCO1a is written to the first latch circuit 214a (P phase W). Thereafter, when the above reset transistor is turned off based on the above reset signal, the reset state of the floating diffusion layer FD is released.

[0179] Next, in the charge transfer period (FD transfer), the first photodiode PD1 of the photoelectric conversion circuit 211a performs photoelectric conversion on the incident light. Subsequently, based on the transmission signal from the pixel driving circuit 23, the first transfer transistor M1 of the photoelectric conversion circuit 211a is turned on. Therefore, the charge accumulated in the first photodiode PD1 is transferred to the floating diffusion layer FD. Thereafter, in the floating diffusion layer FD, an analog pixel signal SIG is generated according to the amount of charge accumulated in the first photodiode PD1.

[0180] Next, in the data acquisition period (D phase), the comparator 212 compares the analog pixel signal SIG based on the light reception of the first photodiode PD1 with the ramp signal RAMP and outputs the second output signal VCO2a. The second data Coln2a of the second output signal VCO2a is written into the second latch circuit 214b (D phase W).

[0181] Next, in the logic transfer cycle, the first data Coln1a stored in the first latch circuit 214a is read by the repeater 26 (P phase R) and written to the repeater 26 (P phase W). The first data Coln1a written to the repeater 26 is read out to the output unit 27 (P1 phase R).

[0182] Next, the second data Coln2a stored in the second latch circuit 214b is read by the repeater 26 (D phase R) and written to the repeater 26 (D phase W). The second data Coln2a written to the repeater 26 is read out to the output unit 27 (D phase R). Thereafter, the same operation as that of the above-described photoelectric conversion circuit 211a is performed in the photoelectric conversion circuit 211b.

[0183] In the pixel 230 according to Comparative Example 3 configured as described above, four latch circuits are provided for the two photoelectric conversion circuits 211a and 211b. Therefore, the signal processing speed in the case of performing multi-channel AD processing is equivalent to that of the present embodiment.

[0184] However, in the pixel 230 according to Comparative Example 3, the comparator 212 is shared by the two photoelectric conversion circuits 211a and 211b. Therefore, even in an operation mode that does not require multi-channel AD processing, such as in an operation mode that performs multi-channel AD processing, it is necessary to perform AD conversion processing on the analog pixel signals SIG of the photoelectric conversion circuit 211a and the photoelectric conversion circuit 211b at different timings. Therefore, signal processing requires time.

[0185] On the other hand, in the above-mentioned embodiment, in the operation mode of performing multiplexed AD processing, by sharing the latch circuits of the pixels 21a and 21b adjacent to each other, it is possible to ensure a signal processing speed equal to that of the comparative example 3. In addition, in the present embodiment, the comparator 212 and the storage circuit 214 are not shared between the pixel 21a and the pixel 21b. Therefore, in the operation mode in which multiplexed AD processing is not performed, the comparators 212 of the corresponding pixels can independently perform AD conversion processing on the analog pixel signals SIG generated in the corresponding photoelectric conversion circuits at the same time. As a result, the speed of signal processing can be accelerated compared to the comparative example 3.

[0186] Therefore, according to the present embodiment, it is possible to suppress a decrease in signal processing speed while realizing multi-channel AD processing.

[0187] (Third Embodiment)

[0188] In the present embodiment, since the circuit configuration of the pixel 21 a and the pixel 21 b is the same as that of the above-described second embodiment, the description thereof will be omitted.

[0189] The pixel 21 a and the pixel 21 b according to the present embodiment perform a single-frame high dynamic range (HDR) process of continuously performing AD conversion processing a plurality of times in a reset period and a data acquisition period according to the illuminance of a light detection target area.

[0190] According to a timing chart similar to that of the multi-channel AD processing described in the second embodiment (see Fig.12) performs single-frame HDR processing. However, in multi-channel AD processing, the light receiving time of the first photodiode PD1 in the first data acquisition cycle (D1 phase) is the same as the light receiving time of the first photodiode PD1 in the second data acquisition cycle (D2 phase). That is, the exposure time of the first photodiode PD1 is the same between the first data acquisition period and the second data acquisition period. On the other hand, in single-frame HDR processing, the exposure time of the first photodiode PD1 in the first data acquisition period is different from the exposure time of the first photodiode PD1 in the second data acquisition period. For example, the exposure time in the second data acquisition cycle is longer than the exposure time in the first data acquisition cycle. In the present embodiment, the exposure time of the first photodiode PD1 is changed, thereby expanding the dynamic range of the analog pixel signal SIG.

[0191] Moreover, in the present embodiment, in the operation mode of performing single-frame HDR processing, as in the multi-channel AD processing described in the second embodiment, the latch circuits of the pixels 21a and 21b adjacent to each other are shared, so that the signal processing speed can be ensured. In addition, also in the present embodiment, as in the second embodiment, the comparator 212 and the storage circuit 214 are not shared between the pixel 21a and the pixel 21b. Therefore, in the operation mode of not performing single-frame HDR processing, the comparators 212 of the corresponding pixels can perform AD conversion processing on the analog pixel signal SIG generated in the corresponding photoelectric conversion circuit independently of each other at the same time. Therefore, a reduction in the signal processing speed can be avoided.

[0192] Therefore, according to the present embodiment, while achieving single-frame HDR processing, the reduction in signal processing speed can be suppressed. It should be noted that in the present embodiment, the comparator 12 can perform multiple AD conversions on the analog pixel signal SIG under the condition that the slope of the ramp signal changes, without being limited to the exposure time of the first photodiode PD1.

[0193] (Fourth Embodiment)

[0194] In the present embodiment, since the circuit configuration of the pixel 21 a and the pixel 21 b is the same as that of the second embodiment described above, the description thereof will be omitted.

[0195] According to the pixel 21a and the pixel 21b of the present embodiment, a bit extension process is performed to improve the image quality. Specifically, when the analog pixel signal SIG is converted into a digital pixel signal in the data acquisition cycle, when the bit depth of the digital pixel signal is not enough to be stored by one latch circuit, an adjacent latch circuit is also used. For example, when the bit depth of the analog pixel signal SIG is 11 bits and the first latch circuit 214a can store up to 10 bits, the analog pixel signal SIG is not only stored in the first latch circuit 214a, but also stored in the second latch circuit 214b adjacent to the first latch circuit 214a.

[0196] See below for more information. Fig.16 Describes the bit extension process. Fig.16 1 is a timing chart for explaining the bit extension process performed by the pixel according to the fourth embodiment.

[0197] First, in the reset operation period R, as in the multiplex AD process described in the second embodiment, the reset transistor (not shown) provided in the photoelectric conversion circuit 211 of the pixel 21a is turned on based on the reset signal from the pixel driving circuit 23. Thereby, the potential of the floating diffusion layer FD is reset.

[0198] Next, in the reset period (P phase), the first output signal VCO1 when the potential of the floating diffusion layer FD is in the reset state is output from the comparator 212 of the pixel 21a. Based on the control of the pixel driving circuit 23, the first latch circuit 214a and the second latch circuit 214b of the pixel 21a are selected as the output destination of the first output signal VCO1 through the operation of the selection circuit 213 of the pixel 21a and the pixel 21b. As a result, a part of the first data Coln1 of the first output signal VCO1 is written to the first latch circuit 214a of the pixel 21a, and the remaining part of the first data Coln1 that cannot be stored in the first latch circuit 214a is written to the second latch circuit 214b of the pixel 21a (P1 phase W).

[0199] Next, in the charge transfer period (FD transfer), the first photodiode PD1 of the pixel 21a performs photoelectric conversion on the incident light. Subsequently, based on the transfer signal from the pixel driving circuit 23, the first transfer transistor M1 of the pixel 21a is turned on. Therefore, the charge accumulated in the first photodiode PD1 is transferred to the floating diffusion layer FD. Therefore, in the floating diffusion layer FD, the analog pixel signal SIG is generated according to the amount of charge accumulated in the first photodiode PD1.

[0200] Next, in the data acquisition period (D phase), the comparator 212 compares the analog pixel signal SIG based on the light received by the first photodiode PD1 of the photoelectric conversion circuit 211 with the ramp signal RAMP and outputs the second output signal VCO2 .

[0201] Based on the control of the pixel driving circuit 23, the first latch circuit 214a and the second latch circuit 214b of the pixel 21b are selected as the output destination of the second output signal VCO2 through the operation of the selection circuit 213 of the pixel 21a and the pixel 21b. As a result, a part of the second data Coln2 of the second output signal VCO2 is written to the first latch circuit 214a of the pixel 21b, and the remaining part of the second data Coln2 that cannot be stored in the first latch circuit 214a is written to the second latch circuit 214b of the pixel 21b (D phase W).

[0202] Next, in the logic transfer cycle, the first data Coln1 stored in the first latch circuit 214a and the second latch circuit 214b of the pixel 21a is read by the repeater 26 (P phase R) and written to the repeater 26 (P phase W). The first data Coln1a written to the repeater 26 is read out to the output unit 27 (P phase R).

[0203] Subsequently, the second data Coln2 stored in the first latch circuit 214a and the second latch circuit 214b of the pixel 21b is read by the repeater 26 (D phase R) and written to the repeater 26 (D phase W). The second data Coln2 written to the repeater 26 is read out to the output unit 27 (D phase R).

[0204] In the operation mode in which the bit extension process is not performed, the pixel 21a and the pixel 21b are configured according to the method described in the second embodiment. Fig.13 The timing diagram shown in FIG. 1 operates, and therefore, a detailed description thereof will be omitted.

[0205] According to the present embodiment described above, the storage circuit 214 is shared between the pixel 21a and the pixel 21b through the selection circuit 213. Therefore, even if the bit depth of the second output signal generated in the data acquisition period increases, the second output signal can be stored in the storage circuit 214. As a result, bit extension processing can be realized.

[0206] Furthermore, in an operation mode in which the bit extension process is not performed, the comparators 212 of the respective pixels perform AD conversion processes independently of each other, and therefore, a decrease in the signal processing speed can be avoided. Therefore, the signal processing speed can be ensured regardless of the necessity of the bit extension process.

[0207] (Fifth Embodiment)

[0208] Fig.17 is a block diagram showing an example of a circuit configuration of a pixel according to a fifth embodiment. Fig.17 In the present invention, the same circuit elements as those of the pixel in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

[0209] The present embodiment is different from the first embodiment in the configuration of the photoelectric conversion circuit 211. The photoelectric conversion circuit 211 of the present embodiment includes an amplifier transistor M4 and a current source transistor M5 in addition to the first photodiode PD1, the second photodiode PD2, the first transfer transistor M1, the second transfer transistor M2, and the reset transistor M3. The reset transistor M3, the amplifier transistor M4, and the current source transistor M5 each include, for example, an N-channel MOS transistor.

[0210] The amplifier transistor M4 and the current source transistor M5 connected in series are used as a source follower circuit for amplifying the analog pixel signal SIG generated in the floating diffusion layer FD. The gate of the amplifier transistor M4 is connected to the floating diffusion layer FD and the source of the reset transistor M3. The drain of the amplifier transistor M4 is connected to a power supply line having a power supply voltage potential, similar to the drain of the reset transistor M3. The source of the amplifier transistor M4 is connected to the drain of the current source transistor M5. The source of the current source transistor M5 is grounded.

[0211] The gate voltage of the current source transistor M5 is controlled by the pixel driving circuit 23. The current flowing between the drain and source of the amplifier transistor M4 can be adjusted according to the gate voltage.

[0212] According to the timing diagram described in the first embodiment, the pixel 21a and the pixel 21b according to the present embodiment configured as described above are also driven in the operation mode in which the image plane phase difference AF processing is performed and the operation mode in which the image plane phase difference AF processing is not performed. However, in the present embodiment, in the data acquisition period, the comparator 212 outputs the comparison result between the analog pixel signal SIG amplified by the amplifier transistor M4 and the ramp signal RAMP as the output signal VCO.

[0213] According to the present embodiment described above, when the operation mode of performing the image plane phase difference AF processing is performed, the latch circuits of adjacent pixels are used as in the first embodiment, so that it is not necessary to provide three latch circuits for each pixel. As a result, the increase in the size of the storage circuit 214 can be suppressed.

[0214] Furthermore, also in the operation mode in which the image plane phase difference AF processing is not performed, as in the first embodiment, the comparator 212 and the storage circuit 214 are not shared between pixels, so that a decrease in the signal processing speed can be suppressed.

[0215] Note that the amplifier transistor M4 and the current source transistor M5 described in this embodiment can also be applied to the above-mentioned second to fourth embodiments. That is, the amplifier transistor M4 and the current source transistor M5 can be provided in the photoelectric conversion circuit 211 described in each of the second to fourth embodiments.

[0216] (Sixth Embodiment)

[0217] Fig.18 is a block diagram showing an example of a circuit configuration of a pixel according to a sixth embodiment. Fig.18 In the present invention, the same circuit elements as those of the pixel in the fifth embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

[0218] The present embodiment differs from the fifth embodiment in the configuration of the photoelectric conversion circuit 211. In addition to the circuit elements described in the fifth embodiment, the photoelectric conversion circuit 211 of the present embodiment newly includes a conversion efficiency switching transistor M6 and a capacitance element C. The conversion efficiency switching transistor M6 and the capacitance element C constitute a conversion efficiency switching circuit that switches the photoelectric conversion efficiency of the first photodiode PD1 and the second photodiode PD2.

[0219] The conversion efficiency switch transistor M6 includes, for example, an N-channel MOS transistor. The drain of the conversion efficiency switch transistor M6 is connected to the source of the reset transistor M3. The source of the conversion efficiency switch transistor M6 is connected to the gate of the floating diffusion layer FD and the amplifier transistor M4. The switching signal is input to the gate of the conversion efficiency switch transistor M6 from the pixel drive circuit 23. At the same time, the capacitive element C is connected between the drain of the conversion efficiency switch transistor M6 and GND.

[0220] In the pixel 21a and the pixel 21b according to the present embodiment configured as described above, when the conversion efficiency switch transistor M6 is turned on, based on the above-mentioned switching signal during the reset operation period R, current flows through the reset transistor M3 and the conversion efficiency switch transistor M6, so that the conversion efficiency of the first photodiode PD1 and the second photodiode PD2 is reduced. On the other hand, when the conversion efficiency switch transistor M6 is turned off based on the above-mentioned switching signal, current flows through the reset transistor M3 and the capacitor element C, so that the conversion efficiency of the first photodiode PD1 and the second photodiode PD2 is increased.

[0221] In addition, also in this embodiment, according to the timing chart described in the first embodiment, driving is performed in the operation mode in which the image plane phase difference AF processing is performed and the operation mode in which the image plane phase difference AF processing is not performed. At this time, in the data acquisition period, as in the fifth embodiment, the comparator 212 outputs the comparison result between the analog pixel signal SIG amplified by the amplifier transistor M4 and the ramp signal RAMP as the output signal VCO.

[0222] According to the present embodiment described above, when the operation mode of performing the image plane phase difference AF processing is performed, the latch circuits of adjacent pixels are used as in the first embodiment, so that it is not necessary to provide three latch circuits for each pixel. As a result, the increase in the size of the storage circuit 214 can be suppressed.

[0223] Furthermore, also in the operation mode in which the image plane phase difference AF processing is not performed, as in the first embodiment, the comparator 212 and the storage circuit 214 are not shared between pixels, so that a decrease in the signal processing speed can be suppressed.

[0224] Note that the conversion efficiency switching transistor M6 and the capacitance element C described in this embodiment can also be applied to the second to fourth embodiments described above. That is, the conversion efficiency switching transistor M6 and the capacitance element C can be provided in the photoelectric conversion circuit 211 described in each of the second to fourth embodiments.

[0225] (Seventh Embodiment)

[0226] Fig.19 is a block diagram showing an example of a circuit configuration of a pixel according to the seventh embodiment. Fig.19 In the embodiment, the same circuit elements as those of the pixel in the sixth embodiment are denoted by the same reference numerals, and their detailed description is omitted. Fig.19 In FIG. 1 , the capacitive element C is not shown.

[0227] In this embodiment, the conversion efficiency switching circuit of the pixel 21a and the conversion efficiency switching circuit of the pixel 21b are connected to each other. That is, the connection point of the reset transistor M3 and the conversion efficiency switch transistor M6 is connected between the pixel 21a and the pixel 21b.

[0228] In the pixel 21 a and the pixel 21 b of the present embodiment configured as described above, the conversion efficiency of the first photodiode PD1 and the second photodiode PD2 can be switched between high and low, similarly to the sixth embodiment.

[0229] In addition, also in this embodiment, according to the timing chart described in the first embodiment, driving is performed in the operation mode in which the image plane phase difference AF processing is performed and the operation mode in which the image plane phase difference AF processing is not performed. At this time, in the data acquisition period, as in the sixth embodiment, the comparator 212 outputs the comparison result between the analog pixel signal SIG amplified by the amplifier transistor M4 and the ramp signal RAMP as the output signal VCO. In addition, in this embodiment, the charge transferred to the floating diffusion layer FD of the pixel 21a and the charge transferred to the floating diffusion layer FD of the pixel 21b can be added together.

[0230] According to the present embodiment described above, when the operation mode of performing the image plane phase difference AF processing is performed, the latch circuits of adjacent pixels are used as in the first embodiment, so that it is not necessary to provide three latch circuits for each pixel. As a result, the increase in the size of the storage circuit 214 can be suppressed.

[0231] Furthermore, also in the operation mode in which the image plane phase difference AF processing is not performed, as in the first embodiment, the comparator 212 and the storage circuit 214 are not shared between pixels, so that a decrease in the signal processing speed can be suppressed.

[0232] It should be noted that the configuration in which the conversion efficiency switching circuit of the pixel 21a and the conversion efficiency switching circuit of the pixel 21b are connected to each other can also be applied to the second to fourth embodiments described above. That is, the connection point of the reset transistor M3 and the conversion efficiency switch transistor M6 can be connected together between the pixel 21a and the pixel 21b.

[0233] (Eighth Embodiment)

[0234] Fig. 20 is a block diagram showing an example of a circuit configuration of a pixel according to an eighth embodiment. Fig. 20 In the embodiment, the same circuit elements as those of the pixel in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. This embodiment is different from the first embodiment in the arrangement of the selection circuit 213 and the storage circuit 214.

[0235] In the first embodiment described above, the storage circuit 214 can be shared between the pixel 21a and the pixel 21b adjacent to the pixel 21a by the switching circuit 215. Thus, the selection circuit 213 includes two input terminals IN0 and IN1. The input terminal IN0 of the pixel 21a is connected to the output terminal of the comparator 212 and the input terminal IN1 of the selection circuit 213 of the pixel 21b. The input terminal IN1 of the pixel 21a is connected to the input terminal IN0 of the selection circuit 213 of the pixel 21b.

[0236] On the other hand, Fig. 20In the present embodiment shown, the storage circuit 214 can be shared between four pixels 21a to 21d arranged close to each other by a switching circuit 215 including four selection circuits 213. Therefore, the storage circuit 214 only includes a first latch circuit 214a. That is, in the present embodiment, the first latch circuit 214a provided in each of the four pixels 21a to 21d can be shared. Among the four pixels, the pixel 21c and the pixel 21d are arranged around the pixel 21a and the pixel 21b.

[0237] In this embodiment, the selection circuit 213 of each pixel has four input terminals IN0 to IN3. Each input terminal is connected to any one of the input terminals of other selection circuits 213. In addition, in each selection circuit 213, any one of the four input terminals IN0 to IN3 is connected to the output terminal of the comparator 212.

[0238] Fig.21 is a diagram showing an example of a layout of pixels according to an eighth embodiment. Figure 5 In the illustrated layout, the repeater 26 is arranged at a position facing the center of the eight photoelectric conversion circuits 211. In addition, the comparator 212, the switching circuit 215, and the storage circuit 214 are arranged symmetrically with the repeater 26 inserted in the row direction X.

[0239] In the present embodiment, some operation modes can be set according to the number of pixels sharing the first latch circuit 214a among the pixels 21a to 21d. Here, a description will be given of some operation modes performed in the pixel according to the present embodiment.

[0240] Fig. 22 2 is a timing diagram for explaining an operation mode when the number of pixels sharing the first latch circuit 214a is set to zero. That is, Fig. 22 2 is a timing diagram of a global shutter process in which the comparator 212 and the first latch circuit 214 a of each pixel operate independently.

[0241] First, in the reset operation period R, reset transistors (not shown) respectively provided in the photoelectric conversion circuits 211 of the pixels 21a to 21d are turned on according to a reset signal from the pixel driving circuit 23. Thereby, the potential of the floating diffusion layer FD is reset.

[0242] Next, in the reset period (P phase), the first output signal VCO1 when the potential of the floating diffusion layer FD is in the reset state is simultaneously output from the comparator 212 of each pixel. Based on the control of the pixel driving circuit 23, the first latch circuit 214a of the corresponding pixel is selected as the output destination of the first output signal VCO1 by the operation of the selection circuit 213 of the corresponding pixel. As a result, the plurality of first data Coln1 of the first output signal VCO1 are simultaneously written to the first latch circuit 214a of the corresponding pixel (P phase W).

[0243] Next, in the P-phase logic transmission cycle, the plurality of pieces of first data Coln1 stored in the first latch circuit 214a of each pixel are sequentially read to the repeater 26 (P-phase R) and written to the repeater 26 (P-phase W). The plurality of pieces of first data Coln1 written to the repeater 26 are sequentially read out to the output unit 27 (P-phase R).

[0244] Next, in the charge transfer period (FD transfer), the first photodiode PD1 and the second photodiode PD2 of the photoelectric conversion circuit 211 of each pixel perform photoelectric conversion on the incident light. Subsequently, based on the transfer signal from the pixel driving circuit 23, the first transfer transistor M1 and the second transfer transistor M2 of each photoelectric conversion circuit 211 are turned on at the same time. Therefore, the charges accumulated in the first photodiode PD1 and the second photodiode PD2 are transferred to the floating diffusion layer FD and converted into the analog pixel signal SIG according to the charge amount.

[0245] Next, in the data acquisition period (D phase), the comparator 212 of each pixel compares the analog pixel signal SIG based on the light reception of the first photodiode PD1 and the second photodiode PD2 with the ramp signal RAMP, and outputs the second output signal VCO2. Based on the control of the pixel driving circuit 23, the first latch circuit 214a of the corresponding pixel is selected as the output destination of the second output signal VCO2 by the operation of the selection circuit 213 of the corresponding pixel. As a result, a plurality of second data Coln2 of the second output signal VCO2 are simultaneously written to the first latch circuit 214a of the corresponding pixel (D phase W).

[0246] Next, in the D-phase logic transmission period, the plurality of second data Coln2 stored in the first latch circuit 214a of each pixel is sequentially read to the repeater 26 (D-phase R) and written to the repeater 26 (D-phase W). The plurality of second data Coln2 written to the repeater 26 is sequentially read out to the output unit 27 (D-phase R). As a result, the global shutter process ends.

[0247] Fig.232 is a timing diagram for explaining an operation mode when the number of pixels sharing the first latch circuit 214a is set to 2. That is, Fig.23 21 is a timing diagram of an operation mode in which one first latch circuit 214a is shared between the pixel 21a and the pixel 21b, and one first latch circuit 214a is shared between the pixel 21c and the pixel 21d.

[0248] First, in the reset operation period R, reset transistors (not shown) provided in the photoelectric conversion circuits 211 of the pixels 21a and 21c are turned on based on a reset signal from the pixel driving circuit 23. Thereby, the potential of the floating diffusion layer FD is reset.

[0249] Next, in the reset period (P phase), the first output signal VCO1 when the potential of the floating diffusion layer FD is in the reset state is simultaneously output from the comparators 212 of the pixel 21a and the pixel 21c. The first latch circuit 214a of the pixel 21a is selected by the selection circuit 213 of each pixel as the output destination of the first output signal VCO1 output from the comparator 212 of the pixel 21a. As a result, the first data Coln1 of the first output signal VCO1 is written to the first latch circuit 214a of the pixel 21a (P phase W). At the same time, the first latch circuit 214a of the pixel 21c is selected by the selection circuit 213 of each pixel as the output destination of the first output signal VCO1 output from the comparator 212 of the pixel 21c. As a result, the first data Coln1 of the first output signal VCO1 is written to the first latch circuit 214a of the pixel 21c (P phase W).

[0250] Next, in the charge transfer period (FD transfer), the first photodiode PD1 and the second photodiode PD2 provided in the photoelectric conversion circuit 211 of each of the pixels 21a and the pixels 21c perform photoelectric conversion on the incident light. Subsequently, based on the transmission signal from the pixel driving circuit 23, the first transfer transistor M1 and the second transfer transistor provided in the photoelectric conversion circuit 211 of each of the pixels 21a and the pixels 21c are turned on at the same time. As a result, in each of the pixels 21a and the pixels 21c, the charges accumulated in the first photodiode PD1 and the second photodiode PD2 are transferred to the floating diffusion layer FD, and are converted into the analog pixel signal SIG according to the charge amount.

[0251] Next, in the data acquisition period (D phase), the comparators 212 of the pixels 21a and 21c each compare the analog pixel signal SIG based on the light reception of the first photodiode PD1 and the second photodiode PD2 with the ramp signal RAMP, and output the second output signal VCO2. The first latch circuit 214a of the pixel 21b is selected as the output destination of the second output signal VCO2 output from the comparator 212 of the pixel 21a by the operation of the selection circuit 213 of each pixel based on the control of the pixel driving circuit 23. As a result, the second data Coln2 of the second output signal VCO2 is simultaneously written to the first latch circuit 214a of the pixel 21b (D phase W). At the same time, the first latch circuit 214a of the pixel 21d is selected as the output destination of the second output signal VCO2 output from the comparator 212 of the pixel 21c by the operation of the selection circuit 213 of each pixel based on the control of the pixel driving circuit 23. As a result, the second data Coln2 of the second output signal VCO2 is written to the first latch circuit 214a of the pixel 21d (D phase W).

[0252] Next, in the logic transfer cycle, the first data Coln1 stored in the first latch circuit 214a of the pixel 21a is read by the repeater 26 (P phase R) and written to the repeater 26 (P phase W). The first data Coln1 written to the repeater 26 is read out to the output unit 27 (P phase R).

[0253] Subsequently, the second data Coln2 stored in the first latch circuit 214a of the pixel 21b is read by the repeater 26 (D phase R) and written to the repeater 26 (D phase W). The second data Coln2 written to the repeater 26 is read out to the output unit 27 (D phase R).

[0254] Subsequently, the first data Coln1 stored in the first latch circuit 214a of the pixel 21c is read by the repeater 26 (P phase R) and written to the repeater 26 (P phase W). The first data Coln1 written to the repeater 26 is read out to the output unit 27 (P phase R).

[0255] Subsequently, the second data Coln2 stored in the first latch circuit 214a of the pixel 21d is read by the repeater 26 (D phase R) and written to the repeater 26 (D phase W). The second data Coln2 written to the repeater 26 is read out to the output unit 27 (D phase R). Thereafter, in the pixel 21b and the pixel 21d, the same operation as that in the above-mentioned pixel 21a and the pixel 21c is performed. In this case, the second data Coln2 of the second output signal VCO2 output from the comparator 212 of the pixel 21b is stored in the first latch circuit 214a of the pixel 21a. At the same time, the second data Coln2 of the second output signal VCO2 output from the comparator 212 of the pixel 21d is stored in the first latch circuit 214a of the pixel 21c.

[0256] According to the above-described operation mode, in each pixel, since the first output signal VCO1 in the reset period (P phase) and the second output signal VCO2 in the data acquisition period (D phase) are continuously sampled, image quality can be improved.

[0257] Fig.24 2 is a timing chart for explaining the operation mode of the image plane phase difference AF processing when the number of pixels sharing the first latch circuit 214a is set to four. That is, Fig.24 21 is a timing chart of the image plane phase difference AF processing in which the first latch circuit 214 a is shared among the four pixels 21 a to 21 d .

[0258] First, in the reset operation period R of the first pixel, a reset transistor (not shown) provided in the photoelectric conversion circuit 211 of the pixel 21a is turned on based on a reset signal from the pixel driving circuit 23. As a result, the potential of the floating diffusion layer FD of the photoelectric conversion circuit 211 is reset.

[0259] Next, in the reset period (P phase), the first output signal VCO1 when the potential of the above-mentioned floating diffusion layer FD is in the reset state is output from the comparator 212 of the pixel 21a. Subsequently, the selection circuit 213 of each pixel selects the first latch circuit 214a of the pixel 21a as the output destination of the first output signal VCO1 based on the selection signal from the pixel driving circuit 23. As a result, the first data Coln1 of the first output signal VCO1 is written to the first latch circuit 214a (P phase W). Thereafter, when the above-mentioned reset transistor is turned off based on the above-mentioned reset signal, the reset state of the floating diffusion layer FD is released.

[0260] Next, in the charge transfer period (FD transfer), only the first photodiode PD1 of the pixel 21a performs photoelectric conversion on the incident light. Subsequently, based on the transfer signal from the pixel driving circuit 23, the first transfer transistor M1 of the pixel 21a is turned on. Therefore, the charge accumulated in the first photodiode PD1 of the pixel 21a is transferred to the floating diffusion layer FD. Thereafter, an analog pixel signal SIG according to the amount of charge is generated in the floating diffusion layer FD.

[0261] Next, in the first data acquisition cycle (D1 phase), the comparator 212 of the pixel 21a compares the analog pixel signal SIG based on the light reception of the first photodiode PD1 with the ramp signal RAMP, and outputs the second output signal VCO2. Subsequently, the selection circuit 213 of each pixel selects the first latch circuit 214a of the pixel 21b as the output destination of the second output signal VCO2 based on the selection signal from the pixel driving circuit 23. As a result, the second data Coln2 of the second output signal VCO2 is written to the first latch circuit 214a of the pixel 21b (D1 phase W).

[0262] Next, in the charge transfer period (FD transfer), both the first photodiode PD1 and the second photodiode PD2 of the pixel 21a photoelectrically convert the incident light. Subsequently, based on the transfer signal from the pixel driving circuit 23, the first transfer transistor M1 and the second transfer transistor M2 of the pixel 21a are turned on at the same time. As a result, the charges accumulated in the first photodiode PD1 and the second photodiode PD2 are transferred to the floating diffusion layer FD. Thereafter, an analog pixel signal SIG according to the amount of charge is generated in the floating diffusion layer FD.

[0263] Next, in the second data acquisition cycle (D2 phase), the comparator 212 of the pixel 21a compares the analog pixel signal SIG based on the light reception of the first photodiode PD1 and the second photodiode PD2 with the ramp signal RAMP, and outputs the third output signal VCO3. Subsequently, the selection circuit 213 of each pixel selects the first latch circuit 214a of the pixel 21c as the storage destination of the third output signal VCO3 based on the selection signal from the pixel driving circuit 23. As a result, the third data Coln3 of the third output signal VCO3 is written to the first latch circuit 214a of the pixel 21c (D2 phase W).

[0264] Next, in the logic transfer cycle, the first data Coln1 stored in the first latch circuit 214a of the pixel 21a is read by the repeater 26 (P phase R) and written to the repeater 26 (P phase W). The first data Coln1 written to the repeater 26 is read out to the output unit 27 (P phase R).

[0265] Subsequently, the second data Coln2 stored in the first latch circuit 214a of the pixel 21b is read by the repeater 26 (D1 phase R) and written to the repeater 26 (D1 phase W). The second data Coln2 written to the repeater 26 is read out to the output unit 27 (D1 phase R).

[0266] Subsequently, the third data Coln3 stored in the first latch circuit 214a of the pixel 21c is read by the repeater 26 (D2 phase R) and written to the repeater 26 (D2 phase W). The third data Coln3 written to the repeater 26 is read out to the output unit 27 (D2 phase R). As a result, the operation of reading the data acquired by the pixel 21a is completed. Thereafter, in the pixel 21b, the same operation as the above-mentioned pixel 21a is performed. In this case, the third data Coln3 of the third output signal VCO3 output from the comparator 212 of the pixel 21b is written into the first latch circuit 214a of the pixel 21a through the selection circuit 213 of the pixel 21a and the pixel 21b. As a result, the image plane phase difference AF processing for the pixel 21a is completed.

[0267] Thereafter, in each of the pixel 21b of the second pixel, the pixel 21c of the third pixel, and the pixel 21d of the fourth pixel, the same operation as that of the above-mentioned pixel 21a is performed. In this case, the second data Coln2 and the third data Coln3 of the pixel 21b are stored in the first latch circuit 214a of any one of the pixel 21a, the pixel 21c, and the pixel 21c through the selection circuit 213. In addition, the second data Coln2 and the third data Coln3 of the pixel 21c are stored in the first latch circuit 214a of any one of the pixel 21a, the pixel 21b, and the pixel 21d through the selection circuit 213. In addition, the second data Coln2 and the third data Coln3 of the pixel 21d are stored in the first latch circuit 214a of any one of the pixel 21a, the pixel 21b, and the pixel 21c through the selection circuit 213.

[0268] According to the present embodiment described above, the first latch circuit 214a can be shared by up to four pixels through the selection circuit 213. Therefore, the storage circuit 214 of each pixel only needs to include one latch circuit. As a result, an increase in the size of the storage circuit 214 can be suppressed.

[0269] It is to be noted that the operation mode of the above-described image plane phase difference AF processing can also be applied to the multi-channel AD processing described in the second embodiment and the single-frame HDR processing described in the third embodiment.

[0270] In addition, in the present embodiment, the number of pixels sharing the first latch circuit 214a is 4 at most, but the number is not particularly limited. For example, if the number of input terminals of the selection circuit 213 is eight, the number of pixels sharing the first latch circuit 214a may be eight. In this case, for example, image processing can be realized in which image plane phase difference AF processing and multi-channel AD processing are combined.

[0271] (Ninth Embodiment)

[0272] Fig.25 is a block diagram showing an example of a circuit configuration of a pixel according to a ninth embodiment. Fig.25 In the present invention, the same circuit elements as those of the pixel in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

[0273] The present embodiment is different from the first embodiment in the configuration of the photoelectric conversion circuit 211 and the selection circuit 213. Specifically, in addition to the first photodiode PD1, the second photodiode PD2, the first transfer transistor M1, the second transfer transistor M2, and the reset transistor M3, the photoelectric conversion circuit 211 also includes a source follower circuit. The source follower circuit includes an amplifier transistor M4, a current source transistor M5, and a selection transistor M7. However, the source follower circuit may not be provided.

[0274] Since the amplifier transistor M4 and the current source transistor M5 (see FIG. 1 ) have been described in the fifth embodiment, Fig.15 ), so its description will be omitted here. The selection transistor M7 is arranged between the amplifier transistor M4 and the current source transistor M5. The selection transistor M7 includes, for example, an N-channel MOS transistor. The drain of the selection transistor M7 is connected to the source of the amplifier transistor M4, and the source of the selection transistor M7 is connected to the drain of the current source transistor M5 and the selection circuit 213. A selection signal is input to the gate of the selection transistor M7 from the pixel driving circuit 23. Based on the selection signal, when the selection transistor M7 is turned on, the analog pixel signal SIG amplified by the amplifier transistor M4 is input to the selection circuit 213.

[0275] In addition, the present embodiment is different from the first embodiment in that the selection circuit 213 is arranged on the input terminal side of the comparator 212. The selection circuit 213 includes a first switching element Q1 and a second switching element Q2. The selection circuit 213 of the pixel 21a and the selection circuit 213 of the pixel 21b constitute a switching circuit 215. The first switching element Q1 and the second switching element Q2 include, for example, N-channel MOS transistors. In addition, the first switching element Q1 and the second switching element Q2 are turned on and off based on a control signal input to each gate from the pixel driving circuit 23.

[0276] The first switch element Q1 of the pixel 21a switches whether to connect the photoelectric conversion circuit 211 of the pixel 21a and the first input terminal of the comparator 212 of the pixel 21a to each other based on the above control signal. At the same time, the second switch element Q2 of the pixel 21a switches whether to connect the photoelectric conversion circuit 211 of the pixel 21a and the first input terminal of the comparator 212 of the pixel 21b to each other.

[0277] The first switch element Q1 of the pixel 21b switches whether to connect the photoelectric conversion circuit 211 of the pixel 21b and the first input terminal of the comparator 212 of the pixel 21b to each other based on the above control signal. At the same time, the second switch element Q2 of the pixel 21b switches whether to connect the photoelectric conversion circuit 211 of the pixel 21b and the first input terminal of the comparator 212 of the pixel 21a to each other.

[0278] Fig.26 is a diagram showing an example of a layout of pixels according to the ninth embodiment. Figure 5 In the illustrated layout, the repeater 26 is arranged at a position facing the center of the eight photoelectric conversion circuits 211. In addition, the comparator 212, the switching circuit 215, and the storage circuit 214 are arranged symmetrically with the repeater 26 inserted in the row direction X. However, in the present embodiment, the switching circuit 215 is provided on the input terminal side of the comparator 212. Therefore, each circuit is arranged.

[0279] Hereinafter, a description will be given of an operation mode in which image plane phase difference AF processing is performed in the pixel 21a according to the present embodiment configured as described above. However, the difference from the first embodiment will be mainly described here.

[0280] In the first reset period (P1 phase), the first switch element Q1 of each pixel is turned on and the second switch element Q2 is turned off. Thus, the first data Coln1a of the first output signal VCO1a outputted from the comparator 212 of the pixel 21a is stored in the first latch circuit 214a of the pixel 21a.

[0281] In the second reset period (P2 phase), the first switch element Q1 of each pixel is turned off and the second switch element Q2 is turned on. Thus, the first data Coln1b of the first output signal VCO1b outputted from the comparator 212 of the pixel 21b is stored in the first latch circuit 214a of the pixel 21b.

[0282] Furthermore, in the first data acquisition period (D1 phase), similarly to the first reset period, the first switch element Q1 of each pixel is turned on and the second switch element Q2 is turned off. Therefore, the comparator 212 of the pixel 21a compares the analog pixel signal SIG output from the photoelectric conversion circuit 211 of the pixel 21a with the ramp signal RAMP, and outputs the second output signal VCO2a. The second data Coln2a of the second output signal VCO2a is stored in the second latch circuit 214b of the pixel 21a.

[0283] In addition, during the second data acquisition period (D2 phase), similarly to the second reset period, the first switch element Q1 of each pixel is turned off and the second switch element Q2 is turned on. Therefore, the comparator 212 of the pixel 21b compares the analog pixel signal SIG output from the photoelectric conversion circuit 211 of the pixel 21a with the ramp signal RAMP, and outputs the second output signal VCO2b. The second data Coln2b of the second output signal VCO2b is stored in the second latch circuit 214b of the pixel 21b. It should be noted that in the second data acquisition cycle, because the first transfer transistor M1 and the second transfer transistor M2 are both turned on, the analog pixel signal SIG has a level different from that in the first data acquisition cycle.

[0284] According to the present embodiment described above, even if the selection circuit 213 is arranged on the input terminal side of the comparator 212, when the analog pixel signal SIG is digitally converted, the storage circuit 214 can be shared between the pixel 21a and the pixel 21b. Therefore, it is possible to suppress a decrease in the signal processing speed while avoiding an increase in the size of the storage circuit 214.

[0285] (Tenth Embodiment)

[0286] Fig. 27 1 is a block diagram showing an example of a circuit configuration of a pixel according to a tenth embodiment. Fig. 27 In the present invention, the same circuit elements as those of the pixel in the ninth embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

[0287] This embodiment is different from the ninth embodiment in the configuration of the selection circuit 213. The selection circuit 213 is different from the selection circuit of the ninth embodiment in that it includes only the first switch element Q1. The first switch element Q1 cooperates with the selection transistor M7 to switch the output destination of the analog pixel signal SIG amplified by the amplifier transistor M4 to the comparator 212 of the pixel 21a or the comparator 212 of the pixel 21b. That is, in this embodiment, the first switch element Q1 and the selection transistor M7 are used as the switching circuit 215.

[0288] The drain of the first switching element Q1 of the pixel 21a is connected to the connection point of the source of the amplifier transistor M4 and the drain of the selection transistor M7. The source of the first switching element Q1 of the pixel 21a is connected to the first input terminal of the comparator 212 of the pixel 21b.

[0289] The drain of the first switching element Q1 of the pixel 21b is connected to the first input terminal of the comparator 212 of the pixel 21a. The source of the first switching element Q1 of the pixel 21b is connected to the connection point of the drains of the amplifier transistor M4 and the selection transistor M7 of the pixel 21b.

[0290] Hereinafter, a description will be given of an operation mode in which image plane phase difference AF processing is performed in the pixel 21a according to the present embodiment configured as described above. However, the difference from the ninth embodiment will be mainly described here.

[0291] In the first reset period (P1 phase), the selection transistor M7 of each pixel is turned on and the first switch element Q1 is turned off. Thus, the first data Coln1a of the first output signal VCO1a outputted from the comparator 212 of the pixel 21a is stored in the first latch circuit 214a of the pixel 21a.

[0292] In the second reset period (P2 phase), the selection transistor M7 of each pixel is turned off and the first switch element Q1 is turned on. Thus, the first data Coln1b of the first output signal VCO1b outputted from the comparator 212 of the pixel 21b is stored in the first latch circuit 214a of the pixel 21b.

[0293] Furthermore, during the first data acquisition period (D1 phase), similarly to the first reset period, the selection transistor M7 of each pixel is turned on and the first switch element Q1 is turned off. Therefore, the comparator 212 of the pixel 21a compares the analog pixel signal SIG amplified by the amplifier transistor M4 of the pixel 21a with the ramp signal RAMP, and outputs the second output signal VCO2a. The second data Coln2a of the second output signal VCO2a is stored in the second latch circuit 214b of the pixel 21a.

[0294] In addition, in the second data acquisition period (D2 phase), as in the second reset period, the selection transistor M7 of each pixel is turned off, and the first switch element Q1 is turned on. Therefore, the comparator 212 of the pixel 21b compares the analog pixel signal SIG amplified by the amplifier transistor M4 of the pixel 21a with the ramp signal RAMP, and outputs a second output signal VCO2b. The second data Coln2b of the second output signal VCO2b is stored in the second latch circuit 214b of the pixel 21b.

[0295] According to the present embodiment described above, the selection transistor M7 cooperates with the selection circuit 213 so that the memory circuit 214 can be shared between the pixel 21 a and the pixel 21 b when the analog pixel signal SIG is digitally converted in the image plane phase difference AF processing.

[0296] Furthermore, in this embodiment, since the second switch element Q2 is not required, the configuration of the selection circuit 213 can be simplified.

[0297] (Eleventh Embodiment)

[0298] Fig.28 1 is a block diagram showing an example of a circuit configuration of a pixel according to an eleventh embodiment. Fig.28 In the present invention, the same circuit elements as those of the pixel in the ninth embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

[0299] This embodiment is different from the ninth embodiment in the configuration of the photoelectric conversion circuit 211. Specifically, the photoelectric conversion circuit 211 is provided with a first photodiode PD1 and a first transfer transistor M1, but is not provided with a second photodiode PD2 or a second transfer transistor M2. In addition, in this embodiment, the amplifier transistor M4, the current source transistor M5, and the selection transistor M7 are not provided in the photoelectric conversion circuit 211. Thus, the drain of the first switch element Q1 is connected to the floating diffusion layer FD.

[0300] Hereinafter, a description will be given of an operation mode in which multi-channel AD processing is performed in the pixel 21a according to the present embodiment configured as described above. However, the difference from the second embodiment will be mainly described here.

[0301] In the first reset period (P1 phase) of the pixel 21a, according to the control of the pixel driving circuit 23, the first transfer transistor M1 of the pixel 21a is turned off, and the first switch element Q1 and the second switch element Q2 are turned on. At this time, in the pixel 21b, the first transfer transistor M1, the first switch element Q1 and the second switch element Q2 are turned off. As a result, the first output signal VCO1a is output from the comparator 212 of the pixel 21a. Subsequently, the first data Coln1a of the first output signal VCO1a is written to the first latch circuit 214a of the pixel 21a.

[0302] In addition, in the present embodiment, the second reset period (P2 phase) is the same as the first reset period (P1 phase). Thus, the first output signal VCO1b is outputted from the comparator 212 of the pixel 21b at the same time as the output of the first output signal VCO1a. Subsequently, the first data Coln1b of the first output signal VCO1b is written to the first latch circuit 214a of the pixel 21b. Thereafter, when the reset transistor of the pixel 21a is turned off based on the reset signal from the pixel driving circuit 23, the reset state of the floating diffusion layer FD is released.

[0303] In addition, in the charge transfer period (FD transfer) of the pixel 21a, the first transfer transistor M1, the first switching element Q1, and the second switching element Q2 of the pixel 21a are turned on. Therefore, in the pixel 21a, the charge accumulated in the first photodiode PD1 is transferred to the floating diffusion layer FD. When the charge is accumulated in the floating diffusion layer FD, the analog pixel signal SIG is generated in the floating diffusion layer FD according to the amount of charge accumulated in the first photodiode PD1.

[0304] In addition, in the first data acquisition period (D1 phase), the comparator 212 of the pixel 21a outputs the second output signal VCO2a. The second data Coln2a of the second output signal VCO2a is written to the first latch circuit 214a of the pixel 21a.

[0305] In addition, in this embodiment, the second data acquisition period (D2 phase) is the same as the first data acquisition period, as in the reset period. Thus, the comparator 12 of the pixel 21b outputs the second output signal VCO2b simultaneously with the output of the second output signal VCO2a. The second data Coln2b of the second output signal VCO2b is written into the second latch circuit 214b of the pixel 21b.

[0306] According to the present embodiment described above, even if the selection circuit 213 is arranged on the input terminal side of the comparator 212, when the analog pixel signal SIG is digitally converted in the multi-channel AD processing, the memory circuit 214 can be shared between the pixel 21a and the pixel 21b. Therefore, it is possible to suppress a decrease in the signal processing speed while avoiding an increase in the size of the memory circuit 214.

[0307] It should be noted that the pixels 21 a and 21 b according to the present embodiment can also be applied to the single-frame HDR processing described in the third embodiment.

[0308] (Twelfth Embodiment)

[0309] Fig.29 1 is a block diagram showing an example of a circuit configuration of a pixel according to a twelfth embodiment. Fig.29In the figure, the same circuit elements as the pixels in the above-mentioned 11th embodiment are marked with the same figure marks, and their detailed description is omitted.

[0310] In this embodiment, the selection circuit 213 includes only the first switch element Q1. Fig.29 In the embodiment of the present invention, the first switching element Q1 is arranged in the photoelectric conversion circuit 211 , but may be arranged between the photoelectric conversion circuit 211 and the comparator 212 .

[0311] The drain of the first switching element Q1 of the pixel 21a is connected to the anode of the first photodiode PD1 of the pixel 21a and the drain of the first transfer transistor M1. The source of the first switching element Q1 is connected to the first input terminal of the comparator 212 of the pixel 21b. At the same time, the drain of the first switching element Q1 of the pixel 21b is connected to the anode of the first photodiode PD1 of the pixel 21b and the drain of the first transfer transistor M1. The source of the first switching element Q1 is connected to the first input terminal of the comparator 212 of the pixel 21a.

[0312] When the first switching element Q1 of the pixel 21a is turned on, the charge photoelectrically converted by the first photodiode PD1 of the pixel 21a is transferred to the floating diffusion layer FD of the pixel 21b based on the control signal from the pixel driving circuit 23. At the same time, when the first switching element Q1 of the pixel 21b is turned on, the charge photoelectrically converted by the first photodiode PD1 of the pixel 21b is transferred to the floating diffusion layer FD of the pixel 21a based on the control signal from the pixel driving circuit 23.

[0313] Hereinafter, a description will be given of an operation mode in which multi-channel AD processing is performed in the pixel 21a according to the present embodiment configured as described above. However, the difference from the second embodiment will be mainly described here.

[0314] In the first reset period (P1 phase) of the pixel 21a, the first transfer transistor M1 and the first switch element Q1 of the pixel 21a are turned off according to the control of the pixel driving circuit 23. At this time, in the pixel 21b, the first transfer transistor M1, the first switch element Q1, and the second switch element Q2 are turned off. As a result, the first output signal VCO1a is output from the comparator 212 of the pixel 21a. Subsequently, the first data Coln1a of the first output signal VCO1a is written to the first latch circuit 214a of the pixel 21a.

[0315] In addition, in the present embodiment, the second reset period (P2 phase) is the same as the first reset period (P1 phase). Thus, the first output signal VCO1b is outputted from the comparator 212 of the pixel 21b at the same time as the output of the first output signal VCO1a. Subsequently, the first data Coln1b of the first output signal VCO1b is written to the first latch circuit 214a of the pixel 21b. Thereafter, when the reset transistor of the pixel 21a is turned off based on the reset signal from the pixel driving circuit 23, the reset state of the floating diffusion layer FD is released.

[0316] In addition, in the charge transfer period (FD transfer) of the pixel 21a, the first transfer transistor M1 and the first switching element Q1 of the pixel 21a are turned on. Therefore, the charge accumulated in the first photodiode PD1 of the pixel 21a is transferred to the floating diffusion layer FD of each of the pixel 21a and the pixel 21b. When the charge is accumulated in the floating diffusion layer FD, an analog pixel signal SIG is generated in the floating diffusion layer FD according to the amount of charge accumulated in the first photodiode PD1 of the pixel 21a.

[0317] In addition, in the first data acquisition period (D1 phase), the comparator 212 of the pixel 21a outputs the second output signal VCO2a. The second data Coln2a of the second output signal VCO2a is written to the second latch circuit 214b of the pixel 21a.

[0318] In addition, in this embodiment, the second data acquisition period (D2 phase) is the same as the first data acquisition period, as in the reset period. Thus, the comparator 212 of the pixel 21b outputs the second output signal VCO2b simultaneously with the output of the second output signal VCO2a. The second data Coln2b of the second output signal VCO2b is written into the second latch circuit 214b of the pixel 21b.

[0319] According to the present embodiment described above, as in the eleventh embodiment, even if the selection circuit 213 is arranged on the input terminal side of the comparator 212, when the analog pixel signal SIG is digitally converted in the multi-channel AD processing, the memory circuit 214 can be shared between the pixel 21a and the pixel 21b. Therefore, a decrease in the signal processing speed can be suppressed while an increase in the size of the memory circuit 214 can be avoided.

[0320] Furthermore, according to the present embodiment, the second switch element Q2 is unnecessary in the selection circuit 213. Therefore, the circuit configuration of the selection circuit 213 can be simplified.

[0321] Note that the pixel according to the present embodiment can also be applied to the single-frame HDR processing described in the third embodiment.

[0322] (Thirteenth embodiment)

[0323] Fig.30 is a diagram showing an example of a color pattern of a pixel according to a thirteenth embodiment. Fig.30 The color pattern shown in is a Bayer array. That is, in the pixel array unit 22, the ratio between the number of green pixels 21Gr and green pixels 21Gb that receive green light, the number of red pixels 21R that receive red light, and the number of blue pixels 21B that receive blue light is 2:1:1. In addition, the green pixel Gr is a pixel that receives incident light that passes through the RG filter that transmits red light and green light. At the same time, the green pixel Gb is a pixel that receives incident light that is transmitted through the GB filter that transmits green light and blue light.

[0324] In the present embodiment, the storage circuit 214 can be shared by pixels adjacent to each other in the row direction X or the column direction Y (i.e., pixels of different colors). However, in a case where the four colors are not completed at the shutter release timing, color deviation occurs when the flash is applied. For this flash coloring countermeasure, it is desirable to share the storage circuit 214 between pixels of the same color. In this case, the pixels sharing the storage circuit 214 may be pixels of the same color arranged along the row direction X, or may be pixels of the same color arranged along the column direction Y. In addition, the number of pixels sharing the storage circuit 214 may be two or four.

[0325] Fig.31 is a diagram showing another example of a color pattern of a pixel according to the thirteenth embodiment. Fig.31 In the color mode shown, the red pixel 21R, the green pixel 21Gr, Gb and the blue pixel 21B are arranged in a 2×2 matrix, respectively. In this case, the number of pixels of the same color that share the memory circuit 214 may be two or four.

[0326] Fig.32 is a diagram showing still another example of a color pattern of a pixel according to the thirteenth embodiment. Fig.32 In the color mode shown, the red pixel 21R, the green pixel 21Gr, Gb and the blue pixel 21B are respectively arranged in a matrix of 3×3. In this case, the number of pixels of the same color sharing the memory circuit 214 may be three or nine.

[0327] In the case where the light detection element according to the present embodiment is applied to a mobile device such as a smartphone, for example, due to a narrow pixel pitch, the comparator 212 and the storage circuit 214 having the minimum necessary functions may not be arranged in the logic chip 120. In this case, by further increasing the number of pixels sharing the storage circuit 214, it is possible to ensure an arrangement space for circuit elements of the pixels.

[0328] Fig.33It is shown that Fig.31 A block diagram of an embodiment of a circuit configuration of a pixel arranged in a color pattern as shown in FIG. Fig.33 , four photoelectric conversion circuits 211Gr and four photoelectric conversion circuits 211B share one comparator 212. In addition, four photoelectric conversion circuits 211R and four photoelectric conversion circuits 211Gb share one comparator 212. The photoelectric conversion circuit 211Gr, the photoelectric conversion circuit 211B, the photoelectric conversion circuit 211R, and the photoelectric conversion circuit 211Gb are respectively provided in the green pixel 21Gr, the blue pixel 21B, the red pixel 21R, and the green pixel 21Gb.

[0329] Furthermore, two selection circuits 213 provided in the switching circuit 215 select one of the first latch circuit 214a to the fourth latch circuit 214d as the output destination of the output signal VCO of each comparator 212. Fig.33 In the circuit configuration shown, the memory circuit 214 is shared by 16 pixels.

[0330] Fig.34 It shows that the setting Fig.33 FIG. 2 is a diagram showing a layout example of the gate wiring of the first transfer transistor M1 in each of the photoelectric conversion circuit 211Gr and the photoelectric conversion circuit 211B. Fig.34 In FIG. 4 , gate lines 400 of first transfer transistors M1 adjacent to each other in the row direction X extend in parallel along the row direction X. Fig.34 In the wiring layout shown, the comparator 212 is shared by eight photoelectric conversion circuits 211Gr and 211B. In the case where the number of photoelectric conversion circuits 211 shared with respect to the comparator 212 increases, it is conceivable to extend the gate line 400 in the row direction X or the column direction Y.

[0331] Fig.35 is a diagram showing a layout example of the gate wiring of the first transfer transistor M1 when the number of photoelectric conversion circuits 211 shared with respect to the comparator 212 increases. Fig.35 A wiring layout in the case where the number of the photoelectric conversion circuits 211 shared with the comparators 212 is increased from 4 to 8 is shown.

[0332] When the photoelectric conversion circuits 211 to be added are arranged along the row direction X, the number of gate lines 400 per unit area is doubled. Fig.35 Therefore, the gate line 400 must be formed at a high density, and further, an increase in the processing load of the pixel driving circuit 23 that controls the first transfer transistor M1 is caused.

[0333] On the other hand, when the photoelectric conversion circuits 211 to be added are arranged in the column direction Y, the number of gate lines 400 per unit area does not change, as shown in FIG. Fig.35 As shown in the lower part of . Therefore, the wiring density does not change, and the processing load of the pixel driving circuit 23 does not increase. Therefore, in the case where the number of photoelectric conversion circuits 211 shared with respect to the comparator 212 increases, it is desirable to increase the arrangement of the photoelectric conversion circuits 211 in the column direction Y, in other words, to extend the gate line 400 in the column direction Y.

[0334] (Fourteenth Embodiment)

[0335] Fig.36 is a block diagram showing a schematic configuration of an electronic device according to a fourteenth embodiment. Fig.36 The electronic device 500 shown in FIG. 5 is an electronic device, for example, an imaging apparatus such as a digital still camera or a video camera, or a mobile terminal device such as a smartphone or a tablet terminal.

[0336] The electronic device 500 includes, for example, a light detecting element 510, an optical system 511, a shutter device 512, a DSP circuit 513, a frame memory 514, a display unit 515, a storage unit 516, an operation unit 517, and a power supply unit 518. In the electronic device 500, the light detecting element 510, the shutter device 512, the DSP circuit 513, the frame memory 514, the display unit 515, the storage unit 516, the operation unit 517, and the power supply unit 518 are connected to each other via a bus 519.

[0337] Any of the light detecting elements described in the above-mentioned first to thirteenth embodiments can be applied to the light detecting element 510. The optical system 511 includes one or more lenses, guides light (incident light) from a subject to the light detecting element 510, and forms an image on a light receiving surface of the light detecting element 510.

[0338] The shutter device 512 is arranged between the optical system 511 and the light detection element 510, and controls the light irradiation period and the light shielding period of the light detection element 510. The DSP circuit 513 is a signal processing circuit that processes the output signal of the light detection element 510. The frame memory 514 temporarily holds the image data processed by the DSP circuit 513 in units of frames.

[0339] The display unit 515 includes, for example, a panel-type display device such as a liquid crystal panel or an organic electroluminescence (EL) panel, and displays a moving image or a still image captured by the light detection element 510. The storage unit 516 records image data of the moving image or the still image captured by the light detection element 510 in a recording medium such as a semiconductor memory or a hard disk.

[0340] The operation unit 517 issues operation commands for various functions of the electronic device 500 according to the operation of the user. The power supply unit 518 appropriately supplies various power sources used as operation power sources for the light detection element 510, the shutter device 512, the DSP circuit 513, the frame memory 514, the display unit 515, the storage unit 516, and the operation unit 517 to these supply targets.

[0341] In the electronic device 500 configured as described above, when the user gives an instruction to start imaging by operating the operation unit 517, the operation unit 517 sends an imaging command to the light detecting element 510. When receiving the imaging command, the light detecting element 510 performs various settings (for example, the above-mentioned image quality adjustment, etc.). Subsequently, the light detecting element 510 performs imaging by a predetermined imaging method.

[0342] The light detection element 510 outputs a signal obtained by imaging to the DSP circuit 513. The DSP circuit 513 performs predetermined signal processing (for example, noise reduction processing, etc.) on the output signal of the light detection element 510. The DSP circuit 513 causes the frame memory 514 to hold the image data subjected to the predetermined signal processing, and the frame memory 514 causes the storage unit 516 to store the image data. In this way, imaging in the electronic device 500 is performed.

[0343] According to the present embodiment described above, any one of the light detecting elements according to the first to thirteenth embodiments described above can be applied to the light detecting element 510. Therefore, a decrease in signal processing speed can be suppressed while an increase in the size of the memory circuit 214 is avoided.

[0344] <Application example of mobile object>

[0345] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented in the form of a device installed on any kind of mobile body (such as a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot).

[0346] Fig.37 is a block diagram showing a schematic configuration example of a vehicle control system which is an example of a moving body control system to which the technology according to the present disclosure can be applied.

[0347] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.37In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional structure of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are exemplified.

[0348] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating a drive force of the vehicle, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, and the like.

[0349] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a backup light, a brake light, a turn signal, a fog light, etc. In this case, a radio wave transmitted from a mobile device as a substitute for a key or a signal of various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, the lights, etc. of the vehicle.

[0350] The vehicle exterior information detection unit 12030 detects information outside the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to an imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receive the captured image. In addition, the vehicle exterior information detection unit 12030 may also detect objects such as people, vehicles, obstacles, signs, and text on the road surface, or detect their distances, based on the received image.

[0351] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may output the electrical signal as an image, or may output the electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0352] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection unit 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that photographs the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off.

[0353] The microcomputer 12051 can calculate the control target value of the driving force generation device, the steering mechanism, or the braking device based on the information about the inside or outside of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of the advanced driver assistance system (ADAS), which includes collision prevention or shock absorption for the vehicle, follow-up driving based on the following distance, maintaining the vehicle speed for driving, warning of vehicle collision, warning of vehicle deviation from the lane, etc.

[0354] In addition, the microcomputer 12051 can perform collaborative control for automatic driving by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about outside or inside the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, thereby enabling the vehicle to travel automatically without relying on the driver's operation, etc.

[0355] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle obtained by the vehicle outside information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to change from high beam to low beam according to the position of the front vehicle or the oncoming vehicle detected by the outside vehicle information detection unit 12030.

[0356] The sound / image output unit 12052 transmits an output signal of at least one of sound or image to an output device, which can visually or auditorily notify the passengers of the vehicle or people outside the vehicle of the information. Fig.37 In the embodiment of FIG. 1 , audio speaker 12061, display portion 12062, and instrument panel 12063 are shown as output devices. For example, display portion 12062 may include at least one of an on-board display or a head-up display.

[0357] Fig.38 12031 is a diagram showing an embodiment of the installation position of the imaging unit 12031.

[0358] exist Fig.38 In the imaging unit 12031, imaging units 12101, 12102, 1210312104 and 12105 are included.

[0359] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at locations within the interior of the vehicle 12100, such as the front nose, side mirrors, rear bumper, rear door, and upper portion of the windshield. Each of the imaging unit 12101 on the front nose and the imaging unit 12105 on the upper portion of the windshield in the interior mainly obtains an image of the area in front of the vehicle 12100. The imaging units 12102 and 12103 provided to the side mirrors mainly obtain an image of the side of the vehicle 12100. The imaging unit 12104 provided to the rear bumper or rear door mainly obtains an image of the rear portion of the vehicle 12100. The imaging unit 12105 provided on the upper portion of the windshield within the vehicle interior is mainly used to detect a front vehicle, pedestrians, obstacles, signals, traffic signs, lanes, and the like.

[0360] Please note that Fig.38 An embodiment of the imaging range of the imaging units 12101 to 12104 is shown. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided to the front nose. Imaging ranges 1211212113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors. Imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 viewed from above is obtained by superimposing image data imaged by the imaging units 12101 to 12104.

[0361] At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera including a plurality of imaging devices, or may be an imaging device having pixels for phase difference detection.

[0362] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting the objects existing on the driving path of the vehicle 12100 and traveling in the same direction as the vehicle 12100 at a prescribed speed (e.g., equal to or greater than 0 km / hour). In addition, the microcomputer 12051 can set the following distance in advance to keep ahead of the leading vehicle, and perform automatic braking control (including follow-up blocking control), automatic acceleration control (including follow-up starting control), etc. Thus, coordinated control for automatic driving that allows the vehicle to travel automatically without relying on the driver's operation, etc. can be performed.

[0363] For example, the microcomputer 12051 can classify the three-dimensional object data related to the three-dimensional object into three-dimensional object data of a two-wheeled vehicle, a standard vehicle, a large vehicle, a pedestrian, a utility pole, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. In the case where the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering via the drive system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0364] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 may, for example, identify a pedestrian by determining whether a pedestrian exists in the captured images of the imaging units 12101 to 12104. This identification of a pedestrian is performed, for example, by a process of extracting feature points in the imaged images of the imaging units 12101 to 12104 as infrared cameras and by performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the imaged images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed as superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon representing a pedestrian or the like is displayed at a desired position.

[0365] In the above, an example of a vehicle control system to which the technology according to the present disclosure can be applied has been described. For example, the technology according to the present disclosure can be applied to the imaging units 7910, 7912, 7914, 7916 and 7918 and the external vehicle information detection units 7920, 7922, 7924, 7926, 7928 and 7930 in the above-mentioned components. Then, in particular, it is possible to suppress the reduction in signal processing speed while avoiding an increase in the size of the imaging device. Therefore, the application of the technology according to the present disclosure can contribute to the miniaturization and acceleration of the vehicle control system.

[0366] It should be noted that the present technology can have the following configurations.

[0367] (1) A light detection element comprising:

[0368] A plurality of pixels arranged in a matrix, wherein

[0369] Multiple pixels include:

[0370] A photoelectric conversion circuit that photoelectrically converts incident light to output an analog pixel signal;

[0371] a comparator, outputting a result of comparing the analog pixel signal with a reference signal;

[0372] a storage circuit that stores data of an output signal of the comparator; and

[0373] A switching circuit switches an output destination of an analog pixel signal or an output signal to share a storage circuit among a plurality of pixels.

[0374] (2) The light detection element according to (1), wherein the switching circuit is arranged on the output terminal side of the comparator.

[0375] (3) The light detection element according to (1), wherein the switching circuit is arranged on the input terminal side of the comparator.

[0376] (4) The light detecting element according to any one of (1) to (3), wherein

[0377] The photoelectric conversion circuit includes a first photodiode and a second photodiode connected to an input terminal of the comparator,

[0378] The comparator outputs a first output signal when the photoelectric conversion circuit is in a reset state; outputs a second output signal indicating a comparison result between an analog pixel signal when the first photodiode photoelectrically converts the incident light and the reference signal; and outputs a third output signal indicating a comparison result between the analog pixel signal when the first photodiode and the second photodiode photoelectrically convert the incident light and the reference signal,

[0379] The storage circuit includes a plurality of latch circuits, and

[0380] The switching circuit switches output destinations of the first output signal, the second output signal, and the third output signal to different latch circuits, respectively.

[0381] (5) The light detecting element according to any one of (1) to (3), wherein

[0382] The photoelectric conversion circuit includes a first photodiode connected to an input terminal of the comparator,

[0383] the comparator outputs a first output signal when the photoelectric conversion circuit is in a reset state, and outputs a second output signal indicating a comparison result between an analog pixel signal when the first photodiode photoelectrically converts the incident light and the reference signal a plurality of times,

[0384] The storage circuit includes a plurality of latch circuits, and

[0385] The switching circuit switches the output destinations of the first output signal and each second output signal to different latch circuits, respectively.

[0386] (6) The light detection element according to (5), wherein the comparator outputs the second output signal a plurality of times by performing a plurality of AD conversion processes on the analog pixel signal once transmitted to the floating diffusion layer.

[0387] (7) The light detection element according to (5), wherein the comparator outputs the second output signal under conditions that are different each time.

[0388] (8) The light detection element according to (5), wherein the comparator outputs the second output signal under the condition that a gain of at least one of the analog pixel signal or the reference signal is changed.

[0389] (9) The light detection element according to any one of (1) to (8), wherein the switching circuit switches an output destination of the analog pixel signal or the output signal so that mutually adjacent pixels among the plurality of pixels share the storage circuit.

[0390] (10) The light detecting element according to any one of (1) to (9), wherein

[0391] Multiple pixels individually receive light beams of multiple colors, and

[0392] The memory circuit is shared by pixels receiving light of the same color.

[0393] (11) The light detecting element according to (4), wherein

[0394] The plurality of pixels include a first pixel and a second pixel adjacent to the first pixel,

[0395] The storage circuit includes a first latch circuit and a second latch circuit, and

[0396] The switching circuit selects the first latch circuit of the first pixel as the output destination of the first output signal, selects the second latch circuit of the first pixel as the output destination of the second output signal, and selects the first latch circuit of the second pixel as the output destination of the third output signal.

[0397] (12) The light detecting element according to (5), wherein

[0398] The plurality of pixels include a first pixel and a second pixel adjacent to the first pixel,

[0399] The comparator outputs the second output signal twice,

[0400] The storage circuit includes a first latch circuit and a second latch circuit, and

[0401] The switching circuit selects the first latch circuit of the first pixel as the output destination of the first output signal, selects the second latch circuit of the first pixel as the output destination of the second output signal for the first time, and selects the first latch circuit of the second pixel as the output destination of the second output signal for the second time.

[0402] (13) The light detecting element according to any one of (1) to (12), wherein

[0403] The plurality of pixels include first to fourth pixels arranged close to each other,

[0404] The storage circuit includes a first latch circuit, and

[0405] The number of pixels sharing the first latch circuit is variable between the first pixel to the fourth pixel.

[0406] (14) The light detecting element according to (1), further comprising:

[0407] a first chip in which a plurality of photoelectric conversion circuits are arranged; and

[0408] A second chip is provided with a plurality of comparators, a plurality of storage circuits, a plurality of switching circuits, and a repeater for reading data from the storage circuits, wherein

[0409] The repeater is arranged at a position facing the center of the plurality of photoelectric conversion circuits, and the plurality of comparators, the plurality of storage circuits, and the plurality of switching circuits are symmetrically arranged with the repeater interposed therebetween.

[0410] (15) The light detection element according to (14), wherein the storage circuit is arranged on both sides of the repeater, the comparator is arranged on one side of the storage circuit, and the switching circuit is arranged on one side of the comparator.

[0411] (16) The light detection element according to (2), wherein the switching circuit includes a multiplexer.

[0412] (17) The light detecting element according to (3), wherein

[0413] The switching circuit includes:

[0414] a first switch element, which switches whether to output the analog pixel signal to a first pixel among the plurality of pixels; and

[0415] The second switch element switches whether to output the analog pixel signal to a second pixel different from the first pixel.

[0416] (18) The light detecting element according to (1), wherein

[0417] The photoelectric conversion circuit includes a selection transistor of a comparator that switches whether to output an analog pixel signal to a first pixel among a plurality of pixels, and

[0418] The switching circuit includes a first switching element that switches whether to output the analog pixel signal to a comparator of a second pixel different from the first pixel.

[0419] (19) The light detecting element according to (1), wherein

[0420] The photoelectric conversion circuit includes a transfer transistor that switches whether to transfer charges obtained by photoelectrically converting incident light to a floating diffusion layer of a first pixel among a plurality of pixels, and

[0421] The switching circuit includes a first switching element that switches whether to transfer the charge to a floating diffusion layer of a second pixel different from the first pixel.

[0422] (20) An electronic device comprising:

[0423] A plurality of pixels arranged in a matrix, wherein

[0424] Multiple pixels include:

[0425] A photoelectric conversion circuit that photoelectrically converts incident light to output an analog pixel signal;

[0426] a comparator, outputting a result of comparing the analog pixel signal with a reference signal;

[0427] a storage circuit that stores data of an output signal of the comparator; and

[0428] A switching circuit switches an output destination of an analog pixel signal or an output signal to share a storage circuit among a plurality of pixels.

[0429] Reference Symbols List

[0430] 1 Light detection element

[0431] 21, 21a to 21d pixels

[0432] 21R red pixel

[0433] 21Gr, 21Gb green pixels

[0434] 21B Blue Pixel

[0435] 26 Repeater

[0436] 110 sensor chip

[0437] 120 Logic Chip

[0438] 211 Photoelectric conversion circuit

[0439] 212 Comparator

[0440] 214 Storage Circuit

[0441] 214a First latch circuit

[0442] 214b Second latch circuit

[0443] 215 Switching Circuit

[0444] 500 Electronic Devices

[0445] FD Floating Diffusion

[0446] M1 first pass transistor

[0447] M2 Second transfer transistor

[0448] M7 select transistor

[0449] PD1 First photodiode

[0450] PD2 Second photodiode

[0451] Q1 First switching element

[0452] Q2 is the second switching element.

Claims

1. A light detection element, comprising: A plurality of pixels are arranged in a matrix, wherein The plurality of pixels comprises: A photoelectric conversion circuit that photoelectrically converts incident light to output an analog pixel signal; a comparator, outputting a result of comparing the analog pixel signal with a reference signal; a storage circuit for storing data of an output signal of the comparator; and A switching circuit switches an output destination of the analog pixel signal or the output signal so as to share the storage circuit among the plurality of pixels.

2. The light detecting element according to claim 1, wherein The switching circuit is arranged on the output terminal side of the comparator.

3. The light detecting element according to claim 1, wherein The switching circuit is arranged on the input terminal side of the comparator.

4. The light detecting element according to claim 1, wherein The photoelectric conversion circuit includes a first photodiode and a second photodiode connected to an input terminal of the comparator, The comparator outputs a first output signal when the photoelectric conversion circuit is in a reset state; outputs a second output signal indicating a comparison result between an analog pixel signal when the first photodiode photoelectrically converts the incident light and the reference signal; and outputs a third output signal indicating a comparison result between the analog pixel signal when the first photodiode and the second photodiode photoelectrically convert the incident light and the reference signal, The storage circuit includes a plurality of latch circuits, and The switching circuit switches output destinations of the first output signal, the second output signal, and the third output signal to different latch circuits, respectively.

5. The light detecting element according to claim 1, wherein The photoelectric conversion circuit includes a first photodiode connected to an input terminal of the comparator, the comparator outputs a first output signal when the photoelectric conversion circuit is in a reset state, and outputs a second output signal indicating a comparison result between an analog pixel signal when the first photodiode photoelectrically converts the incident light and the reference signal a plurality of times, The storage circuit includes a plurality of latch circuits, and The switching circuit switches the output destinations of the first output signal and each second output signal to different latch circuits, respectively.

6. The light detecting element according to claim 5, wherein The comparator outputs the second output signal a plurality of times by performing a plurality of AD conversion processes on the analog pixel signal once transmitted to the floating diffusion layer.

7. The light detecting element according to claim 5, wherein The comparator outputs the second output signal under different conditions each time.

8. The light detecting element according to claim 5, wherein The comparator outputs the second output signal under the condition that a gain of at least one of the analog pixel signal and the reference signal is changed.

9. The light detecting element according to claim 1, wherein The switching circuit switches an output destination of the analog pixel signal or the output signal so that mutually adjacent pixels among the plurality of pixels share the storage circuit.

10. The light detecting element according to claim 1, wherein The plurality of pixels individually receive light beams of a plurality of colors, and The memory circuit is shared by pixels receiving light of the same color.

11. The light detecting element according to claim 4, wherein The plurality of pixels include a first pixel and a second pixel adjacent to the first pixel, the storage circuit includes a first latch circuit and a second latch circuit, and The switching circuit selects the first latch circuit of the first pixel as the output destination of the first output signal, selects the second latch circuit of the first pixel as the output destination of the second output signal, and selects the first latch circuit of the second pixel as the output destination of the third output signal.

12. The light detecting element according to claim 5, wherein The plurality of pixels include a first pixel and a second pixel adjacent to the first pixel, the comparator outputs the second output signal twice, The storage circuit includes a first latch circuit and a second latch circuit, and The switching circuit selects the first latch circuit of the first pixel as the output destination of the first output signal, selects the second latch circuit of the first pixel as the output destination of the second output signal for the first time, and selects the first latch circuit of the second pixel as the output destination of the second output signal for the second time.

13. The light detecting element according to claim 1, wherein The plurality of pixels include first to fourth pixels arranged close to each other, The storage circuit includes a first latch circuit, and The number of pixels sharing the first latch circuit is variable between the first pixel to the fourth pixel.

14. The light detecting element according to claim 1, further comprising: A first chip, in which a plurality of photoelectric conversion circuits are arranged; as well as A second chip is arranged in which a plurality of comparators, a plurality of storage circuits, a plurality of switching circuits and a repeater that reads data from the storage circuits are arranged, wherein: The repeater is arranged at a position facing the center of the plurality of photoelectric conversion circuits, and the plurality of comparators, the plurality of storage circuits, and the plurality of switching circuits are symmetrically arranged with the repeater interposed therebetween.

15. The light detecting element according to claim 14, wherein The storage circuit is arranged at both sides of the repeater, the comparator is arranged at one side of the storage circuit, and the switching circuit is arranged at one side of the comparator.

16. The light detecting element according to claim 2, wherein The switching circuit includes a multiplexer.

17. The light detecting element according to claim 3, wherein The switching circuit comprises: a first switch element, switching whether to output the analog pixel signal to a first pixel among the plurality of pixels; and The second switch element switches whether to output the analog pixel signal to a second pixel different from the first pixel.

18. The light detecting element according to claim 1, wherein The photoelectric conversion circuit includes a selection transistor that switches whether to output the analog pixel signal to a comparator of a first pixel among the plurality of pixels, and The switching circuit includes a first switching element that switches whether to output the analog pixel signal to a comparator of a second pixel different from the first pixel.

19. The light detecting element according to claim 1, wherein The photoelectric conversion circuit includes a transfer transistor that switches whether to transfer charges obtained by photoelectrically converting the incident light to a floating diffusion layer of a first pixel among the plurality of pixels, and The switching circuit includes a first switching element that switches whether to transfer the charges to a floating diffusion layer of a second pixel different from the first pixel.

20. An electronic device comprising: A plurality of pixels are arranged in a matrix, wherein The plurality of pixels comprises: A photoelectric conversion circuit that photoelectrically converts incident light to output an analog pixel signal; a comparator, outputting a result of comparing the analog pixel signal with a reference signal; a storage circuit for storing data of an output signal of the comparator; and A switching circuit switches an output destination of the analog pixel signal or the output signal so as to share the storage circuit among the plurality of pixels.

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