Field effect transistor with multi-step field plate

Abstract

A transistor device according to some embodiments includes a semiconductor barrier layer, a surface dielectric layer on the semiconductor barrier layer, and a gate on the surface dielectric layer. The surface dielectric layer includes an aperture therein laterally spaced apart from the gate. The device includes: an interlayer dielectric layer on a surface dielectric layer, the interlayer dielectric layer extending over a gate and into an aperture in the surface dielectric layer; and a multi-step field plate on the interlayer dielectric layer. The multi-step field plate is laterally spaced apart from the gate. A recessed portion of the multi-step field plate is over the aperture in the surface dielectric layer, and the multi-step field plate includes a first step adjacent to the recessed portion of the field plate on a side of the field plate opposite the gate and a second step adjacent to the first step.

Description

Background Art

[0001] The present disclosure relates to transistor structures, and in particular to field effect transistors including field plates.

[0002] Narrow bandgap semiconductor materials such as silicon (Si) and gallium arsenide (GaAs) are widely used in semiconductor devices for low power and, in the case of Si, in low frequency applications. However, these semiconductor materials may be less suitable for high power and / or high frequency applications, for example due to their relatively small bandgap (1.12 eV for Si and 1.42 eV for GaAs at room temperature) and relatively small breakdown voltage.

[0003] Interest in high power, high temperature and / or high frequency applications and devices has focused on wide bandgap semiconductor materials such as silicon carbide (3.2 eV for 4H-SiC at room temperature) and group III nitrides (e.g., 3.36 eV for GaN at room temperature.) These materials can have higher electric field breakdown strength and higher electron saturation velocity than GaAs and Si.

[0004] Devices of particular interest for high power and / or high frequency applications are high electron mobility transistors (HEMTs), also known as modulation doped field effect transistors (MODFETs). In HEMT devices, a two-dimensional electron gas (2DEG) can be formed at the heterojunction of two semiconductor materials with different bandgap energies, where the smaller bandgap material has a higher electron affinity than the wider bandgap material. The 2DEG is an accumulation layer in the undoped smaller bandgap material and can contain a relatively high sheet electron concentration, for example, in excess of 10 13 Carrier / cm 2 Additionally, electrons originating from the wider bandgap semiconductor can be transferred to the 2DEG, allowing relatively high electron mobility due to reduced ionized impurity scattering. This combination of relatively high carrier concentration and carrier mobility can give the HEMT a relatively large transconductance and can provide performance advantages over metal semiconductor field effect transistors (MESFETs) for high frequency applications.

[0005] HEMTs fabricated in the gallium nitride / aluminum gallium nitride (GaN / AlGaN) material system can generate large amounts of RF power due to a combination of material properties such as relatively high breakdown field, relatively wide band gap, relatively large conduction band offset, and / or relatively high saturated electron drift velocity. Most of the electrons in the 2DEG can be attributed to polarization in the AlGaN.

[0006] Field plates have been used to improve the performance of GaN-based HEMTs at microwave frequencies, and have shown performance improvements over devices without field plates. Many field plate approaches have involved a field plate connected to the source of the transistor, where the field plate is on top of the drain side of the channel. This can result in a reduction in the electric field on the gate-drain side of the transistor, thereby increasing the breakdown voltage and reducing high-field trapping effects. However, some transistors with gate-drain field plates can exhibit relatively poor reliability performance, particularly in class C (or higher) operation where the electric field on the source side of the gate becomes significant.

[0007] FIG. 1 shows a GaN-based HEMT 10 formed on a silicon carbide substrate 12. A GaN channel layer 16 is on the substrate 12, and an AlGaN barrier layer 18 is on the channel layer 16. A two-dimensional electron gas (2DEG) 20 is present in the channel layer 16 adjacent to the barrier layer 18. A source contact 22 and a drain contact 24 are formed on the channel layer 16. The conductivity of the 2DEG 20 is modulated by applying a voltage to a gate 26, which is formed on the barrier layer 18 between the source contact 22 and the drain contact 24. As shown in FIG. 1, the gate 26 may have a mushroom-shaped or T-shaped top configuration, in which the gate 26 contacts the barrier layer 18 in a relatively narrow contact region extending through a surface dielectric layer 25.

[0008] HEMT 10 includes a field plate 28 connected to source contact 22. Field plate 28 is spaced apart from gate 26 by interlayer dielectric layer 21, and is spaced apart from barrier layer 18 by interlayer dielectric layer 21 and surface dielectric layer 25. Field plate 28 extends over gate 26 and laterally toward drain contact 24.

[0009] The field plate 28 is connected to the source contact 22. Connecting the field plate 28 to the source contact 22 provides a reduction in the gate-drain capacitance (Cgd), which can therefore improve the gain of the device. In addition to reducing the gate-drain capacitance Cgd, the presence of the field plate 28 can also improve the linearity of the device and / or reduce the drain bias dependence of the capacitance. Although GaN-based HEMTs generally show good linearity, further improvements may be desired in high power RF applications. In addition, although the structure shown in Figure 1 can have a reduced gate-drain capacitance Cgd compared to a structure without a field plate, the gate-drain capacitance Cgd may still show a large dependence on the bias of the drain contact 24. Summary of the invention

[0010] A transistor device according to some embodiments includes a semiconductor barrier layer, a surface dielectric layer on the semiconductor barrier layer, and a gate on the surface dielectric layer. The surface dielectric layer includes an aperture therein that is laterally spaced from the gate. The device includes: an interlayer dielectric layer on the surface dielectric layer, the interlayer dielectric layer extending above the gate and extending into the aperture in the surface dielectric layer; and a multi-step field plate on the interlayer dielectric layer. The multi-step field plate is laterally spaced from the gate.

[0011] The recessed portion of the multi-step field plate is above the aperture in the surface dielectric layer, and the multi-step field plate includes a first step adjacent to the recessed portion of the field plate on a side of the field plate opposite to the gate, and a second step adjacent to the first step. The recessed portion of the field plate is vertically spaced a first distance from the semiconductor barrier layer, the first step is vertically spaced a second distance from the semiconductor barrier layer, and the second step is vertically spaced a third distance from the semiconductor barrier layer. The second distance is greater than the first distance, and the third distance is greater than the second distance.

[0012] In some embodiments, the first distance is equal to the thickness of the interlayer dielectric layer. In some embodiments, the second distance is equal to the sum of the thickness of the interlayer dielectric layer and the thickness of the surface dielectric layer.

[0013] The interlayer dielectric layer may include a first interlayer dielectric layer, wherein the third distance is equal to a sum of a thickness of the first interlayer dielectric layer plus a thickness of the surface dielectric layer plus a thickness of a second interlayer dielectric layer on the first interlayer dielectric layer.

[0014] The aperture in the surface dielectric layer may extend completely through the surface dielectric layer to expose the semiconductor barrier layer, and the gate may extend through the surface dielectric layer to contact the semiconductor barrier layer.

[0015] In some embodiments, the transistor device may further include a source contact and a drain contact on the semiconductor barrier layer, wherein the gate is between the source contact and the drain contact, and wherein the field plate includes a source wing extending on the semiconductor barrier layer toward the source contact.

[0016] The first distance may be about 0.1 to 0.3 microns, and the second distance may be about 0.15 to 0.4 microns. The third distance may be about 0.25 to 0.5 microns. The recessed portion of the field plate may have a width of about 0.3 to 0.6 microns.

[0017] The first step may have a width of approximately 0.3 to 0.6 micrometers, and the second step may have a width of approximately 0.3 to 0.6 micrometers.

[0018] The interlayer dielectric layer has a vertical thickness, and the field plate may be laterally spaced apart from the gate by a distance approximately equal to the vertical thickness of the interlayer dielectric layer.

[0019] The transistor device may include a third step adjacent to the second step, wherein the third step is vertically spaced apart from the semiconductor by a fourth distance greater than the third distance.

[0020] The method of forming a transistor device according to some embodiments includes: forming a surface dielectric layer on a semiconductor barrier layer; forming an aperture in the surface dielectric layer to expose the semiconductor barrier layer; forming a gate spaced laterally from the aperture on the surface dielectric layer; forming an interlayer dielectric layer on the surface dielectric layer and the gate, wherein the interlayer dielectric layer extends on the gate and extends into the aperture in the surface dielectric layer; and forming a multi-step field plate on the interlayer dielectric layer. The multi-step field plate is spaced laterally from the gate. The recessed portion of the multi-step field plate is above the aperture in the surface dielectric layer. The multi-step field plate includes a first step adjacent to the recessed portion of the multi-step field plate on a side of the multi-step field plate opposite to the gate, and a second step adjacent to the first step. The recessed portion of the multi-step field plate is spaced a first distance vertically from the semiconductor barrier layer, the first step is spaced a second distance vertically from the semiconductor barrier layer, and the second step is spaced a third distance vertically from the semiconductor barrier layer. The second distance is greater than the first distance, and the third distance is greater than the second distance.

[0021] A high electron mobility transistor device according to some embodiments includes a channel layer, a semiconductor barrier layer on the channel layer, a surface dielectric layer on the semiconductor barrier layer, and a gate on the surface dielectric layer. The surface dielectric layer includes an aperture therein that is laterally spaced apart from the gate.

[0022] The device further includes: a source contact and a drain contact on the semiconductor barrier layer, wherein the gate is between the source contact and the drain contact; and an interlayer dielectric layer on the surface dielectric layer, wherein the interlayer dielectric layer extends over the gate and into the aperture in the surface dielectric layer.

[0023] The device further includes a field plate on the interlayer dielectric layer between the gate contact and the drain contact, wherein the field plate is spaced apart from the gate in a laterally direction, a recessed portion of the field plate is above the aperture in the surface dielectric layer, and the field plate includes a first step adjacent to the recessed portion of the field plate on a side of the field plate opposite to the gate, and a second step adjacent to the first step.

[0024] The recessed portion of the field plate is vertically spaced apart from the semiconductor barrier layer by a first distance, the first step is vertically spaced apart from the semiconductor barrier layer by a second distance, and the second step is vertically spaced apart from the semiconductor barrier layer by a third distance. The second distance is greater than the first distance, and the third distance is greater than the second distance. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIG. 1 is a cross-sectional view of a conventional transistor device including a field plate.

[0026] Figure 2A , Figure 2B and Figure 2C is a cross-sectional view of a transistor device including a field plate according to some embodiments.

[0027] Figure 3A and Figure 3B is a cross-sectional view of a transistor device including a field plate according to a further embodiment.

[0028] Figure 4A is a graph of simulated off-state leakage current for a device according to some embodiments.

[0029] Figure 4B is a line graph of simulated drain-source capacitance Cds for a device according to some embodiments.

[0030] FIG. 5A to FIG. 5J is a cross-sectional view illustrating operations for fabricating a transistor device including a field plate, according to some embodiments.

[0031] Figure 6 is a block diagram illustrating operations of forming a transistor device in accordance with some embodiments.

[0032] 7A to 7C is a schematic block diagram of a multi-amplifier circuit in which an RF transistor amplifier incorporating transistor devices according to embodiments may be used. DETAILED DESCRIPTION

[0033] Embodiments of the inventive concept will now be described with respect to the accompanying drawings. Some embodiments described herein provide a transistor device comprising a field plate that is self-aligned with a gate, and in some embodiments the field plate is spaced apart from the gate in the lateral direction so that the field plate does not overlap with the gate in the vertical direction. In some embodiments, the field plate is recessed toward the barrier layer in the recessed region. In still further embodiments, the field plate can be connected to a source outside the active region of the device by means of a connection that does not cross the gate of the device.

[0034] It is also understood that although the ordinal terms first, second, third, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element.

[0035] Further, relative terms, such as "lower" or "bottom" and "upper" or "top", may be used herein to describe the relationship of one element to another element as illustrated in the accompanying drawings. It is understood that, in addition to the orientation depicted in the accompanying drawings, the relative terms are also intended to cover different orientations of the device. For example, if the device in one of the accompanying drawings is turned over, then the features described as being on the "lower" side of the element will be oriented on the "upper" side of the element. Therefore, depending on the specific orientation of the device, the exemplary term "lower" can describe both the lower orientation and the upper orientation. Similarly, if the device in one of the accompanying drawings is turned over, then the elements described as being "below" or "below" other elements will be oriented above those other elements. Therefore, the exemplary terms "below" or "below" can describe both the above and below orientations.

[0036] The terms used in the description disclosed herein are only for the purpose of describing specific embodiments, and are not intended to limit the present disclosure. As used in the description of the present disclosure and the appended claims, the singular forms of "one" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. It is also understood that the term "and / or" used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "including" and "having" specify the existence of the declared steps, operations, features, elements and / or components when used in this specification, but do not exclude the existence or addition of one or more other steps, operations, features, elements, components and / or their groups.

[0037] Embodiments of the present disclosure are described herein with reference to cross-sectional views, which are schematic views of idealized embodiments of the present disclosure. As such, variations in the shapes of the views are to be expected, for example as a result of manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be interpreted as being limited to the specific shapes of the zones illustrated herein, but rather to include deviations in shapes, for example, resulting from manufacturing. The zones illustrated in the accompanying drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the zones of the device, and are not intended to limit the scope of the present disclosure unless otherwise expressly stated. Further, for illustrative reasons, lines that appear to be straight, horizontal, or vertical in the following drawings will often be inclined, curved, non-horizontal, or non-vertical. Further, the thickness of the elements are intended to be schematic in nature at the same time.

[0038] Unless otherwise defined, all terms used in the disclosed embodiments of the present disclosure, including technical and scientific terms, have the same meaning as commonly understood by ordinary technicians in the relevant art, and are not necessarily limited to specific definitions known at the time of the present disclosure. Therefore, these terms may include equivalent terms created after such time. It is further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art.

[0039] Reference Figure 2A , illustrates a transistor device according to some embodiments. In particular, Figure 2A A high electron mobility transistor device 100A is illustrated as being formed on a substrate 112 . A channel layer 116 is formed on the substrate 112 , and a barrier layer 118 is on the channel layer 116 .

[0040] A source contact 122 and a drain contact 124 are formed on the channel layer 116. A gate 126 is formed on the barrier layer 118 between the source contact 122 and the drain contact 124. Figure 2A , gate 26 may have a mushroom or T-top configuration, wherein gate 126 contacts barrier layer 118 in a relatively narrow contact region of a recessed contact portion 127 of gate 126 that extends through surface dielectric layer 125 within a gate aperture 162 extending through surface dielectric layer 125. Gate aperture 162 may have a width of about 0.09 microns to about 0.4 microns.

[0041] The surface dielectric layer 125 also includes a field plate aperture 164 that extends through the surface dielectric layer 125 to expose the barrier layer 118 .

[0042] In some embodiments, the substrate 112 includes silicon carbide, the channel layer 116 includes GaN, and the barrier layer includes AlGaN. However, it will be appreciated that other materials or combinations of materials may be used. In addition, the channel layer 116 and / or the barrier layer 118 may include, for example, AlGaN. x Ga 1-x N, where 0≤x≤1. It will be further appreciated that although a HEMT device is illustrated, the device 100A may be another type of transistor device, such as a metal semiconductor field effect transistor (MESFET), a junction field effect transistor (JFET), a metal oxide semiconductor field effect transistor (MOSFET), etc.

[0043] The field plate 140 is laterally spaced apart from the gate 126 by the first interlayer dielectric layer 121 and is Figure 2A1 , which may suffer from poor step coverage, leading to cracks in the field plate metallization. However, it will be appreciated that in some embodiments, the field plate 140 may overlap the gate 126 in the lateral dimension. The field plate 140 may be outside the active region of the device (and within the active region of the device). Figure 2A ) is electrically connected to the source contact 122.

[0044] Similar to the gate 126, the field plate 140 may have a mushroom-shaped or T-shaped top configuration that is partially recessed, having a central recessed portion 144 and one or more wing portions extending laterally from the recessed portion 144. The central recessed portion 144 is above the field plate aperture 164 and is vertically spaced apart from the barrier layer 118 by a distance d1 in a region above the field plate aperture 164, the distance d1 being equal to the thickness of the first interlayer dielectric layer 121.

[0045] exist Figure 2A In the embodiment shown in FIG. 1 , the field plate 140 includes a source wing portion 146 extending laterally toward the source contact 122 and a drain wing portion 148 extending laterally toward the drain contact 124. The central recessed portion 144 of the field plate 140 may be spaced apart from the barrier layer 118 by a distance d1 of about 0.1 micrometers to about 0.3 micrometers and may have a width L3 of about 0.3 micrometers to about 0.6 micrometers.

[0046] The drain wing portion 148 of the field plate 140 has a multi-step structure including a first step portion 148A adjacent to the central recessed portion 144 .

[0047] The central recessed portion 144 of the field plate 140 is generally vertically spaced apart from the barrier layer 118 by the surface dielectric layer 125. The first stepped portion 148A of the field plate 140 is spaced apart from the barrier layer 118 by the surface dielectric layer 125 and the first interlayer dielectric layer 121. The source side wing portion 146 and the second stepped portion 148B of the field plate 140 are spaced apart from the barrier layer 118 by the surface dielectric layer 125, the first interlayer dielectric layer 121, and the second interlayer dielectric layer 123.

[0048] In some embodiments, the first stepped portion 148A is spaced apart from the barrier layer 118 by a distance d2, and the second stepped portion 148B adjacent to the first stepped portion 148A is spaced apart from the barrier layer 118 by a distance d3 greater than d2. The distance d2 may be about 0.15 micrometers to about 0.4 micrometers. The distances d3 and d4 may be about 0.25 micrometers to about 0.5 micrometers.

[0049] The first stepped portion 148A has a width L4A of about 0.3 micrometers to about 0.6 micrometers, and the second stepped portion 148B has a width L4B of about 0.3 micrometers to about 0.6 micrometers. The total width L4 of the drain wing 148 is about 0.6 micrometers to about 1.2 micrometers.

[0050] exist Figure 2A In the embodiment illustrated in FIG. 8 , the distance d4 between the source wing portion 146 of the field plate 140 and the barrier layer 118 corresponds to the total thickness of the first interlayer dielectric layer 121 , the second interlayer dielectric layer 123 , and the surface dielectric layer 125 .

[0051] Field plate 140 has an overall lateral width L1. Source flank portion 146 of field plate 140 has width L2, recessed portion 144 of field plate 140 has width L3, and drain flank portion 148 of field plate 140 has width L4. Field plate 140 is laterally spaced a distance L5 from gate 126. As will be discussed below, adjusting distances d1 to d4 and widths L1 to L5 provides multiple degrees of freedom for modulating the gate-source capacitance and gate-drain capacitance of the device.

[0052] Passivation layer 132 is formed on first interlayer dielectric layer 121, second interlayer dielectric layer 123, and field plate 140, and field dielectric layer 134 is formed on passivation layer 132. Passivation layer 132 may fill a gap between field plate 140 and gate 126 not filled by first interlayer dielectric layer 121.

[0053] The surface dielectric layer 125, the first interlayer dielectric layer 121, the second interlayer dielectric layer 123, the passivation layer 132, and the field dielectric layer 134 may include one or more layers of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, or other atomic layer deposition films, or a multilayer insulator structure, such as an oxide-nitride-oxide layer. In a specific embodiment, the surface dielectric layer 125, the first interlayer dielectric layer 121, and the second interlayer dielectric layer 123 include silicon nitride, the passivation layer 132 includes silicon oxynitride, and the field dielectric layer 134 includes silicon nitride.

[0054] Figure 2B A high electron mobility transistor device 100B according to a further embodiment is illustrated. The device 100B is similar to the device 100B except that the second interlayer dielectric layer 123 is omitted from the source side of the structure between the field plate 140 and the source contact 122. Figure 2A 1 , the distance d4 between the source wing 146 and the barrier layer 118 is limited only by the thickness of the surface dielectric layer 125 and the first interlayer dielectric layer 121. Therefore, the distance d4 in the device 100B may be about 0.15 microns to about 0.4 microns.

[0055] Figure 2C A high electron mobility transistor device 100C according to a further embodiment is illustrated. The device 100C is similar to the device 100C except that a third interlayer dielectric layer 147 is provided on the drain side of the structure on the second interlayer dielectric layer 123 between the field plate 140 and the drain contact 124. Figure 2A 14A and 14B, respectively, whereby the field plate has a third stepped portion 148C adjacent to the second stepped portion 148B. The third stepped portion 148A is spaced a distance d5 from the barrier layer 118, the distance d5 being greater than d3. The third stepped portion 148C is spaced from the barrier layer 118 by the combined thickness of the surface dielectric layer 125, the first interlayer dielectric layer 121, the second interlayer dielectric layer 123, and the third interlayer dielectric layer 147. It will be appreciated that the field plate 140 may be provided with more than three stepped portions by providing additional interlayer dielectric layers on the drain side of the structure.

[0056] Figure 3A A HEMT transistor device structure 200A according to a further embodiment is illustrated. The device 200 is similar to the HEMT transistor device 200A except that the device 200 does not include the source wing portion 146. Figure 2A 1 , where like numbers refer to like elements. Thus, the distance between the recessed portion 144 of the field plate 140 and the gate 126 defines the distance L5 between the field plate 140 and the gate 126, and the width L2 of the source wing 146 is zero.

[0057] In some embodiments, the distance d1 between the recessed portion 144 of the field plate 140 and the barrier layer 118 can be from about 60 nm to about 300 nm, and in some embodiments between about 100 nm and 200 nm. As described herein, recessing a portion of the field plate 140 can reduce the gate-drain capacitance Cgd, which can increase the efficiency, linearity, gain, and / or bandwidth of an amplifier made using the device. In addition, by forming a field plate aperture 164 in the surface dielectric layer 125 that defines the location of the recessed portion 144 of the field plate 140 using an etching process, precise control of the positioning of the recessed portion 144 can be obtained, which can improve the processing repeatability and manufacturability of the device while also obtaining more precise control over the electrical properties of the device.

[0058] The total width of the field plate 140 ( Figure 2A and Figure 3A L1) in can be from about 0.6 microns to about 1.5 microns.

[0059] Figure 3BA high electron mobility transistor device 200B according to a further embodiment is illustrated. The device 200B is similar to the device 200B except that a third interlayer dielectric layer 147 is provided on the drain side of the structure on the second interlayer dielectric layer 123 between the field plate 140 and the drain contact 124. Figure 3A The device 200A illustrated in FIG. 1A and FIG. 2B , whereby the field plate has a third stepped portion 148C. The third stepped portion 148C is spaced apart from the barrier layer 118 by the combined thickness of the surface dielectric layer 125 , the first interlayer dielectric layer 121 , the second interlayer dielectric layer 123 , and the third interlayer dielectric layer 147 .

[0060] Separating the field plate 140 from the gate 126 in the lateral direction (e.g., by not overlapping the field plate 140 and the gate 126) can also reduce the gate-drain capacitance Cgd and / or the drain-source capacitance Cds of the device by improving the ability of the field plate 140 to block feedback capacitance from the gate to the drain. That is, the overlap of the field plate 140 and the gate 126 may cause additional parasitic capacitance without any added benefit.

[0061] Providing a recessed portion 144 of the field plate 140 changes the drain-source capacitance Cds and the gate-drain capacitance Cgd of the device. In particular, providing a recessed portion 144 of the field plate 140 can reduce the gate-drain capacitance Cgd of the device for a particular level of drain voltage, possibly at the expense of increasing the drain-source capacitance Cds at low drain voltages.

[0062] It is believed that spacing the field plate 140 laterally from the gate 126 can improve the drain-source capacitance Cds while compromising the effect of the field plate 140 on the gate-drain capacitance Cgd. Therefore, the distance of the gap L5 between the field plate 140 and the gate 126 can be selected (e.g., Figure 2A and Figure 3A 140 and gate 126) to reduce the gate-drain capacitance Cgd without negatively affecting the drain-source capacitance Cds. For example, in some embodiments, the gap L5 between the field plate 140 and the gate 126 can be from 0.2 microns to 0.7 microns. A gap less than 0.2 microns may cause reliability issues, while a gap greater than 0.7 microns may cause an undesirably high gate-drain capacitance Cgd. In some embodiments, the gap L5 can be about 0.2 microns to about 0.4 microns.

[0063] In some embodiments, the gate aperture 162 and the field plate aperture 164 can be formed so that they have chamfered or rounded edges. The chamfered or rounded edges of the gate aperture 162 and the field plate aperture 164 create a shape corresponding to the recessed contact portion 127 of the gate 126 and the recessed portion 144 of the field plate 140, which helps reduce field crowding around the gate 126 and the field plate 140.

[0064] The widths L2, L4 of the source wing 146 and drain wing 148 of the field plate 140 may also affect the gate-drain capacitance Cgd and / or drain-source capacitance Cds of the device. The lengths of the wing portions 146, 148 may involve a tradeoff between the gate-drain capacitance Cgd and the drain-source capacitance Cds. For example, the drain wing portion 148 may reduce the gate-drain capacitance Cgd but increase the drain-source capacitance Cds. In particular, as noted above, the drain wing portion 148 may have a length L4 of about 0.6 to about 1.2 microns. The source wing portion 146 may have a length L2 (between about 0 and 0.3 microns). Figure 2A and Figure 3A ). In particular, the source side wing portion 146 may have a length L2 of zero micrometers.

[0065] Additionally, due to the reduction in parasitic capacitance, the field plate 140 may not have to handle such high current levels, and therefore may be formed with a lesser thickness than would otherwise be required.

[0066] Providing a stepped drain wing 148 can increase the off-state breakdown voltage of the device 100A, 100B, 200 while keeping the gate-drain capacitance Cgd and the gate-source capacitance Cgs low, which can allow higher operating voltages, higher frequency operation, and / or higher power added efficiency than would be obtainable without such features.

[0067] In some embodiments, the device may have an off-state breakdown voltage greater than 230 V at an off-state current of 1E-3 A / mm. In some embodiments, the device may have an off-state breakdown voltage greater than 250 V at an off-state leakage current of 1E-3 A / mm. In some embodiments, the device may have an off-state breakdown voltage greater than 275 V at an off-state leakage current of 1E-3 A / mm.

[0068] Providing stepped drain flanks 148 may slightly increase drain-source capacitance Cds compared to a device without stepped drain flanks 148, which may limit the operation of the device for higher frequency applications (e.g., greater than about 10 GHz). However, the increased Cds may not substantially impair the operation of the device at frequencies below about 10 GHz.

[0069] For example, Figure 4A is a graph of simulated drain current (Id) as a function of drain voltage (Vd) for a device with a multi-step field plate (curve 402) and without a multi-step field plate (curve 404). Figure 4AAs shown in , the breakdown voltage of the device with the multi-step field plate (at a drain current of 1 mA / mm) is about 60 V higher than the breakdown voltage of the device without the multi-step field plate.

[0070] Figure 4B 4 is a graph of simulated drain-source capacitance (Cds) as a function of drain-source voltage (Vds) for a device with a multi-step field plate (curve 412) and without a multi-step field plate (curve 414). Figure 4B As shown in FIG. 1 , for Vds less than about 130 V, the Cds of the device with the multi-step field plate is slightly higher than the Cds of the device without the multi-step field plate. As noted above, while this may limit the performance of the device at higher frequency applications, the increased Cds may not substantially impair the operation of the device at frequencies below about 10 GHz.

[0071] FIG. 5A to FIG. 5H is a cross-sectional view illustrating operations for fabricating a transistor device including a field plate, according to some embodiments.

[0072] Reference Figure 5A A substrate 112 is provided, and a channel layer 116 and a barrier layer 118 are formed on the substrate 112. A preliminary surface dielectric layer 125' is formed on the barrier layer 118. A photoresist layer 52 is formed on the preliminary surface dielectric layer 125' and is patterned to form two openings 54, 56 therein.

[0073] Reference Figure 5B The preliminary surface dielectric layer 125' is selectively etched through the two openings 54, 56, such as using reactive ion etching or inductively coupled plasma, to form two corresponding openings 154, 156 therein.

[0074] Reference Figure 5C , a sacrificial dielectric layer 165 is blanket deposited on the preliminary surface dielectric layer 125' to fill the openings 154, 156. The sacrificial dielectric layer 165 may be formed of the same material as the preliminary surface dielectric layer 125'. For example, both the sacrificial dielectric layer 165 and the preliminary surface dielectric layer 125' may be formed of silicon nitride.

[0075] Reference Figure 5D, the sacrificial dielectric layer 165 is anisotropically etched, for example, using reactive ion etching or inductively coupled plasma 167, to remove portions of the sacrificial dielectric layer 165 except for side portions 166 on the inner surface of the opening 154 of the preliminary surface dielectric layer 125′ and side portions 168 on the inner surface of the opening 156 of the preliminary surface dielectric layer 125′ to form a gate aperture 162 and a field plate aperture 164 having rounded or chamfered edges, as in Figure 5E The preliminary surface dielectric layer 125' together with the side portions 166, 168 form the surface dielectric layer 125 on the barrier layer 118. In the presence of the side portions 166, the width of the gate aperture 162 may be about 250 nm.

[0076] Reference Fig. 5F , a metal such as gold is deposited and patterned to form a mushroom-shaped or T-shaped top gate 126 on the surface dielectric layer 125. The recessed contact portion of the gate 126 extends through the gate aperture 162 to contact the barrier layer 118. Then, the first interlayer dielectric layer 121 is blanket deposited on the surface dielectric layer 125 and the gate 126. The first interlayer dielectric layer 121 extends through the field plate aperture 164 to contact the barrier layer 118.

[0077] Reference Figure 5G , then a second interlayer dielectric layer is blanket deposited on the first interlayer dielectric layer 121, and is masked and anisotropically etched, for example, via timed etching, to form a second interlayer dielectric layer 123 on a portion of the drain region of the structure. In some embodiments, the first interlayer dielectric layer 121 and the second interlayer dielectric layer 123 may be formed of different materials, so that the first interlayer dielectric layer 121 may act as an etch stop layer for etching the second interlayer dielectric layer 123. As noted above, in some embodiments, the second interlayer dielectric layer 123 may be omitted from the source side of the structure.

[0078] Then, a metal such as gold is deposited on the first interlayer dielectric layer 121 above the field plate aperture 164 and patterned to form the field plate 140. The field plate extends at least partially onto the second interlayer dielectric layer 123 to form a multi-step profile on the drain side of the field plate 140.

[0079] The field plate 140 is separated from the barrier layer 118 within the field plate aperture 164 by a distance d1 corresponding to the thickness of the first interlayer dielectric layer 121. In the drain wing portion 148 of the field plate 140, the field plate 140 may be spaced apart from the barrier layer 118 by a distance d2 corresponding to the sum of the thicknesses of the first interlayer dielectric layer 121 and the surface dielectric layer 125 in the first stepped region 148A, and a distance d3 corresponding to the sum of the thicknesses of the first interlayer dielectric layer 121, the second interlayer dielectric layer 123, and the surface dielectric layer 125 in the second stepped portion 148B.

[0080] The field plate 140 is laterally spaced apart from the gate 126 by a distance L6, which is approximately equal to the thickness of the first interlayer dielectric layer 121. Therefore, the field plate 140 is self-aligned with the gate 126 by the distance L6.

[0081] Reference Figure 5H A passivation layer 132 such as a SiON layer is formed on the field plate 140 and the first interlayer dielectric layer 121. Finally, a field dielectric layer 134 such as silicon nitride is formed on the passivation layer 132.

[0082] Reference Fig.5I In some embodiments, after forming the second interlayer dielectric layer 123, a third dielectric layer may be blanket deposited on the first interlayer dielectric layer 121 and the second interlayer dielectric layer 123, and masked and anisotropically etched, for example, via timed etching, to form a third interlayer dielectric layer 127 on a portion of the drain region of the structure. In some embodiments, the third interlayer dielectric layer 147 may be omitted from the source side of the structure.

[0083] Then, a metal such as gold is deposited on the first interlayer dielectric layer 121 above the field plate aperture 164 and patterned to form the field plate 140. The field plate extends at least partially onto the second interlayer dielectric layer 123 and the third interlayer dielectric layer 147 to form a multi-step profile on the drain side of the field plate 140. It will be appreciated that similar operations may be performed to form field plates having more than three steps.

[0084] Reference Figure 5J A passivation layer 132 such as a SiON layer is formed on the field plate 140 and the first interlayer dielectric layer 121. Finally, a field dielectric layer 134 such as silicon nitride is formed on the passivation layer 132.

[0085] Figure 6 is a block diagram illustrating operations for forming a transistor device according to some embodiments. Figure 6 and FIG. 5A to FIG. 5H, a method of forming a transistor device according to some embodiments includes: forming a surface dielectric layer 125 on a semiconductor layer (block 602); forming an aperture 164 in the surface dielectric layer (block 604); forming a gate 126 on the surface dielectric layer 125, wherein the gate is laterally spaced apart from the aperture 164 (block 606); forming a first interlayer dielectric layer 121 on the gate and the surface dielectric layer 125, the surface dielectric layer extending into the aperture 164 (block 608); and forming a multi-step field plate 140 on the first interlayer dielectric layer 121 above the aperture 164 (block 610). The multi-step field plate 140 is laterally spaced apart from the gate. The recessed portion 144 of the multi-step field plate 140 is above the aperture 164 in the surface dielectric layer, and the multi-step field plate 1140 includes a first stepped portion 148A adjacent to the recessed portion of the multi-step field plate 140 on a side of the multi-step field plate opposite to the gate 126, and a second stepped portion 148B adjacent to the first stepped portion 148A.

[0086] The recessed portion 144 of the multi-step field plate is vertically spaced apart from the barrier layer 118 by a first distance, the first step portion 148A is vertically spaced apart from the barrier layer 118 by a second distance, and the second step portion 148B is vertically spaced apart from the barrier layer 118 by a third distance. The second distance is greater than the first distance, and the third distance is greater than the second distance.

[0087] The method may further include forming a second aperture 162 in the surface dielectric layer, wherein the first aperture 164 and the second aperture 162 are laterally spaced apart from each other. A gate 126 is formed on the second aperture 162, and the gate 126 includes a recessed contact portion 127 extending through the second aperture 162. The recessed contact portion 127 of the gate may contact the barrier layer 118.

[0088] The method may further include forming a source contact 122 and a drain contact 124 on the barrier layer 118, wherein the gate 126 is between the source contact 122 and the drain contact 124. The field plate 140 may include a recessed portion 144 above the aperture 164 and a drain wing portion 148 extending on the barrier layer 118 toward the drain contact 124. In some embodiments, the field plate 140 includes a source wing portion 146 extending on the barrier layer 118 toward the source contact 122.

[0089] The recessed portion 144 of the field plate 140 may be vertically spaced apart from the barrier layer 118 by the thickness of the first interlayer dielectric layer 121 .

[0090] The drain side wing portion 148 of the field plate may include a first stepped portion 148A and a second stepped portion 148B, wherein the first stepped portion 148A is vertically separated from the barrier layer 118 by the combined thickness of the first interlayer dielectric layer 121 and the surface dielectric layer 125, and the second stepped portion 148B is vertically separated from the barrier layer 118 by the combined thickness of the first interlayer dielectric layer 121, the second interlayer dielectric layer 123 and the surface dielectric layer 125.

[0091] Forming the first aperture and the second aperture may include: forming a preliminary surface dielectric layer 125' on the barrier layer 118; selectively etching the preliminary surface dielectric layer 125' to form a first opening 156 and a second opening 154 in the preliminary surface dielectric layer 125'; and depositing a sacrificial dielectric layer 165 on the barrier layer 118 and the preliminary surface dielectric layer 125', the sacrificial dielectric layer 165 filling the first opening 156 and the second opening 154. The sacrificial dielectric layer 165 may be anisotropically etched to expose portions of the barrier layer 118 in the first opening 156 and the second opening 154, leaving side portions of the sacrificial dielectric layer 165 on the inner sidewalls of the openings 156, 154.

[0092] Transistor devices as described herein can be used in amplifiers that operate in a wide variety of different frequency bands. In some embodiments, an RF transistor amplifier incorporating a transistor device as described herein can be configured to operate at a frequency greater than 1 GHz. In other embodiments, the RF transistor amplifier can be configured to operate at a frequency greater than 2.5 GHz. In still other embodiments, the RF transistor amplifier can be configured to operate at a frequency greater than 3.1 GHz. In additional embodiments, the RF transistor amplifier can be configured to operate at a frequency greater than 5 GHz. In some embodiments, the RF transistor amplifier can be configured to operate in at least one of the 2.5-2.7 GHz, 3.4-4.2 GHz, 5.1-5.8 GHz, 12-18 GHz, 18-27 GHz, 27-40 GHz, or 40-75 GHz frequency bands or sub-portions thereof.

[0093] Although embodiments of the inventive concepts have been discussed above with respect to HEMT devices, it will be understood that the inventive concepts described herein may be applied to other types of semiconductor devices, such as MOSFETs, DMOS transistors, and / or laterally diffused MOS (LDMOS) transistors.

[0094] RF transistor amplifiers incorporating the transistor devices described herein may be used in a stand-alone RF transistor amplifier and / or in a plurality of RF transistor amplifiers. 7A to 7CExamples of how an RF transistor amplifier according to some embodiments may be used in an application including multiple amplifiers are discussed.

[0095] Reference Fig. 7A , schematically illustrates an RF transistor amplifier 1000A including a preamplifier 1010 and a main amplifier 1030 electrically connected in series. Fig. 7A As shown in FIG. 1 , the RF transistor amplifier 1000A includes an RF input 1001, a preamplifier 1010, an interstage impedance matching network 1020, a main amplifier 1030, and an RF output 1002. The interstage impedance matching network 1020 may include, for example, inductors and / or capacitors arranged in any suitable configuration to form a circuit that improves impedance matching between the output of the preamplifier 1010 and the input of the main amplifier 1030. Although Fig. 7A Although not shown in the figure, the RF transistor amplifier 1000A may further include an input matching network inserted between the RF input 1001 and the preamplifier 1010, and / or an output matching network inserted between the main amplifier 1030 and the RF output 1002. The RF transistor amplifier according to the embodiment may be used to implement one or both of the preamplifier 1010 and the main amplifier 1030.

[0096] Reference Figure 7B , schematically illustrates an RF transistor amplifier 1000B, which includes an RF input 1001, a pair of preamplifiers 1010-1, 1010-2, a pair of interstage impedance matching networks 1020-1, 1020-2, a pair of main amplifiers 1030-1, 1030-2 and an RF output 1002. A splitter 1003 and a combiner 1004 are also provided. The preamplifier 1010-1 and the main amplifier 1030-1 (which are electrically connected in series) are arranged electrically in parallel with the preamplifier 1010-2 and the main amplifier 1030-2 (which are electrically connected in series). Like the RF transistor amplifier 1000A of FIG. 9A , the RF transistor amplifier 1000B may further include an input matching network inserted between the RF input 1001 and the preamplifiers 1010 - 1 , 1010 - 2 , and / or an output matching network inserted between the main amplifiers 1030 - 1 , 1030 - 2 and the RF output 1002 .

[0097] As in Figure 7CAs shown in , the RF transistor amplifier according to some embodiments can also be used to implement a Doherty amplifier. As is known in the art, the Doherty amplifier circuit includes a first and a second (or more) power combination amplifier. The first amplifier is called a "main" amplifier or a "carrier" amplifier, and the second amplifier is called a "peaking" amplifier. The two amplifiers can be biased differently. For example, in a common Doherty amplifier implementation, the main amplifier may include a class AB or class B amplifier, and the peaking amplifier may be a class C amplifier. When operating at a power level backed off from saturation, the Doherty amplifier can operate more efficiently than a balanced amplifier. The RF signal input to the Doherty amplifier is separated (e.g., using an orthogonal coupler), and the outputs of the two amplifiers are combined. The main amplifier is configured to be turned on first (i.e., at a lower input power level), and therefore only the main amplifier will operate at a lower power level. As the input power level increases toward saturation, the peaking amplifier is turned on, and the input RF signal is divided between the main amplifier and the peaking amplifier.

[0098] As in Figure 7C As shown in FIG. 1 , the Doherty RF transistor amplifier 1000C includes an RF input 1001, an input splitter 1003, a main amplifier 1040, a peaking amplifier 1050, an output combiner 1004, and an RF output 1002. The Doherty RF transistor amplifier 1000C includes a 90° transformer 1007 at the input of the peaking amplifier 1050 and a 90° transformer 1005 at the input of the main amplifier 1040, and may optionally include an input matching network and / or an output matching network (not shown). According to an embodiment, the main amplifier 1040 and / or the peaking amplifier 1050 may be implemented using any of the RF transistor amplifiers described above.

[0099] An RF transistor amplifier according to an embodiment may be formed as a discrete device, or may be formed as part of a monolithic microwave integrated circuit (MMIC). MMIC refers to an integrated circuit operating on radio and / or microwave frequency signals, in which all circuits for a particular function are integrated into a single semiconductor chip. An example MMIC device is a transistor amplifier including associated matching circuits, feed networks, and the like, all implemented on a common substrate. An MMIC transistor amplifier typically includes a plurality of unit cell HEMT transistors connected in parallel.

[0100] Many variations of the features of the above embodiments are possible. Transistor structures having features that may be used in embodiments of the present invention are disclosed in the following commonly assigned disclosures, the contents of each of which are fully incorporated herein by reference in their entirety: U.S. Patent No. 6,849,882 to Chavarkar et al. and entitled “Group-III Nitride Based High Electron Mobility Transistor (HEMT) With Barrier / Spacer Layer”; U.S. Patent No. 7,230,284 to Parikh et al. and entitled “Insulating Gate AlGaN / GaN HEMT”; U.S. Patent No. 7,501,669 to Parikh et al. and entitled “Wide Bandgap Transistor Devices With Field Plates”; U.S. Patent No. 7126,426 to Mishra et al. and entitled “Cascode Amplifier Structures Including Wide Bandgap Field Effect Transistor With Field Plates”; U.S. Patent No. 7,126,426 to Wu et al. and entitled “Wide Bandgap HEMTs With Source Connected No. 7,550,783, entitled “Wide Bandgap Transistors With Multiple Field Plates” to Wu et al.; U.S. Patent No. 7,573,078, entitled “Wide Bandgap Transistors With Multiple Field Plates” to Wu et al.; U.S. Patent Publication No. 2005 / 0253167, entitled “Wide Bandgap Field Effect Transistors With Source Connected Field Plates” to Wu et al.; U.S. Patent Publication No. 2006 / 0202272, entitled “Wide Bandgap Transistors With Gate-Source Field Plates” to Wu et al.U.S. Patent Publication No. 2008 / 0128752, entitled “GaN Based HEMTs With Buried Field Plates” by Wu et al.; U.S. Patent Publication No. 2010 / 0276698, entitled “Gate Electrodes For Millimeter-Wave Operation and Methods of Fabrication” by Moore et al.; U.S. Patent Publication No. 2012 / 0049973, entitled “High Power Gallium Nitride Field Effect Transistor Switches” by Smith, Jr. et al.; U.S. Patent Publication No. 2012 / 0194276, entitled “Low Noise Amplifiers Including Group III Nitride Based High Electron Mobility Transistors” by Fisher; and U.S. Patent No. 9,847,411, entitled “Recessed fieldplate transistor structures” by Sriram et al.

[0101] Although embodiments of the inventive concept have been described in considerable detail with reference to specific configurations of the inventive concept, other versions are possible. The field plate and gate may also have many different shapes and may be connected to the source contact in many different ways. Therefore, the spirit and scope of the present invention should not be limited to the specific embodiments described above.

Claims

1. A transistor device, comprising: Semiconductor barrier layer; a surface dielectric layer on the semiconductor barrier layer; a gate on the surface dielectric layer, wherein the surface dielectric layer includes an aperture therein that is laterally spaced from the gate; an interlayer dielectric layer on the surface dielectric layer, wherein the interlayer dielectric layer extends over the gate and into the aperture in the surface dielectric layer; as well as a field plate on the interlayer dielectric layer, wherein the field plate is laterally spaced apart from the gate, wherein a recessed portion of the field plate is above the aperture in the surface dielectric layer, wherein the field plate includes a first step adjacent to the recessed portion of the field plate on a side of the field plate opposite the gate, a second step adjacent to the first step; The recessed portion of the field plate is vertically spaced apart from the semiconductor barrier layer by a first distance, the first step is vertically spaced apart from the semiconductor barrier layer by a second distance, and the second step is vertically spaced apart from the semiconductor barrier layer by a third distance, wherein the second distance is greater than the first distance, and the third distance is greater than the second distance. 2 . The transistor device according to claim 1 , wherein the first distance is equal to a thickness of the interlayer dielectric layer. 3 . The transistor device of claim 2 , wherein the second distance is equal to the sum of the thickness of the interlayer dielectric layer and the thickness of the surface dielectric layer.

4. The transistor device of claim 3, wherein the interlayer dielectric layer comprises a first interlayer dielectric layer, wherein the third distance is equal to the sum of the thickness of the first interlayer dielectric layer plus the thickness of the surface dielectric layer plus the thickness of a second interlayer dielectric layer on the first interlayer dielectric layer.

5. The transistor device of claim 1, wherein the aperture in the surface dielectric layer extends completely through the surface dielectric layer to expose the semiconductor barrier layer. The transistor device of claim 1 , wherein the gate extends through the surface dielectric layer to contact the semiconductor barrier layer.

7. The transistor device of claim 2, further comprising a source contact and a drain contact on the semiconductor barrier layer, wherein the gate is between the source contact and the drain contact, and wherein the field plate comprises a source wing portion extending on the semiconductor barrier layer toward the source contact.

8. The transistor device of claim 1, wherein the first distance is approximately 0.1 to 0.3 microns.

9. The transistor device of claim 1, wherein the second distance is approximately 0.15 to 0.4 microns.

10. The transistor device of claim 1, wherein the third distance is approximately 0.25 to 0.5 microns.

11. The transistor device of claim 1, wherein the recessed portion of the field plate has a width of approximately 0.3 to 0.6 microns. 12 . The transistor device of claim 1 , wherein the first step has a width of approximately 0.3 to 0.6 microns.

13. The transistor device of claim 1, wherein the second step has a width of approximately 0.3 to 0.6 micrometers.

14. The transistor device of claim 1, wherein the interlayer dielectric layer has a vertical thickness, and wherein the field plate is laterally spaced apart from the gate by a distance approximately equal to the vertical thickness of the interlayer dielectric layer. 15 . The transistor device of claim 1 , further comprising a third step adjacent to the second step, wherein the third step is vertically spaced apart from the semiconductor by a fourth distance, the fourth distance being greater than the third distance.

16. A method of forming a transistor device, comprising: forming a surface dielectric layer on the semiconductor barrier layer; forming an aperture in the surface dielectric layer to expose the semiconductor barrier layer; forming a gate on the surface dielectric layer and laterally spaced from the aperture; forming an interlayer dielectric layer over the surface dielectric layer and the gate, wherein the interlayer dielectric layer extends over the gate and into the aperture in the surface dielectric layer; as well as forming a multi-step field plate on the interlayer dielectric layer, wherein the multi-step field plate is laterally spaced apart from the gate, wherein a recessed portion of the multi-step field plate is above the aperture in the surface dielectric layer, wherein the multi-step field plate includes a first step adjacent to the recessed portion of the multi-step field plate on a side of the multi-step field plate opposite the gate, a second step adjacent to the first step; The recessed portion of the multi-step field plate is vertically spaced apart from the semiconductor barrier layer by a first distance, the first step is vertically spaced apart from the semiconductor barrier layer by a second distance, and the second step is vertically spaced apart from the semiconductor barrier layer by a third distance, wherein the second distance is greater than the first distance, and the third distance is greater than the second distance. The method of claim 16 , wherein the first distance is equal to a thickness of the interlayer dielectric layer.

18. The method of claim 17, wherein the second distance is equal to the sum of the thickness of the interlayer dielectric layer and the thickness of the surface dielectric layer.

19. The method of claim 18, wherein the interlayer dielectric layer comprises a first interlayer dielectric layer, wherein the third distance is equal to the sum of the thickness of the first interlayer dielectric layer plus the thickness of the surface dielectric layer plus the thickness of a second interlayer dielectric layer on the first interlayer dielectric layer.

20. The method of claim 16, wherein the aperture in the surface dielectric layer extends completely through the surface dielectric layer to expose the semiconductor barrier layer. 21 . The method of claim 16 , wherein the multi-step field plate further comprises a third step adjacent to the second step, wherein the third step is vertically spaced apart from the semiconductor by a fourth distance, the fourth distance being greater than the third distance.

22. A high electron mobility transistor device, comprising: Channel layer; a semiconductor barrier layer on the channel layer; a surface dielectric layer on the semiconductor barrier layer; a gate on the surface dielectric layer, wherein the surface dielectric layer includes an aperture therein that is laterally spaced from the gate; a source contact and a drain contact on the semiconductor barrier layer, wherein the gate is between the source contact and the drain contact; an interlayer dielectric layer on the surface dielectric layer, wherein the interlayer dielectric layer extends over the gate and into the aperture in the surface dielectric layer; as well as a field plate on the interlayer dielectric layer between the gate contact and the drain contact, wherein the field plate is laterally spaced apart from the gate, wherein a recessed portion of the field plate is above the aperture in the surface dielectric layer, wherein the field plate includes a first step adjacent to the recessed portion of the field plate on a side of the field plate opposite the gate, a second step adjacent to the first step; The recessed portion of the field plate is vertically spaced apart from the semiconductor barrier layer by a first distance, the first step is vertically spaced apart from the semiconductor barrier layer by a second distance, and the second step is vertically spaced apart from the semiconductor barrier layer by a third distance, wherein the second distance is greater than the first distance, and the third distance is greater than the second distance.

23. A high electron mobility transistor device, comprising: Channel layer; a barrier layer on the channel layer; a source contact and a drain contact on the barrier layer; and a gate contact on the barrier layer between the source contact and the drain contact; The high electron mobility transistor has an off-state breakdown voltage greater than 230 V at an off-state current of 1E-3 A / mm.

24. The high electron mobility transistor of claim 23, wherein the high electron mobility transistor has an off-state breakdown voltage greater than 250 V at an off-state leakage current of 1E-3 A / mm.

25. The high electron mobility transistor of claim 23, wherein the high electron mobility transistor has an off-state breakdown voltage greater than 275 V at an off-state leakage current of 1E-3 A / mm.

26. The HEMT of claim 23, wherein the barrier layer comprises aluminum nitride and the channel layer comprises gallium nitride.

27. The high electron mobility transistor according to claim 23, further comprising: a surface dielectric layer on the barrier layer, wherein the surface dielectric layer includes an aperture therein that is laterally spaced from the gate; an interlayer dielectric layer on the surface dielectric layer, wherein the interlayer dielectric layer extends over the gate and into the aperture in the surface dielectric layer; as well as a field plate on the interlayer dielectric layer, wherein the field plate is laterally spaced apart from the gate, wherein a recessed portion of the field plate is above the aperture in the surface dielectric layer, wherein the field plate includes a first step adjacent to the recessed portion of the field plate on a side of the field plate opposite the gate, a second step adjacent to the first step; The recessed portion of the field plate is vertically spaced apart from the semiconductor barrier layer by a first distance, the first step is vertically spaced apart from the semiconductor barrier layer by a second distance, and the second step is vertically spaced apart from the semiconductor barrier layer by a third distance, wherein the second distance is greater than the first distance, and the third distance is greater than the second distance.

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