Solid-state imaging device

Abstract

A solid-state imaging device includes: a first pixel that is provided on a first surface side, which is a light incident side, of a substrate, and includes a first photoelectric conversion element that converts light into an electric charge; a first transistor disposed on a second surface side of the base body opposite to the first surface and located at a position corresponding to the first pixel, and including a first gate electrode and a pair of main electrodes, one of the pair of main electrodes of the first transistor being electrically connected to the first photoelectric conversion element; a floating diffusion portion provided on the second surface side of the base body and electrically connected to the other main electrode of the first transistor; and a low dielectric constant region provided between the floating diffusion and the first gate electrode facing the floating diffusion, and having a dielectric constant lower than a dielectric constant of a non-facing region.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device. Background Art

[0002] Patent document 1 discloses a solid-state imaging device. The solid-state imaging device includes a photoelectric converter for each of a plurality of pixels arranged regularly. The photoelectric converter generates a charge as a signal according to incident light. The signal is transmitted to a floating diffusion portion through a transfer transistor provided for each pixel. The floating diffusion portion transmits the signal to a pixel circuit, and the pixel circuit processes the signal. The floating diffusion portion is shared by a plurality of pixels arranged adjacent to each other. Citation List Patent Literature

[0003] Patent Document 1: International Publication No. WO2020 / 262643 Summary of the invention

[0004] Incidentally, in the manufacturing process of the solid-state imaging device, for the gate electrode of the transfer transistor of each of the plurality of pixels, specifically, for the contact portion that supplies the control signal to the gate electrode, misalignment of the floating diffusion portion occurs. This misalignment causes a difference in parasitic capacitance generated by the common contact portion and the floating diffusion portion of each pixel. Therefore, in the solid-state imaging device, it is desirable to suppress signal differences and signal delays caused by parasitic capacitance.

[0005] According to the first aspect of the present disclosure, a solid-state imaging device includes: a first pixel, which is arranged on a first surface side of a substrate as a light incident side, and includes a first photoelectric conversion element that converts light into electric charges; a first transistor, which is arranged on a second surface side of the substrate opposite to the first surface and is located at a position corresponding to the first pixel, and includes a first gate electrode and a pair of main electrodes, one of the pair of main electrodes of the first transistor is electrically connected to the first photoelectric conversion element; a floating diffusion portion, which is arranged on the second surface side of the substrate and is electrically connected to the other main electrode of the first transistor; and a low dielectric constant region, which is arranged between the floating diffusion portion and the first gate electrode opposite to the floating diffusion portion, and has a dielectric constant lower than the dielectric constant of the non-opposite region.

[0006] The solid-state imaging device according to the second aspect of the present disclosure further includes a second pixel, a second transistor and the low dielectric constant region in the solid-state imaging device according to the first aspect. The second pixel is arranged on the first surface side of the substrate and is adjacent to the first pixel, and includes a second photoelectric conversion element that converts light into electric charge. The second transistor is arranged on the second surface side of the substrate and is located at a position corresponding to the second pixel, and includes a second gate electrode and a pair of main electrodes, one of the pair of main electrodes of the second transistor is electrically connected to the second photoelectric conversion element, and the other main electrode is electrically connected to the floating diffusion. The low dielectric constant region is arranged between the floating diffusion and the second gate electrode opposite to the floating diffusion.

[0007] In the solid-state imaging device according to the third aspect of the present disclosure, the low dielectric constant region in the solid-state imaging device according to the first aspect or the second aspect includes a gap.

[0008] In a solid-state imaging device according to a fourth aspect of the present disclosure, the low dielectric constant region in the solid-state imaging device according to the first aspect or the second aspect is formed of a low dielectric constant material. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 : is a circuit diagram showing a pixel and a pixel circuit of a solid-state imaging device according to a first embodiment of the present disclosure. Figure 2 yes Figure 1 The longitudinal cross-sectional structure diagram of the pixel shown (along the Figure 3 AA shown as a cross-sectional view). Figure 3 yes Figure 1 The plan structure diagram of the pixel shown. Figure 4 1 is a cross-sectional view for explaining step by step a first step of the method for manufacturing the solid-state imaging device according to the first embodiment. Figure 5 is a cross-sectional view of the second step. Figure 6 is a cross-sectional view of the third step. Figure 7 is a cross-sectional view of the fourth step. Figure 8 is a cross-sectional view of the fifth step. Fig. 9 is a cross-sectional view of the sixth step. Fig.10 is a cross-sectional view of the seventh step. Fig.11 is a cross-sectional view of the eighth step. Fig.12is a cross-sectional view of the ninth step. Fig.13 is a cross-sectional view of the tenth step. Fig.14 This is the cross-sectional view of step 11. Fig.15 is a cross-sectional view of the twelfth step. Fig.16 is a cross-sectional view of the thirteenth step. Fig.17 is a cross-sectional view of the fourteenth step. Fig.18 is a cross-sectional view of the fifteenth step. Fig.19 is a cross-sectional view of the sixteenth step. Fig. 20 is a cross-sectional view of the seventeenth step. Fig.21 is a cross-sectional view of the eighteenth step. Fig. 22 is a cross-sectional view of the nineteenth step. Fig.23 is a cross-sectional view of the twentieth step. Fig.24 is a cross-sectional view of the twenty-first step. Fig.25 is a cross-sectional view of the twenty-second step. Fig.26 is a pixel of a solid-state imaging device according to a second embodiment of the present disclosure and Figure 2 The corresponding longitudinal cross-sectional structure diagram (along Fig. 27 BB shown in cross section). Fig. 27 yes Fig.26 The pixels shown are Figure 3 The corresponding plan structure diagram. Fig.28 is a pixel of a solid-state imaging device according to a third embodiment of the present disclosure and Figure 2 The corresponding longitudinal cross-sectional structure diagram (along Fig.29 Cross-sectional view taken along cutting line CC as shown). Fig.29 yes Fig.28 The pixels shown are Figure 3 The corresponding plan structure diagram. Fig.30 is a pixel of a solid-state imaging device according to a fourth embodiment of the present disclosure and Figure 2 The corresponding longitudinal cross-sectional structure diagram (along Fig.31 Cross-sectional view taken along the cutting line DD shown). Fig.31 yes Fig.30 The pixels shown are Figure 3 The corresponding plan structure diagram. Fig.32 is a pixel of a solid-state imaging device according to a fifth embodiment of the present disclosure and Figure 2 The corresponding longitudinal cross-sectional structure diagram (along Fig.33 Cross-sectional view taken along cutting line EE as shown). Fig.33 yes Fig.32 The pixels shown are Figure 3 The corresponding plan structure diagram. Fig.34 is a pixel of a solid-state imaging device according to a sixth embodiment of the present disclosure and Figure 2 The corresponding longitudinal cross-sectional structure diagram (along Fig.35 Cross-sectional view taken along the cutting line FF shown). Fig.35 yes Fig.34 The pixels shown are Figure 3 The corresponding plan structure diagram. Fig.36 1 is a cross-sectional view for explaining step by step a first step of the method for manufacturing the solid-state imaging device according to the sixth embodiment. Fig.37 is a cross-sectional view of the second step. Fig.38 is a cross-sectional view of the third step. Fig.39 is a cross-sectional view of the fourth step. Fig.40 is a cross-sectional view of the fifth step. Fig.41 is a cross-sectional view of the sixth step. Fig.42 is a cross-sectional view of the seventh step. Fig.43 is a cross-sectional view of the eighth step. Fig.44 is a cross-sectional view of the ninth step. Fig.45 is a cross-sectional view of the tenth step. Fig.46 This is the cross-sectional view of step 11. Fig.47 is a cross-sectional view of the twelfth step. Fig.48 is a cross-sectional view of the thirteenth step. Fig.49 is a cross-sectional view of the fourteenth step. Fig.50 is a cross-sectional view of the fifteenth step. Fig.51 is a cross-sectional view of the sixteenth step. Fig.52 is a cross-sectional view of the seventeenth step. Fig.53 is a cross-sectional view of the eighteenth step. Fig.54 is a cross-sectional view of the nineteenth step. Fig.55 is a cross-sectional view of the twentieth step. Fig.56 is a cross-sectional view of the twenty-first step. Fig.57 is a cross-sectional view of the twenty-second step. Fig.58 is a cross-sectional view of the twenty-third step. Fig.59 is a cross-sectional view of the twenty-fourth step. Fig.60 is a pixel of a solid-state imaging device according to the seventh embodiment of the present disclosure and Figure 2 The corresponding longitudinal cross-sectional structure diagram (along Fig.61 ) a cross-sectional view taken along the cutting line GG as shown. Fig.61 yes Fig.60 The pixels shown are Figure 3 The corresponding plan structure diagram. Fig.62 1 is a cross-sectional view for explaining step by step a first step of the method for manufacturing the solid-state imaging device according to the eighth embodiment. Fig.63 is a cross-sectional view of the second step. Fig.64 is a cross-sectional view of the third step. Fig.65 is a cross-sectional view of the fourth step. Fig.66 is a cross-sectional view for gradually explaining a first step of a method for manufacturing a solid-state imaging device according to a ninth embodiment. Fig.67 is a cross-sectional view of the second step. Fig.68 is a pixel of a solid-state imaging device according to a tenth embodiment of the present disclosure and Figure 3 The corresponding plan structure diagram. Fig.69 is a pixel of the solid-state imaging device according to the eleventh embodiment of the present disclosure. Figure 2 The corresponding longitudinal cross-sectional structure diagram (along Fig.70 sectional view taken along the cutting line HH shown). Fig.70 yes Fig.69The pixels shown are Figure 3 The corresponding plan structure diagram. Fig.71 is a pixel of a solid-state imaging device according to a twelfth embodiment of the present disclosure and Figure 3 The corresponding plan view. Fig.72 is a block diagram showing a schematic configuration example of a vehicle control system according to a first application example of an embodiment of the present disclosure. Fig.73 It is a diagram for assisting in explaining an example of the installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0010] The following will describe the embodiments of the present disclosure in detail with reference to the accompanying drawings. Note that the description will be made in the following order. 1. First embodiment The first embodiment explains an example in which the present technology is applied to a solid-state imaging device. The first embodiment explains in detail the circuit configuration, planar configuration, and longitudinal cross-sectional configuration of pixels and pixel circuits of the solid-state imaging device and a method for manufacturing the solid-state imaging device. 2. Second embodiment The second embodiment is a first example of changing the isolation structure between the gate electrode of the transfer transistor of the pixel and the floating diffusion in the solid-state imaging device according to the first embodiment. 3. Third embodiment The third embodiment is a second example in which the structure of the pixel isolation region that isolates pixels from each other is changed in the solid-state imaging device according to the first embodiment. 4. Fourth embodiment The fourth embodiment is a fourth example that explains the isolation structure in a region other than the isolation structure in the solid-state imaging device according to the first embodiment in addition to the isolation structure between the gate electrode of the transfer transistor of the pixel and the floating diffusion. 5. Fifth embodiment The fifth embodiment is a fifth example of changing the isolation structure between the gate electrode of the transfer transistor of the pixel and the floating diffusion in the solid-state imaging device according to the first embodiment. 6. Sixth embodiment The sixth embodiment is a sixth example in which the structure of the common contact portion of the floating diffusion portion is changed in the solid-state imaging device according to the first embodiment. A method for manufacturing the solid-state imaging device is also described here. 7. Seventh embodiment The seventh embodiment is a seventh example of providing transistors constituting a pixel circuit for pixels in the solid-state image pickup device according to the first embodiment. 8. Eighth embodiment The eighth embodiment is an eighth example of a manufacturing method that changes the isolation structure between the gate electrode of the transfer transistor of a pixel and the floating diffusion in the solid-state imaging device according to the first embodiment. 9. Ninth embodiment The ninth embodiment is a ninth example of a manufacturing method that changes the isolation structure between the gate electrode of the transfer transistor of a pixel and the floating diffusion in the solid-state imaging device according to the first embodiment. 10. Tenth Embodiment The tenth embodiment is a tenth example in which the structure of a pixel isolation region for isolating pixels from each other is changed in the solid-state imaging device according to the first embodiment. 11. Eleventh Embodiment The eleventh embodiment is an eleventh example in which the structure of a pixel isolation region for isolating pixels from each other is changed in the solid-state imaging device according to the first embodiment. 12. Twelfth Embodiment The twelfth embodiment is a twelfth example in which the structure of a unit pixel is changed in the solid-state imaging device according to the first embodiment. 13. Application examples on mobile objects An example in which the present technology is applied to a vehicle control system as an example of a mobile body control system has been described. 14. Other embodiments <1. First embodiment>

[0011] refer to Figures 1 to 25 The solid-state imaging device 1 according to the first embodiment of the present disclosure has been described. Here, for convenience, the arrow X direction appropriately indicated in the figure indicates a plane direction of the solid-state imaging device 1 placed on a plane. The arrow Y direction indicates another plane direction orthogonal to the arrow X direction. In addition, the arrow Z direction indicates an upward direction orthogonal to the arrow X direction and the arrow Y direction. That is, the arrow X direction, the arrow Y direction, and the arrow Z direction are completely consistent with the X-axis direction, the Y-axis direction, and the Z-axis direction of the three-dimensional coordinate system, respectively. It should be noted that these directions are marked to help understand the description and are not intended to limit the directions used in this technology. [Configuration of Solid-State Imaging Device 1] (1) Circuit Configuration of Pixel 10 and Pixel Circuit 20 of Solid-State Imaging Device 1

[0012] Figure 1 A circuit configuration example of the pixel 10 and the pixel circuit 20 constituting the solid-state imaging device 1 is shown.

[0013] One pixel 10 includes a series circuit composed of a photoelectric conversion element (photodiode) 11 and a transistor 12. Here, four pixels 10 constitute one unit pixel.

[0014] The photoelectric conversion element 11 converts light incident from the outside of the solid-state imaging device 1 into electric charges (electric signals).

[0015] The transistor 12 is used as a transfer transistor for transferring the charge converted in the photoelectric conversion element 11 to the pixel circuit 20. The transistor 12 is an insulated gate field effect transistor (IGFET). Specifically, the transistor 12 is an n-channel conductive type IGFET as a first conductive type. That is, the transistor 12 includes a gate electrode and a pair of main electrodes. Here, the transistor 12 is a “first transistor” or a “second transistor” according to the present technology.

[0016] Among a pair of main electrodes of the transistor 12, one main electrode is electrically connected to the photoelectric conversion element 11. The other main electrode is electrically connected to the pixel circuit 20 via the FD 25 interposed therebetween. The gate electrode is connected to a horizontal signal line not shown. A control signal TG is input to the gate electrode from the horizontal signal line. The on-operation and off-operation of the transistor 12 are controlled by the control signal TG.

[0017] Here, the pixel circuit 20 is provided for each unit pixel. In the first embodiment, one pixel circuit 20 is provided for four pixels 10. The pixel circuit 20 performs signal processing on the charge converted from light in the pixel 10. The pixel circuit 20 includes an amplification transistor 21 , a selection transistor 22 , a floating diffusion conversion gain switching transistor (hereinafter simply referred to as “FD conversion gain switching transistor”) 23 , and a reset transistor 24 .

[0018] The gate electrode of the amplification transistor 21 is connected to the FD 25. One main electrode of the amplification transistor 21 is connected to the power supply voltage terminal VDD, and the other main electrode is connected to one main electrode of the selection transistor 22. The gate electrode of the selection transistor 22 is connected to the selection signal line SEL. The other main electrode of the selection transistor 22 is connected to the vertical signal line VSL and the current source load LC. The current source load LC is connected to the reference voltage terminal GND. A gate electrode of the FD conversion gain switching transistor 23 is connected to the floating diffusion control signal line FDG. One main electrode of the FD conversion gain switching transistor 23 is connected to the FD 25 , and the other main electrode is connected to one main electrode of the reset transistor 24 . A gate electrode of the reset transistor 24 is connected to a reset signal line RST. The other main electrode of the reset transistor 24 is connected to a power supply voltage terminal VDD.

[0019] In the solid-state imaging device 1, the pixel circuit 20 is also connected to an image processing circuit not shown. The image processing circuit includes, for example, an analog-to-digital converter (ADC) and a digital signal processor (DSP). The charge converted from light in the pixel 10 is an analog signal. The analog signal is amplified in the pixel circuit 20. The ADC converts the analog signal output by the pixel circuit 20 into a digital signal. The DSP performs functional processing on the digital signal. That is, the image processing circuit performs signal processing for generating an image. (2) Structure of Pixel 10

[0020] Figure 3 A schematic longitudinal cross-sectional configuration example of the pixel 10 is shown. Figure 4 An example of a schematic planar configuration of the pixel 10 is shown.

[0021] like Figure 3 and 4 As shown, the unit pixel includes four pixels 10 arranged adjacent to each other. In detail, the unit pixel includes two pixels 10A and 10B arranged adjacent to each other in the arrow X direction and two pixels 10C and 10D arranged adjacent to each other in the arrow X direction and adjacent to the pixels 10A and 10B in the arrow Y direction. That is, the pixels 10A to 10D are arranged in a matrix. When viewed from the arrow Z direction (hereinafter referred to as "in a plan view"), each pixel 10A to 10D is formed into a rectangular shape. Here, for ease of understanding and for convenience, the “pixel 10 ” is represented by different reference numerals “pixel 10A” to “pixel 10D.” Note that in some cases, the pixels 10 may be collectively referred to as “pixels 10 .”

[0022] The pixel 10 is provided in a base 15. For example, a semiconductor substrate is used for the base 15. Specifically, the base 15 is used for a single crystal silicon (Si) substrate having a p-type semiconductor region (or a p-type well region), where the p-type is the second conductivity type.

[0023] In addition, each of the pixels 10A to 10D is provided in a region surrounded in a plan view by a pixel isolation region 16. The pixel isolation region 16 is formed in a lattice pattern in a plan view. (3) Structure of pixel isolation region 16

[0024] The pixel isolation region 16 includes a groove 161, an embedding part 163, and an embedding part 164. The groove 161 is formed to extend in the depth direction from the second surface 15B of the base 15 on the arrow Z direction side to the first surface 15A side opposite to the arrow Z direction. Here, the first surface 15A serves as a light incident surface of the pixel 10. The embedded member 163 is embedded in most of the groove 161 on the first surface 15A side of the groove 161. Here, the embedded member 163 is made of, for example, a polycrystalline Si film. The embedded member 164 is embedded in the groove 161 on the second surface 15B side of the groove 161 and is located above the embedded member 163. For example, the embedded member 164 uses a silicon oxide (SiO) film or a silicon nitride (SiN) film. That is, the pixel isolation region 16 is composed of a trench isolation structure. Furthermore, the pixel isolation region 16 includes a pinning region 162 formed in the base 15 in the region of the embedding member 163 along the groove 161 . (4) Structure of Photoelectric Conversion Element 11

[0025] The photoelectric conversion element 11 of the pixel 10 is arranged on the first surface 15A side of the substrate 15. The photoelectric conversion element 11 is arranged for each of the pixels 10A to 10D. That is, one photoelectric conversion element 11 is arranged for the pixel 10A (corresponding to the "first photoelectric conversion element" of the present technology). In addition, one photoelectric conversion element 11 is arranged for the pixel 10B (corresponding to the "second photoelectric conversion element" of the present technology). Similarly, one photoelectric conversion element 11 is arranged for the pixel 10C, and one photoelectric conversion element 11 is arranged for the pixel 10D.

[0026] The photoelectric conversion element 11 is formed at a pn junction between a p-type semiconductor region 11p and an n-type semiconductor region 11n. The p-type semiconductor region 11p is provided on the second surface 15B side of the substrate 15 in a region surrounded by the pixel isolation region 16. Similarly, the n-type semiconductor region 11n is provided on the first surface 15A side of the substrate 15 in a region surrounded by the pixel isolation region 16. (5) Structure of transistor 12

[0027] The transistor (transfer transistor) 12 of the pixel 10 includes an n-type semiconductor region 11 n as one main electrode, an n-type semiconductor region 124 as the other main electrode, a gate insulating film 122 , and a gate electrode 123 .

[0028] The n-type semiconductor region 11 n is the n-type semiconductor region 11 n of the photoelectric conversion element 11 . The gate insulating film 122 is formed along the inner wall of the groove 121 reaching the n-type semiconductor region 11n from the second surface 15B of the base 15. For example, the gate insulating film 122 uses a single layer film such as SiO film or SiN film or a composite film composed of a combination thereof.

[0029] The gate electrode 123 includes a vertical gate electrode portion 123A and a gate electrode contact portion 123B. The gate electrode 123 corresponds to a “first gate electrode” or a “second gate electrode” according to the present technology. The vertical gate electrode portion 123A is embedded in the groove 121 via the gate insulating film 122. For example, a polycrystalline Si film is used for the vertical gate electrode portion 123A. The polycrystalline Si film includes impurities that reduce the resistance value. The gate electrode contact portion 123B is provided on the second surface 15B of the substrate 15. The gate electrode contact portion 123B contacts and is electrically connected to the vertical gate electrode portion 123A. In addition, the gate electrode contact portion 123B is electrically connected to the wiring 7. The control signal TG is input to the gate electrode contact portion 123B from the wiring 7. For example, like the vertical gate electrode portion 123A, the gate electrode contact portion 123B also uses a polycrystalline Si film.

[0030] The n-type semiconductor region 124 is provided on the second surface 15B side of the substrate 15 and is located in the surface portion of the p-type semiconductor region 11p. The n-type semiconductor region 124 is provided at a position close to the pixel isolation region 16. Figure 3 As shown, the respective n-type semiconductor regions 124 of the four pixels 10A to 10D constituting the unit pixel are gathered at the center position of the unit pixel. (6) Structure of the common contact portion 30

[0031] like Figure 2 and 3 As shown, the shared contact portion 30 is electrically connected to the n-type semiconductor region 124 of the transistor 12. The shared contact portion 30 is configured as a common contact portion of a total of four n-type semiconductor regions 124 of the four pixels 10A to 10D constituting the unit pixel. The shared contact portion 30 is configured as the FD 25 (see Figure 1 ) and is electrically connected to the pixel circuit 20 through the wiring 7 (see Figure 1 ).

[0032] The common contact portion 30 is provided so as to overlap with the pixel isolation region 16 on the second surface 15B side of the base 15. In detail, the common contact portion 30 overlaps with the pixel isolation region 16, and the common contact portion 30 extends from the overlapping position to each of the n-type semiconductor regions 124 of the pixels 10A to 10D so as to also overlap with the n-type semiconductor region 124. The common contact portion 30 is electrically connected to each of the four n-type semiconductor regions 124 in the extended and overlapping region.

[0033] like Figure 2As shown in the figure, in the first embodiment, the side surface of the common contact portion 30 located on the gate electrode 123 (gate electrode contact portion 123B) side is formed in a shape that approaches the gate electrode 123 while being away from the second surface 15B of the base 15 (along the arrow Z direction). In other words, the side surface of the common contact portion 30 located on the gate electrode 123 side protrudes toward the common contact portion 30, and is formed in an arc-shaped cross-sectional shape that rides on the upper part of the gate electrode 123. For example, the side surface of the common contact portion 30 of the pixel 10A located on the side of the gate electrode 123 (corresponding to the "first gate electrode" of the present technology) is formed into a shape that is close to the gate electrode (first gate electrode) 123 while being away from the second surface 15B. In addition, the side surface of the common contact portion 30 of the pixel 10B located on the side of the gate electrode 123 (corresponding to the "second gate electrode" of the present technology) is formed into a shape that is close to the gate electrode (second gate electrode) 123 while being away from the second surface 15B. The shape of the side surface of the common contact portion 30 of the pixel 10C and the pixel 10D is also similar.

[0034] For example, a polycrystalline Si film is used for the common contact portion 30. The polycrystalline Si film contains impurities that reduce the resistance value. (7) Structure of Low Dielectric Constant Region 32

[0035] like Figure 2 and 3 As shown, the gate electrode 123 of the transistor 12 of the pixel 10 and the FD 25 (see Figure 1 ) is provided with a low dielectric constant region 32. This point will be described in detail. The low dielectric constant region 32 is provided between the gate electrode contact portion 123B of the gate electrode 123 and the common contact portion 30 which is a part of the FD 25. The dielectric constant of the low dielectric constant region 32 is lower than the dielectric constant of the non-opposing region 33 surrounded by the dotted line. The non-opposing region 33 is provided on the side of the gate electrode contact portion 123B which is opposite to the common contact portion 30.

[0036] Here, the non-opposing region 33 includes an insulating film 34 and an insulating film 35. The insulating film 34 covers a portion of the side surface of the gate electrode contact portion 123B, and the insulating film 35 is stacked in a manner covering the insulating film 34. The insulating film 34 is formed of, for example, a SiO film in the first embodiment. In addition, the insulating film 35 is formed of, for example, a SiN film.

[0037] The low dielectric constant region 32 is a gap in the first embodiment. In more detail, the low dielectric constant region 32 is a gap containing a gas. Air is used as the gas. That is, the low dielectric constant region 32 here is configured as an air gap.

[0038] The low dielectric constant region 32 is provided between the gate electrode contact 123B and the common contact 30, thereby reducing the capacitance value of the parasitic capacitance in which the gate electrode contact 123B is used as one electrode, the low dielectric constant region 32 is used as a dielectric, and the common contact 30 is used as the other electrode. That is, the capacitance value of the parasitic capacitance generated in each pixel 10A to 10D is reduced. Therefore, the difference in the capacitance value of the parasitic capacitance added to the FD 25 can be effectively reduced or prevented.

[0039] Note that, in the present technology, a vacuum may exist inside the gap serving as the low dielectric constant region 32. In addition, the gap serving as the low dielectric constant region 32 may be filled with an inert gas such as nitrogen (N2) or argon (Ar). (8) Structure of wiring 7

[0040] like Figure 2 As shown, the wiring 7 is provided in a contact hole 6H formed in the insulating film 34, the insulating film 35 and the interlayer insulating film 6 covering each of the transistor 12 and the common contact portion 30. The contact hole 6H is a through hole formed in the insulating film 34, the insulating film 35 and the interlayer insulating film 6 in the thickness direction. Here, the interlayer insulating film 6 is formed of, for example, a SiO film. For example, a tungsten (W) film is used for the wiring 7. That is, the wiring 7 is formed as a so-called W plug.

[0041] As described above, one end of the wiring 7 on the substrate 15 side is electrically connected to the transistor 12 via the common contact portion 30 interposed therebetween. The other end of the wiring 7 is electrically connected to the pixel circuit 20 (see FIG. 1 ) not shown in the structural diagram. Figure 1 ). The pixel circuit 20 is provided in a substrate stacked on the interlayer insulating film 6 on the side opposite to the substrate 15. For example, a single crystal Si substrate is used for the substrate. That is, in the solid-state imaging device 1 according to the first embodiment, a two-stage structure in which the substrate 15 and the substrate are stacked on each other is adopted. The substrate 15 includes a photoelectric conversion element 11 and a transistor (transfer transistor) 12. The substrate is stacked on the substrate 15, and the pixel circuit 20 is built in the substrate. [Method of Manufacturing Solid-State Imaging Device 1]

[0042] Figures 4 to 25 An example of a method for manufacturing the solid-state imaging device 1 according to the first embodiment is shown step by step. Note that in the description of this manufacturing method, illustration and description of each structure of the photoelectric conversion element 11 and the transistor (transfer transistor) 12 are simplified or omitted.

[0043] First, if Figure 4 As shown, a substrate 15 is prepared. As described above, the substrate 15 is, for example, a single crystal Si substrate.

[0044] Next, in the formation area of ​​the pixel isolation area 16, a groove 161A is formed from the surface of the second surface 15B of the substrate 15 to the first surface 15A. The depth of the groove 161A is shallower than the depth of the groove 161 formed later. For example, the depth of the groove 161A reaches the n-type semiconductor region 11n of the photoelectric conversion element 11. The groove 161A is formed using, for example, photolithography technology and etching technology. For example, etching is performed using anisotropic etching such as reactive ion etching (RIE: Reactive Ion Etching). like Figure 5 As shown, a mask 171 is formed along the inner wall of the groove 161A. The mask 171 is used as an etching mask and an impurity doping mask. For example, the mask 171 uses a composite film formed by sequentially stacking a SiO film and a SiN film.

[0045] like Figure 6 As shown, the recess 161A is further excavated using a mask 171 to form the recess 161. For example, the recess 161 is formed using anisotropic etching.

[0046] like Figure 7 As shown, a pinning region 162 is formed in the surface portion of the substrate 15 along the inner wall of the groove 161, specifically, in the n-type semiconductor region 11n (see Figure 3 ) is formed in a surface portion of the n-type semiconductor region 11n. The pinning region 162 is formed by doping the n-type semiconductor region 11n with p-type impurities using a mask 171. like Figure 8 As shown, mask 171 is removed.

[0047] like Fig. 9 As shown, the embedded member 163 is formed on the entire second surface 15B of the base 15. The embedded member 163 uses, for example, a polycrystalline Si film formed by a chemical vapor deposition (CVD: Chemical Vaper Deposition) method. Then, the entire surface of the substrate 15 is etched to remove the redundant embedded components 163 on the second surface 15B. Fig.10 As shown, this causes the embedding part 163 to be embedded in the groove 161 .

[0048] like Fig.11 As shown, an embedding member 164 is further embedded on the embedding member 163 in the groove 161. The embedding member 164 uses, for example, a SiO film formed by a CVD method. Like the embedding member 163, the excess embedding member 164 is removed by etching after film formation. When this step is completed, the pixel isolation region 16 is completed.

[0049] An insulating film 341 is formed on the second surface 15B of the base 15 (see Fig.12 ). The insulating film 341 serves as a gate insulating film of the transistor 12. like Fig.12 As shown in FIG. 1 , a gate electrode contact portion 123B is formed on the insulating film 341. Although not illustrated here, a vertical gate electrode portion 123A of the transistor 12 has been formed (see FIG. 1 ). Figure 2 ), and a gate electrode contact portion 123B electrically connected to the vertical gate electrode portion 123A is formed on the vertical gate electrode portion 123A. The gate electrode contact portion 123B uses a polycrystalline Si film formed by, for example, a CVD method. When the gate electrode contact portion 123B is formed, the gate electrode 123 of the transistor 12 having the vertical gate electrode portion 123A and the gate electrode contact portion 123B is completed.

[0050] like Fig.13 As shown in FIG. 1 , an insulating film 342 is formed to cover the side surfaces and the upper surface of the gate electrode contact portion 123B. The insulating film 342 is formed using, for example, a SiO film formed by a CVD method. Then, if Fig.14 As shown, an insulating film 351 is formed on the side surface and the upper surface of the gate electrode contact portion 123B via the insulating film 342. The insulating film 351 uses, for example, a SiN film formed by a CVD method.

[0051] like Fig.15 As shown, the entire surface is etched to leave the insulating film 351 on the side of the gate electrode contact 123B and remove the insulating film 351 in other regions. Etching uses anisotropic etching such as the RIE method. The insulating film 351 remaining on the side of the gate electrode contact 123B serves as a so-called sidewall spacer.

[0052] like Fig.16 As shown in FIG. 1 , an insulating film 343 is formed on the upper surface of the gate electrode contact portion 123B and the upper surface of the insulating film 351. For example, a SiO film formed by a CVD method is used as the insulating film 343. like Fig.17 As shown, the insulating film 343 is used as a buffer film, and an n-type semiconductor region 124 serving as another main electrode of the transistor 12 is formed on the surface portion of the second face 15B of the substrate 15. The n-type semiconductor region 124 is formed by doping the substrate 15 with n-type impurities, for example, using an ion implantation method. When the n-type semiconductor region 124 is formed, the transistor 12 is completed.

[0053] like Fig.18As shown, an opening 343H is formed in the insulating film 343 in a region overlapping with the n-type semiconductor region 124 and the pixel isolation region 16. The opening 343H is formed using a photolithography technique and an etching technique.

[0054] like Fig.19 As shown, a conductive film 301 is formed on the entire surface of the base 15 including the upper surface of the insulating film 343. The conductive film 301 includes a material for forming the common contact portion 30. The conductive film 301 uses, for example, a polycrystalline Si film formed by a CVD method. Subsequently, the conductive film 301 is doped with p-type impurities in a portion corresponding to the opening 343H overlapping the pixel isolation region 16 (except for the formation region of the common contact 30) to form a p-type conductive film 36. The p-type conductive film 36 serves as a path for supplying a reference voltage, for example. like Fig. 20 As shown, n-type impurities are doped into the conductive film 301 in the formation region of the common contact 30. When the conductive film 301 is doped with n-type impurities, the common contact 30 is substantially formed.

[0055] like Fig.21 As shown, the conductive film 301 is patterned to remove excess conductive film 301, thereby forming the common contact portion 30 and the p-type conductive film 36. The patterning uses photolithography technology and etching technology.

[0056] like Fig. 22 As shown, the insulating film 343 and the insulating film 351 are selectively removed. This selective removal uses an etching technique. Here, as described above, the insulating film 351 is formed as a sidewall spacer and is removed to form the low dielectric constant region 32 that becomes the gap between the gate electrode contact portion 123B and the common contact portion 30. That is, the low dielectric constant region 32 is formed by forming a sidewall spacer on the side of the gate electrode contact portion 123B and using the gap from which the sidewall spacer is removed.

[0057] For example, when exposed to the atmosphere during the manufacturing step, the gaps that are low dielectric constant regions 32 are filled with air. In addition, when the furnace is evacuated during the manufacturing step, a vacuum is created in the gaps that are low dielectric constant regions 32. Furthermore, when a carrier gas (e.g., an inert gas) flowing into the furnace is used during the manufacturing step, the gaps that are low dielectric constant regions 32 are filled with the inert gas.

[0058] Then, if Fig.23 As shown in FIG. 1 , an insulating film 34 covering the common contact portion 30 is formed on the entire second surface 15B of the base 15. Fig.24 As shown, an insulating film 35 is formed on the insulating film 34 . Here, on the side surface of gate electrode contact portion 123B, non-opposing region 33 including insulating film 34 and insulating film 35 is formed in a region other than the formation region of low dielectric constant region 32. Low dielectric constant region 32 has a dielectric constant smaller than that of non-opposing region 33.

[0059] Next, if Fig.25 As shown, the interlayer insulating film 6 is formed on the insulating film 35 . Subsequently, a contact hole 6H is formed in the interlayer insulating film 6, and as described above Figure 2 As shown, the wiring 7 is formed in the contact hole 6H. It should be noted that the pixel circuit 20 (see Figure 1 )'s manufacturing method, etc.

[0060] When these series of manufacturing steps are finished, the solid-state imaging device 1 according to the first embodiment is completed, and the manufacturing method ends. [Function and Effect]

[0061] The solid-state imaging device 1 according to the first embodiment includes a pixel (first pixel) 10 , a transistor (first transistor) 12 , and an FD 25 . The pixel 10 is, for example, a pixel 10A. The pixel 10 is provided on the first surface 15A side of the substrate 15 as the light incident side, and includes a photoelectric conversion element (first photoelectric conversion element) 11 that converts light into electric charge. The transistor 12 is provided on the second surface 15B side of the substrate 15 opposite to the first surface 15A and is located at a position corresponding to the pixel 10. The transistor 12 includes a gate electrode (first gate electrode) 123, and one of a pair of main electrodes is electrically connected to the photoelectric conversion element 11. The FD 25 is provided on the second surface 15B side of the substrate 15, and is electrically connected to the n-type semiconductor region 124 as the other main electrode of the transistor 12. like Figure 2 and 3 As shown, the solid-state imaging device 1 further includes a low dielectric constant region 32. The low dielectric constant region 32 is provided between the FD 25 and the gate electrode 123 opposing the FD 25. The low dielectric constant region 32 has a lower dielectric constant than a non-opposing region 33 not opposing the FD 25. This configuration can reduce the capacitance value of the parasitic capacitance using the gate electrode contact portion 123B as one electrode, the low dielectric constant region 32 as a dielectric, and the FD 25 as the other electrode. That is, the capacitance value added to the parasitic capacitance of the FD 25 becomes small, so that the difference in capacitance value can be reduced. Therefore, in the solid-state imaging device 1, it is possible to suppress the signal difference and signal delay caused by the parasitic capacitance.

[0062] In addition, if Figures 1 to 3As shown, the solid-state imaging device 1 further includes a pixel (second pixel) 10 and a transistor (second transistor) 12 . The pixel 10 is, for example, a pixel 10B (or a pixel 10C). The pixel 10 is, for example, arranged adjacent to the pixel 10A as the first pixel. The pixel 10 is arranged on the first surface 15A side of the substrate 15, and includes a photoelectric conversion element (a second photoelectric conversion element) 11 that converts light into electric charge. The transistor 12 is arranged on the second surface 15B side of the substrate 15 and is located at a position corresponding to the pixel 10. The transistor 12 includes a gate electrode (a second gate electrode) 123, and one of a pair of main electrodes is electrically connected to the photoelectric conversion element 11, and the FD 25 is electrically connected to the n-type semiconductor region 124 as the other main electrode. Here, the solid-state imaging device 1 further includes a low dielectric constant region 32 between the FD 25 and the gate electrode 123 opposing the FD 25 . This configuration can reduce the capacitance value of the parasitic capacitance having the gate electrode 123 as one electrode, the low dielectric constant region 32 as one dielectric, and the FD 25 as the other electrode. That is, the capacitance value added to the parasitic capacitance of the FD 25 is reduced, so that the difference in capacitance value can be reduced. Therefore, in the solid-state imaging device 1, the signal difference and signal delay caused by the parasitic capacitance can be suppressed.

[0063] In addition, if Figure 2 and 3 As shown, the solid-state imaging device 1 further includes a pixel isolation region 16 and a common contact portion 30 . The pixel isolation region 16 is provided between two pixels (a first pixel and a second pixel) 10 adjacent to each other in the substrate 15 to electrically and optically isolate the pixels 10 from each other. In the first embodiment, the pixel isolation region 16 has a groove 161, an embedding part 163, and an embedding part 164. The groove 161 is formed along the depth direction of the substrate 15, and the embedding part 163 and the embedding part 164 are embedded in the groove 161. The common contact portion 30 is provided on the second surface 15B side of the substrate 15 so as to overlap with the pixel isolation region 16, and, for example, electrically connects the other main electrode (n-type semiconductor region 124) of the transistor (first transistor) 12 of the pixel 10A and the other main electrode (n-type semiconductor region 124) of the transistor (second transistor) 12 of the pixel 10B to each other. In addition, the FD 25 is electrically connected to the common contact portion 30. In addition, the low dielectric constant region 32 is provided between the gate electrode 123 and the common contact 30 . Thus, the capacitance value of the parasitic capacitance between the gate electrode 123 and the common contact portion 30 can be reduced.

[0064] Furthermore, in the solid-state imaging device 1, as Figure 2 As shown, the side surface of the common contact portion 30 on each gate electrode (first gate electrode and second gate electrode) 123 side is formed in a shape that approaches the gate electrode 123 while moving away from the second surface 15B of the base 15 in the arrow Z direction. In detail, as used in the manufacturing method Fig.21 As shown in FIG. 1 , on the side of the gate electrode 123 (specifically, the gate electrode contact portion 123B), the common contact portion 30 is formed in a shape covering the insulating film 351 as a sidewall spacer. Fig. 22 As shown, the low dielectric constant region 32 is formed by utilizing the gap formed by selectively removing the insulating film 351. Therefore, the low dielectric constant region 32 can be easily formed, and the capacitance value of the parasitic capacitance can be easily reduced.

[0065] Furthermore, in the solid-state imaging device 1, as Figure 2 As shown, the low dielectric constant region 32 is a gap. In addition, a vacuum exists in the gap as the low dielectric constant region 32. Alternatively, the gap as the low dielectric constant region 32 is filled with air or an inert gas. Thus, the low dielectric constant region 32 can have a simple structure, whereby the capacitance value of the parasitic capacitance can be easily reduced. <2. Second embodiment>

[0066] refer to Fig.26 and 27 Note that in the second embodiment and subsequent embodiments, components identical or substantially identical to those of the solid-state imaging device 1 according to the first embodiment are denoted by the same reference numerals, and redundant description is omitted. [Configuration of Solid-State Imaging Device 1]

[0067] Fig.26 An example of a schematic longitudinal cross-sectional configuration of the pixel 10 is shown. Fig. 27 An example of a schematic planar configuration of the pixel 10 is shown.

[0068] like Fig.26 and 27 As shown, in the solid-state imaging device 1 according to the second embodiment, the low dielectric constant region 32 of the solid-state imaging device 1 according to the first embodiment is formed of a low dielectric constant material having a lower dielectric constant than that of the non-opposing region 33 .

[0069] In detail, in the above example, in the non-opposing region 33, the insulating film 34 is formed as a SiO film, and the insulating film 35 is formed as a SiN film. Accordingly, the low dielectric constant region 32 is formed of a single-layer film of a SiO film or a carbon-doped silicon oxide (SiOC) film, or a composite film formed by stacking these films.

[0070] Components other than the above-described components are the same or substantially the same as those of the solid-state imaging device 1 according to the first embodiment. [Function and Effect]

[0071] exist Fig.26 and 27 In the solid-state imaging device 1 according to the second embodiment shown, operations and effects similar to those obtained by the solid-state imaging device 1 of the first embodiment can be obtained. <3. Third embodiment>

[0072] refer to Fig.28 and 29 A description is given of the solid-state imaging device 1 according to the third embodiment of the present disclosure. [Configuration of Solid-State Imaging Device 1]

[0073] Fig.28 An example of a schematic longitudinal cross-sectional configuration of the pixel 10 is shown. Fig.29 An example of a schematic planar configuration of the pixel 10 is shown.

[0074] like Fig.28 and 29 As shown, in the solid-state imaging device 1 according to the third embodiment, the configuration of the pixel isolation region 16 is changed in the solid-state imaging device 1 according to the first embodiment or the second embodiment. In detail, the pixel isolation region 16 includes an insulator region instead of the structure including the groove 161, the embedding member 163, and the embedding member 164. The insulator region is formed by doping the base 15 with impurities using, for example, an ion implantation method.

[0075] Components other than the above-described components are the same or substantially the same as those of the solid-state imaging device 1 according to the first embodiment or the second embodiment. [Function and Effect]

[0076] exist Fig.28 and 29 In the solid-state imaging device 1 of the third embodiment shown, operations and effects similar to those obtained by the solid-state imaging device 1 of the first embodiment or the second embodiment can be obtained.

[0077] Furthermore, in the solid-state imaging device 1, as Fig.28 and 29As shown, the pixel isolation region 16 includes an insulator region. Therefore, the pixel isolation region 16 can be simply configured, so that the structure of the solid-state imaging device 1 can be simply realized. <4. Fourth embodiment>

[0078] refer to Fig.30 and 31 A description is given of the solid-state imaging device 1 according to the fourth embodiment of the present disclosure. [Configuration of Solid-State Imaging Device 1]

[0079] Fig.30 An example of a schematic longitudinal cross-sectional configuration of the pixel 10 is shown. Fig.31 An example of a schematic planar configuration of the pixel 10 is shown.

[0080] like Fig.30 and 31 As shown, the solid-state imaging device 1 according to the fourth embodiment is formed in a state where the insulating film 351 remains in the non-opposing region 33 in the solid-state imaging device 1 according to the first embodiment or the second embodiment. The insulating film 351 is a sidewall spacer formed on the side of the gate electrode contact portion 123B of the transistor 12. That is, in the method for manufacturing the solid-state imaging device 1, in the above Fig. 22 In the step shown, the insulator 351 between the gate electrode contact 123B and the common contact 30 is selectively removed, but the insulator 351 between the gate electrode contact 123B and the non-opposing region 33 is not removed.

[0081] Components other than the above are the same or substantially the same as those of the solid-state imaging device 1 according to the first or second embodiment. In addition, the solid-state imaging device 1 according to the fourth embodiment is applicable to the solid-state imaging device 1 according to the third embodiment. [Function and Effect]

[0082] exist Fig.30 and 31 In the solid-state imaging device 1 according to the fourth embodiment shown, operations and effects similar to those obtained by the solid-state imaging device 1 of the first embodiment or the second embodiment can be obtained.

[0083] Furthermore, in the solid-state imaging device 1, the insulating film 351 as a sidewall spacer is provided on the side of the non-opposing region 33 of the gate electrode 123 (gate electrode contact portion 123B). The low dielectric constant region 32 has a lower dielectric constant than the insulating film 351. In the solid-state imaging device 1 configured as described above, the capacitance value of the parasitic capacitance added to the FD 25 is reduced, so that the signal difference and signal delay caused by the parasitic capacitance can be suppressed. <5. Fifth embodiment>

[0084] refer to Fig.32 and 33 A description is given of the solid-state imaging device 1 according to the fifth embodiment of the present disclosure. [Configuration of Solid-State Imaging Device 1]

[0085] Fig.32 An example of a schematic longitudinal cross-sectional configuration of the pixel 10 is shown. Fig.33 An example of a schematic planar configuration of the pixel 10 is shown.

[0086] like Fig.32 and 33 As shown, in the solid-state imaging device 1 according to the fifth embodiment, the insulating film 35 is formed on the gate electrode contact portion 123B of the transistor 12 and on the common contact portion 30. The insulating film 34 is omitted (see Figure 2 ). As described above, the insulating film 35 is formed of, for example, a SiN film. The embedding property of the insulating film 35 is inferior to that of, for example, a SiO film.

[0087] Components other than the above are the same or substantially the same as those of the solid-state imaging device 1 according to the first or second embodiment. In addition, the solid-state imaging device 1 according to the fifth embodiment can also be applied to the solid-state imaging device 1 according to the third or fourth embodiment. [Function and Effect]

[0088] exist Fig.32 and 33 In the solid-state imaging device 1 of the fifth embodiment shown, operations and effects similar to those obtained by the solid-state imaging device 1 of the first embodiment or the second embodiment can be obtained. <6. Sixth embodiment>

[0089] refer to Figures 34 to 59 A description is given of the solid-state imaging device 1 according to the sixth embodiment of the present disclosure. [Configuration of Solid-State Imaging Device 1]

[0090] Fig.34 An example of a schematic longitudinal cross-sectional configuration of the pixel 10 is shown. Fig.35 An example of a schematic planar configuration of the pixel 10 is shown.

[0091] like Fig.34 and 35 As shown, in the solid-state imaging device 1 according to the sixth embodiment, a part of the common contact portion 30 is embedded in the groove 161 of the pixel isolation region 16 in the solid-state imaging device 1 according to the first embodiment or the second embodiment. In detail, the portion of the common contact 30 is embedded in the upper portion of the groove 161 and is also electrically connected to the side of the n-type semiconductor region 124 of the transistor 12 of the adjacent pixel 10. It is sufficient that the portion of the common contact 30 is embedded to about the junction depth of the n-type semiconductor region 124. [Method of Manufacturing Solid-State Imaging Device 1]

[0092] Figures 36 to 59 An example of a method for manufacturing the solid-state imaging device 1 according to the sixth embodiment is shown step by step. Note that in the description of this manufacturing method, illustration and description of each cross-sectional structure of the photoelectric conversion element 11 and the transistor (transfer transistor) 12 are simplified or omitted.

[0093] First, as Figure 4 According to the steps of the method for manufacturing the solid-state imaging device 1 according to the first embodiment (hereinafter referred to simply as “first manufacturing method”), the base 15 is prepared. like Fig.36 As shown, a mask 172 and a mask 173 are sequentially formed on the second surface 15B of the base 15. The mask 172 serves as an etching stopper, for example, and is formed of a SiN film. The mask 173 serves as an etching hard mask, for example, and is formed of a SiO film.

[0094] like Fig.37 As shown, in the formation region of the pixel isolation region 16, an opening 173H is formed in the mask 173. For example, the opening 173H is formed by a photolithography technique and an etching technique. like Fig.38 As shown, a groove 161A is formed from the surface of the second surface 15B of the substrate 15 toward the first surface 15A using a mask 173. The depth of the groove 161A is relatively shallow. For example, the groove 161A is formed by etching technology.

[0095] as Figure 5 The steps of the first manufacturing method are as follows: Fig.39 As shown, a mask 171 is formed along the inner wall of the groove 161A.

[0096] as Figure 6 The steps of the first manufacturing method are as follows: Fig.40 As shown, the groove 161A is further excavated using a mask 171 to form the groove 161 . as Figure 7 The steps of the first manufacturing method are as follows: Fig.41 As shown, in the surface portion of the base 15, a pinning area 162 is formed along the inner wall of the groove 161. Afterwards, if Fig.42 As shown, mask 171 is removed.

[0097] as Fig. 9 The steps of the first manufacturing method are as follows: Fig.43 As shown, the embedded member 163 is formed on the entire second surface 15B of the base 15. Here, the embedded member 163 is formed on the mask 173. Then, the entire surface of the substrate 15 is etched to remove the redundant embedded parts 163 on the mask 173. Fig.44 As shown, the embedding component 163 is embedded in the groove 161 .

[0098] as Fig.11 The steps of the first manufacturing method are as follows: Fig.45 As shown, the embedding member 164 is further embedded on the embedding member 163 in the groove 161. After the embedding member 164 is formed, the excess embedding member 164 on the mask 173 is removed. Then, if Fig.46 As shown, the mask 173 and the embedded features 164 remaining in the openings 173H are removed. This removal uses an etching technique. Furthermore, a portion of the embedded component 164 is further removed using the mask 172. The upper surface of the embedded component 164 is dug deeper inside the base 15 than the second surface 15B of the base 15. The embedded component 164 is removed using an etching technique. When this step is completed, the pixel isolation region 16 is completed.

[0099] as Fig.19 The steps of the first manufacturing method are as follows: Fig.48 As shown, a conductive film 301 is formed on the entire surface of the substrate 15 including the upper surface of the mask 172. The conductive film 301 includes a material for forming the common contact portion 30. A portion of the conductive film 301 is embedded in the upper portion of the groove 161 of the pixel isolation region 16.

[0100] Subsequently, the conductive film 301 is doped with p-type impurities in a portion overlapping with the pixel isolation region 16 (except for the formation region of the common contact portion 30 ) to form a p-type conductive film 36 . like Fig.49 As shown, n-type impurities are doped into the conductive film 301 in the formation region of the common contact 30. When the conductive film 301 is doped with n-type impurities, the common contact 30 is substantially formed.

[0101] as Fig.21 The steps of the first manufacturing method are as follows: Fig.50 As shown, the conductive film 301 is patterned to remove excess conductive film 301 , thereby forming the common contact portion 30 and the p-type conductive film 36 . Then, if Fig.51 As shown, mask 172 is removed.

[0102] like Fig.52 As shown, in the formation region of the pixel 10 , an insulating film 341 is formed on the second surface 15B of the substrate 15 . Subsequently, the n-type semiconductor region 124 of the transistor 12 is formed (see Fig.53 The n-type semiconductor region 124 is formed by doping the surface portion of the second surface 15B of the substrate 15 with n-type impurities through the insulating film 341. The side surface of the n-type semiconductor region 124 contacts the side surface of the common contact portion 30, and the side surface of the n-type semiconductor region 124 and the side surface of the common contact portion 30 are electrically connected to each other.

[0103] as Fig.12 The steps of the first manufacturing method are as follows: Fig.53 As shown, the gate electrode contact portion 123B of the gate electrode 123 is formed on the insulating film 341 . as Fig.14 The steps of the first manufacturing method are as follows: Fig.54 As shown, the insulating film 342 and the insulating film 351 are sequentially formed on the entire surface on the second face 15B side of the base 15 .

[0104] as Fig.15 The steps of the first manufacturing method are as follows: Fig.55 As shown, the entire surface is etched so that the insulating film 351 on the side of the gate electrode contact portion 123B remains and the insulating film 351 in other regions is removed. The remaining insulating film 351 is formed as a sidewall spacer. Then, if Fig.56 As shown, an insulating film 344 is formed to cover the gate electrode contact portion 123B and the insulating film 351. The insulating film 344 is, for example, a SiO film.

[0105] like Fig.57 As shown, the insulating film 344 and the insulating film 351 are removed. By this removal, the surfaces of the gate electrode contact portion 123B and the common contact portion 30 are exposed.

[0106] like Fig.58 As shown, an insulating film 34 is formed to cover each of the gate electrode contact portion 123B and the common contact portion 30 and the like. As in the first manufacturing method, the insulating film 34 is, for example, a SiO film. Here, when the insulating film 34 is formed, a gap is formed between the gate electrode contact portion 123B and the common contact portion 30. Thus, the low dielectric constant region 32 is formed. Note that when the thickness of the common contact portion 30 in the direction of arrow Z is set thicker, the height of the low dielectric constant region 32 in the direction of arrow Z becomes higher. That is, the volume of the low dielectric constant region 32 can be increased, and the capacitance value of the parasitic capacitance can be reduced. Then, if Fig.59 As shown, an insulating film 35 is formed on the insulating film 34 .

[0107] Afterwards, execute Fig.25 The steps of the first manufacturing method shown and the subsequent steps thereof are performed, thereby completing the solid-state imaging device 1 according to the sixth embodiment, and the manufacturing method ends.

[0108] Components other than the above are the same or substantially the same as those of the solid-state imaging device 1 according to the first or second embodiment. In addition, the solid-state imaging device 1 according to the sixth embodiment is applicable to any of the solid-state imaging devices 1 according to the third to fifth embodiments. [Function and Effect]

[0109] exist Fig.34 and 35 In the solid-state imaging device 1 according to the sixth embodiment shown, actions and effects similar to those obtained by the solid-state imaging device 1 according to the first embodiment or the second embodiment can be obtained. In addition, Figures 36 to 59 In the manufacturing method of the solid-state imaging device 1 according to the sixth embodiment shown, actions and effects similar to those obtained by the first manufacturing method can be obtained. <7. Seventh embodiment>

[0110] refer to Fig.60 and 61 A description is given of a solid-state imaging device 1 according to a seventh embodiment of the present disclosure. [Configuration of Solid-State Imaging Device 1]

[0111] Fig.60 An example of a schematic longitudinal cross-sectional configuration of the pixel 10 is shown. Fig.61 An example of a schematic planar configuration of the pixel 10 is shown.

[0112] like Fig.60 and 61 As shown, in the solid-state imaging device 1 according to the seventh embodiment, a single-stage structure is used in which the pixel circuit 20 is constructed on the substrate 15. Specifically, transistors constituting the pixel circuit 20 are provided on a portion of the second surface 15B of the substrate 15 located at a position corresponding to the pixel 10.

[0113] Although the arrangement layout is not limited, in the seventh embodiment, the amplification transistor 21 is provided on the substrate 15 and is located at a position corresponding to the pixel 10A constituting the unit pixel. In addition, the selection transistor 22 is provided on the substrate 15 and is located at a position corresponding to the pixel 10B. Similarly, the FD conversion gain switching transistor 23 is provided on the substrate 15 and is located at a position corresponding to the pixel 10C, and the reset transistor 24 is provided on the substrate 15 and is located at a position corresponding to the pixel 10D.

[0114] An element isolation region 8 is provided around each of the amplifier transistor 21, the selection transistor 22, the FD conversion gain switching transistor 23, and the reset transistor 24. Although the specific structure of the element isolation region 8 is not illustrated, the element isolation region 8 is composed of a trench isolation structure having a groove and an embedded component embedded in the groove. The groove and the embedded component are not specifically indicated by reference numerals.

[0115] In addition, although the specific structure of each of the amplifying transistor 21, the selecting transistor 22, the FD conversion gain switching transistor 23, and the reset transistor 24 is not described, each of the amplifying transistor 21, the selecting transistor 22, the FD conversion gain switching transistor 23, and the reset transistor 24 includes a gate electrode and a pair of main electrodes. The gate electrode and the pair of main electrodes are not specifically indicated by reference numerals. The gate electrode is formed in the same conductive layer and made of the same conductive material as the gate electrode contact 123B of the transistor 12. The pair of main electrodes are formed of the same n-type semiconductor region as the n-type semiconductor region 124 of the transistor 12.

[0116] Here, an insulating film 351 serving as a sidewall spacer is provided on the side surface of the gate electrode of each of the amplification transistor 21 , the selection transistor 22 , the FD conversion gain switching transistor 23 , and the reset transistor 24 .

[0117] Note that the present technology is not limited to the case where one transistor constituting the pixel circuit 20 is provided at a position corresponding to one pixel 10. For example, one transistor may be provided on two pixels 10. In addition, two transistors may be provided at a position corresponding to one pixel 10.

[0118] Components other than the above are the same or substantially the same as those of the solid-state imaging device 1 according to the first or second embodiment. In addition, the solid-state imaging device 1 according to the seventh embodiment is applicable to any of the solid-state imaging devices 1 according to the third to sixth embodiments. [Function and Effect]

[0119] exist Fig.60 and 61In the solid-state imaging device 1 of the seventh embodiment shown, operations and effects similar to those obtained by the solid-state imaging device 1 according to the first embodiment or the second embodiment can be obtained. <8. Eighth embodiment>

[0120] Figures 62 to 65 A description is given of the solid-state imaging device 1 and a method of manufacturing the same according to the eighth embodiment of the present disclosure. [Method of Manufacturing Solid-State Imaging Device 1]

[0121] Figures 62 to 65 An example of a method for manufacturing the solid-state imaging device 1 according to the eighth embodiment is shown step by step. Note that in the description of this manufacturing method, illustration and description of each cross-sectional structure of the photoelectric conversion element 11 and the transistor (transfer transistor) 12 are simplified or omitted.

[0122] as Fig.17 In the first manufacturing method shown in FIG. 1 , an insulating film 351 serving as a sidewall spacer is formed on the side of the gate electrode contact portion 123B, and an insulating film 343 (see FIG. 1 ) covering the gate electrode contact portion 123B and the insulating film 351 is formed. Fig.62 ). like Fig.62 As shown, an n-type semiconductor region 124 is formed as another main electrode of the transistor 12.

[0123] like Fig.63 As shown, the insulating film 343 and the insulating film 351 are selectively removed. That is, the sidewall spacers are removed. Then, as Fig. 22 The steps of the first manufacturing method are as follows: Fig.64 As shown, a common contact portion 30 and a p-type conductive film 36 are formed.

[0124] Then, as Fig.23 In the first manufacturing method shown in FIG. 1 , an insulating film 34 (see FIG. 1 ) is formed to cover the gate electrode contact portion 123B and the common contact portion 30. Fig.65 When the insulating film 34 is formed, the low dielectric constant region 32 is formed between the gate electrode contact portion 123B and the common contact portion 30 . as Fig.24 The steps of the first manufacturing method are as follows: Fig.65 As shown, an insulating film 35 is formed to cover the insulating film 34.

[0125] Afterwards, execute Fig.25 The steps of the first manufacturing method shown and the subsequent steps thereof are performed, thereby completing the solid-state imaging device 1 according to the eighth embodiment, and the manufacturing method ends.

[0126] Components other than the above-described components are the same or substantially the same as those of the solid-state imaging device 1 and the method for manufacturing the same according to the first embodiment. [Function and Effect]

[0127] exist Figures 62 to 65 In the method of manufacturing the solid-state imaging device 1 according to the eighth embodiment shown, actions and effects similar to those obtained by the method of manufacturing the solid-state imaging device 1 according to the first embodiment can be obtained. <9. Ninth Embodiment>

[0128] refer to Fig.66 and 67 A description is given of the solid-state imaging device 1 and a method of manufacturing the same according to a ninth embodiment of the present disclosure. [Method of Manufacturing Solid-State Imaging Device 1]

[0129] Figures 66 to 67 An example of a method for manufacturing the solid-state imaging device 1 according to the ninth embodiment is shown step by step. Note that in the description of this manufacturing method, illustration and description of each cross-sectional structure of the photoelectric conversion element 11 and the transistor (transfer transistor) 12 are simplified or omitted.

[0130] In the method for manufacturing the solid-state imaging device 1 according to the ninth embodiment, as in Fig.64 The steps of the method for manufacturing the solid-state imaging device 1 according to the eighth embodiment (hereinafter referred to as “the eighth manufacturing method”) are as follows. Fig.66 As shown in FIG. 1 , a common contact portion 30 and a p-type conductive film 36 are formed. Figures 47 to 53 In the step shown in the method of manufacturing the solid-state imaging device 1 according to the sixth embodiment described above, a part of the common contact portion 30 is embedded in the groove 161 of the pixel isolation region 16 .

[0131] as Fig.65 The steps of the eighth manufacturing method shown are as follows: Fig.67 As shown, the insulating film 34 and the insulating film 35 are sequentially formed. Here, when the insulating film 34 is formed, the low dielectric constant region 32 is formed between the gate electrode contact portion 123B and the common contact portion 30 .

[0132] Afterwards, execute Fig.25 The steps of the first manufacturing method shown and the subsequent steps thereof are performed, thereby completing the solid-state imaging device 1 according to the ninth embodiment, and the manufacturing method ends.

[0133] Components other than the above-described components are the same or substantially the same as those of the solid-state imaging device 1 and the method for manufacturing the same according to the eighth embodiment. [Function and Effect]

[0134] exist Fig.66 and 67 In the method for manufacturing the solid-state imaging device 1 according to the ninth embodiment shown, a combination of the actions and effects of the method for manufacturing the solid-state imaging device 1 according to the sixth embodiment and the method for manufacturing the solid-state imaging device 1 according to the eighth embodiment can be obtained. <10. Tenth Embodiment>

[0135] refer to Fig.68 A description is given of the solid-state imaging device 1 according to the tenth embodiment of the present disclosure. [Configuration of Solid-State Imaging Device 1]

[0136] Fig.68 An example of a schematic planar configuration of the pixel 10 is shown.

[0137] like Fig.68 As shown, in the solid-state imaging device 1 according to the tenth embodiment, the pixel isolation region 16 is provided in a part of the region around the pixel 10 . In the tenth embodiment, an isolation portion 16I is provided between the pixel 10A and the pixel 10B constituting the unit pixel, and the pixel isolation region 16 has a break at the isolation portion 16I. In addition, an isolation portion 16I is also provided between the pixel 10C and the pixel 10D, and the pixel isolation region 16 has a break at the isolation portion 16I.

[0138] Components other than the above-described components are the same or substantially the same as those of the solid-state imaging device 1 according to any of the first to ninth embodiments. [Function and Effect]

[0139] exist Fig.68 In the solid-state imaging device 1 according to the tenth embodiment shown, actions and effects similar to those obtained by any of the solid-state imaging devices 1 according to the first to ninth embodiments can be obtained. <11. Eleventh Embodiment>

[0140] refer to Fig.69 and 70 A description is given of the solid-state imaging device 1 according to the eleventh embodiment of the present disclosure. [Configuration of Solid-State Imaging Device 1]

[0141] Fig.69 An example of a schematic longitudinal cross-sectional configuration of the pixel 10 is shown. Fig.70 An example of a schematic planar configuration of the pixel 10 is shown.

[0142] like Fig.69 and 70As shown, in the solid-state imaging device 1 according to the eleventh embodiment, the pixel isolation region 16 includes two pixel isolation regions 16T and 16R.

[0143] The pixel isolation region 16T is the same component as the pixel isolation region 16 of the solid-state imaging device 1 according to the first embodiment or the second embodiment. For the purpose of distinction, the reference numerals are changed. The pixel isolation region 16T has a groove 161, an embedding part 163, and an embedding part 164. The pixel isolation region 16T is provided around the unit pixel, between the pixel 10A and the pixel 10C, and between the pixel 10B and the pixel 10D.

[0144] The pixel isolation region 16R is the same component as the pixel isolation region 16 of the solid-state imaging device 1 according to the third embodiment. Also, for the sake of distinction, the reference numerals are changed. The pixel isolation region 16R includes an insulator region. The pixel isolation region 16R is provided between the pixel 10A and the pixel 10B and between the pixel 10C and the pixel 10D.

[0145] Components other than the above-described components are the same or substantially the same as those of any one of the solid-state imaging devices 1 according to the first to tenth embodiments. [Function and Effect]

[0146] exist Fig.69 and 70 In the solid-state imaging device 1 according to the eleventh embodiment shown, operations and effects similar to those obtained by the solid-state imaging device 1 according to any of the first to tenth embodiments can be obtained. <12. Twelfth Embodiment>

[0147] refer to Fig.71 A description is given of the solid-state imaging device 1 according to the twelfth embodiment of the present disclosure. [Configuration of Solid-State Imaging Device 1]

[0148] Fig.71 An example of a schematic planar configuration of the pixel 10 is shown.

[0149] like Fig.71 As shown, in the solid-state imaging device 1 according to the twelfth embodiment, the unit pixel is composed of a total of eight pixels 10A to 10H. Pixel 10B is arranged adjacent to pixel 10A in the arrow X direction. Pixel 10C is arranged adjacent to pixel 10A in the arrow Y direction. Pixel 10D is arranged adjacent to pixel 10C in the arrow X direction. Pixel 10E is arranged adjacent to pixel 10C in the arrow Y direction. Pixel 10F is arranged adjacent to pixel 10E in the arrow X direction. Pixel 10G is arranged adjacent to pixel 10F in the arrow Y direction. Pixel 10H is arranged adjacent to pixel 10G in the arrow X direction.

[0150] The common contact portion 30 is provided between the pixel 10A and the pixel 10B, between the pixel 10C and the pixel 10D, between the pixel 10E and the pixel 10F, and between the pixel 10G and the pixel 10H. In addition, the common contact portion 30 is shared by all the pixels 10A to 10H in the unit pixel.

[0151] In addition, in the twelfth embodiment, one pixel circuit 20 is provided for one unit pixel (see Figure 1 ).

[0152] Components other than the above-described components are the same or substantially the same as those of the solid-state imaging device 1 according to any one of the first to eleventh embodiments. [Function and Effect]

[0153] exist Fig.71 In the solid-state imaging device 1 according to the twelfth embodiment shown, operations and effects similar to those obtained by the solid-state imaging device 1 of any of the first to eleventh embodiments can be obtained. <13. Application examples on mobile objects>

[0154] Various products can be applied to the technology of the present disclosure (the present technology). For example, the technology of the present disclosure can be implemented in the form of a device installed on any type of mobile body, such as a car, an electric car, a hybrid electric car, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, and a robot.

[0155] Fig.72 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the present disclosure can be applied.

[0156] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.72 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and an in-vehicle network interface (I / F) 12053 are shown as a functional configuration of the integrated control unit 12050.

[0157] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 acts as a control device for the following devices: a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating a vehicle drive force, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a vehicle braking force, etc.

[0158] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for the following devices: a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a reverse light, a brake light, a turn signal, or a fog light. In this case, a radio wave or a signal of various switches transmitted from a portable device as a key substitute may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, or the lights of the vehicle.

[0159] The vehicle exterior information detection unit 12030 detects external information about the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to image the exterior of the vehicle and receive the captured image. Based on the received image, the vehicle exterior information detection unit 12030 may perform processing for detecting objects such as people, vehicles, obstacles, signs, or characters on the road surface, or processing for detecting their distances.

[0160] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may also output an electrical signal as an image, or may output an electrical signal as measured distance information. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0161] The in-vehicle information detection unit 12040 detects interior information about the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting a driver state. The driver state detection unit 12041 includes, for example, a camera for imaging the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off.

[0162] The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the information about the inside and outside of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform coordinated control of functions intended to implement an advanced driver assistance system (ADAS), such as collision avoidance or shock absorption of the vehicle, following driving based on vehicle spacing, speed maintenance driving, vehicle collision warning, or vehicle lane departure warning.

[0163] In addition, based on the environmental information about the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can perform coordinated control for automatic driving by controlling the driving force generating device, steering mechanism or braking device, etc., which enables the vehicle to drive automatically without relying on the driver's operation, etc.

[0164] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the external information about the vehicle acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform coordinated control intended for preventing glare by, for example, controlling the headlights to change from high beam to low beam according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0165] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying the vehicle occupants or the outside of the vehicle of information. Fig. 22 In the example of FIG. 1 , an audio speaker 12061, a display portion 12062, and a dashboard 12063 are shown as output devices. The display portion 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0166] Fig.73 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0167] exist Fig.73 In the figure, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104 and 12105.

[0168] The imaging units 12101, 12102, 12103, 12104 and 12105 are, for example, disposed at locations such as the front nose, rearview mirror, rear bumper, rear door and upper portion of the windshield inside the vehicle 12100. The imaging unit 12101 disposed at the front nose and the imaging unit 12105 disposed at the upper portion of the windshield inside the vehicle mainly acquire images in front of the vehicle 12100. The imaging units 12102 and 12103 disposed at the rearview mirror mainly acquire images on both sides of the vehicle 12100. The imaging unit 12104 disposed at the rear bumper or rear door mainly acquires images behind the vehicle 12100. The imaging unit 12105 disposed at the upper portion of the windshield inside the vehicle is mainly used to detect vehicles ahead, pedestrians, obstacles, signal lights, traffic signs or lanes, etc.

[0169] Notice, Fig.73 An example of the imaging ranges of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided at the rearview mirror. The imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 is obtained by superimposing the image data imaged by the imaging units 12101 to 12104.

[0170] At least one of the imaging units 12101 to 12104 may have a function for obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0171] For example, the microcomputer 12051 can determine the distance of each three-dimensional object within the imaging ranges 12111 to 12114 and the time change of the distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and extract the nearest three-dimensional object as the preceding vehicle, which is particularly present on the travel path of the vehicle 12100 and travels at a predetermined speed (e.g., equal to or greater than 0 km / h) in substantially the same direction as the vehicle 12100. In addition, the microcomputer 12051 can pre-set the following distance to be maintained in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. Therefore, it is possible to perform coordinated control for automatic driving so that the vehicle can travel automatically without relying on the operation of the driver, etc.

[0172] For example, the microcomputer 12051 can classify the three-dimensional object data of the three-dimensional object into two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually identified by the driver of the vehicle 12100 and obstacles that are difficult to be visually identified by the driver of the vehicle 12100. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. When the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver through the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering through the driving system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0173] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in the captured images of the imaging units 12101 to 12104. This pedestrian recognition is performed, for example, by the following process: a process of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras; and a process of determining whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so as to display a square contour line for emphasis superimposed on the identified pedestrian. In addition, the sound / image output unit 12052 may control the display unit 12062 so as to display an icon or the like indicating a pedestrian at a desired position.

[0174] An example of a vehicle control system to which the technology according to the present disclosure can be applied is described above. The technology according to the present disclosure can be applied to the imaging unit 12031 in the above-mentioned configuration. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to realize the imaging unit 12031 with a simpler configuration. <14. Other embodiments>

[0175] The present technology is not limited to the above-described embodiments, and various modifications may be made without departing from the gist of the present technology. For example, among the solid-state imaging devices according to the aforementioned first to twelfth embodiments, the solid-state imaging devices according to two or more embodiments may be combined.

[0176] In addition to imaging applications, the present technology can also be widely used in light receiving devices, photoelectric conversion devices, and light detection devices for sensing applications. In addition, in addition to using visible light incident light, solid-state imaging devices can also use, for example, infrared light, ultraviolet light, or electromagnetic wave incident light. In addition, the present technology can have any desired color filter or bandpass filter set on the light incident side above the photoelectric conversion element, and receive the desired incident light.

[0177] According to the first aspect of the present disclosure, a solid-state imaging device includes a low dielectric constant region located between a first gate electrode of a first transistor and a floating diffusion portion. As a result, the capacitance value of a parasitic capacitance in which the first gate electrode is used as one electrode, the low dielectric constant region is used as a dielectric, and the floating diffusion portion is used as another electrode can be reduced. In other words, the capacitance value of the parasitic capacitance added to the floating diffusion portion is reduced, and the difference in capacitance value can be reduced. Therefore, in the solid-state imaging device, signal differences and signal delays caused by parasitic capacitance can be suppressed.

[0178] The solid-state imaging device according to the second aspect of the present disclosure includes a low dielectric constant region located between the second gate electrode of the second transistor and the floating diffusion in the solid-state imaging device according to the first aspect. As a result, the capacitance value of the parasitic capacitance in which the second gate electrode is used as one electrode, the low dielectric constant region is used as a dielectric, and the floating diffusion is used as another electrode can be reduced. That is, the capacitance value of the parasitic capacitance added to the floating diffusion is reduced, so that the difference in capacitance value can be reduced. Therefore, in the solid-state imaging device, the signal difference and signal delay caused by the parasitic capacitance can be suppressed.

[0179] In the solid-state imaging device according to the third aspect of the present disclosure, the low dielectric constant region in the solid-state imaging device according to the first or second aspect is a gap. Thus, the low dielectric constant region 32 has a simple configuration, making it possible to easily reduce the capacitance value of the parasitic capacitance.

[0180] In the solid-state imaging device according to the fourth aspect of the present disclosure, the low dielectric constant region in the solid-state imaging device according to the first aspect or the second aspect is formed of a low dielectric constant material. Thus, the low dielectric constant region 32 has a simple structure, thereby being able to easily reduce the capacitance value of the parasitic capacitance. <Structure of this technology>

[0181] The present technology has the following configuration. According to the present technology having the following configuration, in a solid-state imaging device, signal variation and signal delay caused by parasitic capacitance can be suppressed. (1) A solid-state imaging device comprising: A first pixel provided on a first surface side of the substrate as a light incident side and including a first photoelectric conversion element that converts light into electric charges; A first transistor, which is provided on a second surface side of the substrate opposite to the first surface and located at a position corresponding to the first pixel, and includes a first gate electrode and a pair of main electrodes, one of the pair of main electrodes of the first transistor being electrically connected to the first photoelectric conversion element; a floating diffusion portion provided on the second surface side of the substrate and electrically connected to the other main electrode of the first transistor; and A low dielectric constant region is provided between the floating diffusion and the first gate electrode facing the floating diffusion and has a dielectric constant lower than a dielectric constant of a non-facing region. (2) The solid-state imaging device according to (1), further comprising: a second pixel disposed on the first surface side of the substrate and adjacent to the first pixel, and including a second photoelectric conversion element that converts light into electric charges; a second transistor provided on the second surface side of the substrate and located at a position corresponding to the second pixel, and including a second gate electrode and a pair of main electrodes, one of the pair of main electrodes of the second transistor being electrically connected to the second photoelectric conversion element and the other being electrically connected to the floating diffusion; and The low dielectric constant region is provided between the floating diffusion and the second gate electrode opposite to the floating diffusion. (3) The solid-state imaging device according to (2), further comprising: a pixel isolation region disposed in the substrate and located between the first pixel and the second pixel, and electrically and optically isolating the first pixel and the second pixel from each other; and a common contact portion, which is arranged on the second surface side of the substrate and overlaps the pixel isolation region, electrically connecting the other main electrode of the first transistor and the other main electrode of the second transistor to each other and to the floating diffusion portion, wherein: The low dielectric constant region is disposed between the first gate electrode and the common contact portion and between the second gate electrode and the common contact portion. (4) The solid-state imaging device according to (3), wherein The side surface of the common contact portion located on the first gate electrode side is formed in a shape that is away from the second surface of the substrate and approaches the first gate electrode, and The side surface of the common contact portion located on the second gate electrode side is formed in a shape that is away from the second surface of the base and approaches the second gate electrode. (5) The solid-state imaging device according to (3) or (4), wherein The pixel isolation region has a groove formed along a depth direction of the base, and an embedding member embedded in the groove. (6) According to the solid-state imaging device according to (3) or (4), the pixel isolation region includes an insulator region formed along a depth direction of the base. (7) The solid-state imaging device according to (3), wherein a part of the common contact portion is embedded in the base. (8) The solid-state imaging device according to any one of (1) to (7), wherein the low dielectric constant region includes a gap. (9) The solid-state imaging device according to (8), wherein a vacuum exists in the gap, or the gap is filled with air or an inert gas. (10) The solid-state imaging device according to any one of (1) to (7), wherein the low dielectric constant region is formed of a low dielectric constant material. (11) The solid-state imaging device according to (10), wherein the low dielectric constant material includes silicon oxide or carbon-doped silicon oxide. (12) The solid-state imaging device according to (2), wherein a side wall spacer is provided on a side surface of the non-opposing region of the first gate electrode and on a side surface of the non-opposing region of the second gate electrode. (13) The solid-state imaging device according to (12), wherein a dielectric constant of the low dielectric constant region is lower than a dielectric constant of the sidewall spacer. (14) The solid-state imaging device according to (2), further comprising a transistor of a pixel circuit, the transistor of the pixel circuit being located on the second surface side of the substrate corresponding to each of the first pixel and the second pixel, the pixel circuit processing the charge generated by the first photoelectric conversion element or the second photoelectric conversion element, wherein A sidewall spacer is provided on the sidewall of the gate electrode of the transistor.

[0182] This application claims the benefit of Japanese Priority Patent Application JP2022-160068 filed in the Japan Patent Office on October 4, 2022, the entire contents of which are incorporated herein by reference.

[0183] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

Claims

1. A solid-state imaging device, comprising: A first pixel provided on a first surface side of the substrate as a light incident side and including a first photoelectric conversion element that converts light into electric charges; A first transistor, which is provided on a second surface side of the substrate opposite to the first surface and located at a position corresponding to the first pixel, and includes a first gate electrode and a pair of main electrodes, one of the pair of main electrodes of the first transistor being electrically connected to the first photoelectric conversion element; a floating diffusion portion, which is provided on the second surface side of the substrate and is electrically connected to the other main electrode of the first transistor; as well as A low dielectric constant region is provided between the floating diffusion and the first gate electrode facing the floating diffusion and has a dielectric constant lower than a dielectric constant of a non-facing region.

2. The solid-state imaging device according to claim 1, further comprising: a second pixel disposed on the first surface side of the substrate and adjacent to the first pixel, and including a second photoelectric conversion element that converts light into electric charges; a second transistor provided on the second surface side of the substrate and located at a position corresponding to the second pixel, and including a second gate electrode and a pair of main electrodes, one of the pair of main electrodes of the second transistor being electrically connected to the second photoelectric conversion element and the other being electrically connected to the floating diffusion; as well as The low dielectric constant region is provided between the floating diffusion and the second gate electrode opposite to the floating diffusion.

3. The solid-state imaging device according to claim 2, further comprising: a pixel isolation region, which is disposed in the substrate and is located between the first pixel and the second pixel, and electrically and optically isolates the first pixel and the second pixel from each other; as well as a common contact portion, which is arranged on the second surface side of the substrate and overlaps the pixel isolation region, electrically connecting the other main electrode of the first transistor and the other main electrode of the second transistor to each other and to the floating diffusion portion, wherein: The low dielectric constant region is disposed between the first gate electrode and the common contact portion and between the second gate electrode and the common contact portion.

4. The solid-state imaging device according to claim 3, wherein The side surface of the common contact portion located on the first gate electrode side is formed into a shape that is close to the first gate electrode while being away from the second surface of the substrate, and the side surface of the common contact portion located on the second gate electrode side is formed into a shape that is close to the second gate electrode while being away from the second surface of the substrate.

5. The solid-state imaging device according to claim 3, wherein The pixel isolation region has a groove formed along a depth direction of the base, and an embedding member embedded in the groove.

6. The solid-state imaging device according to claim 3, wherein The pixel isolation region includes an insulator region formed along a depth direction of the substrate.

7. The solid-state imaging device according to claim 3, wherein: A portion of the common contact is embedded in the base body.

8. The solid-state imaging device according to claim 1, wherein The low dielectric constant region includes a gap.

9. The solid-state imaging device according to claim 8, wherein There is a vacuum in the gap, or the gap is filled with air or an inert gas.

10. The solid-state imaging device according to claim 1, wherein The low dielectric constant region is formed of a low dielectric constant material.

11. The solid-state imaging device according to claim 10, wherein The low dielectric constant material includes silicon oxide or carbon-doped silicon oxide.

12. The solid-state imaging device according to claim 2, wherein: Sidewall spacers are provided on sides of the non-opposing region of the first gate electrode and on sides of the non-opposing region of the second gate electrode.

13. The solid-state imaging device according to claim 12, wherein The low dielectric constant region has a lower dielectric constant than the sidewall spacer.

14. The solid-state imaging device according to claim 2, further comprising a transistor of a pixel circuit, the transistor of the pixel circuit being located on the second surface side of the substrate corresponding to each of the first pixel and the second pixel, the pixel circuit processing the charge generated by the first photoelectric conversion element or the second photoelectric conversion element, wherein A sidewall spacer is provided on the sidewall of the gate electrode of the transistor.

Images