On-chip metasurface and design method thereof

Abstract

The present application belongs to the field of micro-nano optical technology, and discloses a super-structured surface on a chip and a design method thereof. The unit structure of the super-structured surface on the chip comprises a substrate layer, a waveguide layer and a nano-pillar arranged on the working surface of the waveguide layer, the long axis and the short axis of the nano-pillar are parallel to the x-axis and the y-axis respectively, and the heights of all the nano-pillars contained in the super-structured surface on the chip are the same. A plurality of nano-pillars contained in the super-structured surface on the chip form one or more groups of nano-pillar arrays, the geometric sizes of all the nano-pillars contained in each group of nano-pillar arrays are the same, and the geometric sizes of the nano-pillars contained in different groups of nano-pillar arrays are different. For each group of nano-pillar arrays, light is incident on the waveguide layer in a transverse magnetic mode, the extraction efficiency of a certain target wavelength in the outgoing light is the highest and the extraction efficiency of other wavelengths is the lowest, and the geometric size of the nano-pillar in the group of nano-pillar arrays is determined. The present application can realize selective extraction of a certain wavelength range or a plurality of wavelength ranges.

Description

Technical Field

[0001] This invention belongs to the field of micro-nano optical technology, and more specifically, relates to on-chip metasurfaces and their design methods. Background Technology

[0002] Metasurfaces are artificially designed micro- and nano-scale periodic structures that can precisely manipulate electromagnetic waves by adjusting factors such as the shape and size of the surface structure and the physical properties of the material. This manipulative capability of metasurfaces enables the manipulation of light fields, thereby achieving high-resolution holographic imaging and encrypted transmission. The compact structure and relatively low fabrication difficulty of metasurfaces make them a promising candidate for applications in many optical fields, such as dynamic holographic displays, optical communication, and optical information encryption. Recently, integrating metasurfaces onto optical waveguides has become a compact platform for nanoscale waveguide manipulation, facilitating on-chip optical manipulation functions such as optical coupling / decoupling, focusing, and complex optical field engineering, including applications such as nanoprinting and meta-holography. Notably, on-chip displays based on metasurfaces benefit from the absence of zero-order diffraction, thereby enhancing image contrast and fidelity, making them highly promising for advanced display technologies.

[0003] Although the modulation capabilities of on-chip metasurfaces have been extensively studied, such as phase modulation, intensity modulation, and polarization modulation, most on-chip metasurfaces to date have exhibited broadband responses, providing similar optical performance at different wavelengths, making wavelength-selective extraction difficult. Summary of the Invention

[0004] This invention addresses the problem of wavelength-selective extraction that is difficult to achieve with on-chip metasurfaces in the prior art by providing on-chip metasurfaces and their design methods.

[0005] This invention provides a method for designing on-chip metasurfaces, comprising the following steps:

[0006] A unit structure for constructing an on-chip metasurface is provided. The unit structure includes a substrate layer, a waveguide layer located above the substrate layer, and a nanopillar disposed on the working surface of the waveguide layer. The x-axis and y-axis are defined as the directions parallel to two sides of the working surface, respectively. The major and minor axes of the nanopillar are parallel to the x-axis and y-axis, respectively. All nanopillars contained in the on-chip metasurface have the same height. The nanopillars contained in the on-chip metasurface constitute one or more nanopillar arrays. All nanopillars in each nanopillar array have the same geometric dimensions, while different types of nanopillar arrays contain nanopillars with different geometric dimensions.

[0007] Set the target wavelength of the on-chip metasurface; for each group of nanopillar arrays, light is incident from the waveguide layer in transverse magnetic mode, and the optimization target is to maximize the extraction efficiency of a certain target wavelength in the outgoing light and minimize the extraction efficiency of other wavelengths, and determine the geometric dimensions of the nanopillars in the group of nanopillar arrays.

[0008] Preferably, when the on-chip metasurface contains several nanopillars forming multiple nanopillar arrays, the multiple nanopillar arrays of different types are horizontally cascaded, and the on-chip metasurface selectively extracts guided waves of different wavelengths from different spatial locations into free space.

[0009] Preferably, the design method of the on-chip metasurface further includes: setting the target emission angle of the on-chip metasurface; and determining the working surface of the waveguide layer in the unit structure along the geometric dimensions P of the x-axis and y-axis. x and P y As a periodic parameter, the periodic parameter of each group of nanopillar arrays is determined based on the emission angle of a certain target.

[0010] Preferably, when determining the periodic parameters of the nanopillar array, the periodic parameters of the nanopillar array are calculated based on the grating formula and momentum superposition, with the goal that the emission angle of the -1st order light extracted by the nanopillar array is within the angle range that the microscope used for observation can receive.

[0011] Preferably, the on-chip metasurface comprises multiple arrays of nanopillars of different groups cascaded horizontally, and the design method of the on-chip metasurface further includes: acquiring a target color nanoprinting image, and determining the final arrangement of several nanopillars contained in the on-chip metasurface based on the intensity distribution of the binary target image of the target color nanoprinting image in different wavelength channels.

[0012] Preferably, each nanopillar contained in the on-chip metasurface is located at the center of its corresponding working surface.

[0013] Preferably, the design method of the on-chip metasurface further includes: acquiring a target holographic image; using the GS algorithm to obtain the phase distribution required for the on-chip metasurface based on the target holographic image; taking each unit structure as a pixel; taking the nanopillars located at the left edge of the working surface in the x-axis direction and at the midpoint of the working surface in the y-axis direction as the initial position; corresponding the phase recovered by each pixel with the displacement of each nanopillar along the x-axis direction; determining the displacement of each nanopillar along the x-axis direction; and obtaining the final arrangement of the nanopillars contained in the on-chip metasurface.

[0014] Preferably, the displacement of each nanopillar along the x-axis is determined by combining the detour phase, and the detour phase of light is extracted from the on-chip metasurface. The displacement Δx of the nanopillar along the x-axis satisfies the following equation: Where Λ represents the period, Λ = P x P x denoted as , representing the geometric dimensions of the working surface of the waveguide layer in the unit structure along the x-axis.

[0015] Preferably, the displacement of all nanopillars included in the on-chip metasurface along the y-axis is set to 0; or, the displacement of the odd-numbered nanopillars in the on-chip metasurface along the y-axis is set to 0, and the displacement of the even-numbered nanopillars in the on-chip metasurface along the y-axis is set to P. y Half of P y y represents the geometric dimensions of the working surface of the waveguide layer in the unit structure along the y-axis.

[0016] On the other hand, the present invention provides an on-chip metasurface, which is obtained by the above-described on-chip metasurface design method.

[0017] One or more technical solutions provided in this invention have at least the following technical effects or advantages:

[0018] (1) The unit structure of the on-chip metasurface provided by the present invention includes a substrate layer, a waveguide layer located above the substrate layer, and a nanopillar disposed on the working surface of the waveguide layer; the directions parallel to the two sides of the working surface are respectively taken as the x-axis and y-axis, the major axis and minor axis of the nanopillar are parallel to the x-axis and y-axis respectively, and all nanopillars contained in the on-chip metasurface have the same height; the nanopillars contained in the on-chip metasurface constitute one or more sets of nanopillar arrays, and all nanopillars contained in each set of nanopillar arrays have the same geometric dimensions, and the nanopillars contained in different sets of nanopillar arrays have different geometric dimensions; for each set of nanopillar arrays, light is incident from the waveguide layer in a transverse magnetic mode, and the extraction efficiency of a certain target wavelength in the outgoing light is the highest and the extraction efficiency of other wavelengths is the lowest as the optimization target, and the geometric dimensions of the nanopillars in the set of nanopillar arrays are determined. This invention enables selective extraction of a specific wavelength range or multiple wavelength ranges by adjusting the geometric dimensions of the nanopillar array. It utilizes the precise optical manipulation capabilities of on-chip metasurfaces to achieve wavelength selective extraction. When multiple different types of nanopillar arrays are horizontally cascaded on the on-chip metasurface, wavelength division multiplexing and wavelength selective extraction are achieved.

[0019] (2) In order to further ensure that the correct color can be observed after wavelength selective extraction is achieved, the present invention also sets the target emission angle of the on-chip metasurface and determines the period parameters of the nanopillar array for each group of nanopillar arrays based on a certain target emission angle.

[0020] (3) When the on-chip metasurface provided by this invention comprises multiple nanopillar arrays of different groups horizontally cascaded, after determining the geometric dimensions of the nanopillars, this invention can further determine the final arrangement of several nanopillars contained in the on-chip metasurface based on the intensity distribution of the binary target image of the target color nanoprinting image in different wavelength channels. That is, this invention can also set the arrangement of the nanopillar array to a specific target image, extract light to form a color nanoprinting image, and utilize the on-chip metasurface to achieve high-performance color near-field nanoprinting image function.

[0021] (4) After determining the geometric dimensions of the nanopillars, the present invention can further use the GS algorithm based on the target holographic image to obtain the phase distribution required for the on-chip metasurface, taking each unit structure as a pixel point, to obtain the final arrangement of several nanopillars contained in the on-chip metasurface. That is, the present invention can also realize high-performance far-field holographic images and AR displays. Attached Figure Description

[0022] Figure 1 This is a functional schematic diagram of the on-chip metasurface provided by the present invention;

[0023] Figure 2 This is a schematic diagram of the unit structure in the on-chip metasurface provided by the present invention;

[0024] Figure 3 This is a graph showing the experimental results of the relationship between the geometric dimensions of the nanopillars and the wavelength selectivity in Example 1 of this invention;

[0025] Figure 4 This is a graph showing the experimental results of the relationship between the periodic parameters and wavelength selectivity of the unit structure in Embodiment 1 of the present invention;

[0026] Figure 5 This is a schematic diagram of the experimental test optical path for the color nanoprinted image provided in Embodiment 3 of the present invention;

[0027] Figure 6 These are partial scanning electron microscope images and corresponding spectra of nanoprinted images with different wavelength selectivity manufactured in Embodiment 3 of the present invention;

[0028] Figure 7 This is an experimental result diagram of the near-field color nanoprinted image achieved in Embodiment 3 of the present invention;

[0029] Figure 8 This is a flowchart of the design of a nanopillar array using a four-step detour phase in Embodiment 5 of the present invention;

[0030] Figure 9 This is a partial scanning electron microscope image of the on-chip metasurface manufactured in Embodiment 5 of the present invention;

[0031] Figure 10 This is a schematic diagram of the experimental optical path for the far-field color holographic display function provided in Embodiment 5 of the present invention;

[0032] Figure 11 This is an experimental result diagram of the two-wavelength color holographic display achieved in Embodiment 5 of the present invention;

[0033] Figure 12 This is a schematic diagram of the experimental device used for AR display shooting in Embodiment 5 of the present invention;

[0034] Figure 13 This is a diagram showing the AR display implementation result of Embodiment 5 of the present invention. Detailed Implementation

[0035] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0036] A functional schematic diagram of the on-chip metasurface provided by this invention is shown below. Figure 1 As shown, nanoprinting and holographic images can achieve wavelength-selective extraction, wavelength division multiplexing, and color routing. Several embodiments are described below.

[0037] Example 1:

[0038] Example 1 provides a method for designing an on-chip metasurface, comprising the following steps:

[0039] Step 1: Construct the unit structure of the on-chip metasurface.

[0040] See Figure 2 The unit structure includes a substrate layer, a waveguide layer located above the substrate layer, and a nanopillar disposed on the working surface of the waveguide layer; the directions parallel to the two sides of the working surface are respectively taken as the x-axis and y-axis, and the major axis L and minor axis W of the nanopillar are parallel to the x-axis and y-axis, respectively. All nanopillars contained in the on-chip metasurface have the same height H; the nanopillars contained in the on-chip metasurface constitute one or more sets of nanopillar arrays, and all nanopillars contained in each set of nanopillar arrays have the same geometric dimensions. Different sets of nanopillar arrays contain nanopillars with different geometric dimensions.

[0041] Step 2: Use electromagnetic simulation tools to optimize the parameters of the unit structure of the on-chip metasurface.

[0042] Set the target wavelength of the on-chip metasurface; for each group of nanopillar arrays, light is incident from the waveguide layer in transverse magnetic mode, and the optimization target is to maximize the extraction efficiency of a certain target wavelength in the outgoing light and minimize the extraction efficiency of other wavelengths, and determine the geometric dimensions of the nanopillars in the group of nanopillar arrays.

[0043] In this context, when the on-chip metasurface comprises multiple nanopillar arrays, these arrays of different types are horizontally cascaded. The on-chip metasurface selectively extracts guided waves of different wavelengths from different spatial locations into free space. (See [link to relevant documentation]). Figure 1 .

[0044] Furthermore, to further ensure that the correct color can be observed after wavelength-selective extraction, the design method of the on-chip metasurface may also include:

[0045] Step 3: Set the target emission angle of the on-chip metasurface; set the working surface of the waveguide layer in the unit structure along the geometric dimensions P of the x-axis and y-axis. x and P y As a periodic parameter, see Figure 2 For each group of nanopillar arrays, the periodic parameters of the nanopillar arrays are determined based on the emission angle of a certain target.

[0046] Specifically, when determining the periodic parameters of this nanopillar array, the target is that the exit angle of the -1st order light extracted by this nanopillar array is within the angle range that the microscope used for observation can receive. The periodic parameters of this nanopillar array are calculated according to the grating formula and momentum superposition. That is, the periodic parameters are mainly determined based on the exit angle. The period of the working surface of the unit structure is determined by calculating the structural period corresponding to the intensity of the scattered light observed within the set observation angle range.

[0047] The substrate layer can be a fused silica substrate layer (i.e., a SiO2 substrate layer), the waveguide layer can be a silicon nitride waveguide layer (i.e., a Si3N4 band layer), and the nanopillars can be micro / nano silicon nanopillars, which can be fabricated using techniques such as electron beam lithography, thermal evaporation, and reactive ion etching. That is, the on-chip metasurface consists of a structural layer, a waveguide layer, and a substrate layer from top to bottom. Both the entire substrate layer and the entire waveguide layer are divided into multiple periodic unit structures of uniform size. The entire structural layer includes several nanopillars. All nanopillars contained in the on-chip metasurface have the same height, for example, from 350 nm to 380 nm.

[0048] The length, width, and period parameters of the nanopillars in the on-chip metasurface provided in Example 1 can be designed. Nanopillar arrays with different size parameters have different wavelength selectivity, which can realize the demultiplexing function of wavelength division multiplexing.

[0049] Specifically, Figure 3 This is a graph showing the experimental results of the relationship between the geometric dimensions and wavelength selectivity of the nanopillars actually fabricated in Example 1. Figure 3 The left image shows the optical image of the structural color change corresponding to the stepwise scanning of the length and width of the nanopillar. Figure 3 The right figure shows the spectra corresponding to four selected structures that are selective for different wavelengths.

[0050] Figure 4 The figure shows the experimental results of the relationship between the periodic parameters and wavelength selectivity of the unit structure in Example 1. Figure 4 (a) in the text represents the period of changing the x-axis direction (i.e., P). x The spectrum corresponding to the structure, Figure 4 (b) in the diagram represents the period of changing the y-axis direction (i.e., P). y The spectrum corresponding to the structure, Figure 4 (c) in the image shows the optical images of the structures with periods increasing along the x-axis under simultaneous incident red and green wavelengths. Figure 4 In the image (d), the optical image of the structure corresponding to the period from small to large along the y-axis is the result of simultaneous incident red and green wavelengths.

[0051] In summary, the on-chip metasurface provided in Example 1 can selectively extract guided waves of different wavelength components and perform wavelength division multiplexing of visible light after incident transverse magnetic mode light beams. That is, under transverse magnetic mode guided wave incidence, the wavelength selectivity generated by the micro / nano structure layers of the on-chip metasurface enables the specific extraction of different wavelength components. By laterally cascading (i.e., horizontally cascading) micro / nano structures with different dimensional parameters, the demultiplexing function of wavelength division multiplexing can be achieved.

[0052] Example 2:

[0053] Example 2 provides an on-chip metasurface, which is obtained using the on-chip metasurface design method provided in Example 1.

[0054] Building upon Example 1, by arranging the nanopillar array to resemble a specific target image and observing it within a specific viewing angle range, the extracted light forms a nanoprinted image. Holographic image display and Augmented Reality (AR) can be achieved using detour phase encoding. For example, when observing with a microscope, the microscope's numerical aperture (NA) is used as the viewing angle. When designing the on-chip metasurface, it is ensured that the exit angle of the -1st order light extracted by the nanopillar array is within the angle range that the microscope can receive, thus ensuring that the correct color can be observed. Examples 3 to 6 are described below.

[0055] Example 3:

[0056] Example 3 provides a design method for an on-chip metasurface. The on-chip metasurface in Example 3 comprises a horizontally cascaded array of multiple nanopillars of different groups. The design method provided in Example 3, based on Example 1, further includes: acquiring a target color nanoprinting image, and determining the final arrangement of several nanopillars contained in the on-chip metasurface according to the intensity distribution of the binary target image of the target color nanoprinting image in different wavelength channels.

[0057] Specifically, the binary in the binary target image means that each color image has only two intensities, 0 and 1, and does not involve the grayscale design of the image. 0 and 1 correspond to whether or not a nanopillar is placed at the corresponding position. That is, in Example 3, a nanopillar is placed at the position corresponding to intensity 1, and no nanopillar is placed at the position corresponding to intensity 0. The area where the nanopillar is placed constitutes the target color nanoprinted image.

[0058] The design method for on-chip metasurfaces provided in Example 3 includes: constructing the unit structure of the on-chip metasurface, optimizing the parameters of the unit structure of the on-chip metasurface, determining the periodic parameters, and determining whether to place nanopillars in the unit structure for each pixel based on the target color nanoprinted image.

[0059] Each nanopillar contained in the on-chip metasurface is located at the center of its corresponding working surface.

[0060] A laser and a polarizer are sequentially placed in front of the on-chip metasurface provided in Example 3, allowing the observation of a target color nanoprinted image using a microscope. For example, Figure 5 This is a schematic diagram of the experimental test optical path for near-field nanoprinting images. The red and green wavelength beams are incident from the laser onto the waveguide layer of the on-chip metasurface, and the on-chip metasurface is observed using a microscope system (composed of an objective lens, a lens, and a CCD camera).

[0061] Figure 6 Local scanning electron microscope images and corresponding spectra of three nanopillar structures with different wavelength selectivity produced by this invention are shown; among them, Figure 6 The first row corresponds to the red structure in the design (corresponding to a wavelength of 650nm). Figure 6 The second row corresponds to the designed green structure (corresponding to a wavelength of 575nm). Figure 6 The third row corresponds to the traditional non-wavelength selective structure (this structure is used as a contrast structure, which does not have specific wavelength selectivity and is used to indicate that the spectral response of the ordinary structure design is broadband. The broadband response corresponds to the simultaneous extraction of red and green wavelengths, which will result in an orange image). Figure 6 The left-hand image in each row is a partial scanning electron microscope image of the structure. Figure 6 The image on the right side of each row is the spectrum of the structure.

[0062] Figure 7 This is an experimental result of near-field color nanoprinting achieved by the present invention, with a scale bar of 40 μm; Figure 7 The first row corresponds to the target image. Figure 7 The second row corresponds to the experimental image. Figure 7 The nanoprinted images shown exhibit good on-chip wavelength division multiplexing effect: (1) Under green light only, the green leaf and flower pot patterns are strongly extracted, while the red flower is weakly extracted and darker; (2) Under red light only, the red flower and flower pot patterns are bright, while the green leaf is dark; (3) Under green and red light simultaneously, the obtained image reconstructs the image combination of red flower, green leaf and orange pot.

[0063] The above experimental results confirm the application and good effect of the on-chip metasurface provided by the present invention in nanoprinted image display.

[0064] Example 4:

[0065] Example 4 provides an on-chip metasurface, which is obtained using the on-chip metasurface design method provided in Example 3.

[0066] Example 5:

[0067] Example 5 provides a design method for an on-chip metasurface, which, based on Example 1, further includes: acquiring a target holographic image; using the GS algorithm to obtain the phase distribution required for the on-chip metasurface based on the target holographic image; treating each unit structure as a pixel; taking the nanopillars located at the left edge of the working surface in the x-axis direction and at the midpoint of the working surface in the y-axis direction as the initial position; corresponding the phase recovered by each pixel with the displacement of each nanopillar along the x-axis direction; determining the displacement of each nanopillar along the x-axis direction; and obtaining the final arrangement of the nanopillars contained in the on-chip metasurface.

[0068] Specifically, the displacement of each nanopillar along the x-axis is determined by combining the detour phase, and the detour phase of light is extracted from the on-chip metasurface. The displacement Δx of the nanopillar along the x-axis satisfies the following equation: Where Λ represents the period, Λ = P x P x denoted as , representing the geometric dimensions of the working surface of the waveguide layer in the unit structure along the x-axis.

[0069] In addition, the displacement of several nanopillars contained in the on-chip metasurface along the y-axis can be set to 0.

[0070] Alternatively, the displacement of the odd-numbered columns of nanopillars in the on-chip metasurface along the y-axis can be set to 0, and the displacement of the even-numbered columns of nanopillars in the on-chip metasurface along the y-axis can be set to P. y Half of P y This represents the geometric dimension of the working surface of the waveguide layer in the unit structure along the y-axis. This design method can prevent the nanopillars from sticking together during actual fabrication.

[0071] The design method for on-chip metasurfaces provided in Example 5 includes: constructing the unit structure of the on-chip metasurface, optimizing the parameters of the unit structure of the on-chip metasurface, determining the periodic parameters, and determining the displacement of each nanopillar based on the target holographic image.

[0072] For example, this invention successfully achieved wavelength-selective far-field holography at incident wavelengths of 520 nm and 620 nm by utilizing the coding degrees of freedom provided by the on-chip detour phase. The detour phase of the light extracted by the on-chip metasurface can be expressed as... Where Δx represents the relative displacement of the nanopillar within one period Λ, and let Λ = P x =P y =380nm. The target image was designed, and the Gerchberg-Saxton (GS) algorithm was used to calculate the phase design of the metasurface. The structural size of the nanopillars was determined based on the target color. Based on the obtained phase distribution, the recovered phase of each pixel was calculated to correspond one-to-one with the relative displacement of the nanopillar center position within the unit structure, achieving a four-step detour phase design and obtaining the final arrangement of the nanopillars. See [link to documentation]. Figure 8 .

[0073] Figure 9 These are partial scanning electron microscope images of on-chip metasurface holographic display structures with different wavelength selectivity fabricated according to the present invention, wherein... Figure 9 The image on the left is a partial scanning electron microscope image of the green structure. Figure 9 The image on the right is a partial scanning electron microscope image of the red structure.

[0074] Figure 10 This is a schematic diagram of the experimental optical path for the far-field color holographic display function provided by the present invention. By combining a laser, aperture, polarizer, lens, and receiving screen (e.g., a mobile phone placed in the far field to record the displayed holographic image), far-field color holographic display can be achieved. Specifically, the polarized laser is coupled into the waveguide in an end-fire manner, and the projected holographic image is directly captured using the mobile phone camera.

[0075] When the sample is simultaneously illuminated with green and red light, the target images of the designed "cactus" and "sun" holograms are as follows: Figure 11 As shown. That is Figure 11This image shows the experimental results of the two-wavelength color holographic display achieved by this invention. Furthermore, due to its high transparency and zero-order diffraction-free all-dielectric structure, the on-chip metasurface provided by this invention can be integrated with wearable devices for AR displays. See also the image of a virtual image floating in the real world captured by a mobile phone camera. Figure 12 , Figure 12 It also includes experimental equipment for AR display photography. Figure 13 This is a diagram showing the AR display implementation result of the present invention. Figure 13 You can clearly observe the "cactus" floating against the desert background or the "sun" floating against the mountain background, presenting distinguishable image lines and color contrast.

[0076] The above experimental results confirm the application and good effect of the on-chip metasurface provided by the present invention in holographic image display and enhanced display.

[0077] Example 6:

[0078] Example 6 provides an on-chip metasurface, which is obtained using the on-chip metasurface design method provided in Example 5.

[0079] In summary, this invention utilizes the precise optical manipulation capabilities of on-chip metasurfaces to achieve wavelength-selective extraction from these surfaces. It also inherits the ease of integration and lack of zero-order diffraction interference inherent in on-chip metasurfaces, enabling high-performance color near-field nanoprinted images, far-field holographic images, and AR displays. Furthermore, this invention addresses the low energy efficiency of traditional free-space devices that achieve wavelength multiplexing through spatial multiplexing in color displays, achieving a superior energy utilization and allocation strategy. The on-chip cascaded wavelength selection method provided by this invention offers a new paradigm for research in photonic integrated circuits, wearable microdisplays, and next-generation wavelength division multiplexing devices, laying the foundation for these studies. This on-chip wavelength division multiplexing and wavelength-selective meta-optical platform, with its advantages of miniaturization and integration, is expected to find widespread application in various fields such as next-generation wearable display devices, multiplexing and routing of multiplexed information, and intelligent integrated photonic systems.

[0080] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for designing on-chip metasurfaces, characterized in that, Includes the following steps: A unit structure for constructing an on-chip metasurface is provided. The unit structure includes a substrate layer, a waveguide layer located above the substrate layer, and a nanopillar disposed on the working surface of the waveguide layer. The x-axis and y-axis are defined as the directions parallel to two sides of the working surface, respectively. The major and minor axes of the nanopillar are parallel to the x-axis and y-axis, respectively. All nanopillars contained in the on-chip metasurface have the same height. The nanopillars contained in the on-chip metasurface constitute one or more nanopillar arrays. All nanopillars in each nanopillar array have the same geometric dimensions, while different types of nanopillar arrays contain nanopillars with different geometric dimensions. Set the target wavelength of the on-chip metasurface; for each group of nanopillar arrays, light is incident from the waveguide layer in transverse magnetic mode, and the optimization target is to maximize the extraction efficiency of a certain target wavelength in the outgoing light and minimize the extraction efficiency of other wavelengths, and determine the geometric dimensions of the nanopillars in the group of nanopillar arrays. Set the target emission angle of the on-chip metasurface; define the working surface of the waveguide layer in the unit structure along the geometric dimensions P of the x-axis and y-axis. x and P y As a periodic parameter; for each group of nanopillar arrays, the periodic parameter of the group of nanopillar arrays is determined according to a certain target emission angle; when determining the periodic parameter of the group of nanopillar arrays, the target is that the emission angle of the -1st order light extracted by the group of nanopillar arrays is within the angle range that the microscope used for observation can receive, and the periodic parameter of the group of nanopillar arrays is calculated according to the grating formula and momentum superposition. When the on-chip metasurface contains several nanopillars that form multiple nanopillar arrays, multiple nanopillar arrays of different types are horizontally cascaded. The on-chip metasurface selectively extracts guided waves of different wavelengths from different spatial locations into free space, realizing wavelength division multiplexing and wavelength selective extraction.

2. The design method for on-chip metasurfaces according to claim 1, characterized in that, The on-chip metasurface comprises horizontally cascaded arrays of multiple different groups of nanopillars, and the design method of the on-chip metasurface further includes: Obtain a target color nanoprinting image, and determine the final arrangement of several nanopillars contained in the on-chip metasurface based on the intensity distribution of the binary target image in different wavelength channels of the target color nanoprinting image.

3. The design method for on-chip metasurfaces according to claim 2, characterized in that, Each nanopillar contained in the on-chip metasurface is located at the center of its corresponding working surface.

4. The design method for on-chip metasurfaces according to claim 1, characterized in that, The design method for the on-chip metasurface also includes: A target holographic image is acquired. Based on the target holographic image, the GS algorithm is used to obtain the phase distribution required for the on-chip metasurface. Each unit structure is taken as a pixel. The initial position of the nanopillar is taken as the left edge of the working surface in the x-axis direction and the midpoint of the working surface in the y-axis direction. The phase recovered by each pixel is calculated and matched one-to-one with the displacement of each nanopillar in the x-axis direction. The displacement of each nanopillar in the x-axis direction is determined, and the final arrangement of the nanopillars contained in the on-chip metasurface is obtained.

5. The design method for on-chip metasurfaces according to claim 4, characterized in that, By combining the detour phase to determine the displacement of each nanopillar along the x-axis, the on-chip metasurface extracts the detour phase of light. Displacement of the nanopillar along the x-axis Satisfy the following formula: ;in, Indicates period, P x denoted as , representing the geometric dimensions of the working surface of the waveguide layer in the unit structure along the x-axis.

6. The design method for on-chip metasurfaces according to claim 4, characterized in that, The displacement of all nanopillars included in the on-chip metasurface along the y-axis is set to 0; or, the displacement of the odd-numbered nanopillars in the on-chip metasurface along the y-axis is set to 0, and the displacement of the even-numbered nanopillars in the on-chip metasurface along the y-axis is set to P. y Half of P y y represents the geometric dimensions of the working surface of the waveguide layer in the unit structure along the y-axis.

7. An on-chip metasurface, characterized in that, It is obtained by using the design method of on-chip metasurface as described in any one of claims 1-6.

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