High-precision LDO circuit with low noise and high transient enhancement capability

Abstract

The application relates to a high-precision LDO circuit with low noise and high transient enhancement capability. The LDO circuit comprises an LDO circuit body, a reference voltage generation unit for providing a reference voltage required when the LDO circuit body works, a band-gap reference for generating a reference voltage, and an accurate low-pass filter for anti-noise processing of the reference voltage. When the reference voltage is subjected to the anti-noise processing, at least voltage buffering processing and low-pass filtering processing are sequentially performed, and a corresponding reference buffer voltage is generated after the reference voltage is subjected to the voltage buffering processing. When the generated reference buffer voltage is subjected to the low-pass filtering processing, at least power supply noise and / or ground bounce interference of the reference buffer voltage are removed, so that a corresponding reference voltage is generated after the low-pass filtering processing, and the generated reference voltage is loaded to the LDO circuit body. The application has higher anti-noise capability and transient enhancement capability, and improves the precision and stability of an output voltage.

Description

Technical Field

[0001] This invention relates to an LDO circuit, and more particularly to a high-precision LDO circuit with low noise and high transient enhancement capability. Background Technology

[0002] Compared to DC-DC switching regulators, low-dropout regulators (LDOs) have the characteristics of small area and low voltage ripple, and have been widely used in portable electronic devices to provide high-quality voltage sources for other chips.

[0003] As high-performance chips such as FPGAs (Field Programmable Gate Arrays), CPUs (Central Processing Units), and GPUs (Graphics Processing Units) employ increasingly advanced manufacturing processes (7nm~3nm) and higher frequencies, the requirements for the accuracy, transient performance, and stability of voltage sources are also becoming increasingly stringent. For example, the SERDES interface circuit integrated on mainstream domestic billion-gate FPGAs has a transmission rate of 32Gbps. Its internal digital circuit operates at a voltage of 0.9V, and its analog circuit operates at a voltage of 1.2V, with an accuracy deviation of less than ±5%, and it also possesses strong load transient response speed and relatively high noise immunity.

[0004] One of the key technical challenges in designing LDO circuits is achieving high stability and fast transient response under conditions of significant load current differences. Therefore, improving the noise immunity and transient response enhancement capabilities of LDO circuits, as well as enhancing the accuracy of the power supply they provide, are pressing technical challenges that need to be addressed. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a high-precision LDO circuit with low noise and high transient enhancement capability, which has high noise immunity and transient enhancement capability, and improves the accuracy and stability of the output voltage.

[0006] According to the technical solution provided by the present invention, a high-precision LDO circuit with low noise and high transient enhancement capability is provided, the LDO circuit comprising: LDO circuit body; The reference voltage generation unit provides the reference voltage required for the LDO circuit to operate. It includes a bandgap reference for generating the reference voltage and a precision low-pass filter for noise suppression of the reference voltage. When performing noise reduction processing on the reference voltage, it includes at least sequential voltage buffering and low-pass filtering. After voltage buffering of the reference voltage, a corresponding reference buffer voltage is generated. When performing low-pass filtering on the generated reference buffer voltage, at least the power supply noise and / or ground bounce interference of the reference buffer voltage are removed so that a corresponding reference voltage is generated after low-pass filtering, and the generated reference voltage is applied to the LDO circuit body.

[0007] The LDO circuit body includes an error amplifier, a drive buffer, a power transistor circuit, and a voltage feedback circuit, wherein... The reference voltage generated by the reference voltage generation unit is applied to the non-inverting input of the error amplifier. The output of the error amplifier is connected to the drive buffer, and the output of the drive buffer is connected to the gate of the power PMOS transistor in the power transistor circuit, so as to apply the drive voltage VG to the gate of the power PMOS transistor through the drive buffer. The drain terminal of the power PMOS transistor is connected to a voltage feedback circuit to feed back the operating sampling voltage to the inverting input of the error amplifier. The junction between the drain terminal of the power PMOS transistor and the voltage feedback circuit forms the circuit body output terminal of the LDO circuit body.

[0008] It also includes a transient response detection enhancement circuit for transient response detection and enhancement, wherein, The transient response detection enhancement circuit is adapted to the output terminal of the LDO circuit body and the drive buffer to load the output voltage VOUT and drive voltage VG of the LDO circuit body output terminal onto the transient response detection enhancement circuit. Based on the output voltage VOUT, the transient response detection enhancement circuit detects the transient response of the LDO circuit itself, wherein... When a transient response change in the LDO circuit body is detected, the transient response detection enhancement circuit generates a corresponding transient response enhancement signal and loads the transient response enhancement signal into the drive buffer. The drive buffer is then configured to adjust the output drive voltage VG based on the current transient response enhancement signal, so that the output voltage VOUT of the LDO circuit body remains stable. Based on the adjusted drive voltage VG from the drive buffer, the transient response enhancement signal generated by the transient response detection enhancement circuit is controlled to ensure that the transient response enhancement signal generated by the transient response detection enhancement circuit remains stable after transient response enhancement.

[0009] The transient response detection and enhancement circuit includes a voltage detection and control circuit and a transient response enhancement signal generation circuit adapted and connected to the voltage detection and control circuit, wherein... The voltage detection and control circuit is connected to both the output voltage VOUT and the drive voltage VG. The transient response enhancement signal generation circuit generates a transient response enhancement signal and loads the generated transient response enhancement signal into the drive buffer; When the transient response state is determined based on the output voltage VOUT, the voltage detection and control circuit generates a voltage detection and control signal that is adapted to the current transient response state, and loads the voltage detection and control signal into the transient response enhancement signal generation circuit, so as to configure the transient response enhancement signal generation circuit to control the generated transient response enhancement signal in the direction of transient response change. Based on the adjusted drive voltage VG from the drive buffer, the voltage detection and control circuit generates a voltage detection and control signal adapted to the current drive voltage VG, and loads the voltage detection and control signal onto the transient response enhancement signal generation circuit, so as to configure the transient response enhancement signal generation circuit to control the generated transient response enhancement signal in the opposite direction of the drive voltage change. When regulating the transient response enhancement signal generated by the transient response enhancement signal generation circuit, the direction of transient response change is consistent with the direction of driving voltage change.

[0010] The voltage detection and control circuit includes a PMOS transistor P25 and an NMOS transistor N21, wherein, The source terminal of PMOS transistor P25 is connected to the output voltage VOUT through resistor R19. The gate terminal of PMOS transistor P25 is connected to the drain terminal of PMOS transistor P25, the drain terminal of NMOS transistor N21, and the gate terminal of PMOS transistor P26. The source terminal of NMOS transistor N21 is grounded. The gate terminal of NMOS transistor N21 is connected to the gate terminal of NMOS transistor N22, the drain terminal of NMOS transistor N22, and the drain terminal of PMOS transistor P26. The gate terminal of NMOS transistor N21, the gate terminal of NMOS transistor N22, the drain terminal of NMOS transistor N22, and the drain terminal of PMOS transistor P26 are interconnected to form the output connection terminal of the voltage detection and control circuit. The source terminal of PMOS transistor P26 is connected to the drain terminal of PMOS transistor P27 through resistor R20. The gate terminal of PMOS transistor P27 is connected to the drive voltage VG, and the source terminal of PMOS transistor P27 is connected to the power supply VDD. The source terminal of NMOS transistor N22 is grounded. The transient response enhancement signal generation circuit includes PMOS transistor P28, PMOS transistor P29, and NMOS transistor N23, wherein... The source terminal of PMOS transistor P28 is connected to the power supply VDD. The drain terminal of PMOS transistor P28 is connected to the source terminal of PMOS transistor P29, and the drain terminal of PMOS transistor P29 is connected to the drain terminal of NMNOS transistor N23, forming the output connection terminal of the transient response enhancement signal generation circuit. The source terminal of NMOS transistor N23 is grounded, and the gate terminal of NMOS transistor N23 is connected to the output terminal of the voltage detection and control circuit. The gate of PMOS transistor P28 is connected to the bias voltage VBP0, and the gate of PMOS transistor P29 is connected to the bias voltage VBP1.

[0011] It also includes a dynamic frequency compensation circuit for frequency compensation of the LDO circuit body, wherein, The dynamic frequency compensation circuit includes a Miller structure frequency compensation unit and a load current compensation unit that performs dynamic frequency compensation based on load current. The Miller structure frequency compensation unit is adapted to the output terminal of the circuit body and the inverting terminal of the error amplifier, so as to push the pole of the inverting terminal of the error amplifier to a low frequency using the Miller structure frequency compensation unit. The load current compensation unit includes a frequency compensation variable resistor unit, which is adapted and connected to the Miller structure frequency compensation unit. The resistance value of the frequency compensation variable resistor unit is configured based on the driving voltage VG so that the resistance value of the frequency compensation variable resistor is adapted to the load current. After configuring the resistance value of the frequency compensation variable resistor using the driving voltage VG, loop frequency compensation is performed on the LDO circuit body based on the frequency compensation variable resistor unit and the Miller structure compensation unit.

[0012] The bandgap reference includes a bandgap operational amplifier circuit and a zero-temperature-drift reference voltage output unit connected in sequence. The bandgap operational amplifier circuit adopts a gain-bootstrapping operational amplifier circuit; The zero-temperature-drift reference voltage output unit includes a zero-temperature-drift reference voltage generation unit and a reference voltage adjustment unit adapted and connected to the zero-temperature-drift reference voltage generation unit. The zero-temperature-drift reference voltage generation unit within the zero-temperature-drift reference voltage output unit is adapted and connected to the bandgap operational amplifier circuit. The zero-temperature-drift reference voltage generation unit generates a reference voltage difference, which is then converted into a corresponding zero-temperature-drift basic voltage by a bandgap operational amplifier circuit. The zero-temperature-drift base voltage is adjusted using a reference voltage adjustment unit to generate a reference voltage after adjustment.

[0013] The reference voltage adjustment unit includes several current adjustment units based on current adjustment, wherein the current adjustment unit includes a current adjustment main unit and an adjustment reset control signal generation unit adapted and connected to the current adjustment main unit. When performing current adjustment based on the current adjustment unit, pre-adjustment is first performed using the main current adjustment unit, followed by post-adjustment. During pre-adjustment, the pre-adjustment data is loaded into the current adjustment master unit so that the current adjustment master unit generates a pre-adjustment status signal corresponding to the pre-adjustment data. Based on the pre-adjustment state signal generated by the pre-adjustment, the current adjustment target state signal of the current adjustment master unit during the post-adjustment is determined, wherein the state of the current adjustment target state signal is an adjustment effective state or an adjustment ineffective state. During post-adjustment, based on the current adjustment target state signal, the target adjustment data is loaded into the current adjustment main unit, and the corresponding current adjustment target state signal is output through the current adjustment unit. Furthermore, a dual-mode adjustment state signal is formed based on the current adjustment target state signal. When the current adjustment target status signal is in the adjustment active state, the polycrystalline fuse in the current adjustment main unit is blown by current blowing based on the current adjustment target status signal and the adjustment enable signal in the active state, so as to lock the current adjustment target status signal output by the current adjustment main unit after the polycrystalline fuse blows. After the current trimming unit is powered on again, the trimming reset control signal generation unit generates a trimming reset control signal so that the current trimming master unit configures the generated trimming status signal as the corresponding current trimming target status signal under the trimming reset control signal.

[0014] The precise low-pass filter includes a voltage buffer device for performing voltage buffering processing and a low-pass filter for performing low-pass filtering processing, wherein... The voltage buffer includes a PMOS transistor P8 that receives a reference voltage. The source terminal of PMOS transistor P8 is connected to the source terminal of PMOS transistor P9 and the drain terminal of PMOS transistor P7. The source terminal of PMOS transistor P7 is connected to the drain terminal of PMOS transistor P6. The drain terminal of PMOS transistor P8 is connected to the drain terminal of NMOS transistor N6, the gate terminal of NMOS transistor N6, and the gate terminal of NMOS transistor N7. The source terminal of NMOS transistor N6 is grounded through resistor R9, and the source terminal of NMOS transistor N7 is grounded through resistor R10. The drain of NMOS transistor N7 is connected to the drain of PMOS transistor P9 and the gate of NMOS transistor N9. The source of NMOS transistor N9 is grounded through resistor R11. The drain of NMOS transistor N9 is connected to the source of NMOS transistor N8, the gate of PMOS transistor P10, and the gate of PMOS transistor P12. The drain of NMOS transistor N8 is connected to the drain of PMOS transistor P11. The source of PMOS transistor P11 is connected to the drain of PMOS transistor P10. The drain of PMOS transistor P12 is connected to the source of PMOS transistor P13. The drain of PMOS transistor P13 is connected to one end of resistor R12. The other end of resistor R12 is connected to the gate of PMOS transistor P9, one end of resistor R13, and the low-pass filter adapter. The other end of resistor R13 is connected to the voltage buffer trimming unit adapter. The source terminals of PMOS transistors P6, P10, and P12 are all connected to the power supply VDD.

[0015] The error amplifier includes a rail-to-rail input stage and a high-gain output stage, wherein... The error amplifier rail-to-rail input stage receives the reference voltage and is adapted to the drive buffer through the error amplifier high-gain output stage; The error amplification rail-to-rail input stage includes a reference voltage receiver and a sampling voltage receiver. The reference voltage is applied to the reference voltage receiver, and the working sampling voltage is applied to the sampling voltage receiver. The reference voltage receiving section includes an NMOS transistor N12, a PMOS transistor P21, and an NMOS transistor N14. The reference voltage is simultaneously applied to the gate terminals of the NMOS transistor N12, the PMOS transistor P21, and the NMOS transistor N14. The sampling voltage receiving section includes an NMOS transistor N13, a PMOS transistor P22, and an NMOS transistor N15. The working sampling voltage is simultaneously applied to the gate terminals of the NMOS transistor N13, the PMOS transistor P22, and the NMOS transistor N15. The drain of NMOS transistor N12, the source of PMOS transistor P21, the source of PMOS transistor P22, and the drain of NMOS transistor N13 are all connected to the drain of PMOS transistor P20. The source and base of PMOS transistor P20 are connected to the drain of PMOS transistor P19. The source of PMOS transistor P19 is connected to the power supply VDD. The source of NMOS transistors N12 and NMOS transistor N13 are both grounded. The source terminals of NMOS transistors N14 and N15 are connected to the drain terminal of NMOS transistor N16, the source terminal of NMOS transistor N16 is connected to the drain terminal of NMOS transistor N17, and the source terminal of NMOS transistor N17 is grounded. The drain terminal of PMOS transistor P21 is connected to one end of the internal resistor R14 of the error amplification high-gain output stage and the source terminal of PMOS transistor P23. The drain terminal of PMOS transistor P22 is connected to one end of the internal resistor R15 of the error amplification high-gain output stage and the source terminal of PMOS transistor P24. The other ends of resistors R14 and R15 are both connected to the power supply VDD. The drain terminal of PMOS transistor P23 is connected to the drain terminal of NMOS transistor N14, the drain terminal of NMOS transistor N18 in the error amplification high-gain output stage, the gate terminal of NMOS transistor N18, and the gate terminal of NMOS transistor N19 in the error amplification high-gain output stage. The drain terminals of NMOS transistor N19, NMOS transistor N15, PMOS transistor P24, and the error amplification frequency compensation unit in the high-gain output stage of the error amplifier are interconnected to form the error amplification output terminal of the error amplifier. The source terminal of NMOS transistor N18 is grounded through resistor R16, and the source terminal of NMOS transistor N19 is grounded through resistor R17. The gate of PMOS transistor P10 is connected to the bias voltage VBP0, the gate of PMOS transistor P20 is connected to the bias voltage VBP1, and the gates of PMOS transistors P23 and PMOS transistor P24 are both connected to the bias voltage VBP2. The gate of NMOS transistor N16 is connected to a bias voltage VBN1, and the gate of NMOS transistor N16 is connected to a bias voltage VBN0.

[0016] Advantages of the present invention: When the reference voltage generation unit provides the reference voltage, it uses a bandgap reference to generate the reference voltage. A precise low-pass filter can be used to perform noise reduction processing on the reference voltage, so that a high-precision reference voltage can be generated after noise reduction processing, thereby improving the noise reduction capability of the LDO circuit and the accuracy of the output voltage.

[0017] By using a transient response detection enhancement circuit in conjunction with a drive buffer, transient response detection of the LDO circuit load can be achieved, and the transient response of the LDO circuit can be enhanced. By using a dynamic frequency compensation circuit and an error amplification frequency compensation unit, frequency compensation can be achieved, thereby improving the loop stability and reliability of the LDO circuit. Attached Figure Description

[0018] Figure 1 This is a circuit block diagram of one embodiment of the LDO circuit of the present invention.

[0019] Figure 2 This is a circuit schematic diagram of one embodiment of the bandgap reference of the present invention.

[0020] Figure 3 This is a circuit schematic diagram of one embodiment of the precision low-pass filter of the present invention.

[0021] Figure 4 This is a circuit schematic diagram of one embodiment of the error amplifier of the present invention.

[0022] Figure 5 This is a circuit schematic diagram of one embodiment of the transient response detection enhancement circuit of the present invention.

[0023] Figure 6 This is a circuit schematic diagram of one embodiment of the driving buffer of the present invention.

[0024] Figure 7 This is a circuit diagram of one embodiment of the dynamic frequency compensation circuit of the present invention.

[0025] Figure 8 This is a circuit schematic diagram of one embodiment of the reference voltage adjustment unit of the present invention.

[0026] Figure 9 This is a schematic diagram of an embodiment of the equivalent small-signal model of the LDO circuit of the present invention. Detailed Implementation

[0027] The present invention will be further described below with reference to specific accompanying drawings and embodiments.

[0028] To achieve higher noise immunity and improve output voltage accuracy, this invention provides a high-precision LDO circuit with low noise and high transient enhancement capability. Specifically, the LDO circuit includes: LDO circuit body; The reference voltage generation unit provides the reference voltage required for the LDO circuit to operate. It includes a bandgap reference for generating the reference voltage and a precision low-pass filter for noise suppression of the reference voltage. When performing noise reduction processing on the reference voltage, it includes at least sequential voltage buffering and low-pass filtering. After voltage buffering of the reference voltage, a corresponding reference buffer voltage is generated. When performing low-pass filtering on the generated reference buffer voltage, at least the power supply noise and / or ground bounce interference of the reference buffer voltage are removed so that a corresponding reference voltage is generated after low-pass filtering, and the generated reference voltage is applied to the LDO circuit body.

[0029] It is understood that an LDO circuit should include the LDO circuit body, which is the functional circuit that can realize the LDO circuit. That is, the LDO circuit body can provide a stable voltage. The LDO circuit body can adopt the existing commonly used LDO circuit form, and the specific choice can be made according to the needs, which will not be elaborated here.

[0030] Noise is an important performance parameter of LDO circuits, mainly caused by interference from external power supply and ground lines, as well as thermal noise and flicker noise generated by internal components. Generally, the noise state of LDO circuits can be measured by PSRR (Power Supply Rejection Ratio) and SND (Spectral Noise Density).

[0031] Generally, the thermal noise and flicker noise of an LDO circuit are mainly affected by the reference voltage. To improve the noise immunity of the LDO circuit and reduce the noise of the reference voltage, the reference voltage provided by this invention should undergo noise immunity processing. Specifically, when using a reference voltage generation unit to provide the reference voltage, noise immunity processing should be applied to the reference voltage. The reference voltage generation unit may include a bandgap reference and a precise low-pass filter. Figure 1 The figure illustrates one embodiment of the reference voltage generation unit. In the figure, BG (Band Gap) is the bandgap reference, and PLPF (Precision Low Pass Filter) is the precision low pass filter. In this configuration, the bandgap reference can generate a reference voltage, and the precision low pass filter can be used to perform noise reduction processing on the reference voltage. The reference voltage is then generated after the noise reduction processing. Figure 1 In this context, VBG is the reference voltage, and VREF is the reference voltage.

[0032] When a precision low-pass filter performs noise suppression on a reference voltage, it performs at least voltage buffering and low-pass filtering. Specifically, the reference voltage is buffered, and a reference buffer voltage is generated after the voltage buffering process. Then, the reference buffer voltage is low-pass filtered. Through low-pass filtering, power supply noise and / or ground bounce interference in the reference buffer voltage can be removed. As can be seen from the above description, the noise suppression capability of the LDO circuit and the accuracy of the LDO circuit output voltage can be improved after the low-pass filtering because power supply noise and ground bounce interference are removed.

[0033] In one embodiment of the present invention, the bandgap reference includes a bandgap operational amplifier circuit and a zero-temperature drift reference voltage output unit connected in sequence, wherein, The bandgap operational amplifier circuit adopts a gain-bootstrapping operational amplifier circuit; The zero-temperature-drift reference voltage output unit includes a zero-temperature-drift reference voltage generation unit and a reference voltage adjustment unit adapted and connected to the zero-temperature-drift reference voltage generation unit. The zero-temperature-drift reference voltage generation unit within the zero-temperature-drift reference voltage output unit is adapted and connected to the bandgap operational amplifier circuit. The zero-temperature-drift reference voltage generation unit generates a reference voltage difference, which is then converted into a corresponding zero-temperature-drift basic voltage by a bandgap operational amplifier circuit. The zero-temperature-drift base voltage is adjusted using a reference voltage adjustment unit to generate a reference voltage after adjustment.

[0034] To provide an accurate reference voltage, the bandgap reference may include a bandgap operational amplifier circuit and a zero-temperature-drift reference voltage output unit. Specifically, the bandgap operational amplifier circuit may be a gain-bootstrapping operational amplifier circuit, and the zero-temperature-drift reference voltage output unit may include a zero-temperature-drift reference voltage generation unit and a reference voltage adjustment unit. By using the bandgap operational amplifier circuit and the zero-temperature-drift reference voltage generation unit in conjunction, a zero-temperature-drift basic voltage can be generated. Subsequently, the reference voltage adjustment unit adjusts the zero-temperature-drift basic voltage so that a reference voltage can be generated after the adjustment process. At this time, a more accurate reference voltage can be provided.

[0035] Figure 2 The document provides a circuit schematic of one embodiment of a bandgap reference. Figure 2 In this circuit, the bandgap operational amplifier circuit may include a gain bootstrap unit, a second-stage operational amplifier unit, and a first-stage operational amplifier unit. The gain bootstrap unit is connected to the second-stage operational amplifier unit, the second-stage operational amplifier unit is connected to the first-stage operational amplifier unit, and the first-stage operational amplifier unit is connected to a zero-temperature-drift reference voltage generation unit. The following section will discuss this in conjunction with... Figure 2 Explain the specifics of the bandgap operational amplifier circuit. Figure 2 In the above, the gain bootstrap unit includes a PMOS transistor P0, an NMOS transistor N0, an NMOS transistor N1, and a resistor R0. The source terminal of the PMOS transistor P0 is connected to the power supply VDD. The drain terminal of the PMOS transistor P0 is connected to the drain terminal of the NMOS transistor N0, the gate terminal of the NMOS transistor N0, the gate terminal of the NMOS transistor N1, and the gate terminal of the NMOS transistor N2 in the second stage of the operational amplifier. The drain terminal of the NMOS transistor N1 is connected to the source terminal of the NMOS transistor N0. The source terminal of the NMOS transistor N1 is grounded through the resistor R0.

[0036] The second stage of the operational amplifier includes PMOS transistor P1, NMOS transistor N2, NMOS transistor N3 and resistor R1. The source terminal of PMOS transistor P1 is connected to the power supply VDD. The gate terminal of PMOS transistor P1 is connected to the gate terminal of PMOS transistor P0, the drain terminal of PMOS transistor P1 and the drain terminal of NMOS transistor N2. The source terminal of NMOS transistor N2 is connected to the drain terminal of NMOS transistor N3. The source terminal of NMOS transistor N3 is grounded through resistor R1.

[0037] The first stage of the operational amplifier includes PMOS transistors P2, P3, and P4. The source of PMOS transistor P2 is connected to the power supply VDD. The gate of PMOS transistor P2 is connected to the gate of PMOS transistor P1 and the gate of PMOS transistor P0. The source of PMOS transistors P2, P3, and P4 is connected. The drain of PMOS transistor P3 is connected to the gate of NMOS transistor N3 and the drain of NMOS transistor N4 in the first stage of the operational amplifier. The drain of PMOS transistor P4 is connected to the gate of NMOS transistor N4, the gate of NMOS transistor N5 in the first stage of the operational amplifier, and the drain of NMOS transistor N5. The source of NMOS transistor N4 is grounded through resistor R2, and the source of NMOS transistor N5 is grounded through resistor R3.

[0038] For the aforementioned operational amplifier stage 2 and stage 1 units, the output terminal of the stage 1 unit is formed by interconnecting the drain terminals of PMOS transistor P3 and NMOS transistor N4, and the output terminal of the stage 2 unit is formed by interconnecting the gate terminal of PMOS transistor P1, the drain terminal of PMOS transistor P1, and the drain terminal of NMOS transistor N2. Figure 2 In this diagram, OP_O1 is the output terminal of the first stage of the operational amplifier, and OP_O2 is the output terminal of the second stage of the operational amplifier. When the bandgap operational amplifier circuit is constructed using the above-mentioned gain bootstrap unit, the first stage of the operational amplifier, and the second stage of the operational amplifier, the bandgap operational amplifier circuit can have the characteristics of high gain, fast response, and wide bandwidth.

[0039] Figure 2 The zero-temperature-drift reference voltage generation unit includes a PMOS transistor P5, resistors R4, R5, and R7, a PNP transistor Q0, and a PNP transistor Q1. The source terminal of PMOS transistor P5 is connected to the power supply VDD, the gate terminal of PMOS transistor P5 is connected to the gate terminal of PMOS transistor P2, the drain terminal of PMOS transistor P5 is connected to one end of resistor R4 and one end of resistor R5, the other end of resistor R4 is connected to the gate terminal of PMOS transistor P3 and one end of resistor R7, and the other end of resistor R5 is connected to the gate terminal of PMOS transistor P4 and the emitter terminal of PNP transistor Q1. The other end of resistor R7 is connected to the emitter terminal of PNP transistor Q0. The base terminals of PNP transistor Q0, PNP transistor Q1, PNP transistor Q0, and PNP transistor Q1 are all grounded.

[0040] Depend on Figure 2It can be seen that the gate terminals of PMOS transistor P3 and PMOS transistor P4 form the two differential input terminals of the bandgap operational amplifier circuit. The drain terminal of PMOS transistor P5 is connected to resistors R4 and R5 to form the zero-temperature drift basic voltage output terminal, which can be connected to the reference voltage adjustment unit.

[0041] Specifically, PNP transistors Q0 and Q1 should be configured with different areas. When the bandgap reference is operating, the corresponding currents flowing through PNP transistors Q0 and Q1 are the same. Assuming the layout area of ​​PNP transistor Q1 is N times that of PNP transistor Q0, the voltages at the two differential input terminals of the bandgap operational amplifier circuit are equal. Therefore, the voltage difference across the corresponding BE terminals of PNP transistors Q0 and Q1 is equal to the voltage difference across resistor R7. This voltage difference is called... VBE, where the voltage difference across NPN transistor Q0 and PNP transistor Q1 is... VBE = VT * lnN, meaning that the zero-temperature-drift reference voltage generation unit can generate a reference voltage difference through PNP transistor Q0 and the PNP transistor. The generated reference voltage difference is... VBE=VT*lnN, where VT is the thermal voltage, and the thermal voltage characterizes the positive temperature coefficient.

[0042] As explained above, after the two differential input terminals of the bandgap operational amplifier circuit are connected to the zero-temperature-drift reference voltage generation unit, since the voltages at the two differential input terminals of the bandgap operational amplifier circuit should be equal, the current flowing through resistor R7 is: I R7 = VBE / R7= (VT*lnN) / R7, and further, the voltage at the zero-temperature drift basic voltage output terminal can be obtained as: VBB=VBE_Q0+(R4+R7)*(VT*lnN) / R7, where VBB is the zero-temperature drift basic voltage at the zero-temperature drift basic voltage output terminal, VBE_Q0 is the negative temperature coefficient, and VT is the thermal voltage.

[0043] It should be noted that the negative temperature coefficient VBE_Q0 is different from the temperature coefficient of the thermal voltage VT. Generally, the positive temperature coefficient of the thermal voltage VT is about 0.087 mV / ºK, and the negative temperature coefficient VBE_Q0 is about -1.5 mV / ºK. After adjustment by the reference voltage adjustment unit, the negative temperature coefficient VBE_Q0 can be modulated to be equal to the corresponding positive temperature coefficient of the thermal voltage VT. Then, the voltage with the positive temperature coefficient and the voltage with the negative temperature coefficient can be superimposed to obtain the voltage with zero temperature drift, which can be used to generate the zero temperature drift basic voltage.

[0044] After obtaining the zero-temperature-drift basic voltage, the reference voltage adjustment unit can be used to adjust the zero-temperature-drift basic voltage to generate a reference voltage after adjustment. Figure 2 The reference voltage adjustment unit includes resistors R6 and R8, and a reference voltage adjustment unit itself. One end of resistor R6 is connected to the zero-temperature-drift basic voltage output terminal, and the other end of resistor R6 is connected to one end of resistor R8. The other end of resistor R8 is grounded through the reference voltage adjustment unit. The interconnection of resistors R6 and R8 forms the bandgap reference output terminal, through which the reference voltage VBG can be output. Figure 2 X0 in the diagram refers to the reference voltage adjustment unit, which is used to adjust the zero-temperature-drift base voltage VBB. The following example illustrates how the reference voltage adjustment circuit adjusts the zero-temperature-drift base voltage VBB.

[0045] In one embodiment of the present invention, the reference voltage adjustment unit includes a plurality of current adjustment units based on current adjustment, wherein the current adjustment unit includes a current adjustment main unit and an adjustment reset control signal generation unit adapted and connected to the current adjustment main unit. When performing current adjustment based on the current adjustment unit, pre-adjustment is first performed using the main current adjustment unit, followed by post-adjustment. During pre-adjustment, the pre-adjustment data is loaded into the current adjustment master unit so that the current adjustment master unit generates a pre-adjustment status signal corresponding to the pre-adjustment data. Based on the pre-adjustment state signal generated by the pre-adjustment, the current adjustment target state signal of the current adjustment master unit during the post-adjustment is determined, wherein the state of the current adjustment target state signal is an adjustment effective state or an adjustment ineffective state. During post-adjustment, based on the current adjustment target state signal, the target adjustment data is loaded into the current adjustment main unit, and the corresponding current adjustment target state signal is output through the current adjustment unit. Furthermore, a dual-mode adjustment state signal is formed based on the current adjustment target state signal. When the current adjustment target status signal is in the adjustment active state, the polycrystalline fuse in the current adjustment main unit is blown by current blowing based on the current adjustment target status signal and the adjustment enable signal in the active state, so as to lock the current adjustment target status signal output by the current adjustment main unit after the polycrystalline fuse blows. After the current trimming unit is powered on again, the trimming reset control signal generation unit generates a trimming reset control signal so that the current trimming master unit configures the generated trimming status signal as the corresponding current trimming target status signal under the trimming reset control signal.

[0046] Specifically, the current trimming unit may include a current trimming main unit and a trimming reset control signal generation unit. The current trimming main unit can be used to realize the current trimming function, and the trimming reset control signal generation unit can be used to reset the output state of the current trimming main unit after power-on.

[0047] Figure 8 The diagram shows a circuit schematic of one embodiment of the current trimming master unit. The current trimming master unit includes a DFF flip-flop, where DFF0 is the DFF flip-flop. The DFF flip-flop has a data input, a clock input, a set input, and a reset input. Figure 8 In this diagram, D is the data input of the DFF flip-flop, CLK is the clock input, SEB is the reset input, and RSB is the reset input. The DFF flip-flop can be a commonly used D flip-flop. The clock signal CLK applied to the clock input can be used to output the data input. Figure 8 In this context, the Q terminal is the output terminal of the DFF flip-flop.

[0048] Specifically, the data loaded onto the data terminal of the DFF flip-flop is generally "1" or "0". When the data loaded is "1", a high level is obtained at the Q terminal of the DFF flip-flop under the clock signal CLK; when the data loaded is "0", a low level is obtained at the Q terminal of the DFF flip-flop under the clock signal CLK. Furthermore, both the reset and set terminals of the DFF flip-flop are active low. If the level loaded onto the set terminal is low, the Q terminal of the DFF flip-flop is set; if the level loaded onto the reset terminal is low, the Q terminal of the DFF flip-flop is reset. Generally, when setting the DFF flip-flop, the Q terminal is high; when resetting the DFF flip-flop, the Q terminal is low.

[0049] It should be noted that the method of using the reference voltage adjustment unit for adjustment can be consistent with existing technology. For example, several adjustment resistors should be connected in series within the reference voltage adjustment unit, with each adjustment resistor corresponding to an adjustment power transistor. The adjustment power transistor can be a commonly used NMOS transistor. In this case, the drain and source terminals of the adjustment power transistor are connected to the two ends of a corresponding adjustment resistor, and the gate terminal of the adjustment power transistor is connected to a corresponding current adjustment unit. Specifically, the connection to the adjustment current unit means connecting the gate terminal of the adjustment power transistor to the Q terminal of a DFF flip-flop. During adjustment, the Q terminal of the DFF flip-flop should be at a high level so that the NMOS transistor can be turned on. The turned-on NMOS transistor can short-circuit the corresponding adjustment resistor, thereby adjusting the resistance value within the reference voltage adjustment unit. When the current adjustment resistor is not needed, the Q terminal of the DFF flip-flop in the corresponding current adjustment unit should be at a low level. At this time, the NMOS transistor is in the off state, and the adjustment resistor corresponding to the off state will not be short-circuited.

[0050] Based on the above description, when the current adjustment main unit has a DFF flip-flop, the DFF flip-flop can be used to perform pre-adjustment and post-adjustment. In the pre-adjustment, the pre-adjustment data is loaded into the data terminal of the DFF flip-flop. Then, under the action of the clock signal CLK, the corresponding pre-adjustment status signal can be obtained at the Q terminal of the DFF flip-flop. As can be seen from the above description, the pre-adjustment status signal is either a high-level state or a low-level state.

[0051] As explained above, when the pre-adjustment status signal is high, it drives the NMOS transistor to conduct, thus short-circuiting the corresponding adjustment resistor. Therefore, during pre-adjustment, the same adjustment operation can be performed on one or more current adjustment units to adjust the resistance value within the reference voltage adjustment unit using the pre-adjustment status signal, and after measurement, it can be determined whether it matches the expected resistance value. Since only the pre-adjustment data within each current adjustment master unit needs to be adjusted to adjust the corresponding pre-adjustment status signal, pre-adjustment is simple to operate and can improve adjustment accuracy.

[0052] After pre-adjustment, the target current adjustment status signal for each current adjustment master unit can be determined. This target current adjustment status signal is the level output of the Q terminal of the DFF flip-flop within each current adjustment master unit. As explained above, the target current adjustment status signal can be either an effective or ineffective adjustment state. Specifically, a high level indicates an effective adjustment state, while a low level indicates an ineffective adjustment state. Once the target current adjustment status signal for each current adjustment master unit is determined, the corresponding target adjustment data can be loaded onto the data terminal of the corresponding DFF flip-flop. For example, if the target current adjustment status signal is high, the target adjustment data should be "1".

[0053] It should be noted that when the current adjustment target state signal of the current adjustment master unit is in an effective adjustment state, the current adjustment target state signal output by the current adjustment master unit should be locked so as to maintain the current adjustment state in subsequent operations. As in the embodiment described above, the driving NMOS transistor can be kept in the on state. In one embodiment of the present invention, the polysilicon fuse in the current adjustment master unit is blown by current blowing based on the current adjustment target state signal and the adjustment enable signal in an effective state, so as to lock the current adjustment target state signal output by the current adjustment master unit after the polysilicon fuse blows.

[0054] Figure 8 In the diagram, Rfuse-poly is the polycrystalline fuse, and ENB-PGM is the adjustment enable signal, which is typically active low. When using the effective current path to fuse the polycrystalline fuse via current fusing, a fuse breaking voltage should also be applied to the second terminal of the polycrystalline fuse. Figure 8 In this context, Vf represents the fuse breaking voltage. Figure 8 In this circuit, the first end of the polysilicon fuse can be connected to the fuse breaking voltage. The second end of the polysilicon fuse is connected to the drain terminal of the NMOS transistor N100, and the source terminal of the NMOS transistor N100 is connected to the source terminal. The gate terminal of the NMOS transistor N100 is connected to the output terminal of the NOR gate NOR0. The first input terminal of the NOR gate NOR0 receives the trimming enable signal, and the second input terminal of the NOR gate NOR0 is connected to the output terminal of the inverter INV0. The input terminal of the inverter INV0 is connected to the Q terminal of the DFF flip-flop. The NMOS transistor N100 can only be turned on when the Q terminal of the DFF flip-flop is high and the trimming enable signal is low. When the NMOS transistor N100 is turned on, a loop is formed from the fuse breaking voltage - polysilicon fuse - NMOS transistor N100 to ground. The formed loop can serve as an effective current path. Subsequently, the current flowing through the polysilicon fuse is used to blow the fuse.

[0055] It is understandable that the bandgap reference will experience a power-down state. Upon power-up, the Q output of the DFF flip-flop should be restored to the current adjustment target state signal after the adjustment. If the current adjustment target state signal is in an effective adjustment state, the Q output of the DFF flip-flop should be high after power-up. Restoring the output state of the DFF flip-flop's Q output should be based on the polysilicon fuse's blown state to avoid erroneous restoration.

[0056] In order to reset the output of the DFF flip-flop, the current trimming main unit should include a reset position signal generation unit. Figure 8 In the complex position bit signal generation unit, there are PMOS transistor P101 and Schmitt trigger, wherein, The source terminal of PMOS transistor P101 is connected to the power supply VDD. The gate terminal of PMOS transistor P101 is connected to the preload control signal RE-LOAD and connected to one end of NAND gate NAND0 and one end of NAND gate NAND1. The drain terminal of PMOS transistor P101 is connected to the drain terminal of PMOS transistor P100, the drain terminal of NMOS transistor N101, and the input terminal of Schmitt trigger. The output of the Schmitt trigger is connected to the other end of the NAND gate NAND0 and the input of the inverter INV1. The output of the inverter INV1 is connected to the other end of the NAND gate NAND1. The output of NAND gate NAND0 is connected to the set terminal of DFF flip-flop, and the output of NAND gate NAND1 is connected to the reset terminal of DFF flip-flop.

[0057] Figure 8 In this context, SMIT-TRIGO refers to a Schmitt trigger. Schmitt triggers can be implemented in various commonly used forms and can be used to deglitch voltage levels. Figure 8 As can be seen from the reset bit signal generation unit, when the preload control signal RE-LOAD is in an invalid low-level state, the NAND gates NAND0 and NAND gates NAND1 output a high level. At this time, the set drive signal at the set terminal of the DFF flip-flop is high, and the reset drive signal at the reset terminal of the DFF flip-flop is also high. Therefore, the DFF flip-flop is neither performing a set operation nor a reset operation. In specific implementations, the reset bit signal may include both a reset drive signal and a set drive signal. In this case, the reset drive signal is applied to the reset terminal of the DFF flip-flop, and the set drive signal is applied to the set terminal of the DFF flip-flop.

[0058] When the preload control signal RE-LOAD is high, PMOS transistor P101 is off. The input voltage of the Schmitt trigger is only related to the voltage at the drain terminal of PMOS transistor P100. If the voltage at the drain terminal of PMOS transistor P100 is high, the set drive signal output through NAND gate NAND0 is low, while the reset drive signal output through NAND gate NAND1 is high. At this time, the DFF trigger is set, and the Q terminal of the DFF trigger is the current adjustment target state signal for the active state. If the voltage at the drain terminal of PMOS transistor P100 is low, the set drive signal output through NAND gate NAND0 is high, while the reset drive signal output through NAND gate NAND1 is low. At this time, the DFF trigger is reset, and the Q terminal of the DFF trigger is the current adjustment target state signal for the inactive state.

[0059] As explained above, the adjustment and reset control signals include the preload control signal RE-LOAD, the low-level detection control signal CFG-N, and the high-level detection control signal CFG-P. The adjustment and reset control signals are generated by the adjustment and reset control signal generation unit. It can be understood that when the current adjustment main unit is pre-adjusted and post-adjusted, the preload control signal RE-LOAD, the low-level detection control signal CFG-N, and the high-level detection control signal CFG-P should all be in an invalid level state. When the current adjustment unit is powered on again, the high-level detection control signal CFG-P and the low-level detection control signal CFG-N immediately become valid, and the preload control signal RE-LOAD becomes valid after a delay.

[0060] When the preload control signal RE-LOAD, the low-level detection control signal CFG-N are active high, and the high-level detection control signal CFG-P is active low, the reset bit signal generation unit further includes NMOS transistors N101 and N102, and PMOS transistor P100. The source terminal of NMOS transistor N102 is grounded, the drain terminal of NMOS transistor N102 is connected to the source terminal of NMOS transistor N101, the drain terminal of NMOS transistor N101 is connected to the drain terminal of PMOS transistor P100 and the reset bit signal generation unit, and the source terminal of PMOS transistor P100 is connected to the second end of the polyfusible fuse. The gate of NMOS transistor N101 is connected to the low-level detection control signal CFG-N, the gate of NMOS transistor N1022 is connected to the preload control signal RE-LOAD, and the gate of PMOS transistor P100 is connected to the high-level detection control signal CFG-P.

[0061] When the high-level detection control signal CFG-P is low, PMOS transistor P100 is turned on; when the low-level detection control signal CFG-N is high, NMOS transistor N102 is turned on. When the preload control signal RE-LOAD is low, NMOS transistor N101 is turned off; when the preload control signal RE-LOAD is high, NMOS transistor N101 is turned on.

[0062] When power is restored, the fuse breaking voltage must also be applied to the first terminal of the polycrystalline fuse. During normal operation, the fuse breaking voltage needs to be removed. During the power-on phase, the fuse breaking voltage can be lower than the voltage during the polycrystalline fuse breaking phase. Furthermore, during the pre-adjustment phase, the fuse breaking voltage does not need to be applied to the first terminal of the polycrystalline fuse; it is only applied during the post-adjustment phase.

[0063] It is understandable that when NMOS transistors N101, N102, and PMOS transistor P00 are all turned on and the fuse level status signal is obtained, then: when the polysilicon fuse is not blown, the drain terminal of PMOS transistor P100 forms a path to ground through NMOS transistors N101 and N102, and the voltage at the drain terminal of PMOS transistor P100 is 0 level; when the polysilicon fuse is blown, the drain terminal of PMOS transistor P100 is pulled up to the blown voltage by the fuse voltage, and at this time, the voltage at the drain terminal of PMOS transistor P100 is high level.

[0064] In practice, based on the fuse level state, corresponding reset drive signals and set drive signals can be generated. In this way, the set drive or reset drive of the DFF flip-flop can be realized according to the melting state of the polycrystalline fuse, so that the output of the DFF flip-flop can be configured to the corresponding current adjustment target state signal.

[0065] In one embodiment of the present invention, the LDO circuit body includes an error amplifier, a drive buffer, a power transistor circuit, and a voltage feedback circuit, wherein, The reference voltage generated by the reference voltage generation unit is applied to the non-inverting input of the error amplifier. The output of the error amplifier is connected to the drive buffer, and the output of the drive buffer is connected to the gate of the power PMOS transistor in the power transistor circuit, so as to apply the drive voltage VG to the gate of the power PMOS transistor through the drive buffer. The drain terminal of the power PMOS transistor is connected to a voltage feedback circuit to feed back the operating sampling voltage to the inverting input of the error amplifier. The junction between the drain terminal of the power PMOS transistor and the voltage feedback circuit forms the circuit body output terminal of the LDO circuit body.

[0066] Figure 1 The figure illustrates one embodiment of an LDO circuit body. The LDO circuit body may include an error amplifier, a drive buffer, a power transistor circuit, and a voltage feedback circuit. In the figure, EA (Error Amplifier) ​​is the error amplifier, and DB (Driver Buffer) is the drive buffer. Figure 1 The Power-MOS in the text refers to the power transistor circuit. Figure 1 The diagram illustrates an embodiment where a single power PMOS transistor is used within the power transistor circuit. Figure 1 In the diagram, P33 is the power PMOS transistor. Within the LDO circuit, the power PMOS transistor can provide ampere-level current; therefore, its size is relatively large, occupying approximately half of the entire LDO circuit layout area. The drive buffer can apply a drive voltage VG to the gate of the power PMOS transistor, thus the conduction state of the power PMOS transistor can be controlled using the drive voltage VG.

[0067] To improve the stability of LDO circuit operation, a voltage feedback circuit should be configured to form a negative feedback loop. Figure 1 In the circuit, the voltage feedback circuit includes resistor R. FB0 Resistance R FB1 And resistor R24, where resistor R FB0 One end is connected to the drain terminal of the power PMOS transistor, and the resistor R FB0 The other end is connected to resistor R FB1 One end of the resistor R24 ​​is connected to the other end of the resistor R. FB1 The other end of the resistor is grounded, and the other end of resistor R24 ​​is connected to the inverting input of the error amplifier. Figure 1 The diagram also shows the drain terminal of the power PMOS transistor connected to capacitor C. L In one embodiment of grounding, capacitor C L This represents the load connected to the drain terminal of the power PMOS transistor.

[0068] right Figure 1 The LDO circuit shown in the diagram, analyzed from the perspective of the entire loop, has the following characteristics: Since the error amplifier possesses the characteristics of an operational amplifier, the reference voltage applied to the non-inverting input of the error amplifier should be equal to the operating sampling voltage, VREF = VSENSE = VOUT * R. FB1 / (R FB0 +R FB1 Therefore, it can be deduced that the output voltage VOUT of the LDO circuit should be VREF*(R). FB0 +R FB1 ) / R FB1 .

[0069] In one embodiment of the present invention, a transient response detection enhancement circuit for transient response detection and enhancement is further included, wherein, The transient response detection enhancement circuit is adapted to the output terminal of the LDO circuit body and the drive buffer to load the output voltage VOUT and drive voltage VG of the LDO circuit body output terminal onto the transient response detection enhancement circuit. Based on the output voltage VOUT, the transient response detection enhancement circuit detects the transient response of the LDO circuit itself, wherein... When a transient response change in the LDO circuit body is detected, the transient response detection enhancement circuit generates a corresponding transient response enhancement signal and loads the transient response enhancement signal into the drive buffer. The drive buffer is then configured to adjust the output drive voltage VG based on the current transient response enhancement signal, so that the output voltage VOUT of the LDO circuit body remains stable. Based on the adjusted drive voltage VG from the drive buffer, the transient response enhancement signal generated by the transient response detection enhancement circuit is controlled to ensure that the transient response enhancement signal generated by the transient response detection enhancement circuit remains stable after transient response enhancement.

[0070] Specifically, the transient response of an LDO circuit mainly consists of two parts: the load transient response and the linear transient response. The load transient response is affected by various factors, such as the quiescent current of the LDO circuit, the duration of the transient load current change, etc. To enhance the transient response of the LDO circuit, transient response detection enhancement circuits can be provided, such as... Figure 1 middle, Figure 1 In the diagram, TDAE (Transient Detection and Enhancement) is a transient response detection and enhancement circuit. The transient response detection and enhancement circuit is adapted to the output terminal of the LDO circuit body and the drive buffer to form a negative feedback closed loop with the drive buffer. The loop formed is located in the inner loop of the loop formed by the voltage feedback circuit.

[0071] When performing transient response enhancement, the transient response change is first determined based on the output voltage VOUT of the LDO circuit itself. Then, the transient response detection and enhancement circuit adjusts its output transient response enhancement signal to adjust the drive voltage VG output by the drive buffer, thereby adjusting the drive state of the power PMOS transistor. After the drive state of the power PMOS transistor changes, the transient response enhancement signal of the transient response detection and enhancement circuit is further adjusted. At this point, the transient response of the transient response detection and enhancement circuit is adjusted to reset the transient response enhancement signal, restoring it to the state before the transient response change of the LDO circuit itself. This ensures that the transient response enhancement signal remains stable after transient response enhancement; simultaneously, the output voltage VOUT of the LDO circuit also remains stable. This improves the load transient response of the LDO circuit and enhances the stability and reliability of the LDO circuit's operation.

[0072] In one embodiment of the present invention, the transient response detection enhancement circuit includes a voltage detection and control circuit and a transient response enhancement signal generation circuit adapted and connected to the voltage detection and control circuit, wherein, The voltage detection and control circuit is connected to both the output voltage VOUT and the drive voltage VG. The transient response enhancement signal generation circuit generates a transient response enhancement signal and loads the generated transient response enhancement signal into the drive buffer; When the transient response state is determined based on the output voltage VOUT, the voltage detection and control circuit generates a voltage detection and control signal that is adapted to the current transient response state, and loads the voltage detection and control signal into the transient response enhancement signal generation circuit, so as to configure the transient response enhancement signal generation circuit to control the generated transient response enhancement signal in the direction of transient response change. Based on the adjusted drive voltage VG from the drive buffer, the voltage detection and control circuit generates a voltage detection and control signal adapted to the current drive voltage VG, and loads the voltage detection and control signal onto the transient response enhancement signal generation circuit, so as to configure the transient response enhancement signal generation circuit to control the generated transient response enhancement signal in the opposite direction of the drive voltage change. When regulating the transient response enhancement signal generated by the transient response enhancement signal generation circuit, the direction of transient response change is consistent with the direction of driving voltage change.

[0073] Specifically, the voltage detection and control circuit receives the output voltage VOUT and the driving voltage VG. The voltage detection and control circuit can generate a voltage detection and control signal based on the output voltage VOUT and the driving voltage VG. The voltage detection and control signal is used to control the transient response enhancement signal generated by the transient response enhancement signal generation circuit, thereby enhancing the transient response.

[0074] In one embodiment of the present invention, the voltage detection and regulation circuit includes a PMOS transistor P25 and an NMOS transistor N21, wherein, The source terminal of PMOS transistor P25 is connected to the output voltage VOUT through resistor R19. The gate terminal of PMOS transistor P25 is connected to the drain terminal of PMOS transistor P25, the drain terminal of NMOS transistor N21, and the gate terminal of PMOS transistor P26. The source terminal of NMOS transistor N21 is grounded. The gate terminal of NMOS transistor N21 is connected to the gate terminal of NMOS transistor N22, the drain terminal of NMOS transistor N22, and the drain terminal of PMOS transistor P26. The gate terminal of NMOS transistor N21, the gate terminal of NMOS transistor N22, the drain terminal of NMOS transistor N22, and the drain terminal of PMOS transistor P26 are interconnected to form the output connection terminal of the voltage detection and control circuit. The source terminal of PMOS transistor P26 is connected to the drain terminal of PMOS transistor P27 through resistor R20. The gate terminal of PMOS transistor P27 is connected to the drive voltage VG, and the source terminal of PMOS transistor P27 is connected to the power supply VDD. The source terminal of NMOS transistor N22 is grounded. The transient response enhancement signal generation circuit includes PMOS transistor P28, PMOS transistor P29, and NMOS transistor N23, wherein... The source terminal of PMOS transistor P28 is connected to the power supply VDD. The drain terminal of PMOS transistor P28 is connected to the source terminal of PMOS transistor P29, and the drain terminal of PMOS transistor P29 is connected to the drain terminal of NMNOS transistor N23, forming the output connection terminal of the transient response enhancement signal generation circuit. The source terminal of NMOS transistor N23 is grounded, and the gate terminal of NMOS transistor N23 is connected to the output terminal of the voltage detection and control circuit. The gate of PMOS transistor P28 is connected to the bias voltage VBP0, and the gate of PMOS transistor P29 is connected to the bias voltage VBP1.

[0075] Figure 5 The diagram illustrates one embodiment of a transient response detection enhancement circuit. Specifically, when the output voltage VOUT is detected to be low, the current flowing through PMOS transistor P25 and NMOS transistor N21 decreases, thereby reducing the voltage at the corresponding gate terminals of NMOS transistors N21 and N22. Simultaneously, the voltage at the gate terminal of NMOS transistor N23 also decreases, leading to an increase in the voltage at the drain terminal of NMOS transistor N23. This means the transient response enhancement signal generated by the transient response enhancement signal generation circuit becomes larger. Figure 5 In this context, EHO is the transient response enhancement signal, and the transient response enhancement signal is a voltage signal.

[0076] When the transient response enhancement signal increases, the drive voltage VG of the drive buffer output can be reduced, thereby allowing the internal power PMOS transistor of the LDO circuit to provide a larger current, and the output voltage VOUT increases to return to the normal value.

[0077] When the drive voltage VG decreases, it will regulate the drive state of PMOS transistor P27. At this time, it will increase the current flowing through NMOS transistor N22, and increase the voltage at the corresponding gate terminals of NMOS transistors N22 and NMOS transistor N23, thereby enabling the output transient response to be enhanced and the signal to be reset.

[0078] As explained above, the regulation process of output voltage VOUT -> transient response enhancement signal -> drive voltage VG -> transient response enhancement signal EHO can be called a transient enhancement process. It is an automatic start-up and automatic shutdown process that does not affect the feedback coefficient of the entire LDO circuit loop, and therefore does not affect the output voltage VOUT of the LDO circuit. It only becomes faster than the error amplifier response when the load changes rapidly, thereby reducing the overshoot of the output voltage.

[0079] In one embodiment of the present invention, a dynamic frequency compensation circuit for frequency compensation of the LDO circuit body is further included, wherein, The dynamic frequency compensation circuit includes a Miller structure frequency compensation unit and a load current compensation unit that performs dynamic frequency compensation based on load current. The Miller structure frequency compensation unit is adapted to the output terminal of the circuit body and the inverting terminal of the error amplifier, so as to push the pole of the inverting terminal of the error amplifier to a low frequency using the Miller structure frequency compensation unit. The load current compensation unit includes a frequency compensation variable resistor unit, which is adapted and connected to the Miller structure frequency compensation unit. The resistance value of the frequency compensation variable resistor unit is configured based on the driving voltage VG so that the resistance value of the frequency compensation variable resistor is adapted to the load current. After configuring the resistance value of the frequency compensation variable resistor using the driving voltage VG, loop frequency compensation is performed on the LDO circuit body based on the frequency compensation variable resistor unit and the Miller structure compensation unit.

[0080] It should be noted that an LDO circuit is a multi-stage negative feedback closed-loop system with multiple zeros and poles, making its stability issue quite complex. Furthermore, the output impedance of the power PMOS transistor changes with the load, which in turn affects the loop gain and frequency response. This makes the loop stability of the LDO circuit under full load conditions a key factor in the design.

[0081] To improve the stability of LDO circuits, this invention utilizes a dynamic frequency compensation circuit to perform frequency compensation on the LDO circuit. Figure 1 The DFC (Dynamic Frequency Compensation) mentioned here refers to the dynamic frequency compensation circuit. Specifically, based on the change of load current, the dynamic frequency compensation circuit can dynamically realize the frequency compensation of the LDO circuit loop, so that the LDO circuit can ensure stability under different load environments (light load and heavy load).

[0082] Figure 7 This is a circuit schematic diagram of an embodiment of a dynamic frequency compensation circuit. In the diagram, the dynamic frequency compensation circuit includes capacitor C4, resistor R23, capacitor C3, PMOS transistor P32, and resistor R22. One end of capacitor C4 is connected to the inverting input of the error amplifier, and the other end of capacitor C4 is connected to one end of capacitor C3, one end of resistor R22, and the drain terminal of PMOS transistor P32. The other end of resistor R22 is connected to the output terminal of the circuit body, and the other end of capacitor C3 is grounded. The source terminal of PMOS transistor P32 is connected to the power supply VDD through resistor R23, and the gate terminal of PMOS transistor P32 is connected to the driving voltage VG.

[0083] The small-signal model of LDO circuits combined with the Barkhausen criterion is an important method for evaluating system stability. The following section evaluates the stability of LDO circuits using the small-signal model. Figure 9 For the present invention Figure 1 The small-signal model of the LDO circuit can be established using existing commonly used techniques. Figure 1 The small-signal model of the LDO circuit, the method and process of establishing the small-signal model can be consistent with the existing technology, and will not be elaborated here.

[0084] Depend on Figure 9 As can be seen from the small-signal model, the LDO circuit of the present invention can be equivalent to four stages, wherein the first stage is an error amplifier, the second stage is a drive buffer, the third stage is a power PMOS transistor, and the fourth stage is a voltage feedback circuit. Figure 9 In the diagram, gm1 is the transconductance of the error amplifier, gm2 is the transconductance of the drive buffer, gm3 is the transconductance of the power PMOS transistor, gm4 is the transconductance of PMOS transistor P32 in the dynamic frequency compensation circuit, and A FB For feedback coefficients; Figure 1 In the LDO circuit, the feedback coefficient A FB Then we have R FB1 / (R FB0 +R FB1 ).

[0085] Depend on Figure 9 It can be seen that the open-loop path of the corresponding small-signal model of the LDO circuit in this invention is: gm1->gm2->gm3->A FB ->SENSE;R O1 R O2 These are the corresponding output resistors of the error amplifier and the drive buffer; C VG R is the gate capacitance of the power PMOS transistor; L C L R represents the load resistor and load capacitor corresponding to the output voltage VOUT point. ESR For the load capacitor C L The parasitic equivalent resistance on the capacitor. The capacitor C4 connected between point A and the inverting input of the error amplifier can be equivalent to the capacitor C4 between point A and GND. ' And the capacitor C4 between the inverting input of the error amplifier and GND. '' C4 ' ≈C4,C4 '' >>C4. Since the transconductance gm4 does not form a feedforward path, it can be equivalent to a variable resistance R connected to GND. P32 The variable resistance resistor R P32 Used for dynamic frequency compensation.

[0086] Figure 9The open-loop transfer function of the small-signal model is as follows: L(s) = (-g m1 *R S1 )*(-g m2 *R S1 )*(-g m3 *R S3 )*(A FB *ζ)(1) Among them, R S1 R S2 R S3 These are the equivalent output resistances of the first stage, the second stage, and the third stage, respectively, and ζ is the effective coefficient of the fourth stage.

[0087] Based on the above explanation, it can be concluded that... Figure 9 Then we have: R S1 =R O1 ||(R18+1 / S*C1+R N20 ||1 / S*C2)(2) R S2 = R O2 ||1 / S*C VG (3) R S3 =R L ||(R FB0 +R FB1 )||(R ESR +1 / S*C L )||{R 23 +1 / [S*(C3+C4 ' )||(R P32 +R 22 (4) ζ = 1 / S*R 24 *C4 '' (5) Substituting equations (2) to (5) into equation (1), we can obtain the following 6 poles and 4 zeros. Among them, the output of the error amplifier generates 2 poles and 2 zeros. At this time, the poles and zeros can cancel each other out. The remaining 4 poles and 2 zeros are as follows: P0≈ -(1 / R L ) / C L ; P1≈ -(1 / R L ) / (C3+C4 ' ); P2 = -(1 / R) 24 ) / C4 '' ; P3 = -(1 / R)O2 ) / C VG ; / / high frequency Z0≈ -[1 / R 23 +1 / (R 22 +R P32 )] / (C3+C4 ' ); Z1= -(1 / R ESR ) / C L ; Specifically, P0 is the principal pole, and the load capacitance C at the microfarad level at the output of the LDO circuit is... L and load resistance R L P1 is a secondary pole, also generated at the output of the LDO circuit and varying with the load R. L As the voltage decreases, the secondary pole P1 increases; the pole P2 is determined by the output resistor R of the voltage feedback circuit. 24 and equivalent capacitance C4 '' The P3 pole is generated by the output resistor R of the drive buffer. O2 and the gate capacitance C of the power PMOS transistor VG Since the output resistance of the drive buffer is very small, the P3 pole is a high-frequency pole and is far outside the cutoff frequency, so it does not affect the stability of the loop.

[0088] Zero point Z0 is generated by R23 and the series capacitors C4 and C3, and is used for frequency compensation of the secondary pole P1. Zero point Z0 dynamically compensates for the frequency of pole P1 according to changes in the load. Zero point Z1 is generated by the load capacitor C... L and its equivalent series resistance R ESR The zero Z1 is generated and used for frequency compensation of pole P2. Through the above frequency compensation method, there is only one dominant pole P0 equivalently within the cutoff frequency. Therefore, the frequency response of the LDO circuit of this invention is stable.

[0089] As explained above, capacitor C4 and resistor R23 constitute a Miller structure frequency compensation unit, which pushes the pole P2 at the inverting input of the error amplifier to a lower frequency, in conjunction with the load capacitance and parasitic equivalent resistance R. ESR The zero point Z1 formed is zero-pole cancellation. The series resistor R23 forms a zero point Z0, and by connecting PMOS transistor P32 between point A and the power supply VDD, PMOS transistor P32 is used as a variable resistor. When PMOS transistor P32 is used as a variable resistor, the driving voltage VG controls the size of the variable resistor, and the driving voltage VG determines the size of the load current. The change of load current affects both the major pole P0 and the minor pole P1 at the output voltage VOUT. In this way, frequency compensation of the LDO circuit loop can be dynamically realized according to the change of load current.

[0090] In one embodiment of the present invention, the precise low-pass filter includes a voltage buffer device for performing voltage buffering processing and a low-pass filter for performing low-pass filtering processing, wherein, The voltage buffer includes a PMOS transistor P8 that receives a reference voltage. The source terminal of PMOS transistor P8 is connected to the source terminal of PMOS transistor P9 and the drain terminal of PMOS transistor P7. The source terminal of PMOS transistor P7 is connected to the drain terminal of PMOS transistor P6. The drain terminal of PMOS transistor P8 is connected to the drain terminal of NMOS transistor N6, the gate terminal of NMOS transistor N6, and the gate terminal of NMOS transistor N7. The source terminal of NMOS transistor N6 is grounded through resistor R9, and the source terminal of NMOS transistor N7 is grounded through resistor R10. The drain of NMOS transistor N7 is connected to the drain of PMOS transistor P9 and the gate of NMOS transistor N9. The source of NMOS transistor N9 is grounded through resistor R11. The drain of NMOS transistor N9 is connected to the source of NMOS transistor N8, the gate of PMOS transistor P10, and the gate of PMOS transistor P12. The drain of NMOS transistor N8 is connected to the drain of PMOS transistor P11. The source of PMOS transistor P11 is connected to the drain of PMOS transistor P10. The drain of PMOS transistor P12 is connected to the source of PMOS transistor P13. The drain of PMOS transistor P13 is connected to one end of resistor R12. The other end of resistor R12 is connected to the gate of PMOS transistor P9, one end of resistor R13, and the low-pass filter adapter. The other end of resistor R13 is connected to the voltage buffer trimming unit adapter. The source terminals of PMOS transistors P6, P10, and P12 are all connected to the power supply VDD.

[0091] Figure 3 An embodiment of a precision low-pass filter is shown in the figure. Figure 3 X1 in the figure is the voltage buffer adjustment unit. The voltage buffer adjustment unit can take the same form as the reference voltage adjustment unit. For the specific adjustment method and process, please refer to the corresponding description above. It will not be repeated here.

[0092] Specifically, the voltage buffer transmits the reference voltage generated by the bandgap reference to VBG_BUF, which is to... Figure 3Resistors R12 and R13, along with the gate of PMOS transistor P9, are interconnected to form a voltage buffer output node, where a reference buffer voltage can be obtained. As explained above, the voltage buffer adjustment unit within the voltage buffer can be used for adjustment, thereby obtaining a zero-temperature-drift voltage. This voltage buffer adjustment unit improves the accuracy of the obtained reference buffer voltage. Furthermore, the voltage buffer has high input impedance and low output impedance. The high input impedance isolates the voltages of the preceding and following stages, while the low output impedance eliminates ground bounce interference.

[0093] Figure 3 An embodiment of a low-pass filter is also shown in the figure. Figure 3 In the low-pass filter, there are current source circuits and filter capacitors. The current source circuit includes PMOS transistors P14, P15, P16, P17, and P18, and NMOS transistors N10 and NMOS transistor N11. The source terminal of PMOS transistor P14 is connected to the power supply VDD, the drain terminal of PMOS transistor P14 is connected to the source terminal of PMOS transistor P15, the drain terminal of PMOS transistor P15 is connected to the source terminal of PMOS transistor P16, the drain terminal of PMOS transistor P16 is connected to the drain terminal of NMOS transistor N10, the gate terminal of NMOS transistor N10, and the gate terminal of NMOS transistor N11. The source terminals of NMOS transistors N10 and NMOS transistor N11 are both grounded. The drain of NMOS transistor N11 is connected to the drain of PMOS transistor P17, the gate of PMOS transistor P17, and the gate of PMOS transistor P18. The source of PMOS transistor P17 and the source of PMOS transistor P18 are both connected to the voltage buffer output node. The drain of PMOS transistor P18 is grounded through a filter capacitor. Figure 3 In this diagram, C0 is the filter capacitor. Connecting the drain terminal of PMOS transistor P18 to the filter capacitor forms the output of a precise low-pass filter. The reference voltage can be obtained from the filter output. Figure 3 VREF in the figure is the reference voltage.

[0094] In practice, after obtaining the reference buffer voltage, a low-pass filter formed by the current source circuit and the filter capacitor can eliminate noise from the power supply VDD and ground bounce interference from GND, thereby ensuring a highly stable and accurate reference voltage VREF output.

[0095] In one embodiment of the present invention, the error amplifier includes an error amplification rail-to-rail input stage and an error amplification high-gain output stage, wherein, The error amplifier rail-to-rail input stage receives the reference voltage and is adapted to the drive buffer through the error amplifier high-gain output stage; The error amplification rail-to-rail input stage includes a reference voltage receiver and a sampling voltage receiver. The reference voltage is applied to the reference voltage receiver, and the working sampling voltage is applied to the sampling voltage receiver. The reference voltage receiving section includes an NMOS transistor N12, a PMOS transistor P21, and an NMOS transistor N14. The reference voltage is simultaneously applied to the gate terminals of the NMOS transistor N12, the PMOS transistor P21, and the NMOS transistor N14. The sampling voltage receiving section includes an NMOS transistor N13, a PMOS transistor P22, and an NMOS transistor N15. The working sampling voltage is simultaneously applied to the gate terminals of the NMOS transistor N13, the PMOS transistor P22, and the NMOS transistor N15. The drain of NMOS transistor N12, the source of PMOS transistor P21, the source of PMOS transistor P22, and the drain of NMOS transistor N13 are all connected to the drain of PMOS transistor P20. The source and base of PMOS transistor P20 are connected to the drain of PMOS transistor P19. The source of PMOS transistor P19 is connected to the power supply VDD. The source of NMOS transistors N12 and NMOS transistor N13 are both grounded. The source terminals of NMOS transistors N14 and N15 are connected to the drain terminal of NMOS transistor N16, the source terminal of NMOS transistor N16 is connected to the drain terminal of NMOS transistor N17, and the source terminal of NMOS transistor N17 is grounded. The drain terminal of PMOS transistor P21 is connected to one end of the internal resistor R14 of the error amplification high-gain output stage and the source terminal of PMOS transistor P23. The drain terminal of PMOS transistor P22 is connected to one end of the internal resistor R15 of the error amplification high-gain output stage and the source terminal of PMOS transistor P24. The other ends of resistors R14 and R15 are both connected to the power supply VDD. The drain terminal of PMOS transistor P23 is connected to the drain terminal of NMOS transistor N14, the drain terminal of NMOS transistor N18 in the error amplification high-gain output stage, the gate terminal of NMOS transistor N18, and the gate terminal of NMOS transistor N19 in the error amplification high-gain output stage. The drain terminals of NMOS transistor N19, NMOS transistor N15, PMOS transistor P24, and the error amplification frequency compensation unit in the high-gain output stage of the error amplifier are interconnected to form the error amplification output terminal of the error amplifier. The source terminal of NMOS transistor N18 is grounded through resistor R16, and the source terminal of NMOS transistor N19 is grounded through resistor R17. The gate of PMOS transistor P10 is connected to the bias voltage VBP0, the gate of PMOS transistor P20 is connected to the bias voltage VBP1, and the gates of PMOS transistors P23 and PMOS transistor P24 are both connected to the bias voltage VBP2. The gate of NMOS transistor N16 is connected to a bias voltage VBN1, and the gate of NMOS transistor N16 is connected to a bias voltage VBN0.

[0096] Figure 4 An embodiment of the error amplifier is shown. In the rail-to-rail input stage of the error amplifier, NMOS transistors N14 and N15 form a first differential pair, which can be used to process high input voltage signals. PMOS transistors P21 and P22 form a second differential pair, which is used to process low input voltage signals. This enables rail-to-rail voltage processing. The methods and processes for processing low input voltage signals and high input voltage signals are consistent with the prior art and will not be described in detail here.

[0097] An error amplification frequency compensation unit is set within the high-gain output stage of the error amplification. Figure 4 The FC in the LDO circuit is the error amplifier frequency compensation unit. This unit generates two zeros to compensate for the two poles of the error amplifier, thereby reducing the impact of the error amplifier on the phase margin within the entire LDO circuit loop.

[0098] Figure 4 The figure also shows an embodiment of an error amplification frequency compensation unit. The error amplification frequency compensation unit includes a resistor R18, a capacitor C1, a capacitor C2, and an NMOS transistor N20. One end of the resistor R18 is connected to the error amplification output terminal, and the other end of the resistor R18 is connected to the gate terminal of the NMOS transistor N20 and one end of the capacitor C1. The other end of the capacitor C1 is connected to the drain terminal of the NMOS transistor N20 and one end of the capacitor C2. The other end of the capacitor C2 and the source terminal of the NMOS transistor N20 are both grounded.

[0099] For the aforementioned drive buffer, Figure 6 An embodiment of the drive buffer is shown in the figure. Figure 6 In the process, the drive buffer includes PMOS transistors P30 and P31, wherein the source terminal of PMOS transistor P30 and the source ground of PMOS transistor P31 are both connected to the power supply VDD. The gate terminal of PMOS transistor P30 is connected to the drain terminal of PMOS transistor P30, the drain terminal of NMOS transistor N24, the drain terminal of PMOS transistor P31, and one end of resistor R21. After connection, the drive buffer output terminal of the drive buffer is formed, so that the drive voltage VG can be output using the drive buffer output terminal.

[0100] The gate of NMOS transistor N24 is connected to the output of the transient response detection enhancement circuit. The source of NMOS transistor N24 is connected to the drain of NMOS transistor N25. The gate of NMOS transistor N25 is connected to the error amplification output of the error amplifier. The source of NMOS transistor N25 is grounded. The gate of PMOS transistor P31 is connected to the other end of resistor R21 and the drain of NMOS transistor N26. The source of NMOS transistor N26 is connected to the drain of NMOS transistor N27. The source of NMOS transistor N27 is grounded. The gate of NMOS transistor N26 receives bias voltage VBN0, and the gate of NMOS transistor N27 receives bias voltage VBN1.

[0101] Specifically, the drive buffer can output a drive voltage VG to drive the power PMOS transistors. Since the power PMOS transistors have very large gate capacitances, the drive buffer needs to have a relatively large drive capability. In practice, PMOS transistors P30, P31, NMOS transistors N24, and NMOS transistors N25 are designed with relatively large sizes, specifically to meet the drive requirements of the power PMOS transistors. Furthermore, for... Figure 6 The drive buffer shown has a relatively small output resistance, and the pole formed at the output terminal of the drive buffer is a high-frequency pole, which does not affect the stability of the LDO circuit loop.

[0102] It should be noted that the bias voltage used in the above circuit is generally generated by a bias voltage circuit. The bias voltage generation circuit can adopt a commonly used form, specifically one that can meet the requirements of generating the above bias voltage.

Claims

1. A high-precision LDO circuit with low noise and high transient enhancement capability, characterized in that, The LDO circuit includes: LDO circuit body; The reference voltage generation unit provides the reference voltage required for the LDO circuit to operate. It includes a bandgap reference for generating the reference voltage and a precision low-pass filter for noise suppression of the reference voltage. When performing noise reduction processing on the reference voltage, it includes at least sequential voltage buffering and low-pass filtering. After voltage buffering of the reference voltage, a corresponding reference buffer voltage is generated. When performing low-pass filtering on the generated reference buffer voltage, at least the power supply noise and / or ground bounce interference of the reference buffer voltage should be removed so that the corresponding reference voltage can be generated after low-pass filtering, and the generated reference voltage can be applied to the LDO circuit body. The LDO circuit body includes an error amplifier, a drive buffer, a power transistor circuit, and a voltage feedback circuit, wherein... The reference voltage generated by the reference voltage generation unit is applied to the non-inverting input of the error amplifier. The output of the error amplifier is connected to the drive buffer, and the output of the drive buffer is connected to the gate of the power PMOS transistor in the power transistor circuit, so as to apply the drive voltage VG to the gate of the power PMOS transistor through the drive buffer. The drain terminal of the power PMOS transistor is connected to a voltage feedback circuit to feed back the operating sampling voltage to the inverting input of the error amplifier. The junction between the drain terminal of the power PMOS transistor and the voltage feedback circuit forms the circuit body output terminal of the LDO circuit body. It also includes a transient response detection enhancement circuit for transient response detection and enhancement, wherein, The transient response detection enhancement circuit is adapted to the output terminal of the LDO circuit body and the drive buffer to load the output voltage VOUT and drive voltage VG of the LDO circuit body output terminal onto the transient response detection enhancement circuit. Based on the output voltage VOUT, the transient response detection enhancement circuit detects the transient response of the LDO circuit itself, wherein... When a transient response change in the LDO circuit body is detected, the transient response detection enhancement circuit generates a corresponding transient response enhancement signal and loads the transient response enhancement signal into the drive buffer. The drive buffer is then configured to adjust the output drive voltage VG based on the current transient response enhancement signal, so that the output voltage VOUT of the LDO circuit body remains stable. Based on the adjusted drive voltage VG of the drive buffer, the transient response enhancement signal generated by the transient response detection enhancement circuit is controlled so that the transient response enhancement signal generated by the transient response detection enhancement circuit remains stable after transient response enhancement, that is, the transient response enhancement signal is reset. The bandgap reference includes a bandgap operational amplifier circuit and a zero-temperature-drift reference voltage output unit connected in sequence. The bandgap operational amplifier circuit adopts a gain-bootstrapping operational amplifier circuit; The zero-temperature-drift reference voltage output unit includes a zero-temperature-drift reference voltage generation unit and a reference voltage adjustment unit adapted and connected to the zero-temperature-drift reference voltage generation unit. The zero-temperature-drift reference voltage generation unit within the zero-temperature-drift reference voltage output unit is adapted and connected to the bandgap operational amplifier circuit. The zero-temperature-drift reference voltage generation unit generates a reference voltage difference, which is then converted into a corresponding zero-temperature-drift basic voltage by a bandgap operational amplifier circuit. The zero-temperature-drift base voltage is adjusted using a reference voltage adjustment unit to generate a reference voltage after adjustment. The bandgap operational amplifier circuit may include a gain bootstrap unit, a second-stage operational amplifier unit, and a first-stage operational amplifier unit. The gain bootstrap unit is connected to the second-stage operational amplifier unit, the second-stage operational amplifier unit is connected to the first-stage operational amplifier unit, and the first-stage operational amplifier unit is connected to a zero-temperature drift reference voltage generation unit. The gain bootstrap unit includes a PMOS transistor P0, an NMOS transistor N0, an NMOS transistor N1, and a resistor R0. The source terminal of the PMOS transistor P0 is connected to the power supply VDD. The drain terminal of the PMOS transistor P0 is connected to the drain terminal of the NMOS transistor N0, the gate terminal of the NMOS transistor N0, the gate terminal of the NMOS transistor N1, and the gate terminal of the NMOS transistor N2 in the second stage of the operational amplifier. The drain terminal of the NMOS transistor N1 is connected to the source terminal of the NMOS transistor N0. The source terminal of the NMOS transistor N1 is grounded through the resistor R0. The second stage of the operational amplifier includes a PMOS transistor P1, an NMOS transistor N2, an NMOS transistor N3, and a resistor R1. The source terminal of the PMOS transistor P1 is connected to the power supply VDD. The gate terminal of the PMOS transistor P1 is connected to the gate terminal of the PMOS transistor P0, the drain terminal of the PMOS transistor P1, and the drain terminal of the NMOS transistor N2. The source terminal of the NMOS transistor N2 is connected to the drain terminal of the NMOS transistor N3. The source terminal of the NMOS transistor N3 is grounded through the resistor R1. The first stage of the operational amplifier includes PMOS transistors P2, P3, and P4. The source terminal of PMOS transistor P2 is connected to the power supply VDD. The gate terminal of PMOS transistor P2 is connected to the gate terminals of PMOS transistors P1 and P0. The drain terminal of PMOS transistor P2, the source terminal of PMOS transistor P3, and the source terminal of PMOS transistor P4 are connected. The drain terminal of PMOS transistor P3 is connected to the gate terminal of NMOS transistor N3 and the drain terminal of NMOS transistor N4 in the first stage of the operational amplifier. The drain terminal of PMOS transistor P4 is connected to the gate terminal of NMOS transistor N4, the gate terminal of NMOS transistor N5 in the first stage of the operational amplifier, and the drain terminal of NMOS transistor N5. The source terminal of NMOS transistor N4 is grounded through resistor R2, and the source terminal of NMOS transistor N5 is grounded through resistor R3. The output terminal of the first stage of the operational amplifier is formed by connecting the drain terminal of PMOS transistor P3 to the drain terminal of NMOS transistor N4. The output terminal of the second stage of the operational amplifier is formed by connecting the gate terminal of PMOS transistor P1 to the drain terminal of PMOS transistor P1 and the drain terminal of NMOS transistor N2. The zero-temperature-drift reference voltage generation unit includes a PMOS transistor P5, resistors R4, R5, and R7, a PNP transistor Q0, and a PNP transistor Q1. The source terminal of PMOS transistor P5 is connected to the power supply VDD, the gate terminal of PMOS transistor P5 is connected to the gate terminal of PMOS transistor P2, the drain terminal of PMOS transistor P5 is connected to one end of resistor R4 and one end of resistor R5, the other end of resistor R4 is connected to the gate terminal of PMOS transistor P3 and one end of resistor R7, and the other end of resistor R5 is connected to the gate terminal of PMOS transistor P4 and the emitter terminal of PNP transistor Q1. The other end of resistor R7 is connected to the emitter terminal of PNP transistor Q0. The base terminals of PNP transistor Q0, PNP transistor Q1, PNP transistor Q0, and PNP transistor Q1 are all grounded.

2. The high-precision LDO circuit with low noise and high transient enhancement capability according to claim 1, characterized in that: The transient response detection and enhancement circuit includes a voltage detection and control circuit and a transient response enhancement signal generation circuit adapted and connected to the voltage detection and control circuit, wherein... The voltage detection and control circuit is connected to both the output voltage VOUT and the drive voltage VG. The transient response enhancement signal generation circuit generates a transient response enhancement signal and loads the generated transient response enhancement signal into the drive buffer; When the transient response state is determined based on the output voltage VOUT, the voltage detection and control circuit generates a voltage detection and control signal that is adapted to the current transient response state, and loads the voltage detection and control signal into the transient response enhancement signal generation circuit, so as to configure the transient response enhancement signal generation circuit to control the generated transient response enhancement signal in the direction of transient response change. Based on the adjusted drive voltage VG from the drive buffer, the voltage detection and control circuit generates a voltage detection and control signal adapted to the current drive voltage VG, and loads the voltage detection and control signal onto the transient response enhancement signal generation circuit, so as to configure the transient response enhancement signal generation circuit to control the generated transient response enhancement signal in the opposite direction of the drive voltage change. When regulating the transient response enhancement signal generated by the transient response enhancement signal generation circuit, the direction of transient response change is consistent with the direction of driving voltage change.

3. The high-precision LDO circuit with low noise and high transient enhancement capability according to claim 2, characterized in that: The voltage detection and control circuit includes a PMOS transistor P25 and an NMOS transistor N21, wherein, The source terminal of PMOS transistor P25 is connected to the output voltage VOUT through resistor R19. The gate terminal of PMOS transistor P25 is connected to the drain terminal of PMOS transistor P25, the drain terminal of NMOS transistor N21, and the gate terminal of PMOS transistor P26. The source terminal of NMOS transistor N21 is grounded. The gate terminal of NMOS transistor N21 is connected to the gate terminal of NMOS transistor N22, the drain terminal of NMOS transistor N22, and the drain terminal of PMOS transistor P26. The gate terminal of NMOS transistor N21, the gate terminal of NMOS transistor N22, the drain terminal of NMOS transistor N22, and the drain terminal of PMOS transistor P26 are interconnected to form the output connection terminal of the voltage detection and control circuit. The source terminal of PMOS transistor P26 is connected to the drain terminal of PMOS transistor P27 through resistor R20. The gate terminal of PMOS transistor P27 is connected to the drive voltage VG, and the source terminal of PMOS transistor P27 is connected to the power supply VDD. The source terminal of NMOS transistor N22 is grounded. The transient response enhancement signal generation circuit includes PMOS transistor P28, PMOS transistor P29, and NMOS transistor N23, wherein... The source terminal of PMOS transistor P28 is connected to the power supply VDD. The drain terminal of PMOS transistor P28 is connected to the source terminal of PMOS transistor P29, and the drain terminal of PMOS transistor P29 is connected to the drain terminal of NMNOS transistor N23, forming the output connection terminal of the transient response enhancement signal generation circuit. The source terminal of NMOS transistor N23 is grounded, and the gate terminal of NMOS transistor N23 is connected to the output terminal of the voltage detection and control circuit. The gate of PMOS transistor P28 is connected to the bias voltage VBP0, and the gate of PMOS transistor P29 is connected to the bias voltage VBP1.

4. The high-precision LDO circuit with low noise and high transient enhancement capability according to any one of claims 1 to 3, characterized in that: It also includes a dynamic frequency compensation circuit for frequency compensation of the LDO circuit body, wherein, The dynamic frequency compensation circuit includes a Miller structure frequency compensation unit and a load current compensation unit that performs dynamic frequency compensation based on load current. The Miller structure frequency compensation unit is adapted to the output terminal of the circuit body and the inverting terminal of the error amplifier, so as to push the pole of the inverting terminal of the error amplifier to a low frequency using the Miller structure frequency compensation unit. The load current compensation unit includes a frequency compensation variable resistor unit, which is adapted and connected to the Miller structure frequency compensation unit. The resistance value of the frequency compensation variable resistor unit is configured based on the driving voltage VG so that the resistance value of the frequency compensation variable resistor is adapted to the load current. After configuring the resistance value of the frequency compensation variable resistor using the driving voltage VG, loop frequency compensation is performed on the LDO circuit body based on the frequency compensation variable resistor unit and the Miller structure compensation unit.

5. The high-precision LDO circuit with low noise and high transient enhancement capability according to claim 1, characterized in that: The reference voltage adjustment unit includes several current adjustment units based on current adjustment, wherein the current adjustment unit includes a current adjustment main unit and an adjustment reset control signal generation unit adapted and connected to the current adjustment main unit. When performing current adjustment based on the current adjustment unit, pre-adjustment is first performed using the main current adjustment unit, followed by post-adjustment. During pre-adjustment, the pre-adjustment data is loaded into the current adjustment master unit so that the current adjustment master unit generates a pre-adjustment status signal corresponding to the pre-adjustment data. Based on the pre-adjustment state signal generated by the pre-adjustment, the current adjustment target state signal of the current adjustment master unit during the post-adjustment is determined, wherein the state of the current adjustment target state signal is an adjustment effective state or an adjustment ineffective state. During post-adjustment, based on the current adjustment target state signal, the target adjustment data is loaded into the current adjustment main unit, and the corresponding current adjustment target state signal is output through the current adjustment unit. Furthermore, a dual-mode adjustment state signal is formed based on the current adjustment target state signal. When the current adjustment target status signal is in the adjustment active state, the polycrystalline fuse in the current adjustment main unit is blown by current blowing based on the current adjustment target status signal and the adjustment enable signal in the active state, so as to lock the current adjustment target status signal output by the current adjustment main unit after the polycrystalline fuse blows. After the current trimming unit is powered on again, the trimming reset control signal generation unit generates a trimming reset control signal so that the current trimming master unit configures the generated trimming status signal as the corresponding current trimming target status signal under the trimming reset control signal.

6. The high-precision LDO circuit with low noise and high transient enhancement capability according to any one of claims 1 to 3, characterized in that: The precise low-pass filter includes a voltage buffer device for performing voltage buffering processing and a low-pass filter for performing low-pass filtering processing, wherein... The voltage buffer includes a PMOS transistor P8 that receives a reference voltage. The source terminal of PMOS transistor P8 is connected to the source terminal of PMOS transistor P9 and the drain terminal of PMOS transistor P7. The source terminal of PMOS transistor P7 is connected to the drain terminal of PMOS transistor P6. The drain terminal of PMOS transistor P8 is connected to the drain terminal of NMOS transistor N6, the gate terminal of NMOS transistor N6, and the gate terminal of NMOS transistor N7. The source terminal of NMOS transistor N6 is grounded through resistor R9, and the source terminal of NMOS transistor N7 is grounded through resistor R10. The drain of NMOS transistor N7 is connected to the drain of PMOS transistor P9 and the gate of NMOS transistor N9. The source of NMOS transistor N9 is grounded through resistor R11. The drain of NMOS transistor N9 is connected to the source of NMOS transistor N8, the gate of PMOS transistor P10, and the gate of PMOS transistor P12. The drain of NMOS transistor N8 is connected to the drain of PMOS transistor P11. The source of PMOS transistor P11 is connected to the drain of PMOS transistor P10. The drain of PMOS transistor P12 is connected to the source of PMOS transistor P13. The drain of PMOS transistor P13 is connected to one end of resistor R12. The other end of resistor R12 is connected to the gate of PMOS transistor P9, one end of resistor R13, and the low-pass filter adapter. The other end of resistor R13 is connected to the voltage buffer trimming unit adapter. The source terminals of PMOS transistors P6, P10, and P12 are all connected to the power supply VDD.

7. The high-precision LDO circuit with low noise and high transient enhancement capability according to any one of claims 1 to 3, characterized in that: The error amplifier includes a rail-to-rail input stage and a high-gain output stage, wherein... The error amplifier rail-to-rail input stage receives the reference voltage and is connected to the drive buffer through the error amplifier high-gain output stage. The error amplification rail-to-rail input stage includes a reference voltage receiver and a sampling voltage receiver. The reference voltage is applied to the reference voltage receiver, and the working sampling voltage is applied to the sampling voltage receiver. The reference voltage receiving section includes an NMOS transistor N12, a PMOS transistor P21, and an NMOS transistor N14. The reference voltage is simultaneously applied to the gate terminals of the NMOS transistor N12, the PMOS transistor P21, and the NMOS transistor N14. The sampling voltage receiving section includes an NMOS transistor N13, a PMOS transistor P22, and an NMOS transistor N15. The working sampling voltage is simultaneously applied to the gate terminals of the NMOS transistor N13, the PMOS transistor P22, and the NMOS transistor N15. The drain of NMOS transistor N12, the source of PMOS transistor P21, the source of PMOS transistor P22, and the drain of NMOS transistor N13 are all connected to the drain of PMOS transistor P20. The source and base of PMOS transistor P20 are connected to the drain of PMOS transistor P19. The source of PMOS transistor P19 is connected to the power supply VDD. The source of NMOS transistors N12 and NMOS transistor N13 are both grounded. The source terminals of NMOS transistors N14 and N15 are connected to the drain terminal of NMOS transistor N16, the source terminal of NMOS transistor N16 is connected to the drain terminal of NMOS transistor N17, and the source terminal of NMOS transistor N17 is grounded. The drain terminal of PMOS transistor P21 is connected to one end of the internal resistor R14 of the error amplification high-gain output stage and the source terminal of PMOS transistor P23. The drain terminal of PMOS transistor P22 is connected to one end of the internal resistor R15 of the error amplification high-gain output stage and the source terminal of PMOS transistor P24. The other ends of resistors R14 and R15 are both connected to the power supply VDD. The drain terminal of PMOS transistor P23 is connected to the drain terminal of NMOS transistor N14, the drain terminal of NMOS transistor N18 in the error amplification high-gain output stage, the gate terminal of NMOS transistor N18, and the gate terminal of NMOS transistor N19 in the error amplification high-gain output stage. The drain terminals of NMOS transistor N19, NMOS transistor N15, PMOS transistor P24, and the error amplification frequency compensation unit in the high-gain output stage of the error amplifier are interconnected to form the error amplification output terminal of the error amplifier. The source terminal of NMOS transistor N18 is grounded through resistor R16, and the source terminal of NMOS transistor N19 is grounded through resistor R17. The gate of PMOS transistor P10 is connected to the bias voltage VBP0, the gate of PMOS transistor P20 is connected to the bias voltage VBP1, and the gates of PMOS transistors P23 and PMOS transistor P24 are both connected to the bias voltage VBP2. The gate of NMOS transistor N16 is connected to a bias voltage VBN1, and the gate of NMOS transistor N16 is connected to a bias voltage VBN0.

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