Current comparison circuit and electronic chip for external resistor identification

Abstract

The current comparison circuit and electronic chip for external resistor identification provided in this disclosure include: a pin current determination module, a current mirroring module, and N current comparison modules; wherein, the pin current determination module is configured to bias the pin voltage of the mode selection pin to a reference voltage based on a reference voltage, and obtain the pin current based on the pin voltage and the external resistor; the current mirroring module is configured to mirror the pin current to each current comparison module; the current comparison modules are configured to output a level signal based on the reference current and the mirrored pin current, and different reference resistors correspond to different current comparison modules, and the reference current corresponding to different current comparison modules is determined based on the reference resistor and the reference voltage, which simplifies the current comparison circuit logic, saves circuit area, and shortens the time required to identify the external resistor value.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology and related technical fields, and more specifically, to a current comparison circuit and electronic chip suitable for off-chip resistor identification. Background Technology

[0002] In existing technologies, users can connect a resistor to the mode selection pin of a chip. The chip selects its operating mode, operating frequency, etc., by recognizing the resistance value of the external resistor connected to the mode selection pin. Current methods for selecting chip operating modes and frequencies typically involve injecting a preset reference current (IMODE) into the mode selection pin, sampling the voltage at the pin (VMODE = IMODE * RMODE), comparing it with an internal reference voltage (VREF), and then using the comparison result to determine the resistance value of the external resistor connected to the mode selection pin, thereby selecting the chip's operating mode or operating frequency.

[0003] However, existing solutions require time-division multiplexing to use the same voltage comparator to determine the range of the external resistor. Therefore, a time-division multiplexing control circuit is needed to switch the reference current and voltage for each range, sample and compare them, and finally register and integrate the results of each judgment to determine the range of the external resistor connected to the mode selection pin. Furthermore, during the injection of reference current into the mode selection pin, the parasitic capacitance connected in parallel with the external resistor will shunt the current. To obtain an accurate mode selection pin voltage and sample it, sufficient time must be waited for the potential on the parasitic capacitance to stabilize, allowing all the reference current to flow to the external resistor. Similarly, switching the reference voltage between different ranges within the chip presents similar problems. The internal reference voltage is typically divided by a resistor series and then transmitted to the comparator's input stage via a low-pass filter. Due to limited load capacity, once the reference voltage value changes, a corresponding stabilization time is required before the comparator can perform a comparison; otherwise, it may output an incorrect comparison result.

[0004] Because the existing solution uses time-division multiplexing control logic, it is necessary to wait for the sampling signal to stabilize when judging each preset position. Therefore, when judging the resistance value of multiple positions, the sampling signal stabilization time required for the entire detection process is more significant. Summary of the Invention

[0005] The embodiments described herein provide a current comparison circuit and electronic chip for off-chip resistor identification that, compared to existing solutions, charges the mode selection pin faster, requires less settling time, eliminates the need for time-division multiplexing timing control, and reduces the time required for the chip to identify the resistance value of the off-chip resistor.

[0006] In a first aspect, according to the present disclosure, a current comparison circuit for identifying an external resistor is provided. The current comparison circuit includes a mode selection pin, which is electrically connected to the external resistor, and includes: a pin current determination module, a current mirroring module, a reference current generation module, and N current comparison modules.

[0007] The pin current determination module is configured to bias the pin voltage of the mode selection pin to the reference voltage based on the reference voltage, and obtain the pin current based on the pin voltage and the external resistor.

[0008] The current mirroring module is configured to mirror the pin current to each current comparison module;

[0009] The current comparison module is configured to output a level signal based on the reference current and the mirrored pin current. Different current comparison modules correspond to different reference resistors, and the reference current corresponding to different current comparison modules is determined based on the reference resistor, the reference voltage, and the mirror ratio of the current mirror module.

[0010] In some embodiments of this disclosure, the pin current determination module includes an amplifier and a first transistor. The positive input terminal of the amplifier receives a reference voltage. The inverting input terminal of the amplifier and the second terminal of the first transistor are electrically connected to the mode selection pin. The output terminal of the amplifier is electrically connected to the control terminal of the first transistor. The first terminal of the first transistor is electrically connected to the current mirror module.

[0011] In some embodiments of this disclosure, the current mirror module includes N+1 second transistors, the first terminal of each second transistor is electrically connected to a power supply voltage node, the second terminal of the first second transistor is electrically connected to the control terminal of each second transistor, and the second terminals of the other second transistors, except for the first second transistor, are electrically connected to a current comparison module.

[0012] In some embodiments of this disclosure, the current comparison module includes a buffer, the input of which simultaneously receives the pin current and a reference current, and the output of which outputs a level signal.

[0013] In some embodiments of this disclosure, a control module is also included;

[0014] The control module is configured to determine the resistance range of the external resistor based on the level signals output by each of the current comparison modules, and to output a control signal to the reference voltage generation module when the level signals output by each of the current comparison modules are both high or low, thereby controlling the reference voltage generated by the reference voltage generation module to output the reference voltage to the pin current determination module.

[0015] In some embodiments of this disclosure, the reference current is generated based on a reference current generation module inside the current comparison circuit, or based on a reference current generation module outside the current comparison circuit.

[0016] In some embodiments of this disclosure, the first transistor is an NMOS transistor and the second transistor is a PMOS transistor.

[0017] Secondly, according to the present disclosure, an electronic chip is provided, including an off-chip resistor identification current comparator circuit as described in any one of the first aspects.

[0018] The current comparison circuit and electronic chip for external resistor identification provided in this disclosure first determine the pin voltage of the mode selection pin through the feedback loop of the pin current determination module. Then, after the pin voltage potential stabilizes, the pin current is determined based on the pin voltage of the mode selection pin and the external resistor. Compared to the prior art, which injects a fixed reference current into the mode selection pin and waits for the pin voltage potential to stabilize before determining the reference voltage based on the reference current and the external resistor, the charging time of the capacitor based on the fixed voltage is shorter in this solution than the charging time of the capacitor based on the fixed current. Therefore, the time required to wait for the potential of the capacitor connected in parallel with the external resistor to stabilize is shorter. The shorter length reduces the time required for the chip to identify the resistance value of the external resistor. In addition, the current mirroring module samples the pin current and mirrors it to each current comparison module. Then, different current comparison modules receive the reference current and compare the reference current with the mirrored pin current. This eliminates the need for time-division multiplexing timing control, greatly simplifying the logic complexity and saving corresponding chip area. Furthermore, since the current comparison module compares the reference current and the pin current, it is not necessary to build a high-precision reference voltage generation module for each comparison module branch, which simplifies the logic of the current comparison circuit and reduces the overall size of the circuit. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0020] Figure 1 This is a schematic diagram of the structure of a current comparison circuit for identifying an external resistor provided in an embodiment of this disclosure;

[0021] Figure 2 This is a schematic diagram of the specific circuit structure of a current comparison circuit for identifying an external resistor provided in an embodiment of this disclosure;

[0022] Figure 3This is a schematic diagram of another current comparison circuit for identifying off-chip resistors provided in an embodiment of this disclosure. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0025] In all embodiments of this disclosure, terms such as “first” and “second” are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0026] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0027] Based on the problems existing in the prior art, this disclosure provides a current comparison circuit for identifying external resistors. Figure 1This is a schematic diagram of the structure of the current comparison circuit for external resistor identification provided in this embodiment. The current comparison circuit for external resistor identification includes a mode selection pin MODE, which is electrically connected to an external resistor Rmode. The current comparison circuit for external resistor identification includes: a pin current determination module 10, a current mirroring module 20, and N current comparison modules 40. The pin current determination module 10 is configured to bias the pin voltage of the mode selection pin MODE to a reference voltage, and obtain the pin current based on the pin voltage and the external resistor. The current mirroring module 20 is configured to mirror the pin current to each current comparison module 40. The current comparison modules 40 are configured to output a level signal based on the reference current and the mirrored pin current. Different current comparison modules correspond to different reference resistors, and the reference current corresponding to different current comparison modules is determined based on the reference resistor, the reference voltage, and the mirroring ratio of the current mirroring modules.

[0028] The current comparison circuit for external resistor identification provided in this embodiment of the disclosure includes a pin current determination module 10. The pin current determination module 10 first biases a reference voltage onto the mode selection pin MODE. After receiving the reference voltage, the mode selection pin MODE determines the pin current flowing through it based on the external resistor Rmode connected to it and the reference voltage. Then, a current mirroring module 20 mirrors the pin current to each current comparison module 40. Each current comparison module 40 receives the reference current and the pin current mirrored by the current mirroring module 20, compares the reference current and the pin current, and outputs a level signal. Each current comparison module 40 outputs a level signal based on the reference current and the pin current. Since different current comparison modules correspond to different reference resistors, the resistance range of the external resistor electrically connected to the mode selection pin can be determined based on the level signal output by the current comparison module 40, thereby selecting the operating mode or operating frequency of the electronic chip.

[0029] It should be noted that the number of current comparison modules provided in the current comparison circuit for external resistor identification in the embodiments of this disclosure is not specifically limited.

[0030] As a specific example, such as Figure 3As shown, the current comparison circuit for external resistor identification includes four current comparison modules 40. The reference voltage is Vref, and the external resistor is Rmode. The pin voltage of the mode selection pin satisfies: Vmode = Vref, and the pin current satisfies: Imode = Vmode / Rmode = Vref / Rmode. By using the mirroring ratio of the current mirroring module, the pin current input to the first current comparison module can be determined as Imode1 = N1 * Vmode / Rmode = N1 * Vref / Rmode, the pin current input to the second current comparison module is Imode2 = N2 * Vmode / Rmode = N2 * Vref / Rmode, and the pin current input to the third current comparison module is... The pin current of the block is Imode3 = N3 * Vmode / Rmode = N3 * Vref / Rmode, and the pin current input to the fourth current comparison module is Imode4 = N4 * Vmode / Rmode = N4 * Vref / Rmode. N1 is the mirroring ratio of the pin current to the branch corresponding to the first current comparison module by the current mirroring module, N2 is the mirroring ratio of the pin current to the branch corresponding to the second current comparison module by the current mirroring module, N3 is the mirroring ratio of the pin current to the branch corresponding to the third current comparison module by the current mirroring module, and N4 is the mirroring ratio of the pin current to the branch corresponding to the second current comparison module by the current mirroring module. The first current comparison module receives a reference current of Iref1, the second current comparison module receives a reference current of Iref2, the third current comparison module receives a reference current of Iref3, and the fourth current comparison module receives a reference current of Iref4. The first current comparison module outputs a level signal by comparing the comparison pin current Imode1 and the reference current Iref1, the second current comparison module outputs a level signal by comparing the comparison pin current Imode2 and the reference current Iref2, the third current comparison module outputs a level signal by comparing the comparison pin current Imode3 and the reference current Iref3, and the fourth current comparison module outputs a level signal by comparing the comparison pin current Imode4 and the reference current Iref4. Based on the level signals output by each comparison module, the resistance range of the external resistor connected to the mode selection pin is determined.

[0031] For example, if the reference resistor for the first current comparator module is 10kΩ, the reference resistor for the second current comparator module is 20kΩ, the reference resistor for the third current comparator module is 30kΩ, and the reference resistor for the fourth current comparator module is 40kΩ, and the output signal of the first current comparator module is high, the output signal of the second current comparator module is low, the output signal of the third current comparator module is low, and the output signal of the fourth current comparator module is low, then it can be determined that the external resistor connected to the mode selection pin is within the 10kΩ to 20kΩ resistance range.

[0032] It should be noted that in the above embodiments, the reference currents corresponding to different reference currents can be determined based on the reference voltage, the reference resistance, and the mirror ratio of the current mirror module. For example, the reference current Iref1 is determined based on the reference voltage Vref, the reference resistance of the first current comparison module, and the mirror ratio of the current mirror module; the reference current Iref2 is determined based on the reference voltage Vref, the reference resistance of the second current comparison module, and the mirror ratio of the current mirror module; the reference current Iref3 is determined based on the reference voltage Vref, the reference resistance of the third current comparison module, and the mirror ratio of the current mirror module; and the reference current Iref4 is determined based on the reference voltage Vref, the reference resistance of the fourth current comparison module, and the mirror ratio of the current mirror module.

[0033] Furthermore, in the above embodiments, if the level signals output by the four current comparison modules 40 are all low, it indicates that the pin current output by the pin current determination module to each current comparison module is less than the minimum value of the reference current generated by the reference current generation module. In this case, the pin current output to each current comparison module can be increased by increasing the reference voltage. If the level signals output by the four current comparison modules are all high, it indicates that the pin current output by the pin current determination module to each current comparison module is greater than the reference current generated by the reference current generation module. In this case, the pin current output to each current comparison module can be decreased by decreasing the reference voltage.

[0034] The current comparison circuit for external resistor identification provided in this embodiment first determines the pin voltage of the mode selection pin through the feedback loop of the pin current determination module. Then, after the pin voltage potential stabilizes, it determines the pin current based on the pin voltage of the mode selection pin and the external resistor. Compared to the prior art, which injects a fixed reference current into the mode selection pin and waits for the pin voltage potential to stabilize before determining the reference voltage based on the reference current and the external resistor, the charging time of the capacitor based on a fixed voltage is shorter than that based on a fixed current. Therefore, the time required for the potential of the capacitor connected in parallel with the external resistor to stabilize is shorter. The short circuit reduces the time required for the chip to identify the resistance value of the external resistor. In addition, the current mirroring module samples the pin current and mirrors it to each current comparison module. Then, different current comparison modules receive the reference current and compare the reference current with the mirrored pin current. This eliminates the need for time-division multiplexing timing control, greatly simplifying the logic complexity and saving corresponding chip area. Furthermore, since the current comparison module compares the reference current and the pin current, it is not necessary to build a high-precision reference voltage generation module for each comparison module branch, which simplifies the logic of the current comparison circuit and reduces the overall size of the circuit.

[0035] Based on the above embodiments, Figure 2 This is a schematic diagram of the circuit structure of a current comparison circuit for identifying an external resistor provided in an embodiment of this disclosure, as shown below. Figure 2 As shown, the pin current determination module 10 includes an amplifier A and a first transistor M1. The positive input terminal of the amplifier A receives a reference voltage Vref. The inverting input terminal of the amplifier A and the second terminal of the first transistor M1 are electrically connected to the mode selection pin MODE. The output terminal of the amplifier A is electrically connected to the control terminal of the first transistor M1. The first terminal of the first transistor M1 is electrically connected to the current mirror module 20.

[0036] Specifically, such as Figure 2 As shown, the pin current determination module 10 includes amplifier A and first transistor M1. A feedback loop is constructed based on amplifier A and first transistor M1 to realize that the pin voltage Vmode of the mode selection pin MODE follows the reference voltage Vref. At this time, the current flowing through the external resistor Rmode is Imode=Vmode / Rmode=Vref / Rmode. The current flowing through the first transistor is the same as the current flowing through the external resistor, which is the pin current.

[0037] Based on the above embodiments, see below. Figure 2The current mirror module 20 includes N+1 second transistors. The first terminal of each second transistor is electrically connected to the power supply voltage node, the second terminal of the first second transistor is electrically connected to the control terminal of each second transistor, and the second terminals of the other second transistors are electrically connected to a current comparison module 40.

[0038] For example, in combination Figure 2 When the current comparison module 40 includes 4 modules, the number of second transistors is 5. The first second transistor collects the pin current flowing through the first transistor and mirrors the collected pin current flowing through the first transistor to the first current comparison module through the second second transistor. The collected pin current flowing through the first transistor is mirrored to the second current comparison module through the third second transistor. The collected pin current flowing through the first transistor is mirrored to the third current comparison module through the fourth second transistor. The collected pin current flowing through the first transistor is mirrored to the fourth current comparison module through the fifth second transistor.

[0039] It should be noted that in the above embodiments, the first transistor is an NMOS transistor and the second transistor is a PMOS transistor.

[0040] Furthermore, the mirroring ratio of the pin current to each current comparison module can be the same or different, and this disclosure does not specifically limit this.

[0041] In a specific implementation, the reference current can be generated based on the reference current generation module inside the current comparison circuit, or it can be generated based on the reference current generation module outside the current comparison circuit.

[0042] Figure 2 For example, the reference current is generated based on the reference current generation module 30 inside the current comparison circuit, such as... Figure 2 As shown, the reference current generation module 30 includes a current source, the first end of which is electrically connected to the current comparison module, and the second end of which is electrically connected to the grounding node.

[0043] By setting a reference current generation module including a current source, a reference current is generated through the current source. The reference current generated by the current source in one reference current generation module is output to a corresponding current comparison module.

[0044] For example, the reference current generated by the current source included in the first reference current generation module is Iref1, the reference current generated by the current source included in the second reference current generation module is Iref2, the reference current generated by the current source included in the third reference current generation module is Iref3, and the reference current generated by the current source included in the fourth reference current generation module is Iref4. The reference current received by the first current comparison module is the reference current Iref1 generated by the current source included in the first reference current generation module, the reference current received by the second current comparison module is the reference current Iref2 generated by the current source included in the second reference current generation module, the reference current received by the third current comparison module is the reference current Iref3 generated by the current source included in the third reference current generation module, and the reference current received by the fourth current comparison module is the reference current Iref4 generated by the current source included in the fourth reference current generation module.

[0045] Based on the above embodiments, see below. Figure 2 The current comparison module 40 includes a buffer. The input of the buffer receives the pin current and the reference current, respectively, and the output of the buffer outputs a level signal.

[0046] like Figure 2 As shown, the current comparison module includes a buffer, which receives the pin current and the reference current respectively. When the pin current is greater than the reference current, the buffer outputs a high-level signal, and when the pin current is less than the reference current, the buffer outputs a low-level signal. By using the level signals output by each buffer, the resistance range of the external resistor connected to the mode selection pin can be determined, thereby determining the working module or operating frequency of the electronic chip.

[0047] Based on the above embodiments, Figure 3 This is a schematic diagram of another current comparison circuit for external resistor identification provided in this embodiment of the disclosure, as shown below. Figure 3 As shown, the current comparison circuit for external resistor identification also includes: a control module; the control module is configured to determine the resistance value range of the external resistor based on the level signals output by each current comparison module, and to output a control signal to the reference voltage generation module when the level signals output by each current comparison module are both high or low, thereby controlling the reference voltage generated by the reference voltage generation module to output the reference voltage of the pin current determination module.

[0048] Specifically, the current comparison circuit for identifying external resistors provided in this embodiment of the present disclosure further includes a control module 50. The control module 50 acquires the level signals output by each current comparison module, and then determines the resistance range of the external resistor connected to the mode selection pin based on the level signals output by each current comparison module.

[0049] In a specific implementation, the reference voltage can be generated based on the reference voltage generation module 60 inside the current comparison circuit, or it can be generated based on the reference voltage generation module outside the current comparison circuit. This disclosure does not specifically limit this.

[0050] In one implementation, the reference voltage generation module 60 includes M resistors connected in series.

[0051] For example, if the reference resistor corresponding to the reference current Iref1 is 10kΩ, the reference resistor corresponding to the reference current Iref2 is 20kΩ, the reference resistor corresponding to the reference current Iref3 is 30kΩ, and the reference resistor corresponding to the reference current Iref4 is 40kΩ, and if the level signal output by the first current comparison module is high, the level signal output by the second current comparison module is low, the level signal output by the third current comparison module is low, and the level signal output by the fourth current comparison module is low, then it can be determined that the resistance value of the external resistor connected to the mode selection pin is in the range of 10kΩ to 20kΩ.

[0052] Furthermore, in the above embodiments, if the level signals output by the four current comparison modules are all low, it indicates that the pin current output by the pin current determination module to each current comparison module is less than the minimum value of the reference current generated by the reference current generation module. In this case, the control module increases the pin current output to each current comparison module by controlling the reference voltage output by the reference voltage generation module to the pin current determination module. If the level signals output by the four current comparison modules are all high, it indicates that the pin current output by the pin current determination module to each current comparison module is greater than the reference current generated by the reference current generation module. In this case, the control module decreases the pin current output to each current comparison module by controlling the reference voltage output by the reference voltage generation module to the pin current determination module.

[0053] It should be noted that, Figure 3 The example shows that the reference current is generated based on the reference current generation module 30 inside the current comparison circuit. The reference current can also be generated based on the reference current generation module outside the current comparison circuit. This disclosure does not specifically limit this.

[0054] Embodiments of this disclosure also provide an electronic chip. This electronic chip includes an off-chip resistor identification current comparison circuit as provided in embodiments of this disclosure.

[0055] Embodiments of this disclosure also provide an electronic device. This electronic device includes an electronic chip according to embodiments of this disclosure. The electronic device is, for example, a smart terminal device, such as a tablet computer or smartphone.

[0056] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0057] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. Moreover, the above embodiment numbers are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0058] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0059] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A current comparison circuit for identifying an external resistor, the current comparison circuit including a mode selection pin, the mode selection pin being electrically connected to a first terminal of an external resistor, and a second terminal of the external resistor being electrically connected to a ground node, characterized in that, include: Pin current determination module, current mirroring module, and N current comparison modules; The pin current determination module is configured to bias the pin voltage of the mode selection pin to the reference voltage based on the reference voltage, and obtain the pin current based on the pin voltage and the external resistor. The current mirroring module is configured to mirror the pin current to each current comparison module; The current comparison module is configured to output a level signal based on the reference current and the mirrored pin current. Different current comparison modules correspond to different reference resistors, and the reference current corresponding to different current comparison modules is determined based on the reference resistor, the reference voltage, and the mirror ratio of the current mirror module. It also includes a control module; The control module is configured to determine the resistance range of the external resistor based on the level signals output by each of the current comparison modules, and to output a control signal to the reference voltage generation module when the level signals output by each of the current comparison modules are both high or low, thereby controlling the reference voltage generated by the reference voltage generation module to output the magnitude of the reference voltage to the pin current determination module. The reference current is generated based on a reference current generation module inside the current comparison circuit, or based on a reference current generation module outside the current comparison circuit. The pin current determination module includes an amplifier and a first transistor. The positive input terminal of the amplifier receives a reference voltage. The inverting input terminal of the amplifier and the second terminal of the first transistor are electrically connected to the mode selection pin. The output terminal of the amplifier is electrically connected to the control terminal of the first transistor. The first terminal of the first transistor is electrically connected to the current mirror module.

2. The circuit according to claim 1, characterized in that, The current mirror module includes N+1 second transistors. The first terminal of each second transistor is electrically connected to the power supply voltage node, the second terminal of the first second transistor is electrically connected to the control terminal of each second transistor, and the second terminals of the other second transistors (excluding the first second transistor) are electrically connected to a current comparison module.

3. The circuit according to claim 1, characterized in that, The current comparison module includes a buffer, the input of which simultaneously receives the pin current and the reference current, and the output of which outputs a level signal.

4. The circuit according to claim 2, characterized in that, The first transistor is an NMOS transistor, and the second transistor is a PMOS transistor.

5. An electronic chip, characterized in that, Includes the current comparison circuit as described in any one of claims 1-4.

Images