Display panel and display device

Abstract

The application discloses a display panel and a display device, the display panel comprises: at least one pixel circuit, the pixel circuit comprises a drive transistor, a first capacitor and a second capacitor; the first gate of the drive transistor is connected with the first capacitor, and the first capacitor is used for storing the voltage of the first gate of the drive transistor; the first pole of the drive transistor is connected with the second capacitor, and the second capacitor is used for coupling a data voltage to the first gate of the drive transistor, wherein the capacitance value of the second capacitor is greater than the capacitance value of the first capacitor, wherein the capacitance value of the second capacitor is greater than the capacitance value of the first capacitor, the write range of the data voltage is reduced, the difference of display brightness is improved, and the uniformity of display is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the continuous development of display technology, people have increasingly higher requirements for display quality. However, the existing display panels have poor display effects and cannot meet the needs of high-quality displays. Summary of the Invention

[0003] This invention provides a display panel and display device that reduces the writing range of data voltage, improves the difference in display brightness, and enhances the uniformity of the display.

[0004] In a first aspect, embodiments of the present invention provide a display panel, comprising:

[0005] At least one pixel circuit, the pixel circuit including a driving transistor, a first capacitor and a second capacitor;

[0006] The first gate of the driving transistor is connected to the first capacitor, which is used to store the voltage of the first gate of the driving transistor; the first terminal of the driving transistor is connected to the second capacitor, which is used to couple the data voltage to the first gate of the driving transistor, wherein the capacitance value of the second capacitor is greater than the capacitance value of the first capacitor.

[0007] Optionally, the capacitance ratio of the second capacitor to the first capacitor is in the range of 1.2-2.4;

[0008] Optionally, the capacitance ratio of the second capacitor to the first capacitor ranges from 1.6 to 2.0;

[0009] Optionally, the capacitance ratio of the second capacitor to the first capacitor is 1.8;

[0010] Optionally, the capacitance value of the first capacitor is in the range of 50F-100F; the capacitance value of the second capacitor is in the range of 80F-200F.

[0011] Optionally, the display panel further includes:

[0012] Substrate;

[0013] A first conductive layer and a second conductive layer, wherein the first conductive layer is located on one side of the substrate, and the second conductive layer is located on the side of the first conductive layer away from the substrate;

[0014] The first plate of the first capacitor is located on the first conductive layer, and the second plate of the first capacitor is located on the second conductive layer; the first plate of the second capacitor is located on the first conductive layer, and the second plate of the second capacitor is located on the second conductive layer.

[0015] The overlapping area of ​​the orthographic projection of the first plate of the second capacitor on the substrate and the orthographic projection of the second plate of the second capacitor on the substrate is greater than the overlapping area of ​​the orthographic projection of the first plate of the first capacitor on the substrate and the orthographic projection of the second plate of the first capacitor on the substrate.

[0016] Preferably, the first plate of the first capacitor and / or the second plate of the first capacitor include a hole region, and the overlapping position of the orthographic projection of the first plate of the first capacitor on the substrate and the orthographic projection of the second plate of the first capacitor on the substrate at least partially covers the orthographic projection of the hole region on the substrate.

[0017] Optionally, the first gate of the driving transistor is located in the second conductive layer, and the second plate of the first capacitor is multiplexed as the first gate of the driving transistor;

[0018] Optionally, the minimum distance between the orthographic projection of the second plate of the first capacitor on the substrate and the orthographic projection of the first plate of the second capacitor and the second plate of the second capacitor on the substrate is greater than or equal to 3 μm.

[0019] Optionally, the orthographic projection of the first plate of the second capacitor on the substrate at least covers the orthographic projection of the second plate of the second capacitor on the substrate; the minimum distance between the orthographic projection of the second plate of the first capacitor on the substrate and the orthographic projection of the first plate of the second capacitor on the substrate is greater than or equal to 3 μm.

[0020] Optionally, the display panel further includes:

[0021] A first active layer is located on the side of the second conductive layer away from the substrate, and the first active layer extends along a first direction; a third conductive layer is located on the side of the first active layer away from the substrate; the driving transistor includes a second gate, the second gate is located on the third conductive layer, and the second gate of the driving transistor is connected to the second electrode of the driving transistor.

[0022] Wherein, the portion of the first active layer located below the orthographic projection of the second gate of the driving transistor is the channel region of the driving transistor, and the orthographic projection of the second plate of the first capacitor on the substrate at least covers the orthographic projection of the channel region of the driving transistor on the substrate.

[0023] Optionally, in the first direction, the orthographic projection of the second plate of the first capacitor onto the substrate exceeds the orthographic projection of the channel region of the driving transistor onto the substrate by at least a first length dimension;

[0024] Optionally, the first length dimension ranges from 0.4μm to 2μm;

[0025] Optionally, the first length dimension is 1 μm;

[0026] Optionally, in the second direction, the orthographic projection of the second plate of the first capacitor onto the substrate extends beyond the orthographic projection of the channel region of the driving transistor onto the substrate by at least a second length dimension; the second direction is perpendicular to the first direction;

[0027] Optionally, the second length dimension ranges from 2μm to 4μm;

[0028] Optionally, the second length dimension is 3 μm.

[0029] Optionally, the first plate of the first capacitor projects onto the substrate in a positive projection that at least partially covers the positive projection of the channel region of the driving transistor onto the substrate.

[0030] Optionally, the orthographic projection of the second gate of the driving transistor onto the substrate at least covers the orthographic projection of the channel region of the driving transistor onto the substrate;

[0031] Optionally, the second plate of the first capacitor is orthogonally projected onto the substrate, at least covering the orthogonal projection of the second gate of the driving transistor onto the substrate.

[0032] Optionally, the display panel further includes a fourth conductive layer, which is located on the side of the third conductive layer away from the substrate. The fourth conductive layer includes a first connection line, and the second gate of the driving transistor is connected to the second electrode of the driving transistor through the first connection line.

[0033] Optionally, the second gate of the driving transistor is connected to one end of the first connection line via the first via, and the first electrode of the driving transistor is connected to the other end of the first connection line via the second via.

[0034] Optionally, the orthogonal projection of the first connection line on the substrate at least partially covers the orthogonal projection of the second gate of the driving transistor on the substrate.

[0035] Optionally, the display panel further includes:

[0036] A first active layer is located on the side of the second conductive layer away from the substrate, and the first active layer extends along a first direction;

[0037] A third conductive layer is located on the side of the first active layer away from the substrate, and the first gate of the driving transistor is located in the third conductive layer; wherein, the portion of the first active layer located below the orthographic projection of the first gate of the driving transistor is the channel region of the driving transistor.

[0038] Optionally, the orthographic projection of the first gate of the driving transistor on the substrate at least partially covers the orthographic projection of the channel region of the driving transistor on the substrate;

[0039] Optionally, the orthographic projection of the second plate of the first capacitor onto the substrate does not overlap with the orthographic projection of the channel region of the driving transistor onto the substrate.

[0040] Optionally, the orthographic projection of the first plate of the first capacitor onto the substrate at least partially covers the orthographic projection of the channel region of the driving transistor onto the substrate.

[0041] Secondly, embodiments of the present invention provide a display device, including the display panel described in any embodiment of the present invention.

[0042] The display panel provided in this embodiment of the invention has a data voltage range corresponding to the display panel from the highest brightness to the black state. This range is related to the capacitance value c1 of the first capacitor C1 and the capacitance value c2 of the second capacitor C2. Setting the capacitance value c2 of the second capacitor C2 to be greater than the capacitance value c1 of the first capacitor C1 can reduce the data voltage range corresponding to the display panel from the highest brightness to the black state. This is beneficial for the driver chip to provide more accurate data voltage, reduces the fluctuation of data voltage, and thus improves the difference in display brightness and enhances the uniformity of the display. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0044] Figure 2 A schematic diagram of the driving timing of a pixel circuit provided in an embodiment of the present invention;

[0045] Figure 3 This is a schematic diagram of a planar structure of a display panel provided in an embodiment of the present invention;

[0046] Figure 4 for Figure 3 The diagram shows a cross-sectional view of the display panel along section line AA'.

[0047] Figure 5 This is a schematic diagram of the layout structure of a first capacitor provided in an embodiment of the present invention;

[0048] Figure 6 A schematic diagram of the layout structure of another first capacitor provided in an embodiment of the present invention;

[0049] Figure 7 A schematic diagram of the layout structure of another first capacitor provided in an embodiment of the present invention;

[0050] Figure 8 A schematic diagram of a planar structure of another display panel provided in an embodiment of the present invention;

[0051] Figure 9 for Figure 8 The diagram shows a cross-sectional view of the display panel along the cutting line BB'.

[0052] Figure 10 For the reason Figure 8 The diagram shows a cross-sectional view of the display panel along the section line CC'.

[0053] Figure 11 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0054] Figure 12 A schematic diagram of another planar structure of a display panel provided in an embodiment of the present invention;

[0055] Figure 13 for Figure 12 The diagram shows a cross-sectional view of the display panel along the cutting line DD'.

[0056] Figure 14 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0058] Due to the low mobility of indium gallium zinc oxide (IGZO) transistors, the threshold voltage compensation process in the pixel circuit takes a long time to complete, which is detrimental to the application of high refresh rate and high resolution display panels. Currently, separating the data writing and threshold voltage compensation processes can speed up the threshold voltage compensation process, but this also leads to an increase in the range of provided data voltages in the pixel circuit, resulting in poor brightness uniformity.

[0059] In view of this, an embodiment of the present invention provides a display panel, the display panel comprising: at least one pixel circuit, Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. See also... Figure 1 It includes: a driving transistor T0, a first capacitor C1, and a second capacitor C2;

[0060] The first gate G1 of the driving transistor T0 is connected to the first capacitor C1, and the first capacitor C1 is used to store the voltage of the first gate G1 of the driving transistor T0.

[0061] The first terminal of the driving transistor T0 is connected to the second capacitor C2, which is used to couple the data voltage to the first gate G1 of the driving transistor T0; wherein, the capacitance value of the second capacitor C2 is greater than the capacitance value of the first capacitor C1.

[0062] Specifically, the operation of the pixel circuit includes at least a compensation phase and a data writing phase. During the compensation phase, the third node N3 can provide a second initial voltage Vref2 to the second plate of the second capacitor C2, keeping the voltage of the second plate constant. The driving transistor T0 can generate a current flowing from its first terminal to its second terminal until the voltage difference between the first gate G1 and the first terminal of the driving transistor T0 equals the threshold voltage of the driving transistor T0, at which point the driving transistor T0 is turned off. The first plate of the second capacitor C2 stores a voltage associated with the threshold voltage of the driving transistor T0. According to the circuit connection, the voltage stored at the first plate of the second capacitor C2 can be transferred to the first gate G1 of the driving transistor T0, making the voltage of the first gate G1 of the driving transistor T0 associated with the threshold voltage of the driving transistor T0. That is, the voltage of the first gate G1 of the driving transistor T0 can be expressed as Vre1 + Vth, achieving threshold compensation for the driving transistor T0.

[0063] During the data writing phase, the third node N3 can provide a data voltage Vdata to the second plate of the second capacitor C2. The voltage of the second plate of the second capacitor C2 jumps from the second initial voltage Vref2 to the data voltage Vdata. The second initial voltage Vref2 and the data voltage Vdata have a voltage change, which is the voltage change of the third node N3. The second capacitor C2 couples the voltage change of the third node N3 to the first node N1 and transmits it to the first gate G1 of the driving transistor T0, so that the voltage of the first gate G1 of the driving transistor T0 is related to the data voltage input from the third node N3. At this time, the voltage of the first gate G1 of the driving transistor T0 can be expressed as Vre1+Vth+c2△V / (c1+c2+cgs), thereby realizing data writing. In other words, under the coupling effect of the second capacitor C2, the voltage change of the first gate G1 of the driving transistor T0 is c2ΔV / (c1+c2+cgs), where ΔV is the voltage change between the second initial voltage Vref2 and the data voltage Vdata, c1 is the capacitance value of the first capacitor C1, c2 is the capacitance value of the second capacitor C2, and cgs is the capacitance value of the parasitic capacitance between the first gate G1 and the second gate of the driving transistor T0. Therefore, the range of data voltage written from the highest brightness to the black state of the display panel will be related to the capacitance value c1 of the first capacitor C1 and the capacitance value c2 of the second capacitor C2. Setting the capacitance value c2 of the second capacitor C2 to be greater than the capacitance value c1 of the first capacitor C1 can reduce the data voltage writing range while still meeting the display requirements from the highest brightness to the black state of the display panel. This is beneficial for the driver chip to provide more accurate data voltage, reduce data voltage fluctuations, and thus improve the difference in display brightness and enhance the uniformity of the display.

[0064] Figure 2 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention, which can be applied to... Figure 1 The pixel circuit shown. See also Figure 1 and Figure 2 The pixel circuit also includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

[0065] The first transistor T1 is connected between the first gate G1 of the driving transistor T0 and the first node N1. The second transistor T2 is connected to the second node N2, which is also connected to the light-emitting diode D1. The gate of the second transistor T2 is connected to the first scan signal line S1, and the second terminal of the second transistor T2 is connected to the first initialization signal line VRE1. The second transistor T2 is used to initialize the anode of the light-emitting diode D1. The first terminal of the third transistor T3 is connected to the second initialization signal line VRE2, and the gate of the third transistor T3 is connected to the first light-emitting control signal line EM1. The second terminal of the third transistor T3 and the second terminal of the fourth transistor T4 are connected to the third node N3. The first terminal of the fourth transistor T4 is connected to the data line DATA, and the gate of the fourth transistor T4 is connected to the second scan signal line S2. The first terminal of the fifth transistor T5 is connected to the second terminal of the second transistor T2, and the second terminal of the fifth transistor T5 is connected to the first terminal of the second transistor T2. The gate of the fifth transistor T5 is connected to the third scan signal line S3. The fifth transistor T5 is used to initialize the light-emitting diode D1 during the hold frame to achieve low-frequency driving. The first terminal of the sixth transistor T6 is connected to the second terminal of the driving transistor T0. The second terminal of the sixth transistor T6 is connected to the power supply line VDD. The gate of the sixth transistor T6 is connected to the second light-emitting control signal line EM2. The first terminal of the seventh transistor T7 is connected to the second node N2. The second terminal of the seventh transistor T7 is connected to the first terminal of the driving transistor T0. The gate of the seventh transistor T7 is connected to the first light-emitting control signal line EM1. The sixth transistor T6 and the seventh transistor T7 are used to control the power supply voltage on the power supply line VDD to be transmitted to the light-emitting diode D1.

[0066] The working process of the pixel circuit provided in this embodiment includes an initialization stage t1, a compensation stage t2, a data writing stage t3, and a light emission stage t4.

[0067] During the initialization phase t1, the first scan signal S1 is at an off level (e.g., low); the second scan signal S2 is at an off level (e.g., low); the third scan signal S3 is at an on level (e.g., high); the first light-emitting control signal line EM1 is at an off level (e.g., low); and the second light-emitting control signal EM2 is at an off level (e.g., low). Therefore, the fifth transistor T5 is turned on. The first initialization voltage Vref1 is transmitted to the anode of the light-emitting diode D1 via the fifth transistor T5, initializing the anode of the light-emitting diode D1.

[0068] During compensation phase t2, the first scan signal S1 is at an on level (e.g., high); the second scan signal S2 is at an off level (e.g., low); the third scan signal S3 is at an off level (e.g., low); the first light-emitting control signal EM1 is at an on level (e.g., high); and the second light-emitting control signal EM2 is at an off level (e.g., low). Therefore, the first transistor T1, the second transistor T2, the third transistor T3, and the seventh transistor T7 are turned on. The first gate G1 and the first electrode of the driving transistor T0 are shorted to form a diode structure. A discharge path is formed between the first node N1 and the second transistor T2. When the voltage at the first node N1 drops to Vref1 + Vth, the driving transistor T0 is turned off, where Vth is the threshold voltage of the driving transistor T0. At this time, the voltage at the first gate G1 of the driving transistor T0 is also Vref1 + Vth. While achieving threshold compensation, the first initialization voltage Vref1 can also be transmitted to the first gate G1 of the driving transistor T0, thus initializing the first gate G1 of the driving transistor T0. Furthermore, during the compensation phase t2, the voltage at the anode of LED D1 is maintained at the first initialization voltage Vref1 to prevent LED D1 from emitting light. The second capacitor C2 stores the gate voltage of the first transistor T1.

[0069] During the data writing phase t3, the first scan signal S1 is at the on level (e.g., high level); the second scan signal S2 is at the on level (e.g., high level); the first light emission control signal EM1 is at the off level (e.g., low level); and the second light emission control signal EM2 is at the off level (e.g., low level). Therefore, the first transistor T1, the second transistor T2, and the fourth transistor T4 are turned on. The data voltage Vdata is transmitted to the second plate of the second capacitor C2 via the fourth transistor T4. The voltage of the second plate of the second capacitor C2 jumps from the second initialization voltage Vref2 to the data voltage Vdata. The voltage change of the second plate of the second capacitor C2 is Vdata-Vref2. Since the first transistor T1 is in the on state, under the coupling effect of the second capacitor C2, the voltage of the first gate G1 of the driving transistor T0 becomes Vref1+Vth+c1(Vdata-Vref2) / (c1+c2+cgs) and is stored on the second capacitor C2. The voltage of the second plate of the second capacitor C2 is maintained by the holding effect of the second transistor T2 to maintain the first initialization voltage Vref1. The voltage difference across the second capacitor C2 is Vth+c1(Vdata-Vref2) / (c1+c2+cgs).

[0070] During the light-emitting stage t4, the first scan signal S1 is at an off level (e.g., low); the second scan signal S2 is at an off level (e.g., low); the third scan signal S3 is at an off level (e.g., low); the first light-emitting control signal EM1 is at an on level (e.g., high); and the second light-emitting control signal EM2 is at an on level (e.g., high). Therefore, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are turned on. The first power supply voltage VDD is transmitted to point D via the sixth transistor T6, driving transistor T0 to generate a driving current I based on the voltage of the first gate G1 and the first node N1, driving the light-emitting diode D1 to emit light. Simultaneously, the third transistor T3 transmits the second initialization voltage Vref2 to the first terminal of the second capacitor C2, thus initializing the second capacitor C2.

[0071] The drive current I can be expressed as:

[0072]

[0073] Where μ is the electron mobility of driving transistor T0, Cox is the channel capacitance per unit area of ​​driving transistor T0, W / L is the width-to-length ratio of driving transistor T0, Vth is the threshold voltage of driving transistor T0, c1 is the capacitance of the first capacitor C1, c2 is the capacitance of the second capacitor C2, and cgs is the capacitance of the parasitic capacitance between the first gate G1 and the second gate of driving transistor T0.

[0074] According to the formula for the driving current I, it is independent of the first power supply voltage VDD, the second power supply voltage VSS, and the threshold voltage Vth of the first transistor T1. The driving current corresponding to the display panel from its highest brightness to a black state is related to the data voltage, the capacitance value c1 of the first capacitor C1, and the capacitance value c2 of the second capacitor C2. Therefore, setting the capacitance value c2 of the second capacitor C2 to be greater than the capacitance value c1 of the first capacitor C1, i.e., the ratio of the capacitance value c2 of the second capacitor C2 to the capacitance value c1 of the first capacitor C1 is greater than 1, can reduce the data voltage writing range while meeting the display requirements from the highest brightness to the black state of the display panel. In some embodiments, the capacitance ratio of the second capacitor C2 to the first capacitor C1 is in the range of 1.2-2.4, which can meet the display requirements from the highest brightness to the black state of the display panel, and can avoid the problem that when the ratio of the capacitance value c2 of the second capacitor C2 to the capacitance value c1 of the first capacitor C1 is too large, the second capacitor C2 needs a larger capacitance area in the layout design, thereby introducing unnecessary parasitic capacitance and causing a decrease in the brightness uniformity of the display panel. Furthermore, the capacitance ratio of the second capacitor C2 to the first capacitor C1 can range from 1.6 to 2.0. Preferably, the capacitance ratio of the second capacitor C2 to the first capacitor C1 is 1.8, wherein the capacitance value of the first capacitor C1 can range from 50F to 100F, for example, 50F, 60F, 70F, 80F, 90F, or 100F; optionally, the first capacitor C1 is 60F or 80F. The capacitance value of the second capacitor C2 ranges from 80F to 200F, for example, 80F, 90F, 100F, 110F, 120F, 130F, 140F, 150F, 160F, 170F, 180F, 190F, or 200F.

[0075] The display panel provided in this embodiment of the invention can perform threshold compensation and data writing processes in different time sequences, separating the compensation stage from the data writing stage. This allows for complete threshold compensation even at high refresh rates, which helps improve differences in display brightness and enhances display uniformity. Furthermore, by setting the capacitance value c2 of the second capacitor C2 to be greater than the capacitance value c1 of the first capacitor C1, the data voltage writing range can be reduced while meeting the display requirements from the highest brightness to the black state of the display panel.

[0076] Figure 3 This is a schematic diagram of a planar structure of a display panel provided in an embodiment of the present invention. See also: Figure 3 , Figure 4 for Figure 3 The diagram shows a cross-sectional view of the display panel along section line AA'. The display panel provided in this embodiment also includes:

[0077] Substrate 10;

[0078] A first conductive layer and a second conductive layer, wherein the first conductive layer is located on one side of the substrate 10 and the second conductive layer is located on the side of the first conductive layer away from the substrate 10;

[0079] The first plate 11 of the first capacitor C1 is located in the first conductive layer, and the second plate 12 of the first capacitor C1 is located in the second conductive layer; the first plate 21 of the second capacitor C2 is located in the first conductive layer, and the second plate 22 of the second capacitor C2 is located in the second conductive layer.

[0080] The overlapping area of ​​the orthographic projection of the first plate 21 of the second capacitor C2 on the substrate 10 and the orthographic projection of the second plate 22 of the second capacitor C2 on the substrate 10 is greater than the overlapping area of ​​the orthographic projection of the first plate 11 of the first capacitor C1 on the substrate 10 and the orthographic projection of the second plate 12 of the first capacitor C1 on the substrate 10.

[0081] Specifically, the substrate 10 can provide protection and support for the display panel. For example, the substrate 10 can be a flexible substrate formed of materials such as polyimide (PI), polyethylene naphthalate (PEN), or polyethylene terephthalate (PET), or a rigid substrate formed of materials such as glass. A first conductive layer is disposed on one side of the substrate 10, and a second conductive layer is disposed on the side of the first conductive layer away from the substrate 10. The first and second conductive layers are insulated from each other by an insulating layer. Multiple pixel circuits are formed in the display panel. Each pixel circuit includes a first capacitor C1 and a second capacitor C2. The second capacitor C2 is disposed on the side adjacent to the first capacitor C1. The first electrode 11 of the first capacitor C1 is located on the first conductive layer, and the second electrode 12 of the first capacitor C1 is located on the second conductive layer. The orthographic projection of the first electrode 11 of the first capacitor C1 onto the substrate 10 at least partially overlaps with the orthographic projection of the second electrode 12 of the first capacitor C1 onto the substrate 10. The overlapping area constitutes the effective capacitance of the first capacitor C1.

[0082] The first electrode 21 of the second capacitor C2 is located in the first conductive layer, and the second electrode 22 of the second capacitor C2 is located in the second conductive layer. The orthographic projection of the first electrode 21 of the second capacitor C2 on the substrate 10 and the orthographic projection of the second electrode 22 of the second capacitor C2 on the substrate 10 at least partially overlap, and the overlapping area constitutes the effective capacitance of the second capacitor C2. As can be seen from the capacitance calculation formula, the capacitance value is related to the overlapping area of ​​the upper and lower plates. Therefore, by adjusting the overlapping area of ​​the orthographic projection of the first plate 21 of the second capacitor C2 onto the substrate 10 and the orthographic projection of the second plate 22 of the second capacitor C2 onto the substrate 10, or by adjusting the overlapping area of ​​the orthographic projection of the first plate 11 of the first capacitor C1 onto the substrate 10 and the orthographic projection of the second plate 12 of the first capacitor C1 onto the substrate 10, the overlapping area of ​​the first plate 21 of the second capacitor C2 onto the substrate 10 and the orthographic projection of the second plate 22 of the second capacitor C2 onto the substrate 10 can be made greater than the overlapping area of ​​the first plate 11 of the first capacitor C1 onto the substrate 10 and the orthographic projection of the second plate 12 of the first capacitor C1 onto the substrate 10. This will result in the capacitance value c2 of the second capacitor C2 being greater than the capacitance value c1 of the first capacitor C1, thus obtaining a suitable capacitance ratio between the second capacitor C2 and the first capacitor C1.

[0083] Optionally, Figure 5 This is a schematic diagram of the layout structure of a first capacitor provided in an embodiment of the present invention. See also... Figure 5 The first electrode 11 of the first capacitor C1 includes a hole region K0. The overlapping position of the orthographic projection of the first electrode 11 of the first capacitor C1 onto the substrate 10 and the orthographic projection of the second electrode 12 of the first capacitor C1 onto the substrate 10 at least partially covers the orthographic projection of the hole region K0 onto the substrate 10. That is, by removing the first conductive layer at the location of the hole region K0 on the first electrode 11 of the first capacitor C1, the overlapping area between the first electrode 11 and the second electrode 12 of the first capacitor C1 is reduced, thereby reducing the overlapping area between the two electrodes. Therefore, by providing the hole region K0 on the first electrode 11 of the first capacitor C1, the capacitance value of the first capacitor C1 can be adjusted.

[0084] Optionally, Figure 6 For a schematic diagram of another layout structure of the first capacitor provided in an embodiment of the present invention, see [link to schematic diagram]. Figure 6The second electrode 12 of the first capacitor C1 includes a hole region K0. The overlapping position of the orthographic projections of the first electrode 11 and the second electrode 12 of the first capacitor C1 on the substrate 10 at least partially covers the orthographic projection of the hole region K0 on the substrate 10. That is, the second conductive layer at the location of the hole region K0 on the second electrode 12 of the first capacitor C1 is removed to reduce the overlapping area between the first electrode 11 and the second electrode 12 of the first capacitor C1, thereby reducing the overlapping area between the two electrodes. Therefore, by setting the hole region K0 on the second electrode 12 of the first capacitor C1, the capacitance value of the first capacitor C1 can be adjusted.

[0085] Optionally, Figure 7 For a schematic diagram of another layout structure of the first capacitor provided in an embodiment of the present invention, see [link to schematic diagram]. Figure 7 Both the first electrode 11 and the second electrode 12 of the first capacitor C1 include a hole region K0. The overlapping position of the orthographic projections of the first electrode 11 and the second electrode 12 of the first capacitor C1 on the substrate 10 at least partially covers the orthographic projection of the hole region K0 on the substrate 10. That is, on the first electrode 11 of the first capacitor C1, the first conductive layer at the location of the hole region K0 is removed, and on the second electrode 12 of the first capacitor C1, the second conductive layer at the location of the hole region K0 is removed, so as to reduce the overlapping area between the first electrode 11 and the second electrode 12 of the first capacitor C1, thereby reducing the overlapping area between the two electrodes.

[0086] It should be noted that the orthographic projection of the hole region K0 on the first plate 11 of the first capacitor C1 onto the substrate 10 and the orthographic projection of the hole region K0 on the second plate 12 of the first capacitor C1 onto the substrate 10 may or may not overlap.

[0087] exist Figures 5 to 7 In the example, the orthographic projection of the second electrode 12 of the first capacitor C1 onto the substrate 10 falls within the orthographic projection of the first electrode 11 of the first capacitor C1 onto the substrate 10. That is, the area of ​​the second electrode 12 of the first capacitor C1 is smaller than the area of ​​the first electrode 11 of the first capacitor C1. In other embodiments, depending on the wiring relationship between layers, the orthographic projection of the second electrode 12 of the first capacitor C1 onto the substrate 10 may also cover the orthographic projection of the first electrode 11 of the first capacitor C1 onto the substrate 10. That is, the area of ​​the second electrode 12 of the first capacitor C1 may also be greater than or equal to the area of ​​the first electrode 11 of the first capacitor C1.

[0088] Furthermore, when the first gate G1 of the driving transistor T0 and the second plate 12 of the first capacitor C1 are reused in the same layer in the following text, the orthographic projection of the hole region K0 on the second plate 12 of the first capacitor C1 onto the substrate 10 does not overlap with the orthographic projection of the channel region 40 of the driving transistor T0 onto the substrate 10, so as to avoid affecting the control capability of the channel of the driving transistor T0.

[0089] Figure 8 A schematic diagram of the planar structure of another display panel provided in an embodiment of the present invention is shown below. Figure 8 , Figure 9 for Figure 8 The diagram shows a cross-sectional view of the display panel along section line BB'. (See attached diagram.) Figure 6 and Figure 9 The first gate G1 of the driving transistor T0 and the second plate 12 of the first capacitor C1 can be multiplexed on the same layer or independently configured on different layers. Then, the first gate G1 of the driving transistor T0 and the second plate 12 of the first capacitor C1 are electrically connected through vias. In this embodiment of the invention, the second plate 12 of the first capacitor C1 is multiplexed as the first gate G1 of the driving transistor T0. The driving transistor T0 can be a bottom-gate driven type, that is, the first gate G1 of the driving transistor T0 serves as the control electrode, and the second plate 12 of the first capacitor C1 serves as the bottom gate of the driving transistor T0. Figure 8 and Figure 9 As shown, the first active layer 30 is located on the side of the second conductive layer away from the substrate 10, and the first active layer 30 extends along the first direction X. The third conductive layer is located on the side of the first active layer 30 away from the substrate 10. The driving transistor T0 includes a second gate G2, which is located on the third conductive layer. The second gate G2 of the driving transistor T0 is connected to the second electrode of the driving transistor T0. The portion of the first active layer 30 below the orthographic projection of the second gate G2 of the driving transistor T0 is the channel region of the driving transistor T0. The channel region 40 of the driving transistor T0 is located on the first active layer 30. The source region and drain region of the driving transistor T0 are located on both sides of the channel region 40, respectively. The first gate G1 of the driving transistor T0 overlaps with the channel region 40 of the driving transistor T0. That is, the orthographic projection of the second electrode 12 of the first capacitor C1 on the substrate 10 at least covers the orthographic projection of the channel region 40 of the driving transistor T0 on the substrate 10. It should be noted that the material of the first active layer 30 applied to the driving transistor T0 can be a metal oxide, such as indium gallium zinc oxide (IGZO). For the active layers of other transistors, such as the first transistor T1 to the seventh transistor T7, a second active layer can be provided, and the material of the second active layer can be low-temperature polysilicon (LTPS).

[0090] Optionally, the minimum distance W1 between the orthographic projection of the second plate 12 of the first capacitor C1 onto the substrate 10 and the orthographic projections of the first plate 21 and the second plate 22 of the second capacitor C2 onto the substrate 10 is greater than or equal to 3 μm. That is, the minimum distance W1 between the edge of each plate of the second capacitor C2 and the edge of the second plate 12 of the first capacitor C1 needs to be greater than 3 μm to reduce unnecessary parasitic capacitance introduced between the first plate 21 and the second plate 22 of the second capacitor C2 and the second plate 12 of the first capacitor C1, thus affecting the coupling effect of the second capacitors.

[0091] like Figure 8 As shown, in some embodiments, the orthographic projection of the second plate 22 of the second capacitor C2 onto the substrate 10 falls within the orthographic projection of the first plate 21 of the second capacitor C2 onto the substrate 10. The first plate 21 of the second capacitor C2 is closer to the second plate 12 of the first capacitor C1 than the second plate 22 of the second capacitor C2. Therefore, the minimum distance W1 between the orthographic projection of the second plate 12 of the first capacitor C1 onto the substrate 10 and the orthographic projection of the first plate 21 of the second capacitor C2 onto the substrate 10 needs to be greater than or equal to 3 μm in order to reduce the coupling effect of parasitic capacitance between the second plate 12 of the first capacitor C1 and the first plate 21 of the second capacitor C2. In other embodiments, the orthographic projection of the first plate 21 of the second capacitor C2 onto the substrate 10 falls within the orthographic projection of the second plate 22 of the second capacitor C2 onto the substrate 10. Therefore, the second plate 22 of the second capacitor C2 is closer to the second plate 12 of the first capacitor C1 than the second plate 12 of the first capacitor C1. Thus, the minimum distance W1 between the orthographic projection of the second plate 12 of the first capacitor C1 onto the substrate 10 and the orthographic projection of the second plate 22 of the second capacitor C2 onto the substrate 10 needs to be greater than or equal to 3 μm to reduce the coupling effect of parasitic capacitance between the second plate 12 of the first capacitor C1 and the second plate 22 of the second capacitor C2.

[0092] Optionally, in the first direction X, the orthographic projection of the second plate 12 of the first capacitor C1 onto the substrate 10 exceeds the orthographic projection of the channel region 40 of the driving transistor T0 onto the substrate 10 by at least a first length dimension W2; that is, in the first direction X, the length dimension of the second plate 12 of the first capacitor C1 is greater than the channel region 40 of the driving transistor T0.

[0093] Optionally, in the second direction Y, the orthographic projection of the second plate 12 of the first capacitor C1 onto the substrate 10 exceeds the orthographic projection of the channel region 40 of the driving transistor T0 onto the substrate 10 by at least a second length dimension W3; the second direction Y is perpendicular to the first direction X; that is, in the second direction Y, the length dimension of the second plate 12 of the first capacitor C1 is greater than the channel region 40 of the driving transistor T0.

[0094] By extending the length of the second plate 12 of the first capacitor C1 relative to the channel region 40 of the driving transistor T0 in the first direction X and the second direction Y, the coverage area of ​​the second plate 12 of the first capacitor C1 over the channel region 40 of the driving transistor T0 is increased, thereby improving the control capability of the channel of the driving transistor T0. If the first length dimension W2 and / or the second length dimension W3 are too large, parasitic capacitance will also be introduced, thereby affecting the brightness uniformity. Therefore, through experimental research, in the first direction X, the range of the first length dimension W2 is 0.4μm-2μm, for example, the range of the first length dimension W2 is 0.4μm, 0.8μm, 1μm, 1.2μm, 1.6μm or 2μm, preferably, the first length dimension W2 is 1μm; and or, in the second direction Y, the range of the second length dimension W3 is 2μm-4μm, for example, the second length dimension W3 is 2μm, 2.5μm, 3μm, 3.5μm or 4μm, preferably, the second length dimension W3 is 3μm, which can satisfy the control capability of the channel of the driving transistor T0, while reducing the influence of parasitic capacitance.

[0095] Optionally, the first electrode 11 of the first capacitor C1 is projected onto the substrate 10 in a way that at least partially covers the projection of the channel region 40 of the driving transistor T0 onto the substrate 10. The first electrode 11 of the first conductive layer is used as the lower electrode of the first capacitor C1, and can also be reused as a light-shielding layer for the driving transistor T0. This can save layout space and avoid the influence of light on the driving transistor T0, thereby improving the reliability of the pixel circuit and the display panel.

[0096] See also Figure 8 and Figure 9Optionally, the display panel further includes a third conductive layer located on the side of the first active layer 30 away from the substrate 10. The driving transistor T0 includes a second gate G2 located on the third conductive layer and connected to the second electrode of the driving transistor T0. The portion of the first active layer 30 below the orthographic projection of the second gate G2 of the driving transistor T0 forms the channel region of the driving transistor T0. The orthographic projection of the second gate G2 of the driving transistor T0 on the substrate 10 at least partially covers the orthographic projection of the channel region 40 of the driving transistor T0 on the substrate 10. The first electrode of the driving transistor T0 can be the drain, and the second electrode can be the source. The first gate G1 of the driving transistor T0 serves as the bottom gate, and the second gate G2 serves as the top gate. The bottom gate acts as the control electrode to achieve driving control of the driving transistor T0. The dual-gate design of the driving transistor T0 enhances the gate's control over the channel region 40, which is beneficial for improving the subthreshold swing of the driving transistor T0, grayscale expansion, and display brightness uniformity.

[0097] like Figure 9 As shown, in this embodiment, on the first active layer 30, the area covered by the second gate G2 of the driving transistor T0 is used as the channel region 40 of the driving transistor T0, and the orthogonal projection of the second gate G2 of the driving transistor T0 on the substrate 10 at least covers the orthogonal projection of the channel region 40 of the driving transistor T0 on the substrate 10.

[0098] Optionally, the orthographic projection of the second plate 12 of the first capacitor C1 onto the substrate 10 covers the orthographic projection of the second gate of the driving transistor T0 onto the substrate 10. Thus, the orthographic projection of the second plate 12 of the first capacitor C1 can cover the area covered by the second gate G2 of the driving transistor T0, i.e., the channel region 40 of the driving transistor T0. Specifically, in the first direction X, the orthographic projection of the second plate 12 of the first capacitor C1 onto the substrate 10 exceeds the orthographic projection of the channel region 40 of the driving transistor T0 onto the substrate 10 by at least a first length dimension W2, and or, in the second direction Y, the orthographic projection of the second plate 12 of the first capacitor C1 onto the substrate 10 exceeds the orthographic projection of the channel region 40 of the driving transistor T0 onto the substrate 10 by at least a second length dimension W3. This satisfies the control capability of the channel of the driving transistor T0 while reducing the influence of parasitic capacitance.

[0099] Optionally, the display panel further includes a fourth conductive layer located on the side of the third conductive layer away from the substrate 10. The fourth conductive layer includes a first connection line 111, and the second gate G2 of the driving transistor T0 is connected to the first electrode of the driving transistor T0 through the first connection line 111.

[0100] Specifically, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer are isolated from each other by insulating layers. For example, a capacitor insulating layer 110 is provided between the first conductive layer and the second conductive layer, a first gate insulating layer 120 is provided between the second conductive layer and the first active layer 30, a second gate insulating layer 130 is provided between the first active layer 30 and the third conductive layer, an interlayer insulating layer 140 is provided between the third conductive layer and the fourth conductive layer, and a first planarization layer 150 is provided on the side of the fourth conductive layer away from the substrate 10.

[0101] The first connection line 111 is located in the fourth conductive layer and is used to connect the second gate G2 and the second electrode (source of the driving transistor T0) of the driving transistor T0. For example, the second gate G2 of the driving transistor T0 is connected to one end of the first connection line 111 via the first via K1, and the second electrode of the driving transistor T0 is connected to the other end of the first connection line 111 via the first via K1. The second gate G2 and the second electrode of the driving transistor T0 are connected in a bridge manner through the first connection line 111. The first via K1 is a via that penetrates the interlayer insulating layer 140 or the interlayer insulating layer 140 and the second gate insulating layer 130.

[0102] Optionally, the orthogonal projection of the first connection line 111 on the substrate 10 at least partially covers the orthogonal projection of the second gate G2 of the driving transistor T0 on the substrate 10, so as to realize the connection between the first connection line 111, which serves as the second gate G2 of the driving transistor T0, and the first pole of the driving transistor T0.

[0103] Figure 10 For the reason Figure 8 The diagram shows a cross-sectional view of the display panel along the section line CC'. (See attached diagram.) Figure 10 Optionally, the fourth conductive layer further includes a second connection line 112, through which the second electrode 22 of the second capacitor C2 is connected to the first terminal (drain of the driving transistor T0). For example, the second electrode 22 of the second capacitor C2 is connected to one end of the second connection line 112 via a second via K2, and the first terminal of the driving transistor T0 is connected to the other end of the second connection line 112 via a second via K2. The second electrode 22 of the second capacitor C2 and the first terminal of the driving transistor T0 are connected in a bridge manner through the second connection line 112. The first electrode 21 of the second capacitor C2 is located in the first conductive layer, and the second electrode 22 of the second capacitor C2 is located in the second conductive layer.

[0104] Figure 11 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 12 This is a schematic diagram of another planar structure of a display panel provided in an embodiment of the present invention. Figure 13 for Figure 12The diagram shows a cross-sectional view of the display panel along the section line DD'. (See attached diagram.) Figures 11-13 In this embodiment, the first active layer 30 is located on the side of the second conductive layer away from the substrate 10, and the first active layer 30 extends along the first direction X; the third conductive layer is located on the side of the first active layer 30 away from the substrate 10, and the driving transistor T0 is a single-gate transistor, that is, the driving transistor T0 only has a first gate G1, and the first gate G1 of the driving transistor T0 is located in the third conductive layer. The portion of the first active layer 30 below the orthographic projection of the first gate G1 of the driving transistor T0 is the channel region of the driving transistor T0. Optionally, the orthographic projection of the first gate G1 of the driving transistor T0 on the substrate 10 at least partially covers the orthographic projection of the channel region 40 of the driving transistor T0 on the substrate 10; the second plate 12 of the first capacitor C1 is not reused as the first gate G1 of the driving transistor T0, therefore, the orthographic projection of the second plate 12 of the first capacitor C1 on the substrate 10 does not overlap with the orthographic projection of the channel region 40 of the driving transistor T0 on the substrate 10. When the driving transistor T0 is a single-gate transistor, the first connection line 111 can be omitted, and the connection between the first gate G1 of the driving transistor T0 and the second plate 12 of the first capacitor C1 can be achieved through the third connection line 113.

[0105] Optionally, the orthographic projection of the first electrode 11 of the first capacitor C1 onto the substrate 10 at least partially covers the orthographic projection of the channel region 40 of the driving transistor T0 onto the substrate 10. Utilizing the first electrode 11 of the first conductive layer as a light-shielding layer for the driving transistor T0 saves layout space and avoids the influence of light on the driving transistor T0, thereby improving the reliability of the pixel circuitry and the display panel.

[0106] The first gate G1 of the driving transistor T0 is connected to one end of the third connection line 113 via the third via K3, and the second plate 12 of the first capacitor C1 is connected to the other end of the third connection line 113 via the third via K3, thus connecting the first gate G1 of the driving transistor T0 and the second plate 12 of the first capacitor C1. The second plate 22 of the second capacitor C2 and the first terminal of the driving transistor T0 are connected in a bridge manner through the third connection line 113.

[0107] Optionally, embodiments of the present invention also provide a display device, which includes the display panel provided in any embodiment of the present invention. Therefore, the display device also has the beneficial effects described in any of the above embodiments. Figure 14This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. In this embodiment, the display device 200 can be a mobile phone or any electronic product with display function, including but not limited to the following categories: display panels in products such as televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, and touch interactive terminals. The present invention does not impose any special limitations on these.

[0108] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, include: At least one pixel circuit, the pixel circuit including a driving transistor, a first capacitor and a second capacitor; The first gate of the driving transistor is connected to the first capacitor, which stores the voltage of the first gate of the driving transistor; the first terminal of the driving transistor is connected to the second capacitor, which couples the data voltage to the first gate of the driving transistor, wherein the capacitance value of the second capacitor is greater than the capacitance value of the first capacitor; the ratio of the capacitance values ​​of the second capacitor to the first capacitor is in the range of 1.6-2.

0. The pixel circuit further includes a first transistor and a light-emitting diode. The first transistor is connected between the first gate of the driving transistor and the first node, and the second capacitor is connected to the first node. The first capacitor is connected between the first gate and the light-emitting diode. The display panel further includes: a substrate; a first conductive layer and a second conductive layer, wherein the first conductive layer is located on one side of the substrate, and the second conductive layer is located on the side of the first conductive layer away from the substrate; a first electrode of the first capacitor is located on the first conductive layer, and a second electrode of the first capacitor is located on the second conductive layer; a first electrode of the second capacitor is located on the first conductive layer, and a second electrode of the second capacitor is located on the second conductive layer; the overlapping area of ​​the orthographic projection of the first electrode of the second capacitor on the substrate and the orthographic projection of the second electrode of the second capacitor on the substrate is greater than the overlapping area of ​​the orthographic projection of the first electrode of the first capacitor on the substrate and the orthographic projection of the second electrode of the first capacitor on the substrate. The first gate of the driving transistor is located in the second conductive layer, and the second plate of the first capacitor is multiplexed as the first gate of the driving transistor. The orthographic projection of the second plate of the first capacitor on the substrate and the orthographic projection of the first plate of the second capacitor on the substrate are spaced apart; The minimum distance between the orthographic projection of the second plate of the first capacitor on the substrate and the orthographic projection of the first plate of the second capacitor and the second plate of the second capacitor on the substrate is greater than or equal to 3 μm.

2. The display panel according to claim 1, characterized in that, The pixel circuit also includes a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; The first terminal of the second transistor is connected to the second node, and the second node is also connected to the light-emitting diode. The gate of the second transistor is connected to the first scan signal line, and the second terminal of the second transistor is connected to the first initialization signal line. The first terminal of the third transistor is connected to the second initialization signal line, and the gate of the third transistor is connected to the first light-emitting control signal line. The second terminal of the third transistor and the second terminal of the fourth transistor are connected to the third node. The first terminal of the fourth transistor is connected to the data line, and the gate of the fourth transistor is connected to the second scan signal line. The first terminal of the fifth transistor is connected to the second terminal of the second transistor, and the second terminal of the fifth transistor is connected to the first terminal of the second transistor. The gate of the fifth transistor is connected to the third scan signal line. The first terminal of the sixth transistor is connected to the second terminal of the driving transistor, and the second terminal of the sixth transistor is connected to the power supply line. The gate of the sixth transistor is connected to the second light-emitting control signal line. The first terminal of the seventh transistor is connected to the second node, and the second terminal of the seventh transistor is connected to the first terminal of the driving transistor. The gate of the seventh transistor is connected to the first light-emitting control signal line. During the compensation phase, when the voltage of the first node is Vref1+Vth, the driving transistor is turned off; The voltage of the first gate is Vref1 + Vth; where Vref1 is the first initialization voltage and Vth is the threshold voltage of the driving transistor. During the data writing phase, the voltage change of the second plate of the second capacitor is Vdata-Vref2, where Vref2 is the second initialization voltage and Vdata is the data voltage; the voltage of the first gate becomes Vref1 +Vth+c2(Vdata-Vref2) / (c1+c2+cgs); the voltage of the second plate of the first capacitor is Vref1; where c1 is the capacitance value of the first capacitor, c2 is the capacitance value of the second capacitor, and cgs is the capacitance value of the parasitic capacitance between the first gate and the second plate of the driving transistor.

3. The display panel according to claim 1, characterized in that, The driving current of the pixel circuit is: ; Where μ is the electron mobility of the driving transistor, Cox is the channel capacitance per unit area of ​​the driving transistor, W / L is the width-to-length ratio of the driving transistor, c1 is the capacitance of the first capacitor, c2 is the capacitance of the second capacitor, and cgs is the capacitance of the parasitic capacitance between the first gate and the second gate of the driving transistor.

4. The display panel according to claim 1, characterized in that, The capacitance ratio of the second capacitor to the first capacitor is 1.

8.

5. The display panel according to claim 1, characterized in that, The capacitance value of the first capacitor ranges from 50F to 100F; the capacitance value of the second capacitor ranges from 80F to 200F.

6. The display panel according to claim 1, characterized in that, The first plate of the first capacitor and / or the second plate of the first capacitor include a hole region, and the overlapping position of the orthographic projection of the first plate of the first capacitor on the substrate and the orthographic projection of the second plate of the first capacitor on the substrate at least partially covers the orthographic projection of the hole region on the substrate.

7. The display panel according to claim 1, characterized in that, The orthographic projection of the first plate of the second capacitor onto the substrate at least covers the orthographic projection of the second plate of the second capacitor onto the substrate; The minimum distance between the orthographic projection of the second plate of the first capacitor onto the substrate and the orthographic projection of the first plate of the second capacitor onto the substrate is greater than or equal to 3 μm.

8. The display panel according to claim 1, characterized in that, Also includes: A first active layer is located on the side of the second conductive layer away from the substrate, and the first active layer extends along a first direction; A third conductive layer is located on the side of the first active layer away from the substrate. The driving transistor includes a second gate located on the third conductive layer. The second gate of the driving transistor is connected to the second electrode of the driving transistor. Wherein, the portion of the first active layer located below the orthographic projection of the second gate of the driving transistor is the channel region of the driving transistor, and the orthographic projection of the second plate of the first capacitor on the substrate at least covers the orthographic projection of the channel region of the driving transistor on the substrate.

9. The display panel according to claim 8, characterized in that, In the first direction, the orthographic projection of the second plate of the first capacitor onto the substrate exceeds the orthographic projection of the channel region of the driving transistor onto the substrate by at least a first length dimension.

10. The display panel according to claim 9, characterized in that, The first length dimension ranges from 0.4μm to 2μm.

11. The display panel according to claim 10, characterized in that, The first length dimension is 1 μm.

12. The display panel according to claim 8, characterized in that, In the second direction, the orthographic projection of the second plate of the first capacitor onto the substrate extends beyond the orthographic projection of the channel region of the driving transistor onto the substrate by at least a second length dimension; The second direction is perpendicular to the first direction.

13. The display panel according to claim 12, characterized in that, The second length dimension ranges from 2μm to 4μm.

14. The display panel according to claim 13, characterized in that, The second length dimension is 3μm.

15. The display panel according to claim 8, characterized in that, The first plate of the first capacitor projects onto the substrate in a positive projection that at least partially covers the positive projection of the channel region of the driving transistor onto the substrate.

16. The display panel according to claim 8, characterized in that, The second gate of the driving transistor is projected onto the substrate in an orthogonal projection that at least covers the orthogonal projection of the channel region of the driving transistor onto the substrate.

17. The display panel according to claim 16, characterized in that, The second plate of the first capacitor projects onto the substrate at least as well as the second gate of the driving transistor.

18. The display panel according to claim 16, characterized in that, It also includes a fourth conductive layer, which is located on the side of the third conductive layer away from the substrate. The fourth conductive layer includes a first connection line, and the second gate of the driving transistor is connected to the second electrode of the driving transistor through the first connection line.

19. The display panel according to claim 18, characterized in that, The second gate of the driving transistor is connected to one end of the first connection line via a first via, and the first electrode of the driving transistor is connected to the other end of the first connection line via a second via.

20. The display panel according to claim 18, characterized in that, The orthogonal projection of the first connection line on the substrate at least partially covers the orthogonal projection of the second gate of the driving transistor on the substrate.

21. The display panel according to claim 1, characterized in that, Also includes: A first active layer is located on the side of the second conductive layer away from the substrate, and the first active layer extends along a first direction; A third conductive layer is located on the side of the first active layer away from the substrate, and the first gate of the driving transistor is located in the third conductive layer; wherein, the portion of the first active layer located below the orthogonal projection of the first gate of the driving transistor is the channel region of the driving transistor.

22. The display panel according to claim 21, characterized in that, The orthogonal projection of the first gate of the driving transistor onto the substrate at least partially covers the orthogonal projection of the channel region of the driving transistor onto the substrate.

23. The display panel according to claim 21, characterized in that, The orthographic projection of the first plate of the first capacitor onto the substrate at least partially covers the orthographic projection of the channel region of the driving transistor onto the substrate.

24. A display device, characterized in that, Includes the display panel as described in any one of claims 1-23.

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