A method, apparatus, and equipment for grid voltage phase-locking of a power electronic converter

Abstract

This invention discloses a method, apparatus, and device for grid voltage phase-locked loop (PLL) in power electronic converters. Within the normal power system fluctuation range, the output signal of a three-phase PLL is used. When the fluctuation exceeds the normal range, it is considered a grid anomaly. Then, phase and frequency weighting is applied to the output signal of the three-phase PLL to construct an internal PLL signal to track and calculate the phase and frequency within the normal range. Switching to the internal PLL signal output results in a more stable output PLL signal. The grid voltage PLL output is unaffected by grid fluctuations and is less prone to instability. Simultaneously, a grid PLL anomaly indicator is provided, prompting the power electronic converter control system to promptly limit the operating current. This solves the technical problem that existing grid-connected converter PLLs are easily affected by grid fluctuations, leading to control fluctuations or even instability, and overcurrent disconnection from the grid.

Description

Technical Field

[0001] This invention relates to the field of phase-locked loop technology, and in particular to a method, apparatus, and device for phase-locking power grid voltage in a power electronic converter. Background Technology

[0002] Grid-connected power electronic converters require grid connection and support from the power system. Existing power systems consist of generator groups, power grids, and power electronic converters. While the frequency and phase of generator groups do not change abruptly, the power grid is not stable. During single-phase, two-phase, and three-phase faults, such as high-voltage ride-through and low-voltage ride-through, phase changes occur, and the phase-locked loop (PLL) fluctuates. In certain extreme fault conditions, due to grid anomalies, fluctuations caused by the PLL of the grid-connected converter can lead to control fluctuations or even instability in the power electronic converter, resulting in overcurrent disconnection from the grid. Summary of the Invention

[0003] This invention provides a method, apparatus, and device for power electronic converters to lock onto grid voltage, which solves the technical problem that existing grid-connected converter phase-locked loops are easily affected by grid fluctuations, leading to control fluctuations or even instability of the power electronic converter and overcurrent disconnection from the grid.

[0004] In view of this, the first aspect of the present invention provides a power electronic converter grid voltage phase-locking method, comprising:

[0005] S1. Obtain the output signal of the three-phase phase-locked loop;

[0006] S2. Convert the output signal of the three-phase phase-locked loop into a square wave signal;

[0007] S3. Determine whether the square wave signal is normal based on the preset power system stability range. If it is, proceed to step S4; otherwise, proceed to step S5. The preset power system stability range includes frequency range, period range, and phase range.

[0008] S4, Output signal of the three-phase phase-locked loop;

[0009] S5. The phase value of the output signal of the three-phase phase-locked loop is linearly weighted using a sliding window to obtain the weighted phase value. The frequency value of the output signal of the three-phase phase-locked loop is linearly weighted using a sliding window to obtain the weighted frequency value. Then, proceed to step S6.

[0010] S6. Based on the weighted phase value and weighted frequency value, synthesize the output signal of the three-phase phase-locked loop into an internal phase-locked signal for output and mark the phase-locked abnormal signal.

[0011] Optionally, step S3 specifically includes:

[0012] Record the average periodic value Tavg0 and periodic error range dT of the square wave signal within a preset time period. Within the period range Tavg0-dT to Tavg0+dT, for the first period signal, determine whether the square wave signal is a normal signal based on whether the frequency of the square wave signal is between 48Hz and 51.5Hz, whether the frequency change rate does not exceed 0.2Hz / s, and whether there is a sudden change in phase. For signals other than the first period signal, if the previous period signal is a normal signal, then compared with the previous period signal, the continuous periodic change is less than the preset time, and the signal period is considered normal, and step S4 is executed. If the continuous periodic change is not less than the preset time, then the period is considered abnormal, and step S5 is executed. If the previous period signal is an abnormal signal, then compared with the previous period signal, the continuous periodic change is less than the preset time + dT, and the signal period is considered normal, and step S4 is executed. If the continuous periodic change is not less than the preset time + dT, then the period is considered abnormal, and step S5 is executed. The preset time covers multiple signal periods.

[0013] Optionally, the preset duration is 1.6us.

[0014] Optionally, the preset time is 30 seconds.

[0015] Optionally, step S3 further includes:

[0016] Determine if the cumulative time for a square wave signal to be judged as an abnormal signal within 10 seconds exceeds 2 seconds. If so, force the square wave signal that has accumulated for more than 2 seconds within the preset time to be a normal signal.

[0017] Optionally, in step S5, the formula for calculating the weighted phase value is:

[0018]

[0019] in, For weighted phase values, These are the phase values ​​of n moments arranged in reverse chronological order. for One-to-one corresponding phase weight values, The value decreases linearly between [0,1].

[0020] Optionally, in step S5, the formula for calculating the weighted frequency value is:

[0021]

[0022] in, These are weighted frequency values. These are the frequency values ​​of n moments arranged in reverse chronological order. for One-to-one frequency weight values, The value decreases linearly between [0,1].

[0023] A second aspect of the present invention provides a power electronic converter grid voltage phase-locked loop device, comprising: a three-phase phase-locked loop, an internal phase-locked signal construction module, and a comprehensive judgment output module;

[0024] The three-phase phase-locked loop and the inner phase-locked signal construction module are connected, and the three-phase phase-locked loop and the inner phase-locked signal construction module are respectively connected to the comprehensive judgment output module;

[0025] A three-phase phase-locked loop is used to obtain three-phase signals from a three-phase power supply, process the three-phase signals, and output three-phase external phase-locked signals.

[0026] The internal phase-locked signal construction module is used to acquire the output signal of the three-phase phase-locked loop, convert the output signal of the three-phase phase-locked loop into a square wave signal, and perform linear weighted calculation on the phase value of the output signal of the three-phase phase-locked loop using a sliding window to obtain a weighted phase value. It also performs linear weighted calculation on the frequency value of the output signal of the three-phase phase-locked loop using a sliding window to obtain a weighted frequency value. Based on the weighted phase value and the weighted frequency value, the output signal of the three-phase phase-locked loop is synthesized into an internal phase-locked signal for output and to identify phase-locked abnormal signals.

[0027] The comprehensive judgment output module is used to determine whether the square wave signal is normal based on the preset power system stability range. If it is normal, it outputs the output signal of the three-phase phase-locked loop; otherwise, it outputs the internal phase-locked signal synthesized by the internal phase-locked signal construction module. The preset power system stability range includes frequency range, period range, and phase range.

[0028] Optionally, the root synthesis judgment output module is specifically used for:

[0029] Record the average periodic value Tavg0 and periodic error range dT of the square wave signal within a preset time period. Within the period range Tavg0-dT to Tavg0+dT, for the first period signal, determine whether the square wave signal is a normal signal based on whether the frequency of the square wave signal is between 48Hz and 51.5Hz, whether the frequency change rate does not exceed 0.2Hz / s, and whether there is a sudden change in phase. For signals other than the first period signal, if the previous period signal is a normal signal, then compared with the previous period signal, the continuous periodic change is less than the preset time, and the signal period is considered normal, and step S4 is executed. If the continuous periodic change is not less than the preset time, then the period is considered abnormal, and step S5 is executed. If the previous period signal is an abnormal signal, then compared with the previous period signal, the continuous periodic change is less than the preset time + dT, and the signal period is considered normal, and step S4 is executed. If the continuous periodic change is not less than the preset time + dT, then the period is considered abnormal, and step S5 is executed. The preset time covers multiple signal periods.

[0030] Optionally, in the internal phase-locked signal construction module, the formula for calculating the weighted phase value is:

[0031]

[0032] in, For weighted phase values, These are the phase values ​​of n moments arranged in reverse chronological order. for One-to-one corresponding phase weight values, Its value decreases linearly between [0,1].

[0033] The formula for calculating the weighted frequency value is:

[0034]

[0035] in, These are weighted frequency values. These are the frequency values ​​of n moments arranged in reverse chronological order. for One-to-one frequency weight values, The value decreases linearly between [0,1].

[0036] A third aspect of the present invention provides a power electronic converter grid voltage phase-locked loop device, the device comprising a processor and a memory:

[0037] The memory is used to store program code and transmit the program code to the processor;

[0038] The processor is configured to execute the power electronic converter grid voltage phase-locked loop method according to any one of the first aspects, based on the instructions in the program code.

[0039] As can be seen from the above technical solutions, the power electronic converter grid voltage phase-locking method provided by the present invention has the following advantages:

[0040] The power electronic converter grid voltage phase-locked loop (PLL) method provided by this invention utilizes the output signal of a three-phase PLL within the normal power system fluctuation range. When the fluctuation exceeds the normal range, it is considered a grid anomaly. An internal PLL signal is constructed by weighting the phase and frequency of the three-phase PLL output signal to track and calculate the phase and frequency within the normal range. Switching to the internal PLL signal output results in a more stable output PLL signal. The grid voltage PLL output is unaffected by grid fluctuations and is less prone to instability. Simultaneously, a grid PLL anomaly indicator is provided, prompting the power electronic converter control system to promptly limit the operating current. This solves the technical problem that existing grid-connected converter PLLs are easily affected by grid fluctuations, leading to power electronic converter control fluctuations or even instability, and overcurrent disconnection from the grid. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic flowchart of a power electronic converter grid voltage phase-locking method provided in this invention;

[0043] Figure 2 This is a schematic diagram of a power electronic converter grid voltage phase-locked loop method provided in this invention;

[0044] Figure 3 This is a logic block diagram of a power electronic converter grid voltage phase-locked loop method provided in this invention;

[0045] Figure 4 This is a schematic diagram of the structure of a power electronic converter grid voltage phase-locked device provided in this invention. Detailed Implementation

[0046] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] For easier understanding, please refer to Figures 1 to 3 This invention provides an embodiment of a three-power electronic converter grid voltage phase-locked loop method, comprising:

[0048] Step S1: Obtain the output signal of the three-phase phase-locked loop.

[0049] It should be noted that three-phase phase-locked loops (PLLs) are primarily used to detect and track the phase of three-phase voltage or current signals, ensuring that the system can correctly synchronize with the power grid or other power sources, thereby guaranteeing system stability and reliability. Common three-phase PLLs include Synchronous Reference Frame PLLs (SRF-PLLs), Enhanced PLLs (EPLLs), Clarke transform-based PLLs, and Second Order Generalized Integrator PLLs (SOGI-PLLs). Figure 2 and Figure 3 As shown in the embodiment of the present invention, the output signal of the three-phase phase-locked loop is first obtained, which can be denoted as signal 2.

[0050] Step S2: Convert the output signal of the three-phase phase-locked loop into a square wave signal.

[0051] It should be noted that the output signal of the three-phase phase-locked loop is converted into a square wave signal with a 50% duty cycle based on the period information.

[0052] Step S3: Determine whether the square wave signal is normal based on the preset power system stability range. If it is, proceed to step S4; otherwise, proceed to step S5. The preset power system stability range includes frequency range, period range, and phase range.

[0053] It should be noted that power electronic converters used in power systems should have a stable range under normal operating conditions, including frequency, period, and phase domains. If the square wave signal meets the preset power system stable range domain, the square wave signal is normal; otherwise, the square wave signal is abnormal.

[0054] Specifically, the process for determining whether a square wave signal is abnormal is as follows:

[0055] Record the average periodicity Tavg0 and periodicity error range dT of the square wave signal within a preset time period (the preset time period covers multiple signal cycles, e.g., 1500 signal cycles within 30 seconds). The periodicity error range dT = 2 × dT0, where dT0 is the positive or negative error value when covering more than 80% of the data within the preset time period. Within the periodicity range Tavg0-dT to Tavg0+dT, for the first cycle signal, determine whether the square wave signal is normal based on whether the frequency is between 48Hz and 51.5Hz, whether the frequency change rate does not exceed 0.2Hz / s, and whether there is a sudden change in phase. If the frequency of the square wave signal is between 48Hz and 51.5Hz, the frequency change rate does not exceed 0.2Hz / s, and there is no sudden change in phase, then the cycle signal is considered normal; otherwise, the cycle signal is considered abnormal. For signals not in the first cycle, if the previous cycle signal was normal, and the continuous cycle variation compared to the previous cycle signal is less than a preset duration, then the signal cycle is considered normal, and step S4 is executed. If the continuous cycle variation is not less than the preset duration, then the cycle is considered abnormal, and step S5 is executed. If the previous cycle signal was abnormal, and the continuous cycle variation compared to the previous cycle signal is less than a preset duration + dT, then the signal cycle is considered normal, and step S4 is executed. If the continuous cycle variation is not less than a preset duration + dT, then the cycle is considered abnormal, and step S5 is executed.

[0056] In one embodiment, the preset duration is 1.6 µs. To avoid system overload or misjudgment due to prolonged accumulation of abnormal signals, in step S3, as follows... Figure 3 As shown, when an abnormal square wave signal occurs, it is necessary to determine whether the cumulative time for the square wave signal to be judged as an abnormal signal within 10 seconds exceeds 2 seconds. If so, the square wave signal after the cumulative time exceeds 2 seconds within the preset time is forcibly set as a normal signal.

[0057] Step S4: Output the output signal of the three-phase phase-locked loop.

[0058] It should be noted that if the square wave signal is normal, the output signal of the three-phase phase-locked loop will be output directly.

[0059] Step S5: Perform linear weighted calculation on the phase value of the output signal of the three-phase phase-locked loop using a sliding window to obtain the weighted phase value. Perform linear weighted calculation on the frequency value of the output signal of the three-phase phase-locked loop using a sliding window to obtain the weighted frequency value. Then proceed to step S6.

[0060] It should be noted that if the square wave signal is abnormal, a sliding window is used to perform linear weighted phase calculation on the output signal of the three-phase phase-locked loop (PLL) to obtain a weighted phase value. Similarly, a sliding window is used to perform linear weighted frequency calculation on the output signal of the PLL to obtain a weighted frequency value. When using a sliding window to weight the phase values, the closer the phase value is to the current time, the greater its weight; the farther the historical phase value is from the current time, the smaller its weight. This comprehensive weighted calculation ensures the stability and timeliness of the phase value. Likewise, when using a sliding window to weight the frequency values, the closer the frequency value is to the current time, the greater its weight; the farther the historical frequency value is from the current time, the smaller its weight. This comprehensive weighted calculation ensures the stability and timeliness of the frequency value.

[0061] The formula for calculating the weighted phase value is:

[0062]

[0063] in, For weighted phase values, These are the phase values ​​of n moments arranged in reverse chronological order. for One-to-one corresponding phase weight values, The value decreases linearly between [0,1].

[0064] For example, the most recent phase value The weighting is 1, 5 seconds ago Weight percentage is 0, intermediate phase Calculated using linear weights (e.g., phase 2.5s ahead). The weighting is 0.5%.

[0065] The formula for calculating the weighted frequency value is:

[0066]

[0067] in, These are weighted frequency values. These are the frequency values ​​of n moments arranged in reverse chronological order. for One-to-one frequency weight values, The value decreases linearly between [0,1].

[0068] For example, the most recent phase value The weighting is 1, 5 seconds ago Weight percentage is 0, intermediate phase Calculated using linear weights (e.g., phase 2.5s ahead). (Weight percentage is 0.5)

[0069] Step S6: Based on the weighted phase value and weighted frequency value, synthesize the output signal of the three-phase phase-locked loop into an internal phase-locked signal for output and mark the phase-locked abnormal signal.

[0070] It should be noted that after calculating the weighted phase value and weighted frequency value, these values ​​are used as the phase and frequency values ​​of the output signal of the three-phase phase-locked loop (PLL), and synthesized into an internal phase-locked signal for output, such as... Figure 3 As shown, the internal phase-locked signal can be denoted as signal 1. Simultaneously with outputting the internal phase-locked signal, a grid phase-locked anomaly signal is provided to indicate the issue, prompting the power electronic converter control system to promptly limit the operating current. For example... Figure 2 As shown, in this embodiment of the invention, the comprehensive judgment output module needs to determine whether to directly output the output signal of the three-phase phase-locked loop based on whether the acquired output signal of the three-phase phase-locked loop is abnormal. See also Figure 3 The integrated judgment output module can be set with two control values, 1 and 0. If the output signal of the three-phase phase-locked loop is within the normal range, the control value of the integrated judgment output module is 1, and the output signal of the three-phase phase-locked loop is directly used, that is, the integrated judgment output module selects signal 2 for output. If the output signal of the three-phase phase-locked loop is abnormal, the control value of the integrated judgment output module is 0, and the internal phase-locked signal is used for output, that is, the integrated judgment output module selects signal 1 for output.

[0071] The power electronic converter grid voltage phase-locked loop (PLL) method provided by this invention utilizes the output signal of a three-phase PLL within the normal power system fluctuation range. When the fluctuation exceeds the normal range, it is considered a grid anomaly. An internal PLL signal is constructed by weighting the phase and frequency of the three-phase PLL output signal to track and calculate the phase and frequency within the normal range. Switching to the internal PLL signal output results in a more stable output PLL signal. The grid voltage PLL output is unaffected by grid fluctuations and is less prone to instability. Simultaneously, a grid PLL anomaly indicator is provided, prompting the power electronic converter control system to promptly limit the operating current. This solves the technical problem that existing grid-connected converter PLLs are easily affected by grid fluctuations, leading to power electronic converter control fluctuations or even instability, and overcurrent disconnection from the grid.

[0072] For easier understanding, please refer to Figure 4 The present invention provides an embodiment of a power electronic converter grid voltage phase-locked loop device, comprising: a three-phase phase-locked loop, an internal phase-locked signal construction module, and a comprehensive judgment output module;

[0073] The three-phase phase-locked loop and the inner phase-locked signal construction module are connected, and the three-phase phase-locked loop and the inner phase-locked signal construction module are respectively connected to the comprehensive judgment output module;

[0074] A three-phase phase-locked loop is used to obtain three-phase signals from a three-phase power supply, process the three-phase signals, and output three-phase external phase-locked signals.

[0075] The internal phase-locked signal construction module is used to acquire the output signal of the three-phase phase-locked loop, convert the output signal of the three-phase phase-locked loop into a square wave signal, and perform linear weighted calculation on the phase value of the output signal of the three-phase phase-locked loop using a sliding window to obtain a weighted phase value. It also performs linear weighted calculation on the frequency value of the output signal of the three-phase phase-locked loop using a sliding window to obtain a weighted frequency value. Based on the weighted phase value and the weighted frequency value, the output signal of the three-phase phase-locked loop is synthesized into an internal phase-locked signal for output and to identify phase-locked abnormal signals.

[0076] The comprehensive judgment output module is used to determine whether the square wave signal is normal based on the preset power system stability range. If it is normal, it outputs the output signal of the three-phase phase-locked loop; otherwise, it outputs the internal phase-locked signal synthesized by the internal phase-locked signal construction module. The preset power system stability range includes frequency range, period range, and phase range.

[0077] In one embodiment, the comprehensive judgment output module is specifically used for:

[0078] Record the average periodic value Tavg0 and periodic error range dT of the square wave signal within a preset time period. Within the period range Tavg0-dT to Tavg0+dT, for the first period signal, determine whether the square wave signal is a normal signal based on whether the frequency of the square wave signal is between 48Hz and 51.5Hz, whether the frequency change rate does not exceed 0.2Hz / s, and whether there is a sudden change in phase. For signals other than the first period signal, if the previous period signal is a normal signal, then compared with the previous period signal, the continuous periodic change is less than the preset time, and the signal period is considered normal, and step S4 is executed. If the continuous periodic change is not less than the preset time, then the period is considered abnormal, and step S5 is executed. If the previous period signal is an abnormal signal, then compared with the previous period signal, the continuous periodic change is less than the preset time + dT, and the signal period is considered normal, and step S4 is executed. If the continuous periodic change is not less than the preset time + dT, then the period is considered abnormal, and step S5 is executed. The preset time covers multiple signal periods.

[0079] In one embodiment, the formula for calculating the weighted phase value is:

[0080]

[0081] in, For weighted phase values, These are the phase values ​​of n moments arranged in reverse chronological order. for One-to-one corresponding phase weight values, Its value decreases linearly between [0,1].

[0082] In one embodiment, the formula for calculating the weighted frequency value is:

[0083]

[0084] in, For weighted phase values, These are the frequency values ​​of n moments arranged in reverse chronological order. for One-to-one frequency weight values, The value decreases linearly between [0,1].

[0085] In one embodiment, the preset duration is 1.6µs.

[0086] In one embodiment, the preset time is 30 seconds. The comprehensive judgment output module is also used for:

[0087] Determine if the cumulative time for a square wave signal to be judged as an abnormal signal within 10 seconds exceeds 2 seconds. If so, force the square wave signal that has accumulated for more than 2 seconds within the preset time to be a normal signal.

[0088] This invention provides an embodiment of a power electronic converter grid voltage phase-locked loop device, the device including a processor and a memory:

[0089] The memory is used to store program code and transmit the program code to the processor;

[0090] The processor is used to execute the power electronic converter grid voltage phase-locking method provided in this invention according to the instructions in the program code.

[0091] The power electronic converter grid voltage phase-locking device and equipment provided in this invention are both used to execute the power electronic converter grid voltage phase-locking method provided in this invention. Their principles and the technical effects achieved are the same as those of the power electronic converter grid voltage phase-locking method provided in this invention, and will not be repeated here.

[0092] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for phase-locked loop (PLL) of grid voltage in a power electronic converter, characterized in that, include: S1. Obtain the output signal of the three-phase phase-locked loop; S2. Convert the output signal of the three-phase phase-locked loop into a square wave signal; S3. Determine whether the square wave signal is normal based on the preset power system stability range. If it is, proceed to step S4; otherwise, proceed to step S5. The preset power system stability range includes frequency range, period range, and phase range. S4, Output signal of the three-phase phase-locked loop; S5. The phase value of the output signal of the three-phase phase-locked loop is linearly weighted using a sliding window to obtain the weighted phase value. The frequency value of the output signal of the three-phase phase-locked loop is linearly weighted using a sliding window to obtain the weighted frequency value. Then, proceed to step S6. S6. Based on the weighted phase value and weighted frequency value, synthesize the output signal of the three-phase phase-locked loop into an internal phase-locked signal for output and mark the phase-locked abnormal signal.

2. The power electronic converter grid voltage phase-locking method according to claim 1, characterized in that, Step S3 specifically includes: Record the average periodic value Tavg0 and periodic error range dT of the square wave signal within a preset time period. Within the period range Tavg0-dT to Tavg0+dT, for the first period signal, determine whether the square wave signal is a normal signal based on whether the frequency of the square wave signal is between 48Hz and 51.5Hz, whether the frequency change rate does not exceed 0.2Hz / s, and whether there is a sudden change in phase. For signals other than the first period signal, if the previous period signal is a normal signal, then compared with the previous period signal, the continuous periodic change is less than the preset time, and the signal period is considered normal, and step S4 is executed. If the continuous periodic change is not less than the preset time, then the period is considered abnormal, and step S5 is executed. If the previous period signal is an abnormal signal, then compared with the previous period signal, the continuous periodic change is less than the preset time + dT, and the signal period is considered normal, and step S4 is executed. If the continuous periodic change is not less than the preset time + dT, then the period is considered abnormal, and step S5 is executed. The preset time covers multiple signal periods.

3. The power electronic converter grid voltage phase-locking method according to claim 2, characterized in that, The preset duration is 1.6us.

4. The power electronic converter grid voltage phase-locking method according to claim 2, characterized in that, The preset time is 30 seconds.

5. The power electronic converter grid voltage phase-locking method according to claim 4, characterized in that, Step S3 also includes: Determine if the cumulative time for a square wave signal to be judged as an abnormal signal within 10 seconds exceeds 2 seconds. If so, force the square wave signal that has accumulated for more than 2 seconds within the preset time to be a normal signal.

6. The power electronic converter grid voltage phase-locking method according to any one of claims 1-5, characterized in that, In step S5, the formula for calculating the weighted phase value is: in, For weighted phase values, These are the phase values ​​of n moments arranged in reverse chronological order. for One-to-one corresponding phase weight values, The value decreases linearly between [0,1].

7. The power electronic converter grid voltage phase-locking method according to any one of claims 1-5, characterized in that, In step S5, the formula for calculating the weighted frequency value is: in, These are weighted frequency values. These are the frequency values ​​of n moments arranged in reverse chronological order. for One-to-one frequency weight values, The value decreases linearly between [0,1].

8. A power electronic converter grid voltage phase-locked loop device, characterized in that, include: Three-phase phase-locked loop, internal phase-locked signal construction module and comprehensive judgment output module; The three-phase phase-locked loop and the inner phase-locked signal construction module are connected, and the three-phase phase-locked loop and the inner phase-locked signal construction module are respectively connected to the comprehensive judgment output module; A three-phase phase-locked loop is used to obtain three-phase signals from a three-phase power supply, process the three-phase signals, and output three-phase external phase-locked signals. The internal phase-locked signal construction module is used to acquire the output signal of the three-phase phase-locked loop, convert the output signal of the three-phase phase-locked loop into a square wave signal, and perform linear weighted calculation on the phase value of the output signal of the three-phase phase-locked loop using a sliding window to obtain a weighted phase value. It also performs linear weighted calculation on the frequency value of the output signal of the three-phase phase-locked loop using a sliding window to obtain a weighted frequency value. Based on the weighted phase value and the weighted frequency value, the output signal of the three-phase phase-locked loop is synthesized into an internal phase-locked signal for output and to identify phase-locked abnormal signals. The comprehensive judgment output module is used to determine whether the square wave signal is normal based on the preset power system stability range. If it is normal, it outputs the output signal of the three-phase phase-locked loop; otherwise, it outputs the internal phase-locked signal synthesized by the internal phase-locked signal construction module. The preset power system stability range includes frequency range, period range, and phase range.

9. The power electronic converter grid voltage phase-locked device according to claim 8, characterized in that, The comprehensive judgment output module is specifically used for: Record the average periodic value Tavg0 and periodic error range dT of the square wave signal within a preset time period. Within the period range Tavg0-dT to Tavg0+dT, for the first period signal, determine whether the square wave signal is a normal signal based on whether the frequency of the square wave signal is between 48Hz and 51.5Hz, whether the frequency change rate does not exceed 0.2Hz / s, and whether there is a sudden change in phase. For signals other than the first period signal, if the previous period signal is a normal signal, then compared with the previous period signal, the continuous periodic change is less than the preset time, and the signal period is considered normal, and step S4 is executed. If the continuous periodic change is not less than the preset time, then the period is considered abnormal, and step S5 is executed. If the previous period signal is an abnormal signal, then compared with the previous period signal, the continuous periodic change is less than the preset time + dT, and the signal period is considered normal, and step S4 is executed. If the continuous periodic change is not less than the preset time + dT, then the period is considered abnormal, and step S5 is executed. The preset time covers multiple signal periods.

10. A power electronic converter grid voltage phase-locked loop device, characterized in that, The device includes a processor and a memory: The memory is used to store program code and transmit the program code to the processor; The processor is configured to execute the power electronic converter grid voltage phase-locking method according to any one of claims 1-7 according to the instructions in the program code.

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