Mixer array

Abstract

The mixer array comprises eight-channel half-duplex mixers, a first power divider, an amplifying circuit, an FPGA (Field Programmable Gate Array) signal control circuit and a first power supply module, wherein the eight-channel half-duplex mixers can be expanded based on multiple of eight and are arranged along the longitudinal direction; the first power divider, the amplifying circuit, the FPGA signal control circuit and the first power supply module are correspondingly configured with the eight-channel half-duplex mixers; the first power divider and the amplifying circuit are connected with the local oscillation end of the eight-channel half-duplex mixer; the first power supply module is connected with the FPGA signal control circuit, and the FPGA signal control circuit is sequentially connected with a first power supply connector and a first signal connector of the eight-channel half-duplex mixer; the eight-channel half-duplex mixer comprises eight mixing chips, each mixing chip is connected with a mixing control circuit, a second power supply module, an intermediate frequency input / output and a radio frequency input / output, and each mixing chip is connected with a second power divider; the problems that a multi-beam antenna array needs to use a large number of frequency mixers, and a large number of frequency mixers are difficult to meet the requirements of high integration level, integrated power supply, heat dissipation and control can be solved.

Description

Technical Field

[0001] The present invention relates to the field of communications, and in particular to a mixer array. Background Art

[0002] The mixer is a necessary component in the communication system, used to provide signal frequency conversion from intermediate frequency to radio frequency band or vice versa. The current active mixer uses a mixing chip design based on a mixing diode or triode circuit to implement a mixing module to achieve RF input and output up and down mixing, and is mainly used in wireless transceiver systems with superheterodyne structures.

[0003] In order to meet the requirements of wireless communication systems with superheterodyne structures, most current mixers are single-channel modules, that is, independent mixers or common half-duplex mixers are used for the transmit / receive channels. As independent components, mixers are large in size and high in cost. In 5G and future 6G wireless communications, the multi-beam (or large-scale MIMO) antenna arrays of the fully connected architecture require a large number of intermediate frequencies to achieve one-to-one connection with the large-scale antenna arrays, thereby supporting digital multi-beam synthesis. Therefore, a large number of mixers are required. However, a large number of mixers are difficult to meet the problems of high integration, integrated power supply, heat dissipation and control. Summary of the invention

[0004] To overcome the above shortcomings, the purpose of the present invention is to propose a mixer array to solve the problem that a multi-beam antenna array with a fully connected architecture requires the use of a large number of mixers, while a large number of mixers cannot meet the requirements of high integration, integrated power supply, heat dissipation and control.

[0005] In order to achieve the above objectives, the technical solution adopted by the present invention includes an eight-channel half-duplex mixer that can be expanded based on multiples of eight and arranged vertically, and a first power distributor, an amplifier circuit, an FPGA signal control circuit, and a first power supply module configured corresponding to the eight-channel half-duplex mixer; the first power distributor and the amplifier circuit are both connected to the local oscillator end of the eight-channel half-duplex mixer; the first power supply module is connected to the FPGA signal control circuit, and the FPGA signal control circuit is connected to the first power supply connector and the first signal connector of the eight-channel half-duplex mixer in sequence.

[0006] The mixer of the present application is based on an expandable eight-channel half-duplex mixer array, and has the characteristics of compact structure, the number of channels can be expanded by multiples of eight, wide bandwidth, frequency conversion gain and tunable nonlinear parameters. Through module expansion, it can support the operation of 5G and 6G fully connected multi-beam antenna arrays, and has a wide range of applications.

[0007] In the preferred technical solution of the above-mentioned mixer array, the eight-channel half-duplex mixer includes eight mixing chips, each of which is connected to a mixing control circuit, a second power supply module, an intermediate frequency input / output, and a radio frequency input / output, and each of the mixing chips is connected to a second power distributor.

[0008] In the preferred technical solution of the above-mentioned mixer array, the FPGA signal control circuit includes at least an FPGA chip and a second power supply connector and a second signal connector connected to the FPGA chip; the second power supply connector is connected to the first power supply connector of the eight-channel half-duplex mixer through an external line, and the second signal connector is connected to the first signal connector of the eight-channel half-duplex mixer through an external line.

[0009] In the preferred technical solution of the mixer array, in the eight-channel half-duplex mixer, the eight mixer chips share reset and clock signal lines, and four mixer chips are grouped as a group and share serial output and address control words.

[0010] In the preferred technical solution of the above mixer array, the power input of the local oscillator port of a single mixer chip is -6dBm to 0dBm.

[0011] In the preferred technical solution of the mixer array, the eight-channel half-duplex mixer and the first power distributor, the amplifier circuit, the FPGA signal control circuit, and the first power supply module are all arranged in the outer shell.

[0012] In the preferred technical solution of the mixer array described above, an exhaust fan is disposed on the outer shell.

[0013] The beneficial effects of the present invention are: The mixer of the present application is based on an array of scalable eight-channel half-duplex mixers, which has the characteristics of compact structure, the number of channels can be expanded in multiples of eight, wide bandwidth, tunable frequency conversion gain and nonlinear parameters, and through module expansion, it can support the operation of 5G and 6G fully connected multi-beam antenna arrays, and has a wide range of applications. The mixer array of the present application can be used for upconverters and downconverters for 5G millimeter wave applications, and is controlled by a mixing control circuit based on the SPI protocol. The mixer array of the present application can process single-ended intermediate frequency (IF) signals in the range of 2.5-7GHz to suit different communication standards and application scenarios, and can operate on the RF band of 23-30GHz to cover the main frequency bands of 5G millimeter wave communications, ensuring high-speed, low-latency wireless communications. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 A schematic diagram of the mixer of the present invention being installed in an outer shell; Figure 2 is a schematic diagram of an eight-channel half-duplex mixer; Figure 3 is a circuit diagram of an eight-channel half-duplex mixer; Figure 4 is a circuit diagram of a mixer array of the present invention; In the figure: an eight-channel half-duplex mixer 1, a mixing chip 11, a second power distributor 12, a first power distributor 2, an FPGA signal control circuit 3, an FPGA chip 31, a storage chip 32, a serial port conversion chip 33, a network port conversion chip 34, and an outer shell 4. DETAILED DESCRIPTION

[0014] The preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood by those skilled in the art that these embodiments are only used to explain the technical principles of the present invention and are not intended to limit the protection scope of the present invention.

[0015] It should be noted that in the description of the present invention, the terms "upper", "lower", "left", "right", "front", "rear" and the like indicating directions or positional relationships are based on the directions or positional relationships shown in the drawings, which are only for the convenience of description, and do not indicate or imply that the device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0016] In addition, it should be noted that in the description of the present invention, unless otherwise clearly specified and limited, the terms "disposed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0017] like Figures 1 to 4 As shown, the mixer array of the present invention includes an eight-channel half-duplex mixer 1 that can be expanded based on multiples of eight and arranged in the longitudinal direction, and a first power distributor 2, an amplifier circuit, an FPGA signal control circuit 3, and a first power supply module configured corresponding to the eight-channel half-duplex mixer 1; the first power distributor 2 and the amplifier circuit are both connected to the local oscillator end of the eight-channel half-duplex mixer 1; the first power supply module is connected to the FPGA signal control circuit 3, and the FPGA signal control circuit 3 is connected to the first power supply connector and the first signal connector of the eight-channel half-duplex mixer 1 in sequence.

[0018] See also Figure 3 , Figure 4The eight-channel half-duplex mixer 1 is used for signal modulation, demodulation, up-conversion and down-conversion, and only processes signal transmission in one direction at the same time; the mixer array of the present application can be expanded based on the number of eight eight-channel half-duplex mixers 1, thereby expanding to 16 channels, 24 channels, 32 channels, 64 channels, 128 channels, 256 channels, etc., to form support for a fully connected multi-beam antenna array; the following only takes the number of eight eight-channel half-duplex mixers 1 as eight as an exemplary explanation.

[0019] See also Figure 3 The mixer of the present application includes at least eight eight-channel half-duplex mixers 1, a first power distributor 2, an amplifier circuit, an FPGA signal control circuit 3, and a first power supply module.

[0020] The first power distributor 2 is respectively connected to eight eight-channel half-duplex mixers 1 to distribute the local oscillator signal to each of the eight-channel half-duplex mixers 1. The amplifier circuit is used to amplify the local oscillator signal to ensure that the local oscillator signal can drive each of the eight-channel half-duplex mixers 1 to work normally. In addition, the amplifier circuit can filter and denoise the local oscillator signal to improve the quality of the local oscillator signal and improve the performance and stability of each of the eight-channel half-duplex mixers 1. In the local oscillator end connection of the eight-channel half-duplex mixer 1, the first power distributor 2 and the amplifier circuit jointly play a role in signal distribution, amplification and optimization. Specifically, the first power distributor 2 is a one-to-eight local oscillator power distributor, and the amplifier circuit is an amplifier.

[0021] The FPGA signal control circuit 3 is used to control the eight-channel half-duplex mixer 1 to realize signal modulation, demodulation, up-conversion and down-conversion; specifically, the FPGA signal control circuit 3 is connected to the first power supply connector and the second signal connector of the eight-channel half-duplex mixer 1, and the first power supply module is connected to the FPGA signal control circuit 3, and the first power supply module is used to supply power to the FPGA signal control circuit 3 and the eight-channel half-duplex mixer 1.

[0022] The mixer of the present application is based on an expandable eight-channel half-duplex mixer 1 array, and has the characteristics of compact structure, the number of channels can be expanded by multiples of eight, wide bandwidth, frequency conversion gain and tunable nonlinear parameters. Through module expansion, it can support the operation of 5G and 6G fully connected multi-beam antenna arrays and has a wide range of applications.

[0023] In one or more embodiments, the eight-channel half-duplex mixer 1 includes eight mixing chips 11, each mixing chip 11 is connected to a mixing control circuit, a second power supply module, an intermediate frequency input / output, and a radio frequency input / output, and each mixing chip 11 is connected to a second power distributor 12; in the eight-channel half-duplex mixer 1, the eight mixing chips 11 share a reset and clock signal line, and four mixing chips 11 are listed as a group and share a serial output and an address control word; the power input of the local oscillator port of a single mixing chip 11 is -6dBm to 0dBm.

[0024] See also Figure 3 , Figure 4 Each mixer chip 11 is connected to a mixer control circuit or shares a mixer control circuit. The second power supply module is connected to the mixer chip 11 to provide a 3.3V voltage to the mixer chip 11. The mixer chip 11 is also connected to an intermediate frequency input / output and a radio frequency input / output. The eight-channel half-duplex mixer 1 also includes a second power divider 12. The second power divider 12 is a one-to-eight local oscillator power divider. The eight mixer chips 11 are all connected to the input end of the second power divider 12.

[0025] Specifically, when controlling the eight-channel half-duplex mixer 1, a single mixer control circuit uses five signal lines to respectively realize chip reset, clock signal serial input / output and address control word, and the mixer chip 11 has a 2-bit address to support the common control signal of the mixer chips 11 with up to four different addresses; in this application, the eight mixer chips 11 in the eight-channel half-duplex mixer 1 share reset and clock signal lines, and the four mixer chips 11 are listed as a group, sharing serial output and address control words to realize independent control of two groups. In addition, it should be noted that the ideal input power of the local oscillator port of a single mixer chip 11 is -6dBm~0dBm, and the power division loss and insertion loss of the first power divider 2, the second power divider 12 and their connectors and connecting lines are generally 20dB~25dB. Therefore, the power amplifier circuit gain value is configured to be 20dB, and the external local oscillator input power is 0dBm, then the eight-channel half-duplex mixer 1 of this application can work normally.

[0026] The mixer array of the present application can be used for upconverters and downconverters for 5G millimeter wave applications, and is controlled by a mixing control circuit based on the SPI protocol. The mixer array of the present application can process single-ended intermediate frequency (IF) signals in the range of 2.5-7 GHz to suit different communication standards and application scenarios, and can operate on a radio frequency band of 23-30 GHz to cover the main frequency bands of 5G millimeter wave communications, ensuring high-speed, low-latency wireless communications.

[0027] In up-converter mode, it can suppress unwanted sidebands to more than 25dB, reduce signal interference and distortion, and provide a typical 19dBm output 1dB compression point power value, so that when the signal power increases to the threshold, the output power growth tends to be flat, avoiding distortion caused by excessive signal strength. At the same time, the up-converter can achieve a typical conversion gain of 24dB to ensure effective signal amplification, and achieve 31.5dB dynamic amplitude adjustment through a 6-bit variable attenuator, allowing the system to adjust the signal amplitude as needed.

[0028] In the down-converter mode, the down-converter input 1dB compression point power value is -14dBm, and the typical conversion gain is 26dB. When the signal is weak, the down-converter can still effectively amplify and convert the received signal. At the same time, a 31.5dB dynamic amplitude modulation range can be achieved through a 6-bit variable attenuator to ensure the system's receiving performance.

[0029] In addition, it should be noted that the eight-channel half-duplex mixer 1 of the present application is embedded with a temperature sensor and a power sensor for reading the on-chip temperature and on-chip power of the mixer chip 11 to achieve real-time monitoring of the working status of the mixer chip 11 .

[0030] In one or more embodiments, the FPGA signal control circuit 3 includes at least an FPGA chip 31 and a second power supply connector connected to the FPGA chip 31, a second signal connector, a storage chip 32, a voltage control chip, a serial port conversion chip 33, a network port conversion chip 34, a USB interface connector, and a network port connector; the second power supply connector is connected to the first power supply connector of the eight-channel half-duplex mixer 1 through an external line, and the second signal connector is connected to the first signal connector of the eight-channel half-duplex mixer 1 through an external line.

[0031] See also Figure 3 , Figure 4 , FPGA chip 31 is responsible for signal processing and control, storage chip 32 is used to store programs and data to support the operation of FPGA chip 31, voltage control chip is used to adjust and stabilize the power supply voltage, serial port conversion chip 33 and network port conversion chip 34 respectively provide serial port and network port communication functions to transmit and communicate data with external devices, USB interface connector and network port connector are used to provide USB interface and network port physical interface to facilitate connection with external devices.

[0032] Specifically, there are eight second power supply connectors and eight second signal connectors, and the eight second power supply connectors are connected to the voltage control chip. Through external power lines, the eight second power supply connectors are respectively connected to the eight first power supply connectors of the eight-channel half-duplex mixer 1, so as to provide a stable power supply for the array of mixers. The eight second signal connectors are all connected to the FPGA chip 31, and through external signal lines, the eight second signal connectors are respectively connected to the first signal connectors of the eight-channel half-duplex mixer 1 to realize signal input and output. The expandable FPGA signal control circuit 3 of the present application provides accurate signal generation, control and processing for the eight-channel half-duplex mixer 1, realizes independent configuration and monitoring of each channel, ensures synchronization and coordination of signals between channels, has high scalability and integration, and can make the eight-channel half-duplex mixer 1 better adapt to complex application scenarios and requirements.

[0033] In one or more implementations, the eight-channel half-duplex mixer 1 and the first power distributor 2, the amplifier circuit, the FPGA signal control circuit 3, and the first power supply module are all configured in an outer shell 4; an exhaust fan is configured on the outer shell 4.

[0034] See also Figure 1 , Figure 2 The outer shell 4 is made of metal material. Eight eight-channel half-duplex mixers 1 are arranged in sequence in the vertical direction in the outer shell 4. The outer shell 4 has an opening for inserting an external cable. A window is provided on one side of the outer shell 4. The window is a shutter type. The outer shell 4 is provided with an exhaust fan on the opposite side of the window or in the outer shell 4. The exhaust fan is used to agitate the air flow toward the eight eight-channel half-duplex mixers 1 to achieve heat dissipation and cooling of the mixers. In other possible implementations, a semiconductor cooling plate is arranged at the air inlet of the exhaust fan. The semiconductor cooling plate has a cold end and a hot end, wherein the cold end is arranged toward the air inlet of the exhaust fan; in this way, the eight-channel half-duplex mixer 1 can be cooled in the form of cold air, further improving the cooling effect of the present application on the eight-channel half-duplex mixer 1 and ensuring the normal operation of the mixer.

[0035] The above implementation modes are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with this technology to understand the content of the present invention and implement it, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

[0036] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. A mixer array, characterized in that: It includes an eight-channel half-duplex mixer that can be expanded based on multiples of eight and arranged in the longitudinal direction, and a first power distributor, an amplifying circuit, an FPGA signal control circuit, and a first power supply module configured corresponding to the eight-channel half-duplex mixer; The first power distributor and the amplifier circuit are both connected to the local oscillator end of the eight-channel half-duplex mixer; the first power supply module is connected to the FPGA signal control circuit, and the FPGA signal control circuit is connected to the first power supply connector and the first signal connector of the eight-channel half-duplex mixer in sequence.

2. The mixer array according to claim 1, characterized in that: The eight-channel half-duplex mixer includes eight mixing chips, each of which is connected to a mixing control circuit, a second power supply module, an intermediate frequency input / output, and a radio frequency input / output, and each of which is connected to a second power distributor.

3. The mixer array according to claim 2, characterized in that: The FPGA signal control circuit includes at least an FPGA chip and a second power supply connector and a second signal connector connected to the FPGA chip; the second power supply connector is connected to the first power supply connector of the eight-channel half-duplex mixer through an external line, and the second signal connector is connected to the first signal connector of the eight-channel half-duplex mixer through an external line.

4. The mixer array according to claim 2, characterized in that: In the eight-channel half-duplex mixer, eight mixer chips share reset and clock signal lines, and four mixer chips are grouped as a group and share serial output and address control words.

5. The mixer array according to claim 2, characterized in that: The power input of the local oscillator port of a single mixing chip is -6dBm to 0dBm.

6. The mixer array according to claim 1, characterized in that: The eight-channel half-duplex mixer, the first power distributor, the amplifier circuit, the FPGA signal control circuit, and the first power supply module are all arranged in the outer shell.

7. The mixer array according to claim 6, characterized in that: The outer shell is provided with an exhaust fan.

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