An LDPC decoder for ethernet protocol
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING UNIV
- Filing Date
- 2024-12-24
- Publication Date
- 2026-07-21
AI Technical Summary
Existing RS-LDPC decoders in the 802.3an protocol suffer from high design complexity, large resource overhead, and poor decoding performance. In particular, they cannot meet the protocol requirements when the bit error rate reaches the error floor, and the hardware overhead of the entire decoding architecture is too large.
A layered decoder hardware architecture is adopted, which utilizes a multi-layer configurable multi-selector architecture for information routing. It combines a half-layer decoding method with a configurable multi-parameter post-processing module and introduces an early termination module to optimize decoder performance, reduce design complexity and hardware resource consumption.
While meeting throughput requirements, hardware costs are reduced, and decoding performance is improved through algorithm optimization, reducing the bit error rate to 10-12, which meets protocol requirements.
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Figure CN119766398B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of communications, and more specifically to a hardware architecture for an LDPC decoder for the Ethernet protocol. Background Technology
[0002] During information transmission, noise interference can cause the receiver to receive erroneous information. To address this issue, numerous encoding and decoding algorithms have been developed, primarily using redundant information to protect the data. The encoded data can then be recovered from the original data at the receiving end using a specific decoding algorithm. LDPC (Low Density Parity Check Codes), proposed by Gallager in 1962, boasts performance approaching the Shannon limit. RS-LDPC, a subset of LDPC codes, uses RS codes to generate its parity check matrix. It exhibits superior performance and lower hardware implementation complexity, and is adopted by the 802.3an protocol.
[0003] Since RS-LDPC does not have a quasi-cyclic parity check matrix like QC-LDPC (Quasi Cyclic Low Density Parity Check Codes), taking RS-LDPC (2048, 1723) given in the 802.3an protocol as an example, although the submatrix of RS-LDPC's parity check matrix has only one element 1 in each row and column, just like QC-LDPC, the information transfer between variable nodes and parity nodes cannot be achieved through simple cyclic shifting. This invention adopts a multi-layer multi-selector architecture to achieve information transfer. This method has a certain degree of flexibility and can automatically generate the information transfer network through scripts to reduce the complexity of the design.
[0004] Early LDPC decoders used the belief propagation algorithm for decoding. This algorithm is based on rigorous derivation in probability theory to obtain the probability of each information bit being 0 or 1. However, this algorithm involves a lot of multiplication calculations and has high complexity. If the probability information is converted into the form of log-likelihood ratio, the multiplication operation can be converted into an addition operation. This algorithm is called the sum-product algorithm. However, this algorithm involves nonlinear operations and is difficult to implement in hardware. Later research found that by utilizing the monotonicity of nonlinear operations, the minimum or second smallest value in the information can be used to approximate the result of the nonlinear operation. This algorithm is called the minimum sum algorithm. The offset minimum sum algorithm adds an offset value to the minimum and second smallest values based on the minimum sum algorithm. This value is determined through simulation. In order to make the information passed from the check node to the variable node closer to the belief propagation algorithm, this algorithm is widely used because it is relatively easy to implement in hardware and has low hardware overhead.
[0005] The formula for the minimum offset sum algorithm decoding is:
[0006]
[0007] Among them, L (m) (q ij L(P) represents the information passed from variable node i to check node j in the m-th iteration. i ) represents the channel initial information corresponding to the i-th bit, L (m) (r ji C represents the information passed from node j to variable node i in the m-th iteration. i\j R represents all connected check nodes in the i-th column of the check matrix except for the j-th row. j\i This represents all connected variable nodes in the j-th row of the verification matrix except for the i-th column, where β is an offset constant.
[0008] For RS-LDPC (2048, 1723) codes, if BPSK modulation is used and the minimum offset sum algorithm is employed for decoding, with the offset constant set to 1, the bit error rate (BER) reaches its error floor at SNR = 5, on the order of 10. -10 The reason for this phenomenon is that the decoding gets stuck in a specific trap set structure, preventing erroneous bits from being flipped to the correct values. Such performance cannot meet the requirements of the protocol. For the 10Gbps throughput requirement, using a full-layer decoding architecture results in excessive hardware overhead. Therefore, a highly efficient decoding hardware architecture for RS-LDPC codes is needed, along with optimized decoding algorithms, to address the issues of high design complexity, high resource consumption, and poor decoder performance. Summary of the Invention
[0009] Objective: This invention implements a layered decoder to meet the requirements of the 802.3an protocol. Addressing the complexity of RS-LDPC information routing, it employs a multi-layered configurable multi-selector architecture, enabling automatic interconnect configuration via scripts, thus reducing overall design complexity. The design utilizes a half-layer decoding approach, with the decoder processing data from 1024 variable nodes and 64 check nodes per cycle, consuming 12 clock cycles per iteration. Compared to full-layer decoding, this approach saves hardware overhead while meeting throughput requirements. To address the issue of bit error rate reaching the error plateau, a configurable multi-parameter post-processing module is used to further improve decoder performance and provide flexibility. Furthermore, this invention proposes a simple early termination module. After the check nodes have processed all layers of information, they generate a decision value. Based on this decision value, decoding success is determined, and the decoding process is terminated. This early termination module saves hardware resources and improves decoder performance.
[0010] Technical Solution: This invention discloses a hardware architecture for an LDPC decoder suitable for the 802.3an protocol. The hardware architecture mainly includes 1024 variable node modules, 64 check node modules, a variable node data transmission network, a check node data transmission network, an early termination module, and a configurable multi-parameter post-processing module, capable of continuously decoding the input channel information to be decoded. The specific architecture is as follows... Figure 1 As shown:
[0011] The main modules included in this hardware architecture are:
[0012] Verification node processing module: It adopts the minimum offset sum algorithm to obtain the message passed by the variable node, and outputs the minimum value, the second smallest value and the corresponding variable node sign product.
[0013] Variable Node Processing Module: Responsible for storing the input initial channel information LLR values. Each variable node stores two LLR values. It calculates the posterior value corresponding to the node using the information transmitted by the check node. Based on the information transmitted by the early termination module and the set maximum number of iterations, it outputs the decoding information when decoding is complete.
[0014] Post-processing module: Processes the signal transmitted from the verification node using configurable enhancement / de-enhancement information, and passes the enhancement or de-enhancement information to the variable node processing module.
[0015] Interconnection module from variable node to verification node: This module adopts a multi-layer multi-selector structure, selects and transmits 1024 variable node information in a single cycle, and completes single-layer information transmission in two clock cycles.
[0016] Verification node to variable node interconnection module: This module adopts a multi-layer multi-selector structure, which transmits the information of 64 verification nodes to 1024 variable nodes in a single cycle, and completes the single-layer information transmission in two clock cycles.
[0017] The overall design adopts a half-layer decoding architecture, and uses an optimized minimum sum algorithm and an early termination algorithm to achieve a balance between power consumption, area and performance. Attached Figure Description
[0018] Figure 1 This invention presents the hardware architecture for the RS-LDPC decoder.
[0019] Figure 2 This is the specific architecture of the variable node proposed in this invention.
[0020] Figure 3 This is the specific architecture of the verification node proposed in this invention.
[0021] Figure 4This is a flowchart illustrating the decoding process of an embodiment of the present invention.
[0022] Figure 5 The figures represent the performance curves of an embodiment of the present invention. Detailed Implementation
[0023] To illustrate the technical solutions disclosed in this invention in detail, exemplary embodiments of this invention will be described in detail below with reference to the accompanying drawings.
[0024] This invention provides a decoding architecture for an RS-LDPC decoder, the overall architecture of which is as follows: Figure 1 As shown, it includes the following steps:
[0025] Step 1: Buffer LLR information from the channel into the FIFO. Once a frame of data is completely stored, the decoding process begins. When the first frame of data is being processed, the second frame of data can be buffered to improve the system throughput.
[0026] Step 2: Input the data read from the FIFO into the VNU module. In the first assignment cycle, the initial LLR data is assigned to register A in the VNU module. After the assignment is complete, the initialization of variable nodes 1-1024 is finished. In the second assignment cycle, the remaining half-frame data is assigned to register B in the VNU module. The initialization of variable nodes 1025-2048 is completed. At this point, the initial LLR information of all variable nodes has been initialized.
[0027] Step 3: During the normal iteration cycle, the minimum offset sum algorithm is used. The variable nodes perform calculations based on prior information and external information. Each cycle processes half of the data and sends it to the verification node. The entire layer of information is calculated and transmitted in two cycles.
[0028] Step 4: The verification node, based on the information passed from the variable node, performs sign operations, searches for the minimum and second-smallest values, and saves the results of the sign operations. The determination of the minimum and second-smallest values uses a multi-level comparator. First, the data from the 16 variable nodes is grouped. The grouped data is input into a 4-to-2 selection module. This module outputs the minimum and second-smallest values among the four values based on the grouped input information, and saves the maximum and minimum values obtained by the module. In the next cycle, after obtaining the maximum and minimum values of the other 16 variable nodes, the two groups of numbers are compared to obtain the maximum and minimum values corresponding to the entire layer of data, and the results are sent to the variable node.
[0029] Step 5: After one iteration is completed, the verification node outputs the symbols corresponding to the six layers of data. The early termination module first determines whether the verification equations are satisfied based on the symbol information. If satisfied, the iteration is terminated directly and the process proceeds to step 7. If not satisfied, the current iteration number is checked to see if it is greater than the set number of normal iterations. If it is not exceeded, the process proceeds to step 3. If it exceeds the number of normal iterations, the process proceeds to step 6.
[0030] Step Six: During the post-processing iteration, the data transmitted by the verification node is first modified based on the configured data, strengthening information with negative symbols and weakening information with positive symbols. Then, the next iteration begins from Step Three. The post-processing process consists of two parts: configuring a set of enhancement information and a set of weakening information. By iterating through two configurations of post-processing parameters, most of the trap sets are resolved, and the performance of the decoder is improved.
[0031] Step 7: After the iteration is complete, obtain 2048 bits of decoded codewords and store them in a FIFO.
[0032] This invention designs a decoder for LDPC codes specified in the 802.3an protocol. Each cycle processes half a layer of data, with a total of six layers, requiring 12 cycles to complete one iteration. It employs an optimized information exchange strategy. Addressing the complexity of internetwork design, it uses a script-based method to read the parity check matrix to generate the internetwork module. Therefore, this invention is applicable to all similar RS-LDPC codes. To address the issue of a high bit error rate (BER) in the 802.3an protocol, it utilizes a configurable post-processing module and optimizes the decoding algorithm, reducing the decoder's BER to 10. -12 .
Claims
1. An LDPC decoder suitable for 802.3an protocol, characterized in that: It includes 1024 variable node modules (VNU), 64 check node modules (CNU), an information interconnection network module, an early termination module (ET), and a post-processing module with configurable parameters; The information interconnection network module is used to perform information interaction between the variable node module (VNU) and the verification node module (CNU). The information interconnection network module includes a variable node to verification node interconnection network (V2C_Network) and a verification node to variable node interconnection network (C2V_Network). Both adopt a multi-layer multi-selector structure, so that in each clock cycle during the normal iteration cycle, half of the variable nodes and the corresponding verification nodes are selected for information transmission, thereby completing one layer of information transmission in two clock cycles. The variable node module (VNU) is used to store the input initial channel log-likelihood ratio (LLR) value, and calculate the posterior information of the corresponding variable node in each iteration period based on the initial (LLR) value and the extrinsic information transmitted by the verification node module (CNU). The verification node module (CNU) is used to perform sign operations on the information from the variable node module (VNU) and obtain the minimum and second smallest values using the offset minimum sum algorithm, and then send the operation results to the corresponding variable node module (VNU). The Early Termination Module (ET) is used to determine whether all verification equations are satisfied based on the sign information of each verification equation output by the Verification Node Module (CNU) after each iteration. When the decoding is successful, a termination signal is output to stop the subsequent iteration; otherwise, the iteration is allowed to continue or the post-processing iteration is started. The configurable parameter post-processing module is integrated within the variable node module (VNU). If decoding fails within the normal decoding iterations, two post-processing steps are initiated to enhance the information transmitted by the check node module (CNU) that does not satisfy the check equation, and to weaken the information transmitted by the check node module (CNU) that satisfies the check equation. The parameters are obtained by simulation using the initial log-likelihood ratio (LLR) of multiple frames of trapped trap sets. By configuring the parameters, most trap sets can be eliminated and the decoding performance of the decoder can be improved.
2. The LDPC decoder of claim 1, wherein: During the decoding process, the Early Termination Module (ET) takes the symbol information output by the Check Node Module (CNU) as input, calculates the symbol product corresponding to 32 variable nodes every two clock cycles, and saves the obtained symbol product result through a shift register. When a decoding iteration is completed, the Early Termination Module (ET) determines whether all check equations are satisfied based on the symbol product result stored in the shift register. When it is determined that decoding is complete, the subsequent iterations are terminated in advance, thereby improving system throughput and saving power consumption.
3. The LDPC decoder of claim 1, wherein: The information interconnection network module first selects the data of the variable nodes during the normal iteration cycle, and selects half of the variable nodes in a single clock cycle. Data transmission between the variable node module (VNU) and the verification node module (CNU) is realized through a multi-layer multi-selector structure. The information interconnection network module automatically generates the verification matrix by reading the verification matrix through a script, which facilitates the construction of similar LDPC decoders.