Semiconductor element and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device includes a resistive memory (RRAM) device, a dual damascene structure, and a spacer. The dual damascene structure is disposed beside the RRAM element, and the spacer is disposed on a sidewall of the RRAM element. The RRAM element includes a lower electrode, a metal oxide layer, and an upper electrode. The metal oxide layer is disposed on the lower electrode, and the upper electrode is disposed on the metal oxide layer. The dual damascene structure includes a via and a conductive line disposed on the via, wherein a top of the conductive line is coplanar with a top of an upper electrode in the RRAM element.

Description

Technical Field

[0001] The present invention relates to a semiconductor element and a manufacturing method thereof, and more particularly to a semiconductor element and a manufacturing method thereof for simultaneously forming a resistive random access memory (RRAM) element and interconnection. Background Art

[0002] RRAM is a type of non-volatile memory that has the characteristics of small storage cell size, ultra-high-speed operation, low-power operation, and high durability. Therefore, it has become a widely studied non-volatile memory in recent years. However, the manufacturing process of RRAM requires at least three photomask processes. Moreover, the process of RRAM has not yet been studied for integration with the process of dual-damascene structure. Summary of the invention

[0003] The present invention is directed to a semiconductor element, which can manufacture RRAM elements and dual mosaic structures with less photomask processes.

[0004] The present invention is also directed to a method for manufacturing a semiconductor element, which can integrate the process of the RRAM element and the process of the dual damascene structure.

[0005] According to an embodiment of the present invention, a semiconductor element includes a resistive RAM (RRAM) element, a dual damascene structure, and a spacer. The dual damascene structure is disposed next to the RRAM element, and the spacer is disposed on the sidewall of the RRAM element. The RRAM element includes a lower electrode, a metal oxide layer, and an upper electrode. The metal oxide layer is disposed on the lower electrode, and the upper electrode is disposed on the metal oxide layer. The dual damascene structure includes a through hole and a conductive line disposed on the through hole, wherein the top of the conductive line is coplanar with the top of the upper electrode in the RRAM element.

[0006] In the semiconductor device according to the embodiment of the present invention, the top of the spacer may also be coplanar with the top of the upper electrode of the RRAM device.

[0007] In the semiconductor device according to the embodiment of the present invention, the top of the spacer may be coplanar with the top of the conductive line.

[0008] In the semiconductor device according to the embodiment of the present invention, the spacer has a rectangular shape in the cross-sectional view.

[0009] In the semiconductor device according to the embodiment of the present invention, in the cross-sectional view, the thickness of the spacer located on the right side of the RRAM device is different from the thickness of the spacer located on the left side of the RRAM device.

[0010] In the semiconductor element according to the embodiment of the present invention, the metal oxide layer is U-shaped.

[0011] In the semiconductor element according to the embodiment of the present invention, the bottom surface of the lower electrode and the bottom of the dual damascene structure are coplanar.

[0012] In the semiconductor device according to the embodiment of the present invention, the material of the lower electrode may be titanium, the material of the metal oxide layer may be hafnium oxide, and the material of the upper electrode may be titanium nitride.

[0013] According to an embodiment of the present invention, a method for manufacturing a semiconductor element includes forming a dielectric layer on a substrate having a metal layer, and forming an opening in the dielectric layer to expose the metal layer; then forming a spacer on the sidewall of the opening, and forming a lower electrode at the bottom of the opening; conformally forming a metal oxide layer on the lower electrode, and then forming an upper electrode on the metal oxide layer and filling the opening; forming a dual-damascene hole having a hole and a groove in the dielectric layer next to the opening, and then filling the dual-damascene hole with a conductive material, and then performing a planarization process to simultaneously remove a portion of the conductive material and a portion of the upper electrode.

[0014] In a manufacturing method according to another embodiment of the present invention, the method for forming the above-mentioned spacer includes first filling the above-mentioned opening with a nitride layer, then forming a patterned mask on the dielectric layer and exposing a portion of the nitride layer, and then using the above-mentioned patterned mask as an etching mask to etch the exposed portion of the nitride layer until the above-mentioned metal layer is exposed.

[0015] In a manufacturing method according to another embodiment of the present invention, the method of forming the spacer includes conformally depositing a nitride layer on the inner surface of the opening, and then etching back the nitride layer until the metal layer is exposed.

[0016] In a manufacturing method according to another embodiment of the present invention, the step of forming the upper electrode includes forming an excess portion above the dielectric layer outside the opening. The method of forming the above-mentioned dual mosaic hole includes patterning the excess portion above the dielectric layer to form a first patterned mask. The dielectric layer is etched using the first patterned mask as an etching mask to form a groove in the dielectric layer, and then a second patterned mask is formed in the groove to expose a portion of the dielectric layer. The dielectric layer is etched using the second patterned mask as an etching mask to form a hole in the dielectric layer below the groove.

[0017] In a manufacturing method according to another embodiment of the present invention, the method of forming the lower electrode includes filling the opening with a conductive layer, planarizing the conductive layer, and then etching back the conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a cross-sectional schematic diagram of a semiconductor element according to a first embodiment of the present invention;

[0019] FIG. 2A to FIG. 2NIt is a cross-sectional schematic diagram of a manufacturing process of a semiconductor element according to the second embodiment of the present invention.

[0020] Description of Reference Numerals

[0021] 100, 232: Resistive RAM (RRAM) components

[0022] 100a: Sidewall

[0023] 102, 230', 238a, 238b: Dual mosaic structure

[0024] 102a: Bottom

[0025] 104, 208': Spacer

[0026] 104a, 116a, 120a: Top

[0027] 106, 200: substrate

[0028] 108a, 108b, 202: Metal layer

[0029] 110, 122, 201, 228, 240: Barrier layer

[0030] 112, 212': Lower electrode

[0031] 112a: Bottom

[0032] 114, 214: Metal oxide layer

[0033] 116, 216: Upper electrode

[0034] 118: Through hole

[0035] 120: Wire

[0036] 124, 126, 204, 234: Cover layer

[0037] 208: Nitride layer

[0038] 210: Patterned Mask

[0039] 212: Conductive layer

[0040] 218: Extra

[0041] 218': First patterned mask

[0042] 220: Groove

[0043] 222: Second patterned mask

[0044] 224: Holes

[0045] 226: Double inlay hole

[0046] 230: Conductive materials

[0047] IMD, IMD1, IMD2, 206, 236: Dielectric layer

[0048] O1: First opening

[0049] O2: Second opening DETAILED DESCRIPTION

[0050] The present invention is applied to a semiconductor element including a resistive random access memory (RRAM) element and interconnection, and through element and process design, the position and height of the RRAM element can be made the same or similar to the dual-damascene structure in the interconnection, especially in terms of process, at least one photomask process can be reduced, thereby reducing the manufacturing cost, and can be integrated with the interconnection process.

[0051] Some embodiments are given below to illustrate the present invention, but the present invention is not limited to the given embodiments. The given embodiments may be combined with each other.

[0052] Figure 1 is a cross-sectional schematic diagram of a semiconductor device according to a first embodiment of the present invention.

[0053] Please refer to Figure 1The semiconductor device of the first embodiment basically includes a RRAM device 100, a dual damascene structure 102, and a spacer 104. The dual damascene structure 102 is disposed beside the RRAM device 100, and the spacer 104 is disposed on the sidewall 100a of the RRAM device 100. In one embodiment, the RRAM device 100 and the dual damascene structure 102 may be disposed on a substrate 106. The substrate 106 generally includes a semiconductor substrate (not shown) and a dielectric layer IMD1 thereon and metal layers 108a and 108b formed in the dielectric layer IMD1. The material of the dielectric layer IMD1 is, for example, but not limited to, undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (fluorine-doped silicate glass, FSG), silicon oxide (SiO2), SiOC-based materials, or other suitable extremely low dielectric constant (ELK) or ultra low dielectric constant (ULK) materials. The material of the metal layer 108a and the metal layer 108b is, for example, copper (Cu) or other suitable metal materials, such as cobalt (Co), aluminum (Al), tungsten (W), nickel (Ni), platinum (Pt), tantalum (Ta) or titanium (Ti). A barrier layer 110 may be disposed between the metal layer 108a and the dielectric layer IMD1, and another barrier layer 110 may be disposed between the metal layer 108b and the dielectric layer IMD1. The material of the barrier layer 110 is, for example, but not limited to, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a stack of the foregoing materials. Although Figure 1 Although not specifically indicated, it should be known that other metal layers, contacts and other interconnections may be formed under the dielectric layer IMD1, and so on. The material of the dual damascene structure 102 is, for example, but not limited to, a group consisting of Cu, Co, Al, W, Ni, Pt, Ta, Ti, titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but not limited thereto.

[0054] exist Figure 1In the embodiment, the RRAM element 100 includes a lower electrode 112, a metal oxide layer 114 and an upper electrode 116. The metal oxide layer 114 is disposed on the lower electrode 112, and the upper electrode 116 is disposed on the metal oxide layer 114. The lower electrode 112 is connected to the metal layer 108a to achieve electrical connection. The material of the lower electrode 112 is, for example, titanium (Ti) or other suitable conductive materials, such as tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), platinum (Pt), iridium (Ir), ruthenium (Ru), aluminum (Al), copper (Cu), gold (Au), tungsten (W), etc. The material of the upper electrode 116 is, for example, titanium nitride or other suitable conductive materials, such as titanium, tantalum, tantalum nitride, platinum, iridium, ruthenium, aluminum, copper, gold, tungsten, etc. The material of the metal oxide layer 114 is, for example, hafnium oxide (HfO2) or other suitable metal oxides, such as nickel oxide (NiO), titanium oxide (TiO), zinc oxide (ZnO), zirconium oxide (ZrO), tantalum oxide (TaO) or other transition metal oxides (TMO), but is not limited thereto. In addition, due to the process, the metal oxide layer 114 may extend to both sides of the upper electrode 116 and directly contact the spacer 104, so the metal oxide layer 114 is U-shaped. As for the dual-damascene structure 102, it generally includes a through hole 118 and a wire 120 disposed on the through hole 118, wherein the through hole 118 is connected to the metal layer 108b to achieve electrical connection. In the first embodiment, the top 120a of the wire 120 is coplanar with the top 116a of the upper electrode 116 in the RRAM element 100, so the wire 120 and the upper electrode 116 can be obtained by the same planarization process, which can integrate the process of the RRAM element 100 and the dual-damascene structure 102. In one embodiment, the bottom surface 112a of the lower electrode 112 is coplanar with the bottom 102a of the dual damascene structure 102. The RRAM element 100 and the dual damascene structure 102 are generally formed in the dielectric layer IMD2. The material of the dielectric layer IMD2 is, for example, but not limited to, USG, PSG, BSG, BPSG, FSG, SiO2, SiOC-based materials, or other suitable ELK or ULK materials. In addition, a barrier layer 122 may be disposed between the dual damascene structure 102 and the dielectric layer IMD2, and a cap layer 124 may be formed on the dielectric layer IMD1, and a cap layer 126 may also be formed on the dielectric layer IMD2. The material of the barrier layer 122 is, for example, but not limited to, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a stack of the foregoing materials. The materials of the capping layer 124 and the capping layer 126 may each independently include silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or nitrogen doped carbon (NDC), but are not limited thereto.

[0055] Since the operation of the RRAM device 100 is critical to the thickness of the metal oxide layer 114, as long as the thickness of the metal oxide layer 114 is controlled within a desired range, the size (eg, thickness) of the upper electrode 116 and the lower electrode 112 can be adjusted. Figure 1 In one embodiment, the top electrode 116 and the bottom electrode 112 having similar thicknesses may be replaced with a thicker bottom electrode 112 and a thinner top electrode 116; or a thinner bottom electrode 112 and a thicker top electrode 116. In one embodiment, the top 104a of the spacer 104 may also be coplanar with the top 116a of the top electrode 116 of the RRAM element 100. In one embodiment, the top 104a of the spacer 104 may be coplanar with the top 120a of the conductive line 120.

[0056] Please continue to refer to Figure 1 , the spacer 104 may be rectangular in cross-sectional view; that is, the thickness difference between the upper end and the lower end of the spacer 104 is small, so the upper half of the spacer 104 can have a sufficient thickness to make the effect of preventing oxygen atoms from diffusing more prominent. In one embodiment, the material of the spacer 104 is, for example, silicon nitride or other suitable dielectric materials, such as silicon oxynitride or silicon carbide.

[0057] FIG. 2A to FIG. 2N It is a cross-sectional schematic diagram of a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

[0058] Please refer to Figure 2A , a dielectric layer 206 is formed on the substrate 200 having the metal layer 202. The substrate 200 may include a semiconductor substrate (not shown) and a dielectric layer IMD, a metal layer 202, etc. thereon. The materials of the dielectric layer 206 and the dielectric layer IMD independently include, but are not limited to, USG, PSG, BSG, BPSG, FSG, SiO2, SiOC-based materials, or other suitable ELK or ULK materials. The material of the metal layer 202 is, for example, copper or other suitable metal materials, such as Co, Al, W, Ni, Pt, Ta or Ti. A barrier layer 201 may be formed between the metal layer 202 and the dielectric layer IMD, wherein the material of the barrier layer 201 is, for example, but not limited to, Ti, TiN, Ta, TaN or a stack composed of the foregoing materials. Although Figure 1 Although there is no special indication, it should be known that other metal layers, contact windows and other interconnections may be formed under the dielectric layer IMD; and so on. Figure 2A Although not specifically indicated, it should be known that other metal layers, contact windows and other interconnections may be formed in the dielectric layer IMD. In one embodiment, a cap layer 204 may be formed on the substrate 200 before forming the dielectric layer IMD, wherein the material of the cap layer 204 may include SiN, SiON, SiCN or NDC, but is not limited thereto.

[0059] Next, please refer to Figure 2B , an opening O1 is formed in the dielectric layer 206 by a yellow light process to expose the metal layer 202. The method of forming the opening O1 is, for example, a photolithography etching process, and during the etching process, the cap layer 204 is continuously etched after removing a portion of the dielectric layer 206 until a portion of the metal layer 202 is exposed.

[0060] Afterwards, please refer to Figure 2C In order to form a spacer on the sidewall of the opening O1, the opening O1 may be filled with a nitride layer 208, wherein the material of the nitride layer 208 is, for example, silicon nitride or other suitable dielectric materials, such as silicon nitride oxide or silicon nitride carbide. Moreover, after the nitride layer 208 fills the opening O1, a planarization process may be required to remove the nitride outside the opening O1. Next, another yellow light process is used to form a patterned mask 210 on the dielectric layer 206 and expose a portion of the nitride layer 208. The patterned mask 210 may be a photoresist layer or other material layer having an etching selectivity ratio with the nitride layer 208.

[0061] Then, please refer to Figure 2D ,by Figure 2C The patterned mask 210 in the etching process is used as an etching mask. Figure 2C The exposed portion of the nitride layer 208 is removed until the metal layer 202 is exposed and a narrower opening O2 is formed in the original opening O1. The patterned mask 210 is then removed. The spacer 208' formed according to the aforementioned steps is roughly rectangular in shape in the cross-sectional view; that is, the thickness difference between the upper end and the lower end of the spacer 208' is small, and in the cross-sectional view, the thickness of the left spacer 208' obtained after the above two yellow light processes may be different from the thickness of the right spacer 208', but it does not affect the function of the spacer 208' itself as a protective layer. In another embodiment, the spacer 208' can also be made by a general spacer process, for example, first depositing a nitride layer conformally on the inner surface of the opening O1 and then etching back until the metal layer 202 is exposed.

[0062] Next, please refer to Figure 2E In order to form a lower electrode at the bottom of the opening O2, the opening may be filled with a conductive layer 212. The conductive layer 212 may be formed by, for example, evaporation or other suitable deposition methods, and the conductive layer 212 may be made of, for example, Ti or other suitable conductive materials, such as Ta, TiN, TaN, Pt, Ir, Ru, Al, Cu, Au, W, etc.

[0063] Afterwards, please refer to Figure 2F , planarize and etch back Figure 2EAfter the conductive layer 212 in the back etching is formed, the bottom electrode 212' can be obtained, wherein the etchant used for the back etching is, for example, sulfuric acid. Since the operation of the RRAM element is critical to the thickness of the metal oxide layer, the thickness of the bottom electrode 212' can be adjusted, for example, Figure 2F To be thicker or thinner.

[0064] Then, please refer to Figure 2G , a metal oxide layer 214 is conformally formed on the lower electrode 212', wherein the material of the metal oxide layer 214 is, for example, HfO2 or other suitable metal oxides, such as nickel oxide, titanium oxide, zinc oxide, zirconium oxide, tantalum oxide or other transition metal oxides (TMO), but not limited thereto. Then, an upper electrode 216 is formed on the metal oxide layer 214 and fills the opening O2, wherein the material of the upper electrode 216 is, for example, titanium nitride or other suitable conductive materials, such as titanium, tantalum, tantalum nitride, platinum, iridium, ruthenium, aluminum, copper, gold, tungsten, etc. When the upper electrode 216 is formed, an excess portion 218 is formed above the dielectric layer 206 outside the opening O2, and this excess portion 218 may also include the metal oxide layer 214, wherein the thickness of the excess portion 218 may be

[0065] Next, please refer to Figure 2H In order to form a dual damascene hole in the dielectric layer 206 next to the opening O2, the patterning Figure 2G The excess portion 218 in the dielectric layer 206 is removed to form a first patterned mask 218' above the dielectric layer 206 and expose a location where a dual damascene hole is to be formed.

[0066] Then, please refer to Fig.2I , the dielectric layer 206 is etched using the first patterned mask 218' as an etching mask to form a trench 220 in the dielectric layer 206, and the trench 220 can extend into the page. Then, a second patterned mask 222 is formed in the trench 220 to expose a portion of the dielectric layer 206, and the dielectric layer 206 is etched using the second patterned mask 222 as an etching mask to form a hole 224 in the dielectric layer 206 below the trench 220. The second patterned mask 222 will also cover the rest of the area, so that the etching of the hole 224 will not affect the surrounding structure.

[0067] Next, please refer to Figure 2J ,Will Fig.2I After the second patterned mask 222 is removed, a barrier layer 228 may be formed on the inner surface of the dual damascene hole 226 formed by the trench 220 and the hole 224. The material of the barrier layer 228 may be, for example but not limited to, Ti, TiN, Ta, TaN or a stack of the foregoing materials.

[0068] Then, please refer to Figure 2K, the dual damascene hole 226 is filled with a conductive material 230, wherein the conductive material 230 is, for example, but not limited to, a group consisting of Cu, Co, Al, W, Ni, Pt, Ta, Ti, TiAl, CoWP, etc., but not limited thereto.

[0069] Next, please refer to Figure 2L , a planarization process (such as a CMP process) is performed to simultaneously remove a portion of the conductive material and a portion of the upper electrode 216 to obtain a dual damascene structure 230' and a RRAM element 232 located next to the dual damascene structure 230', wherein the RRAM element 232 includes the lower electrode 212', the metal oxide layer 214, and the upper electrode 216. Since the removed portions include different materials, the planarization process may require segmented grinding using different grinding materials.

[0070] Next, please refer to Figure 2M , a connection structure may be further formed on the completed semiconductor device, such as forming a cap layer 234 first, covering the dielectric layer 206, the dual damascene structure 230', the upper electrode 216 and the spacer 208', etc. The material of the cap layer 234 may refer to the cap layer 204, so it is not repeated here.

[0071] Afterwards, please refer to Figure 2N After the dielectric layer 236 is formed, a dual damascene structure 238a and a dual damascene structure 238b may be formed therein, and a barrier layer 240 may be formed between the dual damascene structure 238a and the dielectric layer 236, and a barrier layer 240 may be formed between the dual damascene structure 238b and the dielectric layer 236. The formation method of the dielectric layer 236, the dual damascene structure 238a and the dual damascene structure 238b may refer to Figure 2H to Figure 2L The manufacturing process of the dual damascene structure 230' is not described in detail. The dual damascene structure 238a is connected to the upper electrode 216, and the dual damascene structure 238b is connected to the dual damascene structure 230'.

[0072] In the present embodiment, the opening O1 is formed first, and then the spacer 208' is formed on the sidewall of the opening O1, and then the RRAM element 232 is deposited in the opening O2, and then a series of planarization processes are performed. Therefore, at least one photomask process can be omitted. In addition, before the planarization process of the RRAM element 232, the dual-damascene structure 230' is formed, and then the top of the dual-damascene structure 230' can be planarized while the planarization process is performed on the RRAM element 232, thereby achieving process integration of the RRAM element 232 and the dual-damascene structure 230'.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor element, characterized in that: include: Resistive memory element; A dual damascene structure is disposed next to the resistive memory element; as well as A spacer is disposed on the sidewall of the resistive memory element, wherein The resistive memory element comprises: Lower electrode; a metal oxide layer disposed on the lower electrode; and an upper electrode, disposed on the metal oxide layer; The dual mosaic structure comprises: through holes; and A conductive line is disposed on the through hole, wherein a top of the conductive line is coplanar with a top of the upper electrode of the resistive memory element.

2. The semiconductor device according to claim 1, characterized in that A top of the spacer is coplanar with a top of the upper electrode of the resistive memory element.

3. The semiconductor device according to claim 1, wherein: The top of the spacer is coplanar with the top of the conductive line.

4. The semiconductor device according to claim 1, wherein: In the cross-sectional view, the spacer has a rectangular shape.

5. The semiconductor device according to claim 1, wherein: In the cross-sectional view, the thickness of the spacer located on the right side of the resistive memory element is different from the thickness of the spacer located on the left side of the resistive memory element.

6. The semiconductor device according to claim 1, wherein: The metal oxide layer is U-shaped.

7. The semiconductor device according to claim 1, wherein: The bottom surface of the lower electrode is coplanar with the bottom of the dual damascene structure.

8. The semiconductor device according to claim 1, wherein: The material of the lower electrode includes titanium, the material of the metal oxide layer includes hafnium oxide, and the material of the upper electrode includes titanium nitride.

9. A method for manufacturing a semiconductor element, characterized in that: include: forming a dielectric layer on the substrate having the metal layer; forming an opening in the dielectric layer to expose the metal layer; forming a spacer on a sidewall of the opening; forming a lower electrode at the bottom of the opening; conformally forming a metal oxide layer on the lower electrode; forming an upper electrode on the metal oxide layer and filling the opening; forming a dual damascene hole having a hole and a trench in the dielectric layer adjacent to the opening; filling the dual damascene holes with a conductive material; as well as A planarization process is performed to simultaneously remove a portion of the conductive material and a portion of the upper electrode.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The method of forming the spacer comprises: filling the opening with a nitride layer; forming a patterned mask on the dielectric layer to expose a portion of the nitride layer; and The patterned mask is used as an etching mask to etch the exposed portion of the nitride layer until the metal layer is exposed.

11. The method for manufacturing a semiconductor device according to claim 9, wherein: The method of forming the spacer comprises: conformally depositing a nitride layer on an inner surface of the opening; and The nitride layer is etched back until the metal layer is exposed.

12. The method for manufacturing a semiconductor device according to claim 9, wherein: The step of forming the upper electrode includes having a redundant portion above the dielectric layer outside the opening, and the method of forming the dual damascene hole includes: patterning the excess portion above the dielectric layer to form a first patterned mask; etching the dielectric layer using the first patterned mask as an etching mask to form the trench in the dielectric layer; forming a second patterned mask in the trench to expose a portion of the dielectric layer; and The dielectric layer is etched using the second patterned mask as an etching mask to form the hole in the dielectric layer below the trench.

13. The method for manufacturing a semiconductor device according to claim 9, wherein: The method of forming the lower electrode comprises: filling the opening with a conductive layer; planarizing the conductive layer; and The conductive layer is etched back.

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