Memory preparation method, memory and electronic equipment

Abstract

The invention discloses a preparation method of a memory, the memory and electronic equipment. The preparation method of the memory comprises the following steps: providing a substrate on which a plurality of memory units arranged at intervals are formed; an interlayer dielectric layer with a double-layer structure is formed on the substrate, the interlayer dielectric layer with the double-layer structure comprises a first interlayer dielectric layer and a second interlayer dielectric layer, the first interlayer dielectric layer completely covers the storage unit on the substrate, and the second interlayer dielectric layer completely covers the storage unit on the substrate; the filling height of the first interlayer dielectric layer located in the area between every two storage units is not lower than the height of the storage units, a second interlayer dielectric layer is formed on the first interlayer dielectric layer, and the filling capacity of the first interlayer dielectric layer is superior to that of the second interlayer dielectric layer. Through the scheme disclosed by the invention, air gaps can be prevented from being formed between the storage units in the preparation process of the memory, and meanwhile, the influence of the interlayer dielectric layer on the RC delay problem is reduced, so that the quality and the performance of the manufactured memory are improved.

Description

Technical Field

[0001] The present disclosure generally relates to the field of memory technology, and more specifically, to a method for preparing a memory, a memory, and an electronic device. Background Art

[0002] At present, some new types of memory on the market (such as resistive random access memory RRAM, etc.) will integrate the memory cell into the logic back-end process during the preparation process, and will fill the metal interlayer dielectric after the memory cell process is completed. However, the existing metal interlayer dielectric filling process will cause air gaps (i.e., voids) between the memory cells. The presence of these voids may cause damage to the memory cells in the subsequent process. In addition, the presence of voids will also cause leakage between the subsequent two metal layers.

[0003] In view of this, there is an urgent need to provide a memory preparation solution to effectively solve the problem of gaps between memory cells during the interlayer dielectric filling process. Summary of the invention

[0004] In order to at least solve one or more of the technical problems mentioned above, the present disclosure proposes a preparation method for a memory in multiple aspects.

[0005] In a first aspect, the present disclosure provides a method for preparing a memory, comprising: providing a substrate on which a plurality of memory cells arranged at intervals are formed; and forming an interlayer dielectric layer including a double-layer structure on the substrate, wherein the interlayer dielectric layer of the double-layer structure includes a first interlayer dielectric layer and a second interlayer dielectric layer, the first interlayer dielectric layer completely covers the memory cells on the substrate, and the filling height of the first interlayer dielectric layer located in the area between every two of the memory cells is not less than the height of the memory cells, the second interlayer dielectric layer is formed on the first interlayer dielectric layer, and the filling capacity of the first interlayer dielectric layer is better than that of the second interlayer dielectric layer.

[0006] In some embodiments, forming a double-layer interlayer dielectric layer on the substrate includes: forming a first interlayer dielectric layer on the substrate using a filling material with strong filling ability so that the first interlayer dielectric layer completely covers the storage unit on the substrate; and / or forming a second interlayer dielectric layer on the first interlayer dielectric layer using a filling material including a low dielectric constant.

[0007] In some embodiments, forming a first interlayer dielectric layer on the substrate using a filling material with strong filling ability so that the first interlayer dielectric layer completely covers the storage units on the substrate includes: filling the substrate with a filling material with strong filling ability to form the first interlayer dielectric layer; and planarizing the first interlayer dielectric layer so that the filling height of the first interlayer dielectric layer located in the area between every two of the storage units is not lower than the height of the storage units.

[0008] In some embodiments, planarizing the first interlayer dielectric layer includes: planarizing the first interlayer dielectric layer using a chemical mechanical planarization process.

[0009] In some embodiments, a filling height of the first interlayer dielectric layer located between every two of the memory cells is flush with a height of the memory cells.

[0010] In some embodiments, forming a first interlayer dielectric layer on the substrate using a filling material with strong filling ability so that the first interlayer dielectric layer completely covers the storage unit on the substrate includes: depositing a TEOS film on the substrate using a chemical vapor deposition process to obtain the first interlayer dielectric layer.

[0011] In some embodiments, forming the second interlayer dielectric layer on the first interlayer dielectric layer using a filling material including a low dielectric constant includes: depositing a black diamond film on the first interlayer dielectric layer using a chemical vapor deposition process to obtain the second interlayer dielectric layer.

[0012] In some embodiments, a distance between every two of the storage units is smaller than a threshold.

[0013] In some embodiments, the memory cell includes any one of a memory cell of a resistive random access memory, a memory cell of a phase change random access memory, a memory cell of a ferroelectric random access memory, or a memory cell of a magnetic random access memory.

[0014] In a second aspect, the present disclosure provides a memory, which is prepared by using the memory preparation method as described in the first aspect.

[0015] In a third aspect, the present disclosure provides a memory device, comprising: a substrate, on which a plurality of spaced-apart memory cells and an interlayer dielectric comprising a double-layer structure are formed; wherein the interlayer dielectric layer of the double-layer structure comprises a first interlayer dielectric layer and a second interlayer dielectric layer, wherein the first interlayer dielectric layer completely covers the memory cells on the substrate, and a filling height of the first interlayer dielectric layer located in an area between every two of the memory cells is not less than a height of the memory cells, the second interlayer dielectric layer is formed on the first interlayer dielectric layer, and a filling capacity of the first interlayer dielectric layer is better than that of the second interlayer dielectric layer.

[0016] In a fourth aspect, the present disclosure provides an electronic device, comprising: the memory as described in the second aspect or the memory as described in the third aspect.

[0017] Through the preparation method of the memory provided above, the disclosed embodiment forms a double-layer interlayer dielectric layer on the substrate prepared with the memory cell, so as to completely fill and wrap the memory cell and fill the area between the memory cells through the first interlayer dielectric layer with better filling ability, thereby avoiding the formation of air gaps between the memory cells, and at the same time using a material with a low dielectric constant such as BD as the second interlayer dielectric layer, thereby reducing the comprehensive dielectric constant of the interlayer dielectric layer, and avoiding the RC delay problem in the subsequent logic circuit due to the excessively high dielectric constant. Therefore, the disclosed solution can avoid the formation of air gaps between the memory cells during the preparation process of the memory, while taking into account the reduction of the influence of the interlayer dielectric layer on the RC delay problem, thereby improving the quality and performance of the manufactured memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] By reading the detailed description below with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0019] Figure 1 A cross-sectional schematic diagram of a memory in the related art is shown;

[0020] Figure 2 A schematic diagram showing a process of a method for preparing a memory according to an embodiment of the present disclosure;

[0021] Figure 3 A schematic diagram showing a flow chart of a method for preparing a memory according to another embodiment of the present disclosure; and

[0022] Figure 4a to Figure 4d A cross-sectional schematic diagram of a memory during an interlayer dielectric layer filling process according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0024] It should be understood that the terms "include" and "comprising" used in the specification and claims of the present disclosure indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0025] It should also be understood that the terms used in this disclosure are only for the purpose of describing specific embodiments and are not intended to limit the disclosure. As used in this disclosure and claims, the singular forms of "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" used in this disclosure and claims refers to any combination of one or more of the associated listed items and all possible combinations, including these combinations.

[0026] As used in this specification and claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0027] Exemplary application scenarios

[0028] As described in the background technology above, the existing filling process of metal interlayer dielectrics will cause air gaps (i.e., voids) between storage cells. The presence of these voids may cause damage to the storage cells in subsequent process steps and even cause leakage between subsequent two metal layers.

[0029] In this regard, the inventors have found through research that in the relevant interlayer dielectric filling process, the metal interlayer dielectric layer is required to use low dielectric constant materials, and the current mainstream low dielectric constant materials have weak filling capabilities. Usually, filling materials such as black diamond (BD) film are used to form the interlayer dielectric layer, but this BD film is suitable for filling on a flat structure. Figure 1As shown, in the preparation process of new memory 100 such as RRAM, the memory cell 101 is integrated in the logic back-end process. After the memory cell 101 is integrated, there is a certain distance between the memory cells 101, making the overall structure uneven. At this time, if the BD film 102 is continued to be used to fill the interlayer dielectric, the above-mentioned gap 103 is easily formed.

[0030] In this regard, if a filling material with good filling ability is simply used to replace the BD film, although the generation of air gaps can be avoided, the filling material with good filling ability is more likely to cause RC delay problems in the logic circuit than the filling material with weak filling ability. In order to overcome the problems such as RC delay, the relevant technology adopts the method of first depositing a dielectric layer with strong filling ability, and then depositing a Low K material with weaker filling ability as the second dielectric layer. In this technology, the first dielectric layer is thinner, and even after the first dielectric layer is laid, there is still a recessed area between the storage cells. Using a weaker Low K material to continue filling on this uneven structure will form a gap or void, so as to use the gap to reduce the problem of RC delay. However, as the process is further miniaturized, the spacing between the storage cells is reduced, and the morphology and size of the voids between the storage cells are difficult to control. At this time, the voids are very likely to connect with the metal trench above the storage cell, resulting in poor copper filling of the metal trench. In addition, the voids appear at the TE via above the storage cell, which is also very likely to cause the connection between the TE vias above the two adjacent storage cells, resulting in poor copper filling.

[0031] In order to solve the problem in the above scenario, the inventor proposed a preparation scheme for a memory, in which a first interlayer dielectric layer with good filling ability is used to completely fill and wrap the storage unit and fill the area between the storage units to avoid the formation of air gaps between the storage units. At the same time, a material with a low dielectric constant such as BD is used as the second interlayer dielectric layer, thereby reducing the comprehensive dielectric constant of the interlayer dielectric layer and avoiding RC delay problems in subsequent logic circuits due to excessively high dielectric constants.

[0032] In addition, it should be understood that in the scheme disclosed herein, the strength of the filling capacity of the material can be distinguished by the specific filling performance of the material. Usually, the index of strong filling capacity is characterized by uniform filling and no pores or defects. Among them, uniform filling means that during the preparation process, the material can be evenly filled into the designed grooves, holes or small channels, and there is no or less occurrence of material failure to fully cover. No pores or defects means that there are no or less pores, interlayers or other defects. The index of weak or poor filling capacity is characterized by uneven filling and pores and defects. Among them, uneven filling refers to the uneven filling of materials in complex microstructures, which may cause some areas to have too much material (causing short circuits), or some areas to be unfilled (causing open circuits or poor connections). Pores and defects refer to the fact that insufficient filling will lead to the formation of pores, interlayers, defects or unfilled gaps in the grooves. These gaps will affect the flow of current, resulting in increased resistance and may even cause electrical open circuits.

[0033] Furthermore, in addition to using specific filling performance to distinguish the strength of filling ability, the strength of step coverage can also be used to characterize the strength of material filling ability. Specifically, filling ability can be understood as step coverage. The step coverage corresponds to a fixed calculation formula: step coverage = T top / T bottom. Among them, T top is the deposition thickness at the upper surface of the groove or hole, and T bottom is the deposition thickness at the bottom of the groove or hole. In the scheme disclosed in the present invention, the strong filling ability can be defined as "1 ≥ step coverage ≥ 0.5", in other words, the value of T top / T bottom needs to be greater than or equal to 0.5, and the maximum value is 1. Among them, the endpoint value "1" means: if the material can completely and evenly cover the entire groove (no "dead corner"), then the step coverage is 1. If the step coverage value of the endpoint value "0.5" is less than 0.5, it is difficult to meet the requirements of the material deposition effect in the disclosed scheme, for example, it will be easier to have gaps or voids or more gaps or voids when filling between storage cells. That is, the strong filling ability in the disclosed solution can be specifically reflected in the step coverage ability value of [0.5, 1].

[0034] The following combination Figure 2 to Figure 4d The scheme of the present disclosure is described in detail.

[0035] Figure 2A schematic flow chart of a method 200 for preparing a memory according to an embodiment of the present disclosure is shown. It should be noted that the memory in the scheme of the present disclosure may include a resistive random access memory (such as RRAM), a phase change random access memory (PCRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory, or other memories with similar preparation process requirements.

[0036] like Figure 2 As shown, at step S201, a substrate having a plurality of memory cells spaced apart thereon may be provided. The memory cells here may include any one of a memory cell of a resistive random access memory, a memory cell of a phase change random access memory, a memory cell of a ferroelectric random access memory, or a memory cell of a magnetic random access memory.

[0037] In the scheme disclosed in the present invention, the memory cell can be prepared by the currently common memory cell preparation process. For example, for a resistive random access memory, the memory cell of the resistive random access memory may include a structure formed by a lower electrode, a resistive switching layer, and an upper electrode in sequence from bottom to top (for example, a trapezoidal or other shaped structure). In some embodiments, the substrate may include a base, a dielectric layer located on the base, and the lower electrode may be filled in the lower electrode through hole formed by the dielectric layer. The resistive switching layer is located between the lower electrode and the upper electrode, and a metal layer is also provided between the lower electrode and the resistive switching layer, and a sidewall protection layer is also formed on the outer side of the trapezoidal structure. The scheme of this implementation does not involve too many improvements to the formation of the memory cell, so how to form the memory cell and the specific materials of each structure in the memory cell will not be described in detail here.

[0038] At step S202, an interlayer dielectric layer including a double-layer structure is formed on the substrate. The interlayer dielectric layer of the double-layer structure may include a first interlayer dielectric layer and a second interlayer dielectric layer, the first interlayer dielectric layer completely covers the storage cells on the substrate, and the filling height of the first interlayer dielectric layer located between every two storage cells is not less than the height of the storage cells, the second interlayer dielectric layer is formed on the first interlayer dielectric layer, and the filling capacity of the first interlayer dielectric layer is better than that of the second interlayer dielectric layer.

[0039] In this embodiment, a first interlayer dielectric layer with good filling capacity is used to completely wrap the storage unit, and the filling height of the first interlayer dielectric layer located in the area between every two storage units is not less than the height of the storage unit. As a result, not only are the storage units completely isolated, but the area between the storage units is also filled with the first interlayer dielectric layer. That is, the obviously uneven positions in the entire structure (storage units and the area between every two storage units) have been effectively covered by the first interlayer dielectric layer, which is conducive to making the upper surface of the entire structure approach a plane. At this time, a second interlayer dielectric layer is formed above the first interlayer dielectric layer. Even if the filling capacity of the second interlayer dielectric layer is poor (for example, a filling material with a low dielectric constant such as BD is used), the entire structure will not form an air gap. In addition, the good filling capacity of the first interlayer dielectric layer also means that its dielectric constant may be relatively high. The disclosed solution adopts an interlayer dielectric layer with a double-layer structure including a first interlayer dielectric layer and a second interlayer dielectric layer, so as to reduce the comprehensive dielectric constant of the interlayer dielectric layer through the second interlayer dielectric layer with a lower dielectric constant, and try to avoid the RC delay problem caused by excessively high dielectric constant in the subsequent logic circuit. Therefore, the solution disclosed in the present invention can avoid the formation of air gaps between memory cells during the memory manufacturing process, while reducing the impact of the interlayer dielectric layer on the RC delay problem, thereby improving the quality and performance of the manufactured memory.

[0040] Figure 3 FIG. 3 is a flow chart of a method 300 for preparing a memory according to another embodiment of the present disclosure. It can be understood that: Figure 3 The preparation method 300 can be understood as Figure 2 Further expansion or supplement of the preparation method 200 in the above. Figure 2 The relevant description also applies to the following.

[0041] like Figure 3 As shown, at step S301, a substrate having a plurality of memory cells spaced apart may be provided. As described above, in this embodiment, the memory cell may be prepared by using a common memory cell preparation process, which will not be described in detail here. In addition, the memory prepared in this embodiment may be a resistive random access memory, a phase change random access memory, a magnetic random access memory, a ferroelectric random access memory, or other memory with a similar process technology.

[0042] The storage unit may be any one of a storage unit of a resistive random access memory, a storage unit of a phase change random access memory, a storage unit of a ferroelectric random access memory, or a storage unit of a magnetic random access memory. In some embodiments, the storage unit may include a structure formed by a lower electrode, a resistive switching layer, and an upper electrode in sequence from bottom to top. In addition, as mentioned above, there is a certain distance between the storage units, and with the process technology requirements, especially some advanced process requirements (such as semiconductor back-end processes such as 28nm / 22nm / 14nm processes), the distance between every two storage units will be smaller. In this embodiment, the distance between every two storage units needs to be less than a threshold value, and the threshold value is specifically set according to the preparation process requirements. In particular, it needs to be set according to some advanced process requirements, for example, the threshold value needs to meet the requirements of the semiconductor back-end processes such as 28nm / 22nm / 14nm for the distance between storage units.

[0043] On the above substrate, an interlayer dielectric layer including a double-layer structure may be formed. The double-layer interlayer dielectric layer specifically includes a first interlayer dielectric layer and a second interlayer dielectric layer. In this embodiment, the double-layer interlayer dielectric layer may be formed through steps S302 to S304.

[0044] In practical applications, a filling material with strong filling ability can be used to form a first interlayer dielectric layer on the substrate so that the first interlayer dielectric layer completely covers the storage unit on the substrate. Specifically, at step S302, a filling material with strong filling ability can be filled on the substrate to form a first interlayer dielectric layer. Among them, the filling material with strong filling ability specifically includes a material with uniform filling and no pores or defects, or a material with a step coverage ability value of [0.5, 1]. For example, a TEOS film is deposited on the substrate using a chemical vapor deposition process to obtain a first interlayer dielectric layer. It should be noted that the specific material of the filling material with strong filling ability is not limited here, and it can be a TEOS film, or a material with better or similar filling ability to the TEOS film, or other materials with strong filling ability. For example, polynitrogen silane (PSZ for short), undoped silicon dioxide (USG for short), phosphate glass (PSG for short), borophosphosilicate glass (BPSG for short) materials. Then, in step S303, the first interlayer dielectric layer may be planarized so that the filling height of the first interlayer dielectric layer in the region between every two memory cells is not lower than the height of the memory cells.

[0045] In this embodiment, the first interlayer dielectric layer may be planarized by processes including but not limited to etching, grinding, etc. Preferably, the first interlayer dielectric layer may be planarized by a chemical mechanical planarization process. The surface of the first interlayer dielectric layer after the chemical mechanical planarization process is relatively flat, which is conducive to the formation of the second interlayer dielectric layer.

[0046] Furthermore, in some embodiments, the filling height of the first interlayer dielectric layer located in the area between every two storage cells is flush with the height of the storage cells. In this implementation scenario, the first interlayer dielectric layer can completely cover or wrap the storage cells and the area between the storage cells, or more space can be reserved to form a second interlayer dielectric layer.

[0047] At step S304, a second interlayer dielectric layer may be formed on the first interlayer dielectric layer using a filling material including a low dielectric constant. In the scheme disclosed herein, the filling material with a low dielectric constant may be understood as a filling material with a dielectric constant lower than 3.0. For example, a black diamond film is deposited on the first interlayer dielectric layer using a chemical vapor deposition process to obtain a second interlayer dielectric layer. It should be noted that the description of the filling material with a low dielectric constant here is only an exemplary description, and the scheme disclosed herein is not limited to using a black diamond film as a filling material with a low dielectric constant, and other materials with a low dielectric constant may also be used as a filling material to form a second interlayer dielectric layer. For example, the filling material with a low dielectric constant may also include materials such as coral, silk, BCB, fox, and MSQ.

[0048] In addition, the scheme disclosed in the present invention does not limit the filling height ratio of the first interlayer dielectric layer and the second interlayer dielectric layer. For example, the filling height of the first interlayer dielectric layer located in the area between every two storage cells can be set to be flush with or equal to the height of the storage cell, and the other remaining space above the first interlayer dielectric layer is used to form the second interlayer dielectric layer. For another example, the filling height of the first interlayer dielectric layer located in the area between every two storage cells can be set to be higher than the height of the storage cell, and the other remaining space above the first interlayer dielectric layer is used to form the second interlayer dielectric layer. In the actual preparation process, the storage cell of the memory specifically needs to be set between two metal layers, so the filling height of the first interlayer dielectric layer and the second interlayer dielectric layer can be specifically set according to the height between the metal layers and the height of the storage cell.

[0049] After the second interlayer dielectric layer is formed, subsequent standard logic processes may be performed to complete the preparation of the entire memory.

[0050] Therefore, in the process of preparing the memory, the solution disclosed in the present invention solves a series of problems caused by the air gap by forming a first interlayer dielectric layer made of materials such as TEOS, and forms a second interlayer dielectric layer by grinding off as much TEOS as possible and depositing a low dielectric constant material of a standard logic process, thereby minimizing the impact of TEOS on RC delay and other problems.

[0051] The following combination Figure 4a to Figure 4d The preparation process of the above memory is further described.

[0052] In this embodiment, it is necessary to first provide a substrate on which a plurality of memory cells arranged at intervals are formed, and then form an interlayer dielectric layer of a double-layer structure on the substrate. The interlayer dielectric layer of the double-layer structure includes a first interlayer dielectric layer and a second interlayer dielectric layer, the first interlayer dielectric layer completely covers the memory cells on the substrate, and the filling height of the first interlayer dielectric layer located between every two memory cells is not less than the height of the memory cells, the second interlayer dielectric layer is formed on the first interlayer dielectric layer, and the filling capacity of the first interlayer dielectric layer is better than that of the second interlayer dielectric layer.

[0053] Specifically, Figure 4a As shown, the memory 400 includes a plurality of memory cells 402 arranged at intervals, and these memory cells 402 are specifically formed on a substrate 401. Among them, the memory cell 402 may specifically include a structure formed by a lower electrode 4021, a resistive layer 4022, and an upper electrode 4023 in sequence from bottom to top. In some embodiments, the substrate 401 may include a base 4011, a dielectric layer 4012 located on the base, and the lower electrode 4021 may be filled in a lower electrode through hole formed by the dielectric layer 4012. The resistive layer 4022 is located between the lower electrode 4021 and the upper electrode 4023, and a metal layer 4024 is also provided between the lower electrode 4021 and the resistive layer 4022, and a sidewall protection layer 4025 is also formed on the outer side of the trapezoidal structure. It should be noted that the specific structural description of the memory cell here is only an exemplary description, and the scheme disclosed herein does not limit the specific structure and specific formation process of the memory cell.

[0054] After the storage unit 402 is prepared, an interlayer dielectric may be filled into the storage unit 402. Figure 4bAs shown, a first interlayer dielectric layer 403 may be formed on a substrate 401 using a filling material with a strong filling ability (such as a TEOS film, etc.), so that the first interlayer dielectric layer 403 completely covers the storage cells 403 on the substrate. In this embodiment, the first interlayer dielectric layer 403 completely covers the storage cells 403 on the substrate, which can be understood as completely wrapping each storage cell 402 and the area between the storage cells 402. Among them, the filling height of the first interlayer dielectric layer 403 located in the area between every two storage cells 402 is not lower than the storage cell 402.

[0055] Then, if Figure 4c As shown, the first interlayer dielectric layer 403 may be planarized to remove the redundant portion. Preferably, the first interlayer dielectric layer 403 located above the top of the memory cell 402 may be completely removed by using a chemical mechanical planarization process, so that the filling height of the first interlayer dielectric layer 403 located between every two memory cells 402 is flush with the height of the memory cell 402.

[0056] Then, if Figure 4d As shown, a second interlayer dielectric layer 404 is formed on the first interlayer dielectric layer 403. For example, a filling material with a low dielectric constant (i.e., a low K value) such as a black diamond film can be deposited on the first interlayer dielectric layer 403 by a chemical vapor deposition process to obtain the second interlayer dielectric layer 404. Then, a subsequent standard logic process is performed to complete the preparation of the memory 400.

[0057] Through the preparation process of the memory 400, a double-layer interlayer dielectric layer (including a first interlayer dielectric layer 403 and a second interlayer dielectric layer 404) can be formed on the substrate 401 on which the memory cells 402 are prepared, so that the first interlayer dielectric layer 403 with good filling ability can completely fill and wrap the memory cells 402 and fill the area between the memory cells 402, thereby avoiding the formation of air gaps between the memory cells 402. At the same time, a material with a low dielectric constant is used as the second interlayer dielectric layer 404 to reduce the comprehensive dielectric constant of the interlayer dielectric layer, thereby avoiding the RC delay problem of the subsequent logic circuit due to the excessively high dielectric constant. Therefore, when forming the first interlayer dielectric layer 403, since the first interlayer dielectric layer 403 is formed by using a material with a strong filling ability, no air gap will be formed. After the storage cells 402 on the substrate are filled with the first interlayer dielectric layer 403, the filling height of the first interlayer dielectric layer in the area between the storage cells is not less than the height of the storage cells, so that the surface of the entire structure after filling is relatively flat (especially after flattening). At this time, the second interlayer dielectric layer 404 with a low dielectric constant is used to continue filling, and no air gap will be formed. It can be seen that the solution disclosed in the present invention can not only avoid the formation of air gaps between the storage cells 402, but also reduce the influence of the interlayer dielectric layer on the RC delay problem, thereby improving the quality and performance of the manufactured memory 400.

[0058] In addition, the disclosed solution also proposes a memory, which includes a substrate, on which a plurality of memory cells arranged at intervals are formed, and an interlayer dielectric including a double-layer structure. The interlayer dielectric layer of the double-layer structure includes a first interlayer dielectric layer and a second interlayer dielectric layer, the first interlayer dielectric layer completely covers the memory cells on the substrate, and the filling height of the first interlayer dielectric layer located in the area between every two memory cells is not less than the height of the memory cells, the second interlayer dielectric layer is formed on the first interlayer dielectric layer, and the filling capacity of the first interlayer dielectric layer is better than that of the second interlayer dielectric layer.

[0059] The memory here may include resistive random access memory, phase change random access memory, ferroelectric random access memory, magnetic random access memory or other memory with similar preparation process requirements. The structure of the memory includes Figure 4d The same, similar or similar structure shown. In some embodiments, the first interlayer dielectric layer in the memory can be formed by a filling material with strong filling ability. Among them, the filling material with strong filling ability can include TEOS film, PSZ, USG, PSG, BPSG, or other materials with uniform filling and no pores or defects, or other materials with a step coverage ability value of [0.5, 1]. Further, the filling height of the first interlayer dielectric layer located in the area between every two memory cells needs to be flush with the height of the memory cell.

[0060] In addition, the second interlayer dielectric layer in the memory may be formed by a filling material with a low dielectric constant, wherein the filling material with a low dielectric constant may include black diamond film, coral, silk, BCB, fox, MSQ, or other materials with a dielectric constant lower than 3.0.

[0061] In practical applications, the above can be combined with Figure 2 to Figure 4d The preparation method described is used to prepare the above memory. It should be noted that the preparation method of the memory with the above structure is not limited to Figure 2 to Figure 4d The preparation method described can also be used to formulate a specific preparation method according to actual application requirements and design requirements to obtain the memory of the above structure.

[0062] In addition, using Figure 2 to Figure 4d The memory prepared by the preparation method described or the memory having the above structure can be applied to various electronic devices such as computers, mobile phones, cameras, game consoles, cars, wearable devices, etc. The specific category of electronic devices is not limited here, and can include any device with storage requirements.

[0063] Although multiple embodiments of the present disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Those skilled in the art may think of many changes, modifications, and alternatives without departing from the thought and spirit of the present disclosure. It should be understood that in the process of practicing the present disclosure, various alternatives to the embodiments of the present disclosure described herein may be adopted. The attached claims are intended to define the scope of protection of the present disclosure, and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for preparing a memory, characterized in that: include: providing a substrate having a plurality of memory cells spaced apart and formed thereon; as well as An interlayer dielectric layer including a double-layer structure is formed on the substrate, wherein the interlayer dielectric layer of the double-layer structure includes a first interlayer dielectric layer and a second interlayer dielectric layer, the first interlayer dielectric layer completely covers the storage units on the substrate, and the filling height of the first interlayer dielectric layer located in the area between every two of the storage units is not lower than the height of the storage units, the second interlayer dielectric layer is formed on the first interlayer dielectric layer, and the filling capacity of the first interlayer dielectric layer is better than that of the second interlayer dielectric layer.

2. The method for preparing a memory according to claim 1, characterized in that: Forming an interlayer dielectric layer of a double-layer structure on the substrate comprises: A first interlayer dielectric layer is formed on the substrate using a filling material with strong filling ability so that the first interlayer dielectric layer completely covers the storage unit on the substrate; and / or a second interlayer dielectric layer is formed on the first interlayer dielectric layer using a filling material including a low dielectric constant.

3. The method for preparing a memory according to claim 2, characterized in that: Forming a first interlayer dielectric layer on the substrate using a filling material with strong filling ability so that the first interlayer dielectric layer completely covers the storage unit on the substrate comprises: Filling the substrate with a filling material having a strong filling ability to form the first interlayer dielectric layer; The first interlayer dielectric layer is planarized so that a filling height of the first interlayer dielectric layer located between every two of the memory cells is not lower than a height of the memory cells.

4. The method for preparing a memory according to claim 3, characterized in that: The planarizing process of the first interlayer dielectric layer includes: The first interlayer dielectric layer is planarized by using a chemical mechanical planarization process.

5. The method for preparing a memory according to claim 1, characterized in that: The filling height of the first interlayer dielectric layer located in the area between every two of the memory cells is flush with the height of the memory cells.

6. The method for preparing a memory according to claim 2, characterized in that: Forming a first interlayer dielectric layer on the substrate using a filling material with strong filling ability so that the first interlayer dielectric layer completely covers the storage unit on the substrate comprises: A TEOS film is deposited on the substrate by using a chemical vapor deposition process to obtain the first interlayer dielectric layer.

7. The method for preparing a memory according to claim 2, characterized in that: Forming a second interlayer dielectric layer on the first interlayer dielectric layer using a filling material having a low dielectric constant comprises: A black diamond film is deposited on the first interlayer dielectric layer by using a chemical vapor deposition process to obtain the second interlayer dielectric layer.

8. The method for preparing a memory according to any one of claims 1 to 7, characterized in that: The distance between every two of the storage units is smaller than a threshold.

9. The method for preparing a memory according to any one of claims 1 to 7, characterized in that: The storage unit includes any one of a storage unit of a resistive random access memory, a storage unit of a phase change random access memory, a storage unit of a ferroelectric random access memory or a storage unit of a magnetic random access memory.

10. A memory, characterized in that: The memory is prepared by the memory preparation method according to any one of claims 1 to 9.

11. A memory, characterized in that: include: A substrate having a plurality of memory cells spaced apart and an interlayer dielectric having a double-layer structure formed thereon; Among them, the interlayer dielectric layer of the double-layer structure includes a first interlayer dielectric layer and a second interlayer dielectric layer, the first interlayer dielectric layer completely covers the storage unit on the substrate, and the filling height of the first interlayer dielectric layer located in the area between every two of the storage units is not lower than the height of the storage unit, the second interlayer dielectric layer is formed on the first interlayer dielectric layer, and the filling capacity of the first interlayer dielectric layer is better than that of the second interlayer dielectric layer.

12. An electronic device, characterized in that: include: The memory as claimed in claim 10 or the memory as claimed in claim 11.

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