Resistor and preparation method thereof, integrated circuit and electronic equipment

Abstract

The invention provides a resistor and a preparation method thereof, an integrated circuit and electronic equipment, relates to the technical field of semiconductor chips, and aims to solve the problem that the size of the resistor is increased when the resistance of the resistor is increased. The integrated circuit comprises a substrate, a channel layer and a barrier layer which are stacked, the integrated circuit is provided with a first device region and a second device region which are arranged at intervals; the integrated circuit further comprises a resistor located in the first device region and a transistor located in the second device region. The resistor includes: a conductive channel; the integrated circuit further comprises a P-type GaN layer located on the side, away from the substrate, of the barrier layer. The P-type GaN layer comprises a first part located in the first device region and a second part located in the second device region; the first part and the conductive channel are overlapped in a first direction, and the first direction is vertical to the substrate; wherein the thickness of the first part is smaller than that of the second part. The resistor is applied to the electronic equipment and is used for providing resistance.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a resistor and a preparation method thereof, an integrated circuit, and an electronic device. Background Art

[0002] Gallium nitride (GaN) is a semiconductor material with a high bandgap width, which shows excellent performance in the field of high-frequency and high-power electronic devices. Compared with traditional silicon (Si) materials, GaN has higher electron mobility and breakdown electric field strength, which makes it very suitable for high-frequency applications. However, the parasitic inductance in the interconnect bonding wires and PCB (Printed Circuit Board) traces in GaN packaged devices can cause voltage spikes / oscillations at high frequencies, leading to various reliability issues, which has become a bottleneck for the development of high-frequency application potential of GaN devices.

[0003] In some examples, by integrating the gate drive circuit with the power switch on a monolithic chip, the parasitic inductance between the gate driver and the power device can be reduced, thereby obtaining a clearer gate drive signal and a more robust switching characteristic. Monolithic integrated component modules include, for example, GaN power switch devices, low-voltage GaN devices, diodes, capacitors, and resistors, and various functional modules are built based on these components to make the system design more compact.

[0004] In order to achieve more cost-effective GaN power ICs (Integeral Cirtcuit, integrated circuits), it is of great significance to promote the development of high integration of GaN power ICs and reduce the size and process complexity of semiconductor devices. Summary of the invention

[0005] Embodiments of the present disclosure provide a resistor and a method for manufacturing the same, an integrated circuit, and an electronic device, aiming to provide a resistor with high square resistance and adjustable square resistance, while reducing the size of the resistor and the size of the integrated circuit including the resistor.

[0006] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0007] On the one hand, an integrated circuit is provided, which includes: a substrate and a channel layer and a barrier layer stacked on one side of the substrate; the integrated circuit has a first device region and a second device region that are spaced apart; the integrated circuit also includes: a resistor located in the first device region and a transistor located in the second device region; the resistor includes: a first electrode and a second electrode that are spaced apart and located on a side of the channel layer away from the substrate, and a conductive channel that electrically connects the first electrode and the second electrode; the integrated circuit also includes: a P-type GaN layer located on a side of the barrier layer away from the substrate; the P-type GaN layer includes: a first portion located in the first device region and a second portion located in the second device region; the first portion and the conductive channel overlap in a first direction, and the first direction is perpendicular to the substrate; wherein the thickness of the first portion is less than the thickness of the second portion.

[0008] The integrated circuit provided by the above-mentioned embodiments of the present disclosure, by setting a P-type GaN layer including a first part and a second part with different thicknesses, the thickness of the first part is less than the thickness of the second part, the first part can consume the 2DEG in the conductive channel and the 2DEG in the conductive channel is not exhausted to obtain a resistor with a larger square resistance, and the square resistance of the resistor can be adjusted by adjusting the thickness of the first part; compared with the increase of the resistance of the resistor by extending the length of the conductive channel provided in some embodiments, extending the length of the conductive channel will increase the size of the resistor, the above-mentioned embodiments of the present disclosure achieve the purpose of increasing the square resistance of the resistor through the setting of the first part, and the size of the resistor can be relatively small, thereby obtaining a resistor with high square resistance and adjustable square resistance and an integrated circuit including the resistor.

[0009] In some embodiments, the ratio of the thickness of the first portion to the thickness of the second portion ranges from 1% to 40%.

[0010] In some embodiments, the thickness of the first portion ranges from 1 nm to 40 nm.

[0011] In some embodiments, the first portion has a rectangular shape in an orthographic projection onto the substrate.

[0012] In some embodiments, one end of the first portion along the second direction contacts the first pole, and the other end of the first portion along the second direction contacts the second pole; wherein the second direction is parallel to the substrate and parallel to the direction in which the first pole and the second pole are arranged.

[0013] In some embodiments, the first portion includes: a first sub-portion and a second sub-portion, the first sub-portion and the second sub-portion are arranged in a direction parallel to the substrate; wherein a thickness of the first sub-portion is smaller than a thickness of the second sub-portion.

[0014] In some embodiments, one end of the first portion along the second direction contacts one of the first pole and the second pole, and the other end of the first portion along the second direction is spaced apart from the other of the first pole and the second pole.

[0015] In some embodiments, the integrated circuit also includes: the transistor includes: a third electrode and a fourth electrode located on a side of the channel layer away from the substrate and spaced apart, and a control electrode located between the third electrode and the fourth electrode; the control electrode is located on a side of the second part away from the substrate; wherein the thickness of the second part ranges from 80nm to 100nm.

[0016] In some embodiments, the integrated circuit further includes: an isolation region located between the first device region and the second device region; the isolation region is configured to electrically isolate the first device region from the second device region.

[0017] On the other hand, a resistor is provided, which includes: a substrate and a channel layer and a barrier layer stacked on one side of the substrate; the resistor also includes: a first pole and a second pole spaced apart on a side of the channel layer away from the substrate, and a conductive channel electrically connecting the first pole and the second pole; the resistor also includes: a first part located on a side of the barrier layer away from the substrate, the material of the first part includes P-type GaN; the first part and the conductive channel overlap in a first direction; wherein the thickness of the first part ranges from 1nm to 40nm.

[0018] In some embodiments, the first portion has a rectangular shape in an orthographic projection onto the substrate.

[0019] On the other hand, a method for preparing a resistor is provided, wherein a channel layer is formed on one side of a substrate; a barrier layer is formed on a side of the channel layer away from the substrate; a first electrode and a second electrode are formed on a side of the channel layer away from the substrate, and the first electrode and the second electrode are electrically connected through a conductive channel; a first part is formed on a side of the barrier layer away from the substrate, and a material of the first part includes P-type GaN; the first part and the conductive channel overlap in a first direction, and the first direction is perpendicular to the substrate; and a thickness of the first part ranges from 1 nm to 40 nm.

[0020] In some embodiments, a first portion is formed on a side of a barrier layer away from a substrate, including: forming an initial first portion having a first thickness on a side of the barrier layer away from the substrate; forming a first mask layer on a side of the initial first portion away from the substrate; removing a portion of the first mask layer located in a first device region; the first device region is a region for forming a resistor; removing a portion of the initial first portion away from the substrate to form an initial first portion having a second thickness; forming a second mask layer on a side of the initial first portion having the second thickness away from the substrate; removing a portion of the second mask layer located in the first sub-region, the first device region except for the region where the first portion is pre-formed is the first sub-region; removing a portion of the initial first portion located in the first sub-region to obtain the first portion.

[0021] In some embodiments, the ratio of the second thickness to the first thickness ranges from 1% to 40%.

[0022] In some embodiments, a first portion is formed on a side of a barrier layer away from a substrate, including: forming an initial first portion having a first thickness on a side of the barrier layer away from the substrate; forming a first mask layer on a side of the initial first portion away from the substrate; removing a portion of the first mask layer located in the first sub-region; removing a portion of the initial first portion located in the first sub-region and away from the substrate; removing a portion having a second thickness; removing a remaining portion of the first mask layer; removing a portion of the initial first portion away from the substrate having a third thickness to obtain the first portion; wherein the sum of the third thickness and the second thickness is equal to the first thickness.

[0023] In some embodiments, the ratio of the third thickness to the first thickness ranges from 60% to 99%.

[0024] In some embodiments, the material of the mask layer includes: at least one of silicon oxide and silicon nitride; the mask layer includes: a first mask layer and a second mask layer.

[0025] On the other hand, an electronic device is provided, comprising an integrated circuit and a circuit board according to any one of the above embodiments, wherein the integrated circuit is arranged on the circuit board.

[0026] It can be understood that the beneficial effects that can be achieved by the resistor, the method for preparing the resistor, and the electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the integrated circuit mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required for use in some embodiments of the present disclosure are briefly introduced below.

[0028] Figure 1 The structure of the integrated circuit according to some embodiments of the present disclosure is shown in FIG. Figure 1 ;

[0029] Figure 2 Based on Figure 1 A cross-sectional view of the integrated circuit shown along the section line AA;

[0030] Figure 3 The structure of the integrated circuit according to some embodiments of the present disclosure is shown in FIG. Figure 2 ;

[0031] Figure 4 Based on Figure 3 A cross-sectional view of the integrated circuit shown along the section line BB;

[0032] Figure 5 is a graph showing the relationship between the concentration of the two-dimensional electron gas of the conductive channel and the thickness of the P-type GaN layer according to some embodiments;

[0033] Figure 6The structure of the resistor according to some embodiments of the present disclosure is shown in FIG. Figure 1 ;

[0034] Figure 7 The structure of the resistor according to some embodiments of the present disclosure is shown in FIG. Figure 2 ;

[0035] Figure 8 is a flow chart of a method for preparing a resistor according to some embodiments of the present disclosure;

[0036] Fig. 9 The structures corresponding to the steps of the method for preparing a resistor according to some embodiments of the present disclosure are as follows: Figure 1 ;

[0037] Fig.10 The structures corresponding to the steps of the method for preparing a resistor according to some embodiments of the present disclosure are as follows: Figure 2 ;

[0038] Fig.11 The structures corresponding to the steps of the method for preparing a resistor according to some embodiments of the present disclosure are as follows: Figure 3 ;

[0039] Fig.12 The structures corresponding to the steps of the method for preparing a resistor according to some embodiments of the present disclosure are as follows: Figure 4 ;

[0040] Fig.13 It is a schematic diagram of the structure of an electronic device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0041] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0042] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0043] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0044] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0045] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0046] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0047] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0048] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0049] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0050] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0051] Semiconductor: A semiconductor is a material with electrical conductivity between that of a conductor and an insulator at room temperature; semiconductors include intrinsic semiconductors and impurity semiconductors. A pure semiconductor without impurities and defects, in which the concentration of electrons and holes is equal, is called an intrinsic semiconductor.

[0052] In some examples, such as Figure 1 As shown, an integrated circuit 100 is provided, and the integrated circuit 100 has different device areas. For example, the integrated circuit 100 includes a first device area 11 and a second device area 12; the integrated circuit 100 includes a resistor 10 located in the first device area 11, and the integrated circuit 100 also includes a high electron mobility transistor (HEMT), a diode or a capacitor located in the second device area 12, which is not limited here.

[0053] For example, Figure 1 and Figure 2 As shown, the integrated circuit 100 includes: a substrate 101 , and a channel layer 102 and a barrier layer 103 stacked on one side of the substrate 101 .

[0054] Exemplarily, the material of the substrate 101 includes: silicon, silicon carbide, gallium nitride, sapphire or diamond, etc., which is not limited here.

[0055] Exemplarily, the material of the channel layer 102 includes GaN or unintentionally doped AlN, and the material of the barrier layer 103 includes at least one of AlN and AlGaN. The following description is made by taking the example that the material of the channel layer 102 is GaN and the material of the barrier layer 103 is AlGaN.

[0056] AlGaN / GaN can form a heterojunction. The AlGaN / GaN heterojunction forms a high-density two-dimensional electron gas (2DEG) at the heterojunction interface through spontaneous polarization and piezoelectric polarization effects. This two-dimensional electron gas is spatially separated from ionized impurities to form a resistor 10 with a certain resistance.

[0057] In some examples, such as Figure 1 and Figure 2 As shown, the first device region 11 and the second device region 12 are arranged at intervals, for example, an isolation region 13 is arranged between the first device region 11 and the second device region 12, and the isolation region 13 is configured to electrically isolate the first device region 11 and the second device region 12. The two-dimensional electron gas in the portion of the isolation region 13 at the interface between the channel layer 102 and the barrier layer 103 is depleted, so that the 2DEG of the first device region 11 and the second device region 12 are electrically isolated.

[0058] Exemplarily, ion implantation is performed in the portion of the barrier layer 103 located in the isolation region 13 to deplete the 2DEG at the interface between the channel layer 102 and the barrier layer 103 located in the isolation region 13 , so that the 2DEG of the first device region 11 and the second device region 12 are electrically isolated.

[0059] In some examples, such as Figure 1 and Figure 2 As shown, the resistor 10 includes: a first electrode 104 and a second electrode 105 which are located on a side of the channel layer 102 away from the substrate 101 and are spaced apart from each other, and a conductive channel 106 electrically connects the first electrode 104 and the second electrode.

[0060] Exemplarily, the materials of the first electrode 104 and the second electrode 105 are independently selected from at least one of Ti / Al / Ti / Au, Ti / Al / Ni / Au, Ta / Ti / Ni / Au, Ti / Ag, Ti / Al / Ni / TiN and Ti / Al / Ti / TiN.

[0061] Exemplarily, the conductive channel 106 is formed by a 2DEG at the interface of the channel layer 102 and the barrier layer 103 at the first device region 11, and the conductive channel 106 is electrically connected to the first pole 104 and the second pole 105. The conductive channel 106 has a certain square resistance, for example, by changing the size of the conductive channel 106 to form a resistor 10 with different resistance values. Wherein, square resistance refers to the voltage drop generated by the current density per unit area (i.e., the amount of current per unit area) in the thickness direction of the material. The unit of square resistance is ohm per square (Ω / □). The square resistance of the conductive channel 106 is positively correlated with the resistance value of the resistor 10, that is, the larger the square resistance of the conductive channel 106, the larger the resistance value of the resistor 10.

[0062] For example, Figure 1 As shown, the conductive channel 106 has a width W1 and a length L1, the length L1 of the conductive channel 106 is the extension length of the conductive channel 106, and the width W1 of the conductive channel 106 is the average value of the dimension of the conductive channel 106 in a direction perpendicular to the extension length. The smaller the width W1 of the conductive channel 106, the greater the resistance of the resistor 10, and the longer the length L1 of the conductive channel 106, the greater the resistance of the resistor 10.

[0063] For example, the conductive channel 106 is curved or serpentine, and the length L1 of the conductive channel 106 can be the length of one of the contour lines L2 of the conductive channel 106, or the average length of the two contour lines L2 of the conductive channel 106, or the length L1 of the conductive channel 106 is the length of the line connecting the midpoint of the width W1 of the conductive channel 106 in the extension direction of the conductive channel 106, which is not limited here. For example, in the embodiment of the present disclosure, the length L1 of the conductive channel 106 is the length of the line connecting the midpoint of the width W1 of the conductive channel 106 in the extension direction of the conductive channel 106, and the length L1 of the conductive channel 106 is equal to the length of the line connecting the midpoint N of the width W1 of the conductive channel 106 near the first pole 104 to the midpoint M of the width W1 of the conductive channel 106 near the second pole 105 in the extension direction of the conductive channel 106.

[0064] In order to obtain a resistor 10 with a larger resistance value, on the one hand, the width W1 of the conductive channel 106 can be reduced. However, due to the influence of the process accuracy of forming the conductive channel 106, it is difficult to continue to reduce the width W1 of the conductive channel 106 after it is reduced to a certain value; on the other hand, the length L1 of the conductive channel 106 can be increased. For example, the conductive channel 106 can be formed into a curved shape, and the distance between the first pole 104 and the second pole 105 can be increased to obtain a resistor 10 with a longer length L1 of the conductive channel 106, thereby obtaining a resistor 10 with a larger resistance value.

[0065] However, increasing the length L1 of the conductive channel 106 will increase the area of ​​the integrated circuit 100 , which is not conducive to the preparation of a small-sized integrated circuit 100 .

[0066] Based on this, Figure 3 and Figure 4 As shown, an embodiment of the present disclosure provides an integrated circuit 100, which further includes: a P-type GaN layer 107 located on a side of the barrier layer 103 away from the substrate; the P-type GaN layer 107 includes: a first portion 171 located in the first device region 11 and a second portion 172 located in the second device region 12; the first portion 171 and the conductive channel 106 overlap in a first direction Y, and the first direction Y is perpendicular to the substrate 101, wherein a thickness d1 of the first portion 171 is less than a thickness d2 of the second portion 172, that is, d1 <d2。

[0067] Exemplarily, the P-type GaN layer 107 includes Mg-doped GaN, wherein the doping concentration of Mg is in the range of 1×10 18 cm -3 ~6×10 19 cm -3 Among them, doping concentration refers to the amount of impurities contained in a material per unit volume or unit mass, usually expressed in terms of the number of atoms or ions.

[0068] The provision of the P-type GaN layer 107 can consume the 2DEG in the conductive channel 106. The consumption here can be understood as that the concentration of the 2DEG in the conductive channel 106 is reduced due to the provision of the P-type GaN layer 107. That is, the concentration of the 2DEG in the conductive channel 106 can be adjusted by providing the P-type GaN layer 107 with different thicknesses.

[0069] Exemplarily, the integrated circuit 100 includes a transistor located in the second device area 12, and the transistor includes: a third electrode 121 and a fourth electrode 122 located on a side of the channel layer 102 away from the substrate 101 and spaced apart, and a control electrode 123 located between the third electrode 121 and the fourth electrode 122; the control electrode 123 is located on a side of the second part 172 away from the substrate 101.

[0070] For example, if the transistor is a HEMT, the second portion 172 may deplete the 2DEG in the conductive channel 106 , making the transistor a normally-off transistor.

[0071] Since the thickness d1 of the first portion 171 is less than the thickness d2 of the second portion 172, the first portion 171 can consume the 2DEG in the conductive channel 106, and the 2DEG in the conductive channel 106 is not depleted. Therefore, the provision of the first portion 171 increases the square resistance of the first device region 11, and the first device region 11 can be used to provide a resistor 10 with a higher resistance, thereby obtaining a resistor 10 with a larger resistance value.

[0072] Figure 5 The relationship between the concentration of the two-dimensional electron gas of the conductive channel 106 and the thickness of the P-type GaN layer 107 is shown in a curve, wherein the abscissa represents the thickness of the P-type GaN layer 107 in nm; the ordinate represents the concentration of the 2DEG of the conductive channel 106 in cm -2 .

[0073] For example, Figure 1 and Figure 2 As shown, according to the electrical performance characterization method, it can be tested that the square resistance of the conductive channel 106 with the P-type GaN layer 107 completely etched is about 300Ω / □. In the case where the P-type GaN layer 107 is not provided, to form a resistor 10 with a resistance of 600kΩ, when the width W1 of the conductive channel 106 is 1μm, the required length L1 of the conductive channel 106 is: 600kΩ÷300Ω / □ⅹ1μm=2mm. In the orthographic projection to the substrate 101, the area of ​​the conductive channel 106 is about 2mmⅹ1μm=2000μm. 2 .

[0074] like Figure 3 to Figure 5 As shown in FIG. 1 , the concentration of 2DEG in the conductive channel 106 without the P-type GaN layer 107 is about 8×10 12 cm -2 When the thickness of the P-type GaN layer 107 is 30 nm, the concentration of the 2DEG of the conductive channel 106 is about 0.8 x 10 12 cm -2 According to the square resistance of the conductive channel 106 of the completely etched P-type GaN layer 107 being about 300Ω / □, it can be obtained that the square resistance of the conductive channel 106 is about 3000Ω / □. To form a resistor 10 with a resistance of 600kΩ, when the width W1 of the conductive channel 106 is 1μm, the required length L1 of the conductive channel 106 is: 600kΩ÷3000Ω / □ⅹ1μm=0.2mm. In the orthographic projection onto the substrate 101, the area of ​​the conductive channel 106 is about 0.2mmⅹ1μm=200μm. 2 .

[0075] In summary, the size of the resistor 10 including the P-type GaN layer 107 is reduced by about 90% compared to the resistor 10 without the P-type GaN layer 107. That is, compared to the conductive channel 106 provided in a curved shape, the embodiment of the present disclosure consumes the 2DEG in the conductive channel 106 through the P-type GaN layer 107 having a certain thickness range, thereby obtaining a resistor 10 with a larger square resistance, thereby reducing the size of the resistor 10, so that the size of the integrated circuit 100 including the resistor 10 is reduced.

[0076] Furthermore, the resistor 10 with adjustable square resistance can be obtained by adjusting the thickness d1 of the first portion 171 .

[0077] Exemplarily, when forming the integrated circuit 100, a P-type GaN layer 107 with a thickness of d2 is first formed, and the portion of the P-type GaN layer 107 located in the first device region 11 is thinned to a thickness of d1 to obtain a first portion 171 with a thickness of d1. The formation of the portion of the P-type GaN layer 107 with a thickness of d1 located in the first device region 11 is described with reference to the content of the resistor preparation method and is not described in detail here.

[0078] In some embodiments, Figure 4 As shown, the ratio of the thickness d1 of the first portion 171 to the thickness d2 of the second portion 172 ranges from 1% to 40%.

[0079] Exemplarily, the ratio of the thickness d1 of the first portion 171 to the thickness d2 of the second portion 172 is 1%, 3%, 5%, 10%, 12%, 15%, 18%, 20%, 25%, 30%, 33%, 35%, 38% or 40%, etc., which is not limited here.

[0080] Exemplarily, the thickness d2 of the second portion 172 ranges from 80 nm to 100 nm. For example, the thickness d2 of the second portion 172 is 80 nm, 82 nm, 85 nm, 88 nm, 90 nm, 95 nm or 100 nm, etc., which is not limited here. The thickness d2 of the second portion 172 can be the thickness of the P-type GaN layer 107 grown on the side of the barrier layer 103 away from the substrate 101, and the portion of the P-type GaN layer 107 located in the first device region 11 is thinned to form the first portion 171 having a thickness d1.

[0081] When the thickness of the portion of the P-type GaN layer 107 located in the first device region 11 is thinned to a thickness d1, that is, when the ratio of the thickness d1 of the first portion 171 to the thickness d2 of the second portion 172 is in the range of 1% to 40%, the setting of the first portion 171 can make the resistor 10 have a higher square resistance, facilitating the preparation of a resistor 10 with a larger resistance value and a smaller size, thereby obtaining an integrated circuit 100 with a smaller size.

[0082] In some examples, such as Figure 4 As shown, the thickness d1 of the first portion 171 ranges from 1 nm to 40 nm.

[0083] For example, the thickness d1 of the first portion 171 is 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, or 40 nm, which is not limited here.

[0084] By setting the thickness d1 of the first portion 171 in the range of 1 nm to 40 nm, the resistor 10 can have a higher square resistance, which facilitates the preparation of a resistor 10 with a larger resistance value and a smaller storage capacity, thereby obtaining an integrated circuit 100 with a smaller size.

[0085] In some examples, such as Figure 3 As shown, in the orthographic projection onto the substrate 101 , the first portion 171 is rectangular.

[0086] Exemplarily, the conductive channel 106 of the resistor 10 is rectangular, that is, the conductive channel 106 of the resistor 10 is not bent. Figure 1 Compared with the curved conductive channel 106 shown in the figure, since the embodiment of the present disclosure provides the first portion 171, the rectangular first portion 171 can consume the 2DEG at the interface between the channel layer 102 and the barrier layer 103 located therebelow, thereby making the square resistance of the resistor 10 larger, so as to obtain a resistor 10 with a smaller size.

[0087] In some examples, such as Figure 4 As shown, one end of the first portion 171 along the second direction X contacts the first pole 104, and the other end of the first portion 171 along the second direction X contacts the second pole 105. The second direction X is parallel to the substrate 101 and parallel to the direction in which the first pole 104 and the second pole 105 are arranged.

[0088] Exemplarily, the conductive channel 106 of the resistor 10 is rectangular, and in the orthographic projection onto the substrate 101, the first portion 171 can cover the conductive channel 106 of the resistor 10, so that the first portion 171 can fully adjust the concentration of 2DEG in the conductive channel 106 of the resistor 10 to obtain resistors 10 with different resistance values.

[0089] In some examples, such as Figure 6 As shown, the first portion 171 includes: a first sub-portion 1711 and a second sub-portion 1712 , and the first sub-portion 1711 and the second sub-portion 1712 are arranged in a direction parallel to the substrate 101 ; wherein the thickness d11 of the first sub-portion 1711 is less than the thickness d12 of the second sub-portion 1712 .

[0090] For example, the first sub-portion 1711 and the second sub-portion 1712 may be arranged along the second direction X.

[0091] Exemplarily, the first sub-portion 1711 and the second sub-portion 1712 may be connected to each other. In other examples, the first sub-portion 1711 and the second sub-portion 1712 may be spaced apart.

[0092] By configuring the first portion 171 to include the first sub-portion 1711 and the second sub-portion 1712 , the concentration of the 2DEG in the conductive channel 106 of the resistor 10 can be further adjusted by adjusting the thickness of the first portion 171 to obtain resistors 10 with different resistances.

[0093] In some embodiments, Figure 7 As shown, one end of the first portion 171 along the second direction X contacts one of the first pole 104 and the second pole 105 , and the other end of the first portion 171 along the second direction X is spaced apart from the other of the first pole 104 and the second pole 105 .

[0094] Exemplarily, one end of the first portion 171 along the second direction X contacts the first pole 104 , and the other end of the first portion 171 along the second direction X is spaced apart from the second pole 105 .

[0095] In some other examples, one end of the first portion 171 along the second direction X contacts the second pole 105 , and the other end of the first portion 171 along the second direction X is spaced apart from the first pole 104 .

[0096] In some other examples, one end of the first portion 171 along the second direction X is spaced apart from the first pole 104 , and the other end of the first portion 171 along the second direction X is spaced apart from the second pole 105 .

[0097] By arranging the first portion 171 in different positional relationships with the first electrode 104 and the second electrode 105 , the concentration of the 2DEG in the conductive channel 106 of the resistor 10 can be flexibly adjusted to obtain the resistor 10 with different resistances.

[0098] In some embodiments, Figure 4 As shown, the integrated circuit 100 further includes a buffer layer 108 between the substrate 101 and the channel layer 102. The material of the buffer layer 108 includes: C-doped GaN, unintentionally doped GaN, AlN or AlGaN, etc., which are not limited here. When the material of the buffer layer 108 is C-doped GaN, the concentration range of C is 1x10 19 ~1ⅹ10 20 .

[0099] In some embodiments, a nucleation layer (not shown) is further included between the buffer layer 108 and the substrate 101 . The material of the nucleation layer is, for example, AlN.

[0100] Since the buffer layer 108 and the substrate 101 are made of different materials and usually have different lattice constants and thermal expansion coefficients, if the buffer layer 108 is directly disposed on the substrate 101, cracks may be generated in the buffer layer 108 due to lattice mismatch and thermal mismatch, resulting in a decrease in crystal quality. Therefore, a nucleation layer is provided to effectively avoid the generation of cracks in the buffer layer 108.

[0101] In some embodiments, an insertion layer (not shown) is further included between the channel layer 102 and the barrier layer 103 .

[0102] Exemplarily, the material of the insertion layer includes AlN, and the potential barrier of the insertion layer can be greater than the potential barrier of the barrier layer 103. The provision of the insertion layer can promote the polarization effect between the channel layer 102 and the barrier layer 103, and increase the 2DEG concentration of the heterojunction of the channel layer 102 and the barrier layer 103.

[0103] like Figure 4 As shown, an embodiment of the present disclosure also provides a resistor 10, the resistor 10 includes: a substrate 101 and a channel layer 102 and a barrier layer 103 stacked on one side of the substrate 101; the resistor 10 also includes: a first pole 104 and a second pole 105 spaced apart on a side of the channel layer 102 away from the substrate 101, and a conductive channel 106 electrically connecting the first pole 104 and the second pole 105; the resistor 10 also includes: a first part 171, the material of the first part 171 includes P-type GaN; the first part 171 and the conductive channel 106 overlap in the first direction Y; wherein, the thickness d1 of the first part 171 ranges from 1nm to 40nm.

[0104] Exemplarily, the P-type GaN includes: Mg-doped GaN, wherein the doping concentration of Mg is in the range of 1×10 18 cm -3 ~6×10 19 cm -3 .

[0105] For the introduction of the resistor 10 , please refer to the above content and will not be repeated here.

[0106] The resistor 10 provided in the embodiment of the present disclosure can provide a resistor 10 with a larger resistance and a smaller size by disposing the first portion 171 with a thickness d1 ranging from 1 nm to 40 nm.

[0107] like Figure 4 and Figure 8 As shown, an embodiment of the present disclosure provides a method for preparing a resistor, the method comprising steps: R1 to R4.

[0108] R1. Form a channel layer 102 on one side of the substrate 101.

[0109] Exemplarily, the material of the substrate 101 includes: silicon, silicon carbide, gallium nitride, sapphire or diamond, etc., which is not limited here.

[0110] Exemplarily, the channel layer 102 is formed on one side of the substrate 101 by an epitaxial growth method.

[0111] Exemplarily, when a buffer layer 108 is further disposed on one side of the substrate 101 , the channel layer 102 is formed on a side of the buffer layer 108 away from the substrate 101 .

[0112] R2. Form a barrier layer 103 on a side of the channel layer 102 away from the substrate 101.

[0113] Exemplarily, the material of the barrier layer 103 includes at least one of AlN and AlGaN.

[0114] Exemplarily, the barrier layer 103 is formed on a side of the channel layer 102 away from the substrate 101 by an epitaxial growth method.

[0115] There is a conductive channel 106 at the interface between the channel layer 102 and the barrier layer 103 .

[0116] R3. A first portion 171 is formed on a side of the barrier layer 103 away from the substrate 101. The material of the first portion 171 includes P-type GaN. The first portion 171 overlaps with the conductive channel 106 in the first direction Y. The thickness d1 of the first portion 171 ranges from 1 nm to 40 nm.

[0117] In some examples, such as Figure 3 , Fig. 9 and Fig.10 As shown, the step of forming the first portion 171 on the side of the barrier layer 103 away from the substrate 101 includes: R31-R37.

[0118] R31. Form an initial first portion 17a having a first thickness d3 on a side of the barrier layer 103 away from the substrate 101.

[0119] Exemplarily, the initial first portion 17 a is formed by an epitaxial growth method.

[0120] Exemplarily, the first thickness d3 can be equal to the thickness d2 of the second part 172, that is, P-type GaN is used to form a film layer with a thickness of the first thickness d3, and the portion of the film layer located in the second device region 12 is used to form the second part 172. The thickness d2 of the second part 172 is the thickness of the film layer, and the portion of the film layer located in the first device region 11 is used as the initial first part 17a, and the first part 171 is formed after thinning treatment.

[0121] R32. Form a first mask layer 301 on a side of the initial first portion 17a away from the substrate 101.

[0122] Exemplarily, the first mask layer 301 is formed by an epitaxial growth method.

[0123] Exemplarily, the material of the first mask layer 301 includes at least one of silicon oxide and silicon nitride.

[0124] R33, removing the portion of the first mask layer 301 located in the first device region 11; the first device region 11 is a region where the resistor 10 is formed.

[0125] Exemplarily, the portion of the first mask layer 301 located in the first device region 11 is removed by a dry etching process or a wet etching process.

[0126] R34. Remove the portion of the initial first portion 17a away from the substrate 101 to form the initial first portion 17a having a second thickness d4.

[0127] Exemplarily, a portion of the initial first portion 17 a away from the substrate 101 is removed by a dry etching process to form the initial first portion 17 a having the second thickness d4 .

[0128] Exemplarily, the ratio of the second thickness d4 to the first thickness d3 ranges from 1% to 40%. For example, the ratio of the second thickness d4 to the first thickness d3 is 1%, 6%, 10%, 15%, 20%, 25%, 30%, 35% or 40%, etc., which is not limited here. The second thickness d4 is equal to the thickness d1 of the preformed first portion 171.

[0129] Illustratively, after step R34 , the method further includes removing a portion of the first mask layer 301 located in the second device region 12 .

[0130] R35. Form a second mask layer 302 on a side of the initial first portion 17a away from the substrate 101.

[0131] Exemplarily, the second mask layer 302 is formed by an epitaxial growth method.

[0132] Exemplarily, the material of the second mask layer 302 includes at least one of silicon oxide and silicon nitride.

[0133] R36. Remove the portion of the second mask layer 302 located in the first sub-region S1. The first device region 11 except the region where the first portion 171 is pre-formed is the first sub-region S1.

[0134] Exemplarily, the portion of the second mask layer 302 located in the first sub-region S1 is removed by a dry etching process or a wet etching process.

[0135] R37. Remove the portion of the initial first portion 17a located in the first sub-region S1 to obtain the first portion 171.

[0136] Illustratively, after step R37 , the method further includes: removing the remaining portion of the second mask layer 302 .

[0137] Through the above steps R31 to R37 , the first portion 171 is formed by a secondary growth mask layer method, so as to further form a resistor 10 with relatively large square resistance and relatively small size.

[0138] In other examples, such as Figure 3 , Fig.11 and Fig.12 As shown, the step of forming the first portion 171 on the side of the barrier layer 103 away from the substrate 101 includes: T31-T36.

[0139] T31 . Form an initial first portion 17 a having a first thickness d3 on a side of the barrier layer 103 away from the substrate 101 .

[0140] For the introduction of this step, please refer to the content of step R31, which will not be repeated here.

[0141] T32 . Form a first mask layer 301 on a side of the initial first portion 17 a away from the substrate 101 .

[0142] For the introduction of this step, please refer to the content of step R33, which will not be repeated here.

[0143] T33 , removing the portion of the first mask layer 301 located in the first sub-region S1 .

[0144] Exemplarily, the portion of the first mask layer 301 located in the first sub-region S1 is removed by a dry etching process or a wet etching process.

[0145] T34, removing a portion of the initial first portion 17a located in the first sub-region S1 and away from the substrate 101; the thickness of the removed portion is the second thickness d4.

[0146] Exemplarily, a portion of the initial first portion 17 a located in the first sub-region S1 and away from the substrate 101 is removed by a dry etching process.

[0147] T35 , removing the remaining portion of the first mask layer 301 .

[0148] Exemplarily, the remaining portion of the first mask layer 301 is removed by a dry etching process or a wet etching process.

[0149] T36. Remove the portion of the initial first portion 17a having the third thickness d5 away from the substrate 101 to obtain the first portion 171; wherein the sum of the third thickness d5 and the second thickness d4 is equal to the first thickness d3.

[0150] Exemplarily, a portion of the initial first portion 17 a having the third thickness d5 away from the substrate 101 is removed by a dry etching process.

[0151] Since the sum of the third thickness d5 and the second thickness d4 is equal to the first thickness d3, that is, d3=d4+d5, when the portion of the initial first portion 17a with the third thickness d5 away from the substrate 101 is removed, the portion of the initial first portion 17a located in the first sub-region S1 is completely removed, and the remaining portion of the initial first portion 17a forms the first portion 171 with the second thickness d4.

[0152] Through the above steps T31 to T36, the first portion 171 is formed by using a method of growing a mask layer once, so as to further form a resistor 10 with relatively large square resistance and relatively small size.

[0153] R4. A first electrode 104 and a second electrode 105 are formed on a side of the channel layer 102 away from the substrate 101 , and the first electrode 104 and the second electrode 105 are electrically connected via a conductive channel 106 .

[0154] Exemplarily, an ohmic metal is deposited by a deposition process, and the ohmic metal includes at least one of Ti / Al / Ti / Au, Ti / Al / Ni / Au, Ta / Ti / Ni / Au, Ti / Ag, Ti / Al / Ni / TiN and Ti / Al / Ti / TiN, and then an annealing treatment is performed.

[0155] Further, such as Figure 4 As shown, the method for preparing the resistor further includes: ion implantation, wherein ion implantation is performed in a region where the isolation region 13 is preformed, so as to achieve electrical isolation between the first device region 11 and the second device region 12 .

[0156] Through the above steps R1 to R4, a resistor 10 including a first portion 171 is formed. Since the material of the first portion 171 includes P-type GaN, the first portion 171 consumes the 2DEG in the conductive channel 106, thereby obtaining a resistor 10 with a larger square resistance and reducing the size of the resistor 10.

[0157] The embodiment of the present disclosure also provides an electronic device 1000, such as Fig.13 As shown, the electronic device 1000 includes the integrated circuit 100 provided by any of the above embodiments. The integrated circuit 100 includes the resistor 10 provided by any of the above embodiments.

[0158] The electronic device 1000 further includes a circuit board 200 , and the integrated circuit 100 is disposed on the circuit board 200 .

[0159] like Fig.13As shown, the electronic device 1000 includes the integrated circuit 100 provided in any of the above embodiments. Therefore, the electronic device 1000 provided in the embodiment of the present disclosure has all the beneficial effects of the integrated circuit 100 provided in any of the above embodiments, which will not be described in detail here.

[0160] Exemplarily, the electronic device 1000 is a user device or terminal device of different types such as a computer, a mobile phone, a tablet computer, a wearable device, and a vehicle-mounted device; the electronic device 1000 may also be a network device such as a base station. The embodiment of the present application does not impose any special restrictions on the specific form of the electronic device 1000.

[0161] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. An integrated circuit, characterized in that: include: A substrate and a channel layer and a barrier layer stacked on one side of the substrate; The integrated circuit comprises a first device region and a second device region which are spaced apart from each other; The integrated circuit further comprises: a resistor located in the first device region and a transistor located in the second device region; the resistor comprises: a first electrode and a second electrode located at a side of the channel layer away from the substrate and spaced apart, and a conductive channel electrically connecting the first electrode and the second electrode; The integrated circuit further comprises: a P-type GaN layer located on a side of the barrier layer away from the substrate; the P-type GaN layer comprises: a first portion located in the first device region and a second portion located in the second device region; the first portion and the conductive channel overlap in a first direction, and the first direction is perpendicular to the substrate; Wherein, the thickness of the first portion is smaller than the thickness of the second portion.

2. The integrated circuit according to claim 1, characterized in that The ratio of the thickness of the first portion to the thickness of the second portion is in a range of 1% to 40%.

3. The integrated circuit according to claim 2, characterized in that The thickness of the first portion ranges from 1 nm to 40 nm.

4. The integrated circuit according to claim 1, characterized in that In an orthographic projection onto the substrate, the first portion is rectangular.

5. The integrated circuit according to claim 1, characterized in that One end of the first portion along the second direction contacts the first pole, and the other end of the first portion along the second direction contacts the second pole; The second direction is parallel to the substrate and parallel to the direction in which the first pole and the second pole are arranged.

6. The integrated circuit according to claim 5, characterized in that The first portion includes: a first sub-portion and a second sub-portion, wherein the first sub-portion and the second sub-portion are arranged in a direction parallel to the substrate; wherein the thickness of the first sub-portion is smaller than the thickness of the second sub-portion.

7. The integrated circuit according to claim 1, characterized in that One end of the first portion along the second direction contacts one of the first pole and the second pole, and the other end of the first portion along the second direction is spaced apart from the other of the first pole and the second pole.

8. The integrated circuit according to claim 1, characterized in that The transistor comprises: a third electrode and a fourth electrode which are located at a side of the channel layer away from the substrate and are spaced apart from each other, and a control electrode located between the third electrode and the fourth electrode; the control electrode is located at a side of the second portion away from the substrate; Wherein, the thickness of the second portion ranges from 80nm to 100nm.

9. The integrated circuit according to any one of claims 1 to 8, characterized in that: The integrated circuit further includes: an isolation region located between the first device region and the second device region; the isolation region is configured to electrically isolate the first device region from the second device region.

10. A resistor, characterized in that: include: A substrate and a channel layer and a barrier layer stacked on one side of the substrate; The resistor further comprises: a first electrode and a second electrode spaced apart and arranged on a side of the channel layer away from the substrate, and a conductive channel electrically connecting the first electrode and the second electrode; The resistor further comprises: a first portion located at a side of the barrier layer away from the substrate, wherein the material of the first portion comprises P-type GaN; the first portion and the conductive channel overlap in a first direction; Wherein, the thickness of the first part ranges from 1 nm to 40 nm.

11. The resistor according to claim 10, characterized in that In an orthographic projection onto the substrate, the first portion is rectangular.

12. A method for preparing a resistor, characterized in that: include: forming a channel layer on one side of the substrate; forming a barrier layer on a side of the channel layer away from the substrate; A conductive channel is provided at the interface between the channel layer and the barrier layer; A first portion is formed on a side of the barrier layer away from the substrate, wherein the material of the first portion includes P-type GaN; the first portion and the conductive channel overlap in a first direction, and the first direction is perpendicular to the substrate; and the thickness of the first portion ranges from 1 nm to 40 nm; A first electrode and a second electrode are formed on a side of the channel layer away from the substrate and spaced apart from each other. The first electrode and the second electrode are electrically connected through the conductive channel.

13. The method for preparing a resistor according to claim 12, characterized in that: The step of forming a first portion on a side of the barrier layer away from the substrate comprises: forming an initial first portion having a first thickness on a side of the barrier layer away from the substrate; forming a first mask layer on a side of the initial first portion away from the substrate; removing a portion of the first mask layer located in a first device region; the first device region is a region where a resistor is formed; removing a portion of the initial first portion away from the substrate to form an initial first portion having a second thickness; forming a second mask layer on a side of the initial first portion having the second thickness away from the substrate; The portion of the second mask layer located in the first sub-region is removed, and the first device region except the region where the first portion is pre-formed is the first sub-region; The first portion is obtained by removing a portion of the initial first portion located in the first sub-region.

14. The method for preparing a resistor according to claim 13, characterized in that: The ratio of the second thickness to the first thickness ranges from 1% to 40%.

15. The method for preparing a resistor according to claim 12, characterized in that: The step of forming a first portion on a side of the barrier layer away from the substrate comprises: forming an initial first portion having a first thickness on a side of the barrier layer away from the substrate; forming a first mask layer on a side of the initial first portion away from the substrate; removing the portion of the first mask layer located in the first sub-region; Removing a portion of the initial first portion located in the first sub-region and away from the substrate, the thickness of the removed portion being a second thickness; removing the remaining portion of the first mask layer; A portion of the initial first portion having a third thickness away from the substrate is removed to obtain a first portion; wherein the sum of the third thickness and the second thickness is equal to the first thickness.

16. The method for preparing a resistor according to claim 15, characterized in that: The ratio of the third thickness to the first thickness ranges from 60% to 99%.

17. The method for preparing a resistor according to any one of claims 12 to 16, characterized in that: The material of the mask layer includes: at least one of silicon oxide and silicon nitride; the mask layer includes: a first mask layer and a second mask layer.

18. An electronic device, characterized in that: include: An integrated circuit as claimed in any one of claims 1 to 9; A circuit board, wherein the integrated circuit is arranged on the circuit board.

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