Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and is applied to the technical field of semiconductors. According to the semiconductor device and the manufacturing method thereof, the film layer structure of the lower electrode is arranged to be multiple layers, and the shapes and the heights of the multiple lower electrode layers in the lower electrode are different, so that the semiconductor device with different shapes among the multiple lower electrodes and height differences among the multiple lower electrode layers in the vertical direction is formed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] As various electronic products develop towards miniaturization, the design of semiconductor devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with a recessed gate structure, since it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, it has gradually replaced the dynamic random access memory with only a planar gate structure under the current mainstream development trend. Generally speaking, a dynamic random access memory with a recessed gate structure is composed of a large number of memory cells gathered to form an array area for storing information, and each memory cell can be composed of a transistor component and a capacitor component connected in series to receive voltage information from a word line (WL) and a bit line (BL). In response to product requirements, the density of memory cells in the array area must be continuously improved, resulting in increasing difficulty and complexity in related manufacturing processes and designs. Therefore, the existing technology or structure needs to be further improved to effectively improve the performance and reliability of related memory devices. Summary of the invention

[0003] The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, so as to improve the performance and reliability of the semiconductor device.

[0004] In a first aspect, in order to solve the above technical problems, the present invention provides a semiconductor device, which may at least include:

[0005] substrate;

[0006] A plurality of lower electrodes are arranged on the substrate at intervals, and the lower electrodes include a first lower electrode layer, which is in an asymmetric U-shape and has a bottom that is in direct contact with the substrate;

[0007] A second lower electrode layer, in an asymmetric columnar shape and filled into the first lower electrode layer;

[0008] a dielectric layer, located on the plurality of lower electrodes;

[0009] an upper electrode, located on the dielectric layer;

[0010] The second lower electrode layer in at least one of the lower electrodes has a horizontal extension portion extending in a horizontal direction and covering a portion of the top surface of the first lower electrode layer in the at least one of the lower electrodes.

[0011] Optionally, a top surface of the horizontal extension portion is flush with a top surface of the second lower electrode layer in all the lower electrodes.

[0012] Optionally, the first lower electrode layer in at least one of the lower electrodes has a first side wall and a second side wall relative to each other, the second side wall is located on a side away from the remaining lower electrodes, and the top surface of the first lower electrode layer located on the first side wall is higher than the top surface of the first lower electrode layer located on the second side wall.

[0013] Optionally, a bottom surface of the horizontal extension portion directly contacts a first lower electrode layer located on the second side wall of at least one of the lower electrodes.

[0014] Optionally, the semiconductor device may further include:

[0015] The supporting layer is located on the outer side of the second side wall of the first lower electrode layer in at least one of the lower electrodes.

[0016] Optionally, the sidewall of the support layer simultaneously contacts the horizontal extension portions of the first lower electrode layer and the second lower electrode layer in at least one of the lower electrodes.

[0017] In a second aspect, the present invention further provides a semiconductor device, which may at least include:

[0018] substrate;

[0019] A first U-shaped material bottom electrode layer is located on the substrate, wherein at least one of the first U-shaped material bottom electrode layers has an upper top surface of unequal height;

[0020] A second material bottom electrode layer, covering at least one top surface of the first U-shaped material bottom electrode layer;

[0021] A dielectric layer, located on the lower electrode layer of the second material;

[0022] The upper electrode is located on the dielectric layer.

[0023] Optionally, at least one of the first U-shaped material lower electrode layers has a relative first side wall and a second side wall, the second side wall is located on the side away from the remaining first U-shaped material lower electrode layers, and the top surface of the first U-shaped material lower electrode layer located on the first side wall is higher than the top surface of the first U-shaped material lower electrode layer located on the second side wall.

[0024] Optionally, the second material lower electrode layer is in an asymmetric columnar shape, and at least one of the second material lower electrode layers has a horizontal extension portion extending in a horizontal direction and covering a portion of the top surface of at least one of the first U-shaped material lower electrode layers.

[0025] Optionally, the bottom surface of the horizontal extension portion directly contacts at least one portion of the first U-shaped material lower electrode layer located on the second side wall, and its side wall is flush with the side wall of the first U-shaped material lower electrode layer located on the second side wall along the vertical direction.

[0026] In a third aspect, based on the same inventive concept, the present invention also provides a method for manufacturing a semiconductor device, which may at least include the following steps:

[0027] providing a substrate including a first region and a second region;

[0028] A stacked support structure layer and a first mask layer are located on the first region and the second region, and the first mask layer is located on the support structure layer;

[0029] forming a through hole located in the first region, wherein the through hole penetrates the first mask layer and the supporting structure layer;

[0030] forming a first lower electrode layer located on the inner surface of the through hole and extending laterally to cover the first mask layer in the first area and the second area;

[0031] forming a second mask layer on the first lower electrode layer in the first region and the second region;

[0032] removing the second mask layer, a portion of the first lower electrode layer and the first mask layer on the second region, so that the upper top surfaces of the first lower electrode layer on the two side walls of at least one of the through holes adjacent to the second region are not at the same height;

[0033] forming a second lower electrode layer to fill the through hole;

[0034] forming a dielectric layer on the second lower electrode;

[0035] An upper electrode is formed on the dielectric layer.

[0036] Optionally, before forming the second lower electrode layer, the method further includes:

[0037] The second mask layer on the first region is removed to expose the first lower electrode layer.

[0038] Optionally, after forming the second lower electrode layer, the method further includes:

[0039] The second lower electrode layer and a portion of the first lower electrode layer on the first region are removed until the support structure layer is exposed, and the first lower electrode layer and the second lower electrode layer remaining in each of the through holes on the first region form a lower electrode.

[0040] Optionally, the through hole adjacent to the supporting structure layer on the second zone has relative first side wall and second side wall, the first lower electrode layer located on the first side wall is in direct contact with the supporting structure layer on the first zone, and the first lower electrode layer located on the second side wall is in direct contact with the supporting structure layer on the second zone.

[0041] Optionally, a top surface of the first lower electrode layer located on the first side wall is higher than a top surface of the first lower electrode layer located on the second side wall.

[0042] Optionally, the second lower electrode layer located in the through hole adjacent to the supporting structure layer on the second region fills the through hole and has a horizontal extension portion extending in a horizontal direction and covering a top surface of the first lower electrode layer located on the second side wall of the through hole.

[0043] Optionally, the supporting structure layer includes a first sacrificial layer, a first supporting layer, a second sacrificial layer and a second supporting layer stacked in sequence from bottom to top.

[0044] Optionally, after forming the lower electrode, the method further includes:

[0045] forming a third mask layer on the first region and the second region;

[0046] Forming a first photoresist layer having a first opening located on the third mask layer on the first region, wherein the first opening exposes a portion of the top surface of the third mask layer in the first region;

[0047] Using the first photoresist layer as a mask, the third mask layer and a portion of the second supporting layer and all of the second sacrificial layer in the supporting structure layer corresponding to the opening are removed.

[0048] Optionally, after removing a portion of the second supporting layer in the supporting structure layer, the method further includes: forming an oxidized supporting layer on the supporting structure layer and the lower electrode exposed on the first region.

[0049] Optionally, after forming the oxidized support layer, the method further includes:

[0050] forming a fourth mask layer on the first region and the second region;

[0051] Forming a second photoresist layer having a second opening located on a portion of the top surface of the fourth mask layer on the first region, wherein the second opening is located opposite to the first opening;

[0052] Using the second photoresist layer as a mask, the fourth mask layer and a portion of the first supporting layer and all of the first sacrificial layer in the supporting structure layer corresponding to the second opening are removed.

[0053] In the present invention, multiple lower electrodes can all include multiple layers of lower electrode layer materials with different shapes, for example, including a first lower electrode layer in an asymmetric U-shape and a second lower electrode layer in an asymmetric columnar shape, and the second lower electrode layer in at least one of the lower electrodes has a horizontal extension portion that extends in a horizontal direction and covers a portion of the top surface of the first lower electrode layer in the at least one of the lower electrodes. That is, by setting the film layer structure of the lower electrode to be multi-layer and the shapes and heights of the multiple layers of lower electrode layers in the lower electrode are different, a semiconductor device with different shapes between the multiple lower electrodes and height differences in the vertical direction between the multiple layers of lower electrode layers is formed, thereby achieving the purpose of improving the performance and reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application but do not constitute a limitation to the present application. In the accompanying drawings:

[0055] Figure 1 A flowchart of a method for preparing a semiconductor memory provided in one embodiment of the present invention;

[0056] Figure 2 to Figure 13 The present invention is a schematic structural diagram of a method for manufacturing a semiconductor device during the manufacturing process according to an embodiment of the present invention.

[0057] Wherein, the accompanying drawings are marked as follows:

[0058] 100-substrate, 101-first region, 102-second region, 110 / 110' / 110"-support structure layer, 111-first sacrificial layer, 112-first support layer, 113-second sacrificial layer, 114-second support layer, 120-first mask layer, OP-through hole, 131-first lower electrode layer, 131a / 131a'-first lower electrode layer on the first sidewall, 131b / 131b'-first lower electrode layer on the second sidewall Polar layer, 132-second lower electrode layer, 1321-horizontal extension part, 130-lower electrode, 140 / 140'-second mask layer, 150-third photoresist layer, 160-third mask layer, 170-first photoresist layer, 180-oxidation support layer, 190-fourth mask layer, 200-second photoresist layer, 210-dielectric layer, 220-upper electrode, 221-first upper electrode layer, 222-second upper electrode layer, CAP-capacitor.

[0059] In the drawings, the same reference numerals are used for the same components, and the drawings are not drawn to scale. DETAILED DESCRIPTION

[0060] In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0061] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the accompanying drawings are all in very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It is understood that the meanings of "on", "above" and "above" in the present invention should be interpreted in the broadest way, so that "on" not only means that it is "on" something and there are no intervening features or layers (i.e. directly on something), but also includes the meaning of being "on" something and having intervening features or layers.

[0062] For ease of understanding, a horizontal direction and a vertical direction are defined below, wherein the horizontal direction is a direction parallel to the surface of the substrate 100 ; and the vertical direction is a direction perpendicular to the surface of the substrate 100 .

[0063] Please refer to Fig.13 , which is a cross-sectional schematic diagram of the semiconductor device in the first embodiment of the invention. The semiconductor device of the present invention can be used to manufacture dynamic random access memory (DRAM), and the present invention can also be applied to other types of memory without departing from the spirit of the present invention.

[0064] like Fig.13As shown, the semiconductor device includes a substrate 100, a plurality of capacitors CAP composed of a plurality of lower electrodes 130, a dielectric layer 210 and an upper electrode 220, and a supporting structure layer 110" located between the plurality of lower electrodes 130. The substrate 100 can be divided into a first region 101 and a second region 102 which are adjacent to each other. The first region 101 is, for example, a storage region (cell region) of a semiconductor memory, and the second region 102 is, for example, a peripheral region (periphery region) of a semiconductor memory; and components such as a bit line structure, a sidewall structure, a contact structure and a connection pad structure (not shown) can be formed in the substrate 100, but the invention is not limited thereto. In one embodiment, the substrate 100 is any suitable substrate material known in the art, for example, a silicon substrate, a silicon-containing substrate (such as SiC, SiGe) or a silicon-on-insulator substrate or a substrate composed of other suitable materials, but the invention is not limited thereto.

[0065] The multiple lower electrodes 130 can be arranged on the substrate 100 of the first area 101 at intervals from each other in the horizontal direction, and each of the lower electrodes 130 can include multiple layers of lower electrode layer materials, for example, may include a first lower electrode layer 131 (also referred to as a first U-shaped material lower electrode layer) and a second lower electrode layer 132 (also referred to as a second material lower electrode layer). In one embodiment, the shape of the first lower electrode layer 131 in each of the lower electrodes 130 may be U-shaped, and the shape of the first lower electrode layer 131 in at least one of the lower electrodes 130 is U-shaped with an uneven top surface (i.e., an asymmetric U-shape), for example, the shape of the first lower electrode layer 131 in the rightmost lower electrode 130 (also the lower electrode 130 adjacent to the second area 102) on the first area 101 along the horizontal direction is an asymmetric U-shape; the shape of the second lower electrode layer 132 in each of the lower electrodes 130 may be columnar, for example, a columnar structure in which the length of the short side along the horizontal direction is less than the length of the long side along the vertical direction, and the second lower electrode layer 132 is filled into the first lower electrode layer 131 in each of the lower electrodes 130 in the shape of a U-shape, so as to form a solid lower electrode structure with multiple film layers proposed in the embodiment of the present invention. Exemplarily, the top surface of the second lower electrode layer 132 is flush with the top surface of the first lower electrode layer 131.

[0066] Specifically, a support structure layer 110" is disposed between adjacent lower electrodes 130 and on the second region 102 of the substrate 100, and a side wall of at least a portion of the first lower electrode layer 131 located on the first region 101 of the substrate 100 is in direct contact with the corresponding support structure layer 110", wherein the first lower electrode layer 131 having an asymmetric U-shaped shape may have a first side wall 131a' and a second side wall 131b' disposed opposite to each other in a horizontal direction; specifically, the first side wall 131a' is located on the first region 101 of the substrate 100 and is in direct contact with a support structure layer 110" on the first region 101. 10”, and the second side wall 131b’ is located on a side away from all the other lower electrodes 130 and adjacent to the supporting structure layer 110” on the second area 102 of the substrate 100; preferably, the top surface of the first lower electrode layer 131 located on the first side wall 131a’ is higher than the top surface of the first lower electrode layer 131 located on the second side wall 131b’, and the top surface of the first lower electrode layer 131 located on the second side wall 131b’ is also lower than the top surface of the supporting structure layer 110” on the second area 102, such as the top surface of the second supporting layer 114, but not limited to this.

[0067] In the present embodiment, the second lower electrode layer 132 of at least one of the multiple lower electrodes 130 not only has a columnar film structure, but also has a horizontal extension portion 1321 extending in the horizontal direction, and the horizontal extension portion 1321 can be located at the top of one side of the columnar film structure of the second lower electrode layer 132, so that the overall morphology of the second lower electrode layer 132 is an inverted L-shape; specifically, the second lower electrode layer 132 with an overall inverted L-shape can be filled in the first lower electrode layer 131 with an asymmetric U-shape, and the horizontal extension portion 1321 of the second lower electrode layer 132 is located on the second side wall 131b' of the asymmetric U-shaped first lower electrode layer 131 , so that the bottom surface of the horizontal extension portion 1321 directly contacts the first lower electrode layer 131 located on the second sidewall 131b', and the sidewall of the horizontal extension portion 1321 is flush with the sidewall of the first lower electrode layer 131 located thereunder and located on the second sidewall 131b', and is also in direct contact with the sidewall of the supporting structure layer 110" on the second region 102 (for example, the sidewall of the second supporting layer 114). In addition, the materials of the first lower electrode layer 131 and the second lower electrode layer 132 can both be conductive materials, such as doped silicon, tungsten, copper, titanium nitride or others, but are not limited thereto, and the materials of the first lower electrode layer 131 and the second lower electrode layer 132 can be the same or different.

[0068] Furthermore, the dielectric layer 210 may include a high dielectric constant material layer, such as TaOO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, BST((Ba,Sr)TiO), STO(SrTiO), BTO(BaTiO), PZT(Pb(Zr,Ti)O), (Pb,La)(Zr,Ti)O, Ba(Zr,Ti)OO, Sr(Zr,Ti)O, a combination of the above materials, or other suitable dielectric materials, and the material of the upper electrode 220 may include titanium nitride, tantalum nitride, SiGe, a combination of the above materials, or other suitable multi-layer conductive materials, such as a double-layer conductive material comprising a first upper electrode layer 221 and a second upper electrode layer 222, but is not limited thereto. Furthermore, the dielectric layer 210 and the upper electrode 220 will also fill up the areas corresponding to the first sacrificial layer 111, the second sacrificial layer 113, the first supporting layer 112 and the second supporting layer 114 that have been removed from the supporting structure layer 110", and extend laterally on the top surface of the supporting structure layer 110" exposed on the first area 101 and the second area 102, but is not limited to this.

[0069] In order to enable a person skilled in the art to which the present invention relates to easily understand the method for manufacturing a semiconductor device in an embodiment of the present invention, the method for manufacturing a semiconductor device proposed in the present invention will be further described below in conjunction with various structural schematic diagrams of the manufacturing method during the preparation process.

[0070] Please refer to Figures 1 to 13 , which is a structural schematic diagram of a method for manufacturing a semiconductor device provided in an embodiment of the present invention during the preparation process.

[0071] like Figure 1As shown, first, a substrate 100 (for example, a silicon substrate) is provided, and the substrate 100 is divided into a first area 101 and a second area 102 adjacent to each other in a horizontal direction; then, a support structure layer 110 and a first mask layer 120 located on the top surface of the support structure layer 110 are conformally formed on the surface of the substrate 100 by using at least one of a deposition process such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc.; in one embodiment, the support structure layer 110 may include a first sacrificial layer 111, a first supporting layer 112, a second sacrificial layer 113, and a second supporting layer 114 stacked in sequence from bottom to top, so as to provide a plurality of supporting layers to facilitate a more secure support for the lower electrode, but the present invention is not limited thereto. Specifically, the first sacrificial layer 111 and the second sacrificial layer 113 may respectively include a single layer or multiple layers of oxide materials, such as silicon oxide, boro-phospho-silicate-glass (BPSG) or other sacrificial materials having a desired etching selectivity with the material of the support layer, but not limited thereto; the first support layer 112 and the second support layer 114 may be silicon carbonitride (SiCN). The material of the first mask layer 120 may include silicon oxide, amorphous silicon, polycrystalline silicon or a combination of the above materials, but not limited thereto.

[0072] Next, an etching process such as at least one of dry etching and wet etching may be further used to form a plurality of through holes OP spaced apart from each other in a horizontal direction in the first mask layer 120 and the supporting structure layer 110 in the first area 101 of the substrate 100, that is, the through holes OP penetrate the first mask layer 120 and the supporting stack layer 110, and the bottom of the through holes OP exposes the substrate 100, but is not limited to this; and after etching to form the through holes OP, the top surface of the portion of the first mask layer 120 located on the first area 101 may be lower than the top surface of the portion thereof located on the second area 102.

[0073] like Figure 2 As shown, at least one of the above deposition processes can be used to conformally form a conductive material (such as tungsten, copper or titanium nitride) of a first lower electrode layer 131 on the first region 101 and the second region 102 of the substrate 100; specifically, the conductive material of the formed first lower electrode layer 131 is specifically located on the inner surface of the through hole OP, the top surface of the first mask layer 120 in the first region 101 exposed between adjacent through holes OP, and the top surface of the first mask layer 120 in the second region 102, at which time the conductive material of the first lower electrode layer 131 does not fill the through holes OP located on the first region 101, and the top surface of the portion of the conductive material of the first lower electrode layer 131 located on the second region 102 is higher than the top surface of the portion located on the first region 101.

[0074] like Figure 3 As shown, at least one of the above deposition processes is then used to sequentially form a second mask layer 140 and a third photoresist layer 150 on the first area 101 and the second area 102 of the substrate 100 from bottom to top; the second mask layer 140 fills the gaps between adjacent through holes OP in the first area 101, and extends laterally in the horizontal direction to cover the top surface of the first lower electrode layer 131 between the adjacent through holes OP and the top surface of the first lower electrode layer 131 located on the second area 102, that is, the second mask layer 140 buries the film layer structures on the first area 101 and the second area 102, and due to the height difference between the support structure layer 110 in the first area 101 and the second area 102, the second mask layer 140 is stepped at the junction of the first area 101 and the second area 102, but is not limited to this. The third photoresist layer 150 is located on a portion of the top surface of the second mask layer 140 in the first region 101, and exposes the top surface of the second mask layer 140 aligned with the first lower electrode layer 131 adjacent to the sidewall of the support structure layer 110 in the second region 102. In one embodiment, the material of the second mask layer 140 may be the same as that of the first mask layer 120, for example, both are silicon oxide, or may be different, for example, the material of the first mask layer 120 is silicon oxide, and the material of the second mask layer 140 is polysilicon, but the present invention is not limited thereto.

[0075] like Figure 4 and Figure 5 As shown, the third photoresist layer 150 can be further used as a mask to remove a portion of the second mask layer 140 and a portion of the first lower electrode layer 131 located on the first area 101 that are not covered by the third photoresist layer 150, as well as all of the second mask layer 140 and all of the first mask layer 120 located on the second area 102, so as to expose the support structure layer 110 on the second area 102, and the first lower electrode layer 131 on the side wall of the through hole OP adjacent to the support structure layer 110 and located on the first area 101, so as to form a Figure 4 The structure shown in FIG. 1 is shown in FIG. 1 ; the second mask layer remaining after the etching step is marked with reference numeral 140'. Next, the third photoresist layer 150 on the first region 101 and the remaining second mask layer 140' thereunder are further removed to expose the first lower electrode layer 131 on the first region 101, forming the structure shown in FIG. Figure 5The structure shown, i.e., a first lower electrode layer 131 located on the rightmost side from left to right in the horizontal direction on the first zone 101 is shaped like an asymmetric U-shape, while the other first lower electrode layers 131 are shaped like symmetrical U-shapes; specifically, the top surface of the second side wall 131b of the asymmetric U-shaped first lower electrode layer 131 that is in direct contact with the supporting structure layer 110 on the second zone 102 is lower than the top surface of the first side wall 131a on the first zone 101.

[0076] like Figure 6 and Figure 7 As shown, a deposition process such as a chemical vapor deposition process is then used to form a conductive material (such as tungsten, copper or titanium nitride) of a second lower electrode layer 132 on the first area 101 and the second area 102 of the substrate 100; the conductive material forming the second lower electrode layer 132 not only fills the portion of the multiple through holes OP on the first area 101 that is not filled by the material of the first lower electrode layer 131, but also extends laterally to cover the exposed support structure layer 110 in the second area 102. Then, an etching process such as a dry etching process is used to vertically etch back the conductive material forming the second lower electrode layer 132 and a portion of the height of the first lower electrode layer 131, so as to expose a portion of the height of the support structure layer 110 in the first area 101 and the second area 102, for example, to expose a portion of the height of the second support layer 114 in the support structure layer 110. For easy distinction, the two sidewalls of the asymmetric U-shaped first lower electrode layer 131 remaining after this etching are represented by reference numerals 131a' and 131b' respectively; thus, a plurality of lower electrodes 130 with multiple film layers (conductive materials) proposed in the embodiment of the present invention are formed.

[0077] like Figure 8 and Fig. 9As shown, a deposition process such as a chemical vapor deposition process can be further used to conformally form a third mask layer 160 and a first photoresist layer 170 having a first opening from bottom to top on the first area 101 and the second area 102 of the substrate 100; wherein the top surface of the third mask layer 160 is higher than the top surface of the second lower electrode layer 132, and the first photoresist layer 170 has at least one first opening, and the first opening exposes the third mask layer 160 on a portion of the supporting structure layer 110 in the first area 101, so as to prepare for the subsequent removal of a portion of the film layer in the supporting structure layer 110. Exemplarily, the first photoresist layer 170 in the embodiment of the present invention has two first openings. Next, an etching process such as a wet etching process can be used to remove the third mask layer 160 aligned with the opening pattern and the second supporting layer 114 and the second sacrificial layer 113 in the supporting structure layer 110 along the first opening in the first photoresist layer 170, so as to form a plurality of gaps in the supporting structure layer on the first area 101 and the second area 102, and the supporting structure layer remaining after etching here is marked with the figure mark 110'.

[0078] like Fig.10 and Fig.11 As shown, the first photoresist layer 170 may be removed first, and then a layer of oxide support layer 180 with a moderate thickness may be formed on the inner surface of the multiple gaps in the support structure layer 110' on the first area 101 and the second area 102 and in the area of ​​the second support layer 114 and the second sacrificial layer 113 removed by the multiple first openings of the first photoresist layer 170 by using a deposition process such as a physical vapor deposition process, so as to enhance the supporting function of the support structure layer 110' on the first area 101, wherein the material of the oxide support layer 180 may be an insulating material, such as oxide silicon dioxide, or nitride silicon nitride, etc. Then, a fourth mask layer 190 that buries all the film layer structures on the first area 101 and the second area 102 and a second photoresist layer 200 with a second opening located on the fourth mask layer 190 are formed on the oxide support layer 180 by using a deposition process. Since the formed oxidized support layer 180 does not fill up the multiple gaps in the support structure layer 110' and the areas of the second support layer 114 and the second sacrificial layer 113 removed by using the multiple first openings of the first photoresist layer 170, the subsequently formed fourth mask layer 190 will further fill up the multiple gaps in the support structure layer 110' and the areas of the second support layer 114 and the second sacrificial layer 113 removed by using the multiple first openings of the first photoresist layer 170, but is not limited to this; the second photoresist layer 200 also has an opening pattern, namely, second openings, and the number and specific positions of the second openings in the second photoresist layer 200 are the same as the number and specific positions of the first openings in the first photoresist layer 170.

[0079] like Fig.12 and Fig.13 As shown, the second photoresist layer 200 can then be used as a mask to remove the fourth mask layer 190 corresponding to the second opening, the oxidized support layer 180, and the first sacrificial layer 111 in the support structure layer 110', and then the remaining fourth mask layer 190 and oxidized support layer 180 on the second photoresist layer 200 and the substrate 100 are removed to form a Fig.12 The support structure layer 110" is composed only of the first support layer 112 and the second support layer 114, and then the dielectric layer 210 and the upper electrode layer 220 are deposited in sequence on the substrate 100. In one embodiment, the upper electrode 220 may be a multi-layer conductive material, for example, a double-layer conductive material including a first upper electrode layer 221 and a second upper electrode layer 222, and the dielectric layer 210 and the upper electrode 220 will also fill the areas corresponding to the first sacrificial layer 111, the second sacrificial layer 113, the first support layer 112 and the second support layer 114 that have been removed from the support structure layer 110", and extend laterally on the top surface of the support structure layer 110" exposed on the first area 101 and the second area 102.

[0080] It should be understood that the “common shape” in the embodiments of the present invention refers to constructing a continuous structural shape by utilizing the morphological similarities and associations between two or more shapes.

[0081] In summary, the multiple lower electrodes in the present invention can all include multiple layers of lower electrode layer materials with different shapes, for example, including a first lower electrode layer in an asymmetric U-shape and a second lower electrode layer in an asymmetric columnar shape, and the second lower electrode layer in at least one of the lower electrodes has a horizontal extension portion that extends in the horizontal direction and covers a portion of the top surface of the first lower electrode layer in the at least one of the lower electrodes. That is, by setting the film layer structure of the lower electrode to be multi-layer and the shapes and heights of the multiple layers of lower electrode layers in the lower electrode are different, a semiconductor device with different shapes between the multiple lower electrodes and height differences in the vertical direction between the multiple layers of lower electrode layers is formed, thereby achieving the purpose of improving the performance and reliability of the semiconductor device.

[0082] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: substrate; A plurality of lower electrodes are arranged on the substrate at intervals, and the lower electrodes include a first lower electrode layer, which is in an asymmetric U-shape and has a bottom that is in direct contact with the substrate; A second lower electrode layer, in an asymmetric columnar shape and filled into the first lower electrode layer; a dielectric layer, located on the plurality of lower electrodes; an upper electrode, located on the dielectric layer; The second lower electrode layer in at least one of the lower electrodes has a horizontal extension portion extending in a horizontal direction and covering a portion of the top surface of the first lower electrode layer in the at least one of the lower electrodes.

2. The semiconductor device according to claim 1, wherein The top surface of the horizontal extension portion is flush with the top surface of the second lower electrode layer in all the lower electrodes.

3. The semiconductor device according to claim 1, wherein The first lower electrode layer in at least one of the lower electrodes has a first side wall and a second side wall opposite to each other, the second side wall is located on a side away from the other lower electrodes, and the top surface of the first lower electrode layer on the first side wall is higher than the top surface of the first lower electrode layer on the second side wall.

4. The semiconductor device according to claim 3, characterized in that The bottom surface of the horizontal extension portion directly contacts a first lower electrode layer located on the second side wall of at least one of the lower electrodes.

5. The semiconductor device according to claim 3, wherein: Also includes: The supporting layer is located on the outer side of the second side wall of the first lower electrode layer in at least one of the lower electrodes.

6. The semiconductor device according to claim 5, characterized in that The sidewall of the support layer contacts the horizontal extension portions of the first lower electrode layer and the second lower electrode layer in at least one of the lower electrodes simultaneously.

7. A semiconductor device, characterized in that: include: substrate; A first U-shaped material bottom electrode layer is located on the substrate, wherein at least one of the first U-shaped material bottom electrode layers has an upper top surface of unequal height; A second material bottom electrode layer, covering at least one top surface of the first U-shaped material bottom electrode layer; A dielectric layer, located on the lower electrode layer of the second material; The upper electrode is located on the dielectric layer.

8. The semiconductor device according to claim 7, wherein: At least one of the first U-shaped material lower electrode layers has a first side wall and a second side wall relative to each other, the second side wall is located on a side away from the other first U-shaped material lower electrode layers, and the top surface of the first U-shaped material lower electrode layer located on the first side wall is higher than the top surface of the first U-shaped material lower electrode layer located on the second side wall.

9. The semiconductor device according to claim 8, characterized in that The second material lower electrode layer is in an asymmetric columnar shape, and at least one of the second material lower electrode layers has a horizontal extension portion extending in a horizontal direction and covering a portion of the top surface of at least one of the first U-shaped material lower electrode layers.

10. The semiconductor device according to claim 9, wherein: The bottom surface of the horizontal extension portion directly contacts at least one portion of the first U-shaped material lower electrode layer located on the second side wall, and its side wall is flush with the side wall of the first U-shaped material lower electrode layer located on the second side wall along the vertical direction.

11. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate including a first region and a second region; A stacked support structure layer and a first mask layer are located on the first region and the second region, and the first mask layer is located on the support structure layer; forming a through hole located in the first region, wherein the through hole penetrates the first mask layer and the supporting structure layer; forming a first lower electrode layer located on the inner surface of the through hole and extending laterally to cover the first mask layer in the first area and the second area; forming a second mask layer on the first lower electrode layer in the first region and the second region; removing the second mask layer, a portion of the first lower electrode layer and the first mask layer on the second region, so that the upper top surfaces of the first lower electrode layer on the two side walls of at least one of the through holes adjacent to the second region are not at the same height; forming a second lower electrode layer to fill the through hole; forming a dielectric layer on the second lower electrode; An upper electrode is formed on the dielectric layer.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: Before forming the second lower electrode layer, the method further includes: The second mask layer on the first region is removed to expose the first lower electrode layer.

13. The method for manufacturing a semiconductor device according to claim 11, wherein: After forming the second lower electrode layer, the method further includes: The second lower electrode layer and a portion of the first lower electrode layer on the first region are removed until the support structure layer is exposed, and the first lower electrode layer and the second lower electrode layer remaining in each of the through holes on the first region form a lower electrode.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: The through hole adjacent to the supporting structure layer on the second zone has opposite first side walls and second side walls, the first lower electrode layer located on the first side wall is in direct contact with the supporting structure layer on the first zone, and the first lower electrode layer located on the second side wall is in direct contact with the supporting structure layer on the second zone.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: A top surface of the first lower electrode layer located on the first side wall is higher than a top surface of the first lower electrode layer located on the second side wall.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: The second lower electrode layer located in the through hole adjacent to the support structure layer on the second region fills the through hole and has a horizontal extension portion extending in a horizontal direction and covering the top surface of the first lower electrode layer located on the second side wall of the through hole.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: The supporting structure layer includes a first sacrificial layer, a first supporting layer, a second sacrificial layer and a second supporting layer which are sequentially stacked from bottom to top.

18. The method for manufacturing a semiconductor device according to claim 17, wherein: After forming the lower electrode, the method further comprises: forming a third mask layer on the first region and the second region; Forming a first photoresist layer having a first opening located on the third mask layer on the first region, wherein the first opening exposes a portion of the top surface of the third mask layer in the first region; Using the first photoresist layer as a mask, the third mask layer and a portion of the second supporting layer and all of the second sacrificial layer in the supporting structure layer corresponding to the opening are removed.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: After removing part of the second supporting layer in the supporting structure layer, the method further comprises: An oxidized support layer is formed on the support structure layer and the lower electrode exposed on the first region.

20. The method for manufacturing a semiconductor device according to claim 19, wherein: After forming the oxidized support layer, the method further comprises: forming a fourth mask layer on the first region and the second region; Forming a second photoresist layer having a second opening located on a portion of the top surface of the fourth mask layer on the first region, wherein the second opening is located opposite to the first opening; Using the second photoresist layer as a mask, the fourth mask layer and a portion of the first supporting layer and all of the first sacrificial layer in the supporting structure layer corresponding to the second opening are removed.

Images