A layout structure of a low leakage and low breakdown voltage PN junction and a manufacturing method thereof
By changing the layout structure at the PN junction and adjusting the electric field distribution, the problem of leakage current increases when reducing the breakdown voltage in the prior art is solved, and a device design with low leakage and low breakdown voltage is realized.
Patent Information
- Application Number
- CN202411838206.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-13
- Publication Date
- 2025-04-04
AI Technical Summary
When the prior art reduces the breakdown voltage of integrated circuit devices, it is often necessary to increase the concentration of impurities, resulting in an increase in leakage current, which in turn affects the reliability and life of the device.
By changing the layout structure at the PN junction, especially the curvature shape of the N+ type region, the electric field distribution is adjusted, thereby reducing the breakdown voltage without increasing the leakage current.
It realizes that the breakdown voltage of the device is reduced without increasing the leakage current, and the breakdown mechanism is mainly avalanche breakdown, extending the device life and improving protection performance.
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Abstract
Description
Technical Field
[0001] The present invention belongs to the field of semiconductor integrated circuits, and in particular, relates to a layout structure of a low leakage and low breakdown voltage PN junction and a manufacturing method thereof. Background Art
[0002] As the manufacturing process size of integrated circuits (ICs) continues to shrink, the operating voltage of devices will inevitably decrease. In this case, the devices are more susceptible to electrostatic discharge (ESD), so devices with lower breakdown voltage are needed to provide effective protection.
[0003] Devices with low breakdown voltage can ensure that the circuit operates at a lower voltage, which helps to improve the reliability of the entire system. In modern electronic devices, especially those integrated circuits manufactured using high-precision processes, devices with low breakdown voltage can absorb harmful ESD energy faster and avoid irreversible damage to the IC and surrounding components. Furthermore, devices with low breakdown voltage usually have lower parasitic capacitance and faster response time, and can provide better protection performance without adding additional costs.
[0004] Figure 1 The figure shows a traditional finger-shaped PN junction layout structure. The breakdown of this structure often occurs at the metallurgical interface of the pn junction formed by the N-type region (04) and the pwell (02). This structure often needs to increase the impurity concentration to meet the demand for low breakdown voltage. As the doping concentration of the device increases, the breakdown mechanism of the device gradually transitions from avalanche breakdown to Zener breakdown, which will increase the leakage current of the device. Excessive leakage current will lead to problems such as increased static power consumption and shortened device life, which poses a great challenge to device design.
[0005] Therefore, how to reduce the breakdown voltage of the device by changing the layout shape without significantly increasing the leakage current of the device, thereby improving the design performance of related protection devices, is a technical problem that needs to be solved in the layout design of low breakdown voltage devices. Summary of the invention
[0006] The present invention provides a layout structure of a low leakage and low breakdown voltage PN junction and a manufacturing method thereof, which can reduce the breakdown voltage of a device without significantly increasing the leakage current of the device by changing the layout shape.
[0007] In order to achieve the above-mentioned purpose, the present invention provides a PN junction layout structure, including an N-type substrate, a P-type well region, a P+ type contact region and an N+ type region, characterized in that a processing technology is used to make the N+ type region have a variable curvature on a side facing the P+ type contact region.
[0008] Preferably, the N+ type region has an N type fold line region.
[0009] Preferably, the N+ type region is a triangular structure, a trapezoidal structure or an arc structure in a top view.
[0010] Preferably, the N+ type region forms a triangular pyramid structure, and the cross-sectional area decreases with increasing depth, so that the side view of the N+ type region presents a shape that is wide at the top and narrow at the bottom.
[0011] Preferably, the P+ type contact region has a concave structure corresponding to the curvature of the N+ type region on a side facing the N+ type region.
[0012] The present invention also provides a method for manufacturing the aforementioned PN junction layout structure, characterized in that it comprises the following steps:
[0013] (1) Preparing an N-type substrate;
[0014] (2) forming a P-type well region through ion implantation and thermal diffusion processes;
[0015] (3) performing a process on a designated area of the P-type well region to form the P+-type contact region and the N+-type region;
[0016] (4) Subsequent processing to form a PN junction structure with low leakage and low breakdown voltage.
[0017] Preferably, the process includes multiple ion implantation and high temperature rapid annealing process.
[0018] Preferably, the process includes a trench process.
[0019] The present invention also provides an NPN transistor layout structure, including a P-type substrate, an N-type epitaxial layer, a P-type well region, a P+ type contact region and an N+ type region, characterized in that the N+ type region, on a side facing the P+ type contact region, also includes an N-type fold line region with a fold line edge.
[0020] The present invention also provides an SCR layout structure, including a P-type substrate, an N-type well region, a P-type well region, a first P+ region 64, a first N+ region, a second P+ region, a second N+ region and a P-type Zener doped region, characterized in that an N+ region with a certain curvature or shape is also provided at the junction of the N-type well region and the P-type Zener doped region.
[0021] The beneficial effects of the present invention are as follows: a layout structure of a PN junction with low leakage and low breakdown voltage and a manufacturing scheme thereof are proposed, and by changing the curvature of the PN junction junction, the breakdown condition is changed, so that the PN junction with the structure has a lower breakdown triggering condition than the PN junction without the structure. The structure eliminates the need to reduce the breakdown voltage by increasing the impurity concentration of the P-type well region, reduces the possibility of the tunneling effect in the PN junction, and makes the breakdown mechanism of the device still mainly avalanche breakdown under the condition of low breakdown voltage, and the leakage current of the device is reduced, which can not only reduce the breakdown voltage, but also achieve lower leakage current by changing the layout shape of the N-type region. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 It is the layout structure of the finger-shaped PN junction in the prior art.
[0023] Figure 2 This is a schematic diagram of the layout structure in Example 1 of the present invention.
[0024] FIG. 3 is a schematic diagram of a method for manufacturing a layout structure in Embodiment 2 of the present invention.
[0025] FIG. 4 is a schematic diagram of a method for manufacturing a layout structure in Embodiment 3 of the present invention.
[0026] FIG. 5 is a schematic diagram of a method for manufacturing a layout structure in Embodiment 4 of the present invention.
[0027] Figure 6 This is a schematic diagram of the layout structure in Embodiment 5 of the present invention.
[0028] Figure 7 This is a schematic diagram of the layout structure in Example 6 of the present invention.
[0029] Figure 8 This is a schematic diagram of the layout structure in Example 7 of the present invention.
[0030] Fig. 9 This is a schematic diagram of the layout structure in Example 8 of the present invention. DETAILED DESCRIPTION
[0031] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0032] The embodiment of the present invention provides a PN junction layout structure with low leakage and low breakdown voltage, including an N-type substrate, a P-type well region, a P+ type contact region and an N+ type region. Specifically, a P-type layer is epitaxially grown on the N-type substrate to form a P-type well region, and a P+ type contact region and an N+ type region are implanted on the surface of the P-type well region.
[0033] Different from the prior art method of reducing the breakdown voltage by increasing the impurity concentration, the multiple embodiments proposed in the present invention are to adjust the electric field distribution by changing the layout structure of the N+ type region, thereby reducing the breakdown voltage of the PN junction without changing the doping concentration of the PN junction and increasing the leakage current. Specifically, in the embodiments of the present invention, the processing technology makes the N+ type region have a variable curvature on the side facing the P+ type contact region, thereby achieving the technical effect of reducing the breakdown voltage of the PN junction by adjusting the electric field distribution. Furthermore, in some embodiments, by changing the processing technology, the P+ type contact region has a variable curvature on the side facing the N+ type region, which can also achieve the technical effect of reducing the PN breakdown voltage.
[0034] Embodiment 1:
[0035] In one embodiment, if Figure 2 As shown, the layout structure includes: N-type substrate 11, P-type well region 12, P+ type contact region 13 and N+ type region 14, wherein the N+ type region 14 further includes an N-type fold line region 15 with a fold line edge on the side facing the P+ type contact region. The P-type well region 12 is formed on the N-type substrate 11. Ion implantation and other processes are used on the surface of the P-type well region 12 to form the P+ type contact region 13 and the N+ type region 14 with the fold line edge N-type fold line region 15.
[0036] When a certain reverse voltage is applied to the pn junction in this embodiment, the peak of the edge of the N-type fold line region 15 will be induced to break down before the non-peak, so that the PN junction with this structure has a lower breakdown trigger condition than the PN junction without this structure. This structure eliminates the need to reduce the breakdown voltage by increasing the impurity concentration of the P-type well region 12, reduces the possibility of the tunneling effect in the PN junction, and makes the breakdown mechanism of the device still mainly avalanche breakdown under the condition of low breakdown voltage, and reduces the leakage current of the device.
[0037] As an example, this embodiment also provides a method for manufacturing the layout structure, which specifically includes the following steps:
[0038] (1) Preparing an N-type substrate 11;
[0039] (2) forming a P-type well region 12 by ion implantation and thermal diffusion processes;
[0040] (3) performing multiple ion implantations in designated areas of the P-type well region to form a P+ type contact region 13 and an N+ type region 14;
[0041] (4) Using a high temperature rapid annealing process, the N-type fold line region 15 having a certain curvature or shape is formed at the edge of the N+ type region 14.
[0042] (5) Subsequent processing to form a PN junction structure with low leakage and low breakdown voltage.
[0043] Embodiment 2:
[0044] In another embodiment, as shown in FIG. 3( c ), the layout structure comprises: an N-type substrate 101, a P-type well region 102, a P+ type contact region 103 and an N+ type region 104, wherein the N+ type region 104 is a triangular structure in a top view, and one corner faces the P+ type contact region 103. Accordingly, the structure of the P+ type contact region 103 becomes a concave bevel shape corresponding to the N+ type region 104. The P-type well region 102 is formed on the N-type substrate 101. Ion implantation and other processes are used on the surface of the P-type well region 102 to form the P+ type contact region 103 and the N+ type region 104. In this embodiment, the curvature of the pointed structures of the P+ type contact region 103 and the N+ type region 104 are adjustable, and are not limited to the curvature values specified in the drawings of this embodiment.
[0045] As mentioned above, this embodiment also has a lower breakdown trigger condition, reduces the possibility of tunneling effect in the PN junction, and makes the breakdown mechanism of the device still mainly avalanche breakdown under the condition of low breakdown voltage, thereby reducing leakage current.
[0046] As an example, as shown in FIG. 3(a)-(c), this embodiment also provides a method for manufacturing the layout structure, which specifically includes the following steps:
[0047] (1) As shown in FIG. 3( a ), an N-type substrate 101 is prepared;
[0048] (2) As shown in FIG. 3( b ), a P-type well region 102 is formed by ion implantation and thermal diffusion processes;
[0049] (3) performing high energy ion implantation in a designated area of the P-type well region 102;
[0050] (4) As shown in FIG. 3( c ), a high temperature rapid annealing process is used to form a P+ type contact region 103 and an N+ type region 104 having a certain curvature or shape at the edge on the P-type well region 102 ;
[0051] (5) Subsequent processing to form a PN junction structure with low leakage and low breakdown voltage.
[0052] Embodiment three:
[0053] In another embodiment, as shown in FIG. 4( e), the layout structure includes: an N-type substrate 201, a P-type well region 202, a P+ type contact region 203 and an N+ type region 204, wherein the N+ type region 204 is a triangular structure in a top view, with one corner facing the P+ type contact region 203, and the cross-sectional area decreases as the depth increases, so that the side view of the N+ type region 204 is wide at the top and narrow at the bottom, and the whole constitutes a triangular pyramid structure. Correspondingly, the structure of the P+ type contact region 203 is an inwardly concave bevel shape corresponding to the N+ type region 104. Among them, the P-type well region 202 is formed on the N-type substrate 201. Ion implantation and other processes are used on the surface of the P-type well region 202 to form the P+ type contact region 203 and the N+ type region 204. In this embodiment, the curvature of the pointed structure of the P+ type contact region 203 and the N+ type region 204 is adjustable, and is not limited to the curvature value specified in the drawings of this embodiment.
[0054] As mentioned above, this embodiment also has a lower breakdown trigger condition, reduces the possibility of tunneling effect in the PN junction, and makes the breakdown mechanism of the device still mainly avalanche breakdown under the condition of low breakdown voltage, thereby reducing leakage current.
[0055] As an example, as shown in FIG. 4(a)-(e), this embodiment also provides a method for manufacturing the layout structure, which specifically includes the following steps:
[0056] (1) As shown in FIG. 4( a ), an N-type substrate 201 is prepared;
[0057] (2) As shown in FIG. 4( b ), a P-type well region 202 is formed by ion implantation and thermal diffusion processes;
[0058] (3) As shown in FIG. 4( c ), the first ion implantation is performed in a designated area of the P-type well region 202 ;
[0059] (4) As shown in FIG. 4( d ), a different mask is used to perform a second ion implantation in a designated area of the P-type well region 202 ;
[0060] (5) Using a different mask, a third ion implantation is performed in a designated area of the P-type well region 202;
[0061] (6) As shown in FIG. 4( e ), a high temperature rapid annealing process is used to form a P+ type contact region 203 and an N+ type region 204 having a certain curvature or shape at the edge on the P type well region 202 ;
[0062] (7) Subsequent processing to form a PN junction structure with low leakage and low breakdown voltage.
[0063] Embodiment 4:
[0064] In another embodiment, as shown in FIG. 5( f), the layout structure includes: an N-type substrate 301, a P-type well region 302, a P+ type contact region 307 and an N+ type region 308 formed by a precipitation process, wherein the N+ type region 308 is a triangular structure in a top view, and one corner faces the P+ type contact region 307. Correspondingly, the P+ type contact region 307 structure is an inwardly concave bevel shape corresponding to the N+ type region 308. The P-type well region 302 is formed on the N-type substrate 301. The P+ type contact region 307 and the N+ type region 308 are formed by trenching, deposition and other processes on the surface of the P-type well region 302. In this embodiment, the curvature of the pointed structures of the P+ type contact region 307 and the N+ type region 308 are adjustable, and are not limited to the curvature values specified in the drawings of this embodiment.
[0065] As mentioned above, this embodiment also has a lower breakdown trigger condition, reduces the possibility of tunneling effect in the PN junction, and makes the breakdown mechanism of the device still mainly avalanche breakdown under the condition of low breakdown voltage, thereby reducing leakage current.
[0066] As an example, as shown in FIG. 5( a)-(e), this embodiment further provides a method for manufacturing the layout structure using a trench process, which specifically includes the following steps:
[0067] (1) As shown in FIG. 5( a ), an N-type substrate 301 is prepared;
[0068] (2) As shown in FIG. 5( b ), a P-type well region 302 is formed by ion implantation and thermal diffusion processes;
[0069] (3) As shown in FIG. 5( c ), a groove is dug in a designated area of the P-type well region 302 by an etching process to form the desired window shapes of the P+ type contact region 307 and the N+ type region 308 , i.e., a P-type groove and an N-type groove;
[0070] (4) As shown in FIG. 5( d ), P-type doped and N-type doped polysilicon are deposited in the formed P-type groove and N-type groove, respectively;
[0071] (5) As shown in FIG. 5( e ), a P+ contact region 307 and an N+ region 308 are formed with edges having a certain curvature or shape through a thermal diffusion process;
[0072] (6) As shown in FIG. 5( f ), subsequent processing such as etching polysilicon and depositing metal forms a PN junction structure with low leakage and low breakdown voltage.
[0073] Embodiment five:
[0074] In yet another embodiment, Figure 6As shown, when forming the N+ type region 34, the top view structure of the region is set to a trapezoidal structure. At the same time, in order to adapt to the trapezoidal N+ type region 34, the structure of the P+ type contact region 33 is changed to a corresponding concave bevel shape. The curvature of the trapezoidal structure in this deformed structure is adjustable, and is not limited to the curvature value specified in the drawings of this embodiment.
[0075] Embodiment six:
[0076] In yet another embodiment, Figure 7 As shown, when forming the N+ type region 44, the N+ type region 44 is set to an arc-shaped structure on the side facing the P+ type contact region 43. In this embodiment, the P+ type contact region 43 structure is a rectangular parallelepiped structure in the prior art. In other embodiments, the P+ type contact region 43 can also be set to an inwardly concave arc shape to correspond to the outwardly convex arc shape of the N+ type region 44. The curvature of the arc-shaped structure in this deformed structure is adjustable, and is not limited to the curvature value specified in the drawings of this embodiment.
[0077] Embodiment seven:
[0078] like Figure 8 As shown, this embodiment provides a low leakage, low breakdown voltage NPN transistor layout structure, including: a P-type substrate 51, an N-type epitaxial layer 52, a P-type well region 53, a P+ type contact region 54 and an N+ type region 55, and the N+ type region 55 further includes an N-type fold line region 56 with a fold line edge on the side facing the P+ type contact region 54. Among them, the N-type epitaxial layer 52 and the P-type well region 53 are formed on the P-type substrate 51. Ion implantation and other processes are used on the surface of the P-type well region 53 to form the P+ type contact region 54 and the N+ type region 55 with a fold line edge N-type fold line region 56.
[0079] As an example, this embodiment also provides a method for manufacturing a low leakage, low breakdown voltage NPN transistor, comprising the following steps:
[0080] (1) Preparing a P-type substrate 51;
[0081] (2) growing an N-type epitaxial layer 52 through an epitaxial process;
[0082] (3) forming a P-type well region 53 through ion implantation and thermal diffusion processes;
[0083] (4) performing multiple ion implantations in a designated area of the P-type well region 53;
[0084] (5) high temperature rapid annealing process to form a P+ type contact region 54 and an N+ type region 55 with a certain curvature or shape at the edge;
[0085] (6) Subsequent processing to form an NPN transistor structure with low leakage and low breakdown voltage.
[0086] Embodiment eight:
[0087] like Fig. 9 As shown, this embodiment provides a SCR layout structure with low trigger voltage and low leakage current: P-type substrate 61, N-type well region 62, P-type well region 63, first P+ region 64, first N+ region 65, second P+ region 66, second N+ region 67 and P-type Zener doping region 68, and an N+ region 69 with a certain curvature or shape is also provided at the junction of the N-type well region 62 and the P-type Zener doping region 68. Among them, the N-type well region 62 and the P-type well region 63 are formed by implantation on the P-type substrate 61. The first P+ region 64 and the first N+ region 65 are formed on the surface of the N-type well region 62. The second P+ region 66 and the second N+ region 67 are formed on the surface of the P-type well region 63. The P-type Zener doping region 68 is formed by implantation on the surface of the P-type well region 63. The N+ region 69 with a certain curvature or shape is also formed at the junction of the N-type well region 62 and the P-type Zener doping region 68 by ion implantation and annealing.
[0088] For the SCR device using the layout structure of this embodiment, when a certain forward voltage is applied to it, the peak of the edge of the P-type Zener doped junction will be induced to break down before the non-peak, so that the SCR device with this structure has a lower triggering condition than the SCR without this structure. This structure eliminates the need to reduce the breakdown voltage by increasing the impurity concentration of the P-type well region, reduces the possibility of tunneling effect in the P-type Zener doped junction, and makes the breakdown mechanism of the device still mainly avalanche breakdown under the condition of low breakdown voltage, and reduces the leakage current of the device.
[0089] As an example, this embodiment also provides a method for manufacturing a low leakage and low breakdown voltage SCR structure, comprising the following steps:
[0090] (1) Preparing a P-type substrate 61;
[0091] (2) Forming an N-type well region 62 and a P-type well region 63 through ion implantation and thermal diffusion processes;
[0092] (3) performing multiple ion implantations in designated areas of the N-type well region 62 and the P-type well region 63 to form a first P+ region 64, a first N+ region 65, a second P+ region 66 and a second N+ region 67;
[0093] (4) forming a P-type Zener doped region 68 in a designated area of the P-type well region 63 by ion implantation and thermal diffusion processes;
[0094] (5) Using a high temperature rapid annealing process, an N+ region 69 having a certain curvature or shape is formed at the junction of the N-type well region 62 and the P-type Zener doping region 68;
[0095] (6) Subsequent processing to form an SCR structure with low leakage and low breakdown voltage.
[0096] In summary, the present invention proposes a layout structure of a low leakage, low breakdown voltage PN junction and its manufacturing scheme, which can not only reduce the breakdown voltage, but also achieve lower leakage current by changing the layout shape of the N-type region. For different processes and application scenarios, embodiments of structures with different layout shapes are given, and the curvature and shape of the layout structure are adjustable, and are not limited to the morphologies listed in the embodiments of the present invention. And on the basis of the PN junction layout, a triode layout structure with low breakdown voltage and an SCR layout structure with low trigger voltage are further proposed. Therefore, the new structure and manufacturing method proposed in the present invention are very suitable for applications with low voltage triggering requirements.
[0097] The device structure, manufacturing method and drawings proposed in the present invention are only a display and explanation of the low leakage and low breakdown voltage layout structure. In addition to the structure in the drawings, anyone familiar with this technology can modify or change the above structure without violating the spirit and scope of the present invention, such as changing the SCR structure described above to a PNP structure, a diode structure, a MOS structure, etc., or changing the number of stacked series or stacked packages according to different application scenarios, and these structures should obviously be within the protection scope of the present invention.
[0098] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. The protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the present technical field may modify or change the above embodiments without violating the spirit and scope of the present invention, and may easily conceive of changes or substitutions, which shall be within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims
1. A PN junction layout structure, comprising an N-type substrate, a P-type well region, a P+ type contact region and an N+ type region, characterized in that: The processing technology is used to make the N+ type region have a variable curvature on a side facing the P+ type contact region.
2. A PN junction layout structure as claimed in claim 1, characterized in that: The N+ type region has an N type fold line region.
3. A PN junction layout structure as claimed in claim 1, characterized in that: The N+ type region is a triangular structure, a trapezoidal structure or an arc structure in a top view.
4. A PN junction layout structure as claimed in claim 3, characterized in that: The N+ type region forms a triangular pyramid structure, and the cross-sectional area decreases as the depth increases, so that the side view of the N+ type region presents a shape that is wide at the top and narrow at the bottom.
5. A PN junction layout structure as claimed in claim 1, characterized in that: The P+ type contact region has a concave structure corresponding to the curvature of the N+ type region on a side facing the N+ type region.
6. A method for manufacturing the PN junction layout structure as claimed in claims 1 to 5, characterized in that: The following steps are involved: (1) Preparing an N-type substrate; (2) forming a P-type well region through ion implantation and thermal diffusion processes; (3) performing a process on a designated area of the P-type well region to form the P+-type contact region and the N+-type region; (4) Subsequent processing to form a PN junction structure with low leakage and low breakdown voltage.
7. The method according to claim 6, characterized in that The process includes multiple ion implantation and high temperature rapid annealing process.
8. The method according to claim 6, characterized in that The process includes a trench process.
9. An NPN transistor layout structure, comprising a P-type substrate, an N-type epitaxial layer, a P-type well region, a P+ type contact region and an N+ type region, characterized in that: The N+ type region further includes an N type fold line region with a fold line edge on a side facing the P+ type contact region.
10. An SCR layout structure, comprising a P-type substrate, an N-type well region, a P-type well region, a first P+ region 64, a first N+ region, a second P+ region, a second N+ region and a P-type Zener doped region, characterized in that: An N+ region with a certain curvature or shape is also provided at the junction of the N-type well region and the P-type Zener doping region.