Schottky diode element and its manufacturing method
By adopting wafer-level wafer packaging technology and horizontal structure in Schottky diode components, combined with the design of the backside metal film, the problems of poor heat dissipation and large reverse leakage current of traditional Schottky diode components are solved, and more efficient heat dissipation and low reverse leakage current are achieved.
Patent Information
- Application Number
- CN202311258070.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-27
- Publication Date
- 2025-04-04
AI Technical Summary
Traditional Schottky diode components have problems such as poor heat dissipation and large reverse leakage current, which limits their application range.
The wafer-level wafer packaging technology is used to design the anode and cathode structures as horizontal, the lead frame and sealing process are eliminated, and the backside metal film is used to reduce the equivalent resistance inside the wafer.
It achieves better heat dissipation and low reverse leakage current, reducing the overall component thickness and reducing the forward voltage.
Smart Images
Figure CN119767697A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a Schottky diode component and a manufacturing method thereof, and more particularly to a Schottky diode component with better heat dissipation effect and low reverse leakage current (low IR) and a manufacturing method thereof. Background Art
[0002] Schottky diodes use metal-semiconductor junctions to achieve high-speed switching, and are therefore widely used in power rectifiers. However, Schottky diodes still have the disadvantage of large reverse leakage current, which limits their application.
[0003] Traditional Schottky diode packaging components such as Figure 7 As shown, a diode chip 71 is included. The diode chip 71 is a vertical structure, having an N-type doped layer 72 and a metal layer 73. The metal layer 73 is formed on the bottom surface of the N-type doped layer 72, and the junction surface between the two has the characteristics of a Schottky barrier.
[0004] The Schottky diode chip 71 needs to be packaged using a packaging process, the metal layer 73 is set on a first pin 74 formed by a lead frame, and then a contact on the surface of the N-type doped layer 72 is electrically connected to a second pin 75 formed by the lead frame through a lead line, and finally the Schottky diode chip 71 is covered with a sealing layer 76.
[0005] The conventional Schottky diode package components use the steps of die bonding, lead wire, and sealant coating, and the diode chip 71 is coated by the sealant layer 76, resulting in poor heat dissipation. In addition, many factors such as the thickness of the lead frame, the line height of the lead wire, and the thickness of the sealant layer 76 will make it difficult to reduce the overall thickness of the package component. Summary of the invention
[0006] In view of this, the main object of the present invention is to provide a Schottky diode element and a manufacturing method thereof, which can have better heat dissipation effect and low reverse leakage current.
[0007] To achieve the above-mentioned object, the Schottky diode element of the present invention comprises:
[0008] A substrate is formed with an epitaxial layer, a cathode region and an anode region are defined on the surface of the epitaxial layer, a cathode structure is formed in the cathode region, and an anode structure is formed in the anode region; a back metal film is formed on a back surface of the substrate, and a back protective layer covers the surface of the back metal film;
[0009] The cathode structure comprises:
[0010] An N-type heavily doped region diffusely extends from the surface of the epitaxial layer toward the inner side of the substrate;
[0011] An N-type lightly doped region is formed in the epitaxial layer and surrounds the N-type heavily doped region N+;
[0012] a cathode contact formed above and in contact with the N-type heavily doped region and comprising a stacked metal material;
[0013] The anode structure comprises:
[0014] A plurality of P-type doping regions, each of which diffuses and extends from the surface of the epitaxial layer to the inner side of the substrate, and adjacent P-type doping regions are separated by an injection spacing;
[0015] An anode contact is formed above the plurality of P-type doping regions and contacts the plurality of P-type doping regions, wherein the anode contact protrudes from the surface of the substrate and comprises stacked metal materials.
[0016] The Schottky diode element manufacturing method of the present invention comprises:
[0017] A substrate is prepared, an epitaxial layer is formed on the surface of the substrate, and a cathode region and an anode region are defined on the surface of the epitaxial layer;
[0018] Forming an N-type heavily doped region and an N-type lightly doped region in the cathode region of the substrate, wherein the N-type heavily doped region diffuses and extends from the surface of the epitaxial layer to the inner side of the substrate, and the N-type lightly doped region is located in the epitaxial layer and surrounds the N-type heavily doped region;
[0019] A plurality of P-type doping regions are formed in the anode region of the substrate, each of the P-type doping regions diffuses and extends from the surface of the epitaxial layer to the inner side of the substrate, and adjacent P-type doping regions are separated by an implantation spacing;
[0020] Forming a metal silicide film on the N-type heavily doped region and on the plurality of P-type doped regions respectively;
[0021] forming a cathode conductive layer on the metal silicide film above the N-type heavily doped region, and forming an anode conductive layer on the metal silicide film above the plurality of P-type doped regions;
[0022] Forming a surface insulating layer on the surface of the epitaxial layer, the surface insulating layer insulating and isolating the cathode conductive layer and the anode conductive layer;
[0023] Forming a contact metal layer on the surface of the cathode conductive layer and the surface of the anode conductive layer respectively;
[0024] A back metal film is completely formed on the back side of the substrate, and the back metal film is not electrically connected to the contact metal layer;
[0025] forming a back side protection layer on the surface of the back side metal film;
[0026] The substrate is cut into pieces to form a plurality of separate Schottky diode elements.
[0027] The anode structure of the Schottky diode element of the present invention includes a plurality of densely spaced P-type doping regions, and a plurality of depletion regions can be formed between the P-type doping regions and the N-type substrate. Under reverse bias, the channels between adjacent depletion regions are extremely narrow, so the reverse current can be reduced. The present invention is made by using wafer-level chip packaging (WLCSP) technology, and does not need to use a lead frame and does not need to perform lead and sealing processes, so the overall element thickness can be reduced and the heat dissipation effect can be improved.
[0028] Furthermore, the back metal film is formed on the back of the substrate, and the back metal film provides an impedance with a very small resistance value, so the equivalent resistance inside the chip can be reduced, thereby reducing the forward voltage drop generated when the chip works under the forward bias. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1A to Figure 1F : Schematic diagram of the cathode manufacturing process of Schottky diode chip of the present invention.
[0030] Figure 2A to Figure 2E : Schematic diagram of the anode manufacturing process of Schottky diode chip of the present invention.
[0031] Figure 3A to Figure 3G : Schematic diagram of the packaging process of the Schottky diode chip of the present invention.
[0032] Figure 4 : A schematic diagram of the structural cross section of a Schottky diode of the present invention.
[0033] Figure 5 : Schematic diagram of the reverse current distribution when a reverse voltage is applied to the present invention.
[0034] Figure 6 : Schematic diagram of the distribution of forward current of the present invention.
[0035] Figure 7 : A cross-sectional schematic diagram of an existing Schottky diode packaging component. DETAILED DESCRIPTION
[0036] The present invention is a Schottky diode having an anode and a cathode, wherein the anode and the cathode are both formed on the same side of a substrate, so that the anode and the cathode are distributed in a horizontal structure rather than a traditional vertical structure. The following is a process for explaining the manufacturing process of the anode and the cathode, which is not limited to being performed in sequence, and the present invention uses wafer-level chip packaging technology (WLCSP) to directly complete the manufacturing of Schottky diode components on a wafer.
[0037] Cathode process:
[0038] Please refer to Figure 1A First, a semiconductor substrate 100 is prepared. The substrate 100 may be a silicon substrate. A cathode region (N) and an anode region (P) are defined on the substrate 100 to form the cathode and anode of the wafer, respectively. In this embodiment, an epitaxial layer 102 is formed on the surface of the substrate 100, and an oxidation protection layer 104 is formed on the epitaxial layer 102.
[0039] Please refer to Figure 1B As shown, the local oxidation protection layer 104 in the cathode area (N) is removed by a development and etching process to form a cathode pattern window 106, so that the epitaxial layer 102 is directly exposed from the cathode pattern window 106; the oxidation protection layer 104 in the anode area (P) still completely covers the substrate 100.
[0040] Please refer to Figure 1C As shown, the substrate 100 is doped with a high concentration of N-type doping material by ion implantation, for example, phosphorus (P) ions are implanted into the substrate 100, and the area not covered by the oxidation protection layer 104 will have the N-type doping material. As shown in the figure, the N-type doping material will be implanted into the epitaxial layer 102 exposed by the cathode pattern opening 106, and a first implantation region 108 will be formed in the epitaxial layer 102.
[0041] Please refer to Figure 1D As shown, a deposition process is performed on the substrate 100 , and the material of the first dielectric layer 110 can be tetraethoxysilane (TEOS).
[0042] Please refer to Figure 1E As shown, the substrate 100 is annealed so that the N-type doping material in the first injection region 108 is evenly distributed outward through thermal diffusion to form an N-type heavily doped region N+. The substrate 100 is patterned to remove the oxidation protection layer 104 and the first dielectric layer 110 around the N-type heavily doped region N+, exposing the epitaxial layer 102 and the N-type heavily doped region N+ in the cathode region (N). In addition to the cathode region (N), the patterning step also removes the oxidation protection layer 104 and the first dielectric layer 110 around the anode region (P).
[0043] Please refer to Figure 1FAs shown, the substrate 100 is doped with low-concentration ion implantation of N-type doping material, and the N-type doping material is implanted into the areas not covered by the oxidation protection layer 104 and the first dielectric layer 110, including the epitaxial layer 102 and the N-type heavily doped area N+, to form an N-type lightly doped area N- with a relatively low doping concentration in these areas; the N-type doping material used can be phosphorus (P) ions, and its concentration is lower than the ion concentration implanted into the N-type heavily doped area N+.
[0044] In this embodiment, after the cathode region (N) is preliminarily completed, the process of the anode region (P) is continued; in other embodiments, the anode region (P) may be manufactured first and then the cathode region (N) is continued.
[0045] Anode process:
[0046] Please refer to Figure 2A As shown, a second dielectric layer 116 is covered on the surface of the substrate 100. The material of the second dielectric layer 116 can be tetraethoxysilane (TEOS). The second dielectric layer 116 overlaps and covers the original first dielectric layer 110 and the N-type lightly doped region N-. For the convenience of subsequent description, the first dielectric layer 110 and the second dielectric layer 116 are combined and referred to as a dielectric protection layer 120.
[0047] Please refer to Figure 2B As shown, a patterning step is performed on the dielectric protection layer 120 and the oxidation protection layer 104 on the anode region (P) so that the dielectric protection layer 120 and the oxidation protection layer 104 form a plurality of vertical gate-like barriers 200, and a groove 202 is formed between adjacent gate-like barriers 200, and the bottom of each groove 202 exposes the epitaxial layer 102 of the substrate 100; wherein, the dielectric protection layer 120 and the oxidation protection layer 104 adjacent to the cathode region (N) are still retained on the substrate 100, serving as an insulating barrier layer between the anode and the cathode.
[0048] Please refer to Figure 2C As shown, high-concentration P-type doping is performed on the substrate 100 of the anode area (P), for example, boron (B) ions are implanted into the substrate 100, so that the P-type doping material is implanted into the epitaxial layer 102 at the bottom of the trench 200, and a plurality of adjacent spaced P-type doping regions P+ are formed inside the epitaxial layer 102, and two adjacent P-type doping regions P+ are separated by an implantation spacing.
[0049] Please refer to Figure 2DAs shown, the gate barrier 202 in the anode region (P) is etched away, wherein the dielectric protection layer 120 and the oxidation protection layer 104 adjacent to the cathode region (N), and the dielectric protection layer 120 and the oxidation protection layer 104 at the edge of the anode region (P) are still retained on the substrate 100. A metal silicide film MS is formed on the surface of the epitaxial layer 102 exposed in the cathode region (N) and the anode region (P) respectively, so as to effectively reduce the subsequent junction resistance with the metal material. After the metal silicide film MS is formed, a third dielectric layer 122 can be further formed on the surface of the dielectric protection layer 120, wherein the third dielectric layer 122 is also present on the peripheral surface of the metal silicide film MS in the anode region (P).
[0050] Refer to Figure 2E As shown, an anode conductive layer PM and a cathode conductive layer NM are respectively formed on the surface of the metal silicide film MS in the anode region (P) and the cathode region (N). The anode conductive layer PM and the cathode conductive layer NM can be formed by stacking metal layers of a composite material. In one embodiment, the anode conductive layer PM and the cathode conductive layer NM are mainly formed of aluminum (Al) material.
[0051] In completion Figure 2E After the steps, the basic structure of the Schottky diode chip of the present invention has been roughly completed. Next, the present invention will further explain how to complete the packaging product through wafer-level chip packaging technology (WLCSP). In order to clearly show the packaging process, the following description and drawings will simplify some of the aforementioned components or material layers.
[0052] Please refer to Figure 3A For each Schottky diode chip, a surface dielectric layer 300 is covered in the area other than the anode conductive layer PM and the cathode conductive layer NM. The surface dielectric layer 300 can be formed by a patterned polyimide film (PI).
[0053] Please refer to Figure 3B A seed layer 302 is pre-formed on the surface of the substrate 100. In this embodiment, a seed layer 302 of titanium or copper material is formed by sputtering. The seed layer 302 fully covers the anode conductive layer PM, the cathode conductive layer NM and the surface dielectric layer 300.
[0054] Please refer to Figure 3CAfter the seed layer 302 is formed, a contact metal layer 304 is formed by electroplating on the surface of the seed layer 302. The contact metal layer 304 may be made of copper, and a layer of tin film (not shown) may be electroplated on the surface of the contact metal layer 304. After the contact metal layer 304 is fully formed, it is patterned. This step will retain the contact metal layer 304 in the area above the anode conductive layer PM and the cathode conductive layer NM, while the contact metal layer 304 and the seed layer 302 in the remaining area will be etched away together.
[0055] Please refer to Figure 3D , flip the substrate 100 and perform a planarization operation on the back side thereof, for example, mechanically polish the back side of the substrate 100 to form a flat surface on the back side thereof and control the entire substrate 100 to be reduced to a desired thickness.
[0056] Please refer to Figure 3E and Figure 3F A back metal film 306 is formed on the back of the substrate 100 after the planarization operation has been completed. In this embodiment, a titanium-nickel-silver or titanium-copper metal film is formed by sputtering. The back metal film 306 covers the entire back of the substrate 100. A back protective layer 308 is formed on the surface of the back metal film 306. The surface of the back protective layer 308 can be laser engraved to form a specified identification pattern or text. The main function of the back metal film 306 of the present invention is to reduce the forward voltage of the diode, rather than serving as a contact point for external connection like a traditional Schottky diode. Therefore, the back metal film 306 will not be electrically connected to the anode conductive layer PM.
[0057] Please refer to Figure 3G The substrate 100 that has completed the back side process is temporarily attached to a carrier film T with the back side protection layer 308, and cut along the cutting line between adjacent Schottky diode chips to obtain a plurality of separated Schottky diode chips.
[0058] Please refer to Figure 4 As shown, after the above-mentioned process is completed, the Schottky diode element structure of the present invention includes:
[0059] A substrate 100 is formed with an epitaxial layer 102, the surface of the epitaxial layer 102 is used as a contact connection surface, and a cathode region (N) and an anode region (P) are defined on the contact connection surface, a cathode structure is formed in the cathode region (N), and an anode structure is formed in the anode region (P); a back side of the substrate 100 is completely covered with a back side metal film 306, and a back side protective layer 308 is formed on the surface of the back side metal film 306; and the four sides of the substrate 100 are directly exposed and are not covered by any sealing layer;
[0060] The cathode structure comprises:
[0061] An N-type heavily doped region N+ diffuses and extends from the surface of the epitaxial layer 102 to the inner side of the substrate 100;
[0062] an N-type lightly doped region N− formed in the epitaxial layer 102 and surrounding the N-type heavily doped region N+, wherein the doping concentration in the N-type lightly doped region N− is lower than the doping concentration in the N-type heavily doped region N+, and the extension depth of the N-type lightly doped region N− is lower than the extension depth of the N-type heavily doped region N+;
[0063] A cathode contact 400 is formed above the N-type heavily doped region N+ and in contact therewith. The cathode contact 400 protrudes from the surface of the substrate 300 and includes stacked metal material layers, such as a metal silicide film MS, a cathode conductive layer NM mainly made of aluminum material, and a contact metal layer 304.
[0064] The anode structure comprises:
[0065] A plurality of P-type doped regions P+, each of which diffuses and extends from the surface of the epitaxial layer 102 to the inner side of the substrate 100, and adjacent P-type doped regions P+ are separated by an injection spacing; and the outermost P-type doped region P+ is separated from the N-type lightly doped region N- by a lateral spacing d;
[0066] An anode contact 500 is formed above the multiple P-type doped regions P+ and in contact with the P-type doped regions P+, wherein the anode contact 500 protrudes from the surface of the substrate 300 and includes stacked metal material layers, such as a metal silicide film MS, an anode conductive layer PM mainly made of aluminum material, and a contact metal layer 304.
[0067] The cathode structure and the anode structure are insulated and isolated, specifically, a surface insulating layer is provided on the surface of the substrate 300, and the surface insulating layer surrounds the cathode structure and the anode structure. The surface insulating layer mainly includes the surface dielectric layer 300 in the aforementioned process, and a composite dielectric layer 600 composed of multiple layers such as the oxidation protection layer 104, the first dielectric layer 110, the second dielectric layer 116, and the third dielectric layer 122 in the aforementioned process.
[0068] Please refer to Figure 5 As shown, when a reverse bias is applied to the present invention, the reverse current IR flows from the N-type material region to the P-type material region. Because the present invention provides a plurality of densely spaced P-type doped regions P+ in the N-type epitaxial layer in terms of the anode structure, a plurality of depletion regions are naturally formed between the P / N materials, and the channel width between these depletion regions DR is relatively reduced or even clamped, thereby achieving the purpose of reducing the reverse current.
[0069] Please refer to Figure 6 As shown, when a forward bias is applied between the anode and the cathode, a forward current IF will be generated inside the chip. The equivalent resistance Rt inside the chip can be expressed as follows:
[0070] Rt=R1+Rbase+R2
[0071] Among them, R1 can be regarded as the equivalent resistance between the anode contact 500 and the substrate 100; R2 is the equivalent resistance between the cathode contact 400 and the substrate. Rbase is regarded as the equivalent resistance after R3 and R4 are connected in parallel, R3 refers to the impedance of the substrate 100 itself (i.e., the impedance of the silicon substrate itself); and R4 is the resistance of the back metal film 306 formed on the back of the substrate 100. Because the resistance of the metal film 306 is extremely small, when R3 and R4 are connected in parallel, the Rbase will be smaller than the impedance value of the single R3. In other words, by forming the back metal film 306 on the back of the substrate 100, the overall Rbase value can be reduced.
[0072] Once Rbase can be effectively reduced, the equivalent resistance Rt inside the chip can also be reduced accordingly, and the forward voltage VF of the chip = IF×Rt, so the forward voltage value of the present invention can also be effectively reduced.
[0073] In summary, the Schottky diode element of the present invention has the following characteristics:
[0074] 1. The anode structure and the cathode structure are arranged horizontally on the same surface of the substrate, and the present invention adopts wafer-level chip packaging. The present invention can be directly welded on a circuit board without using a lead frame, and without the need for lead wire and sealing processes.
[0075] 2. Since the chip is not covered with a traditional molding compound, the heat dissipation efficiency of the chip can be improved.
[0076] 3. The anode structure includes a plurality of densely spaced P-type doped regions. The P-type doped regions and the N-type substrate form a plurality of depletion regions that can reduce the reverse current.
[0077] 4. A back metal film is formed on the back of the substrate to reduce the equivalent resistance Rt inside the chip, thereby reducing the forward voltage (VF). The present invention is measured without forming the back metal film and with forming the back metal film. Under the conditions of forward current of 1 ampere and 2 amperes, the forward voltages measured by the two groups of samples are shown in the following table, wherein the back metal film is titanium nickel silver (TiNiAg) material:
[0078] The first set of samples:
[0079]
[0080] The second set of samples:
[0081]
[0082] According to the above test examples, it can be proved that when the backside metal film is provided, the forward voltage can be further reduced.
Claims
1. A Schottky diode element, characterized in that: Contains: A substrate is formed with an epitaxial layer, a cathode region and an anode region are defined on the surface of the epitaxial layer, a cathode structure is formed in the cathode region, and an anode structure is formed in the anode region; a back metal film is formed on a back surface of the substrate, and a back protective layer covers the surface of the back metal film; The cathode structure comprises: An N-type heavily doped region diffusely extends from the surface of the epitaxial layer toward the inner side of the substrate; An N-type lightly doped region is formed in the epitaxial layer and surrounds the N-type heavily doped region N+; a cathode contact formed above and in contact with the N-type heavily doped region and comprising a stacked metal material; The anode structure comprises: A plurality of P-type doping regions, each of which diffuses and extends from the surface of the epitaxial layer to the inner side of the substrate, and adjacent P-type doping regions are separated by an injection spacing; An anode contact is formed above the plurality of P-type doping regions and contacts the plurality of P-type doping regions, wherein the anode contact protrudes from the surface of the substrate and comprises stacked metal materials.
2. The Schottky diode element according to claim 1, wherein: The surface of the substrate has a surface insulating layer, which is arranged between the anode contact and the cathode contact to insulate and isolate the anode contact and the cathode contact; wherein the surface insulating layer extends to be flush with the surrounding sides of the substrate.
3. The Schottky diode element according to claim 2, wherein: The surface insulating layer at least comprises a surface dielectric layer made of polyimide and a dielectric layer made of tetraethoxysilane.
4. The Schottky diode element according to claim 1, wherein: The outermost periphery of the plurality of P-type doped regions is separated from the N-type lightly doped region by a lateral distance.
5. The Schottky diode element according to claim 1, wherein: The substrate is a silicon substrate; The cathode contact includes a metal silicide film, a cathode conductive layer and a contact metal layer; The anode contact includes a metal silicide film, an anode conductive layer and a contact metal layer; The cathode conductive layer and the anode conductive layer include aluminum material; the contact metal layers of the cathode contact and the anode contact include copper material.
6. The Schottky diode element according to claim 1, wherein: The four sides of the substrate are directly exposed to the outside without being covered.
7. A method for manufacturing a Schottky diode element, characterized in that: Include: A substrate is prepared, an epitaxial layer is formed on the surface of the substrate, and a cathode region and an anode region are defined on the surface of the epitaxial layer; Forming an N-type heavily doped region and an N-type lightly doped region in the cathode region of the substrate, wherein the N-type heavily doped region diffuses and extends from the surface of the epitaxial layer to the inner side of the substrate, and the N-type lightly doped region is located in the epitaxial layer and surrounds the N-type heavily doped region; A plurality of P-type doping regions are formed in the anode region of the substrate, each of the P-type doping regions diffuses and extends from the surface of the epitaxial layer to the inner side of the substrate, and adjacent P-type doping regions are separated by an implantation spacing; Forming a metal silicide film on the N-type heavily doped region and on the plurality of P-type doped regions respectively; forming a cathode conductive layer on the metal silicide film above the N-type heavily doped region, and forming an anode conductive layer on the metal silicide film above the plurality of P-type doped regions; Forming a surface insulating layer on the surface of the epitaxial layer, the surface insulating layer insulating and isolating the cathode conductive layer and the anode conductive layer; Forming a contact metal layer on the surface of the cathode conductive layer and the surface of the anode conductive layer respectively; A back metal film is completely formed on the back side of the substrate, and the back metal film is not electrically connected to the contact metal layer; forming a back side protection layer on the surface of the back side metal film; The substrate is cut into pieces to form a plurality of separate Schottky diode elements.
8. The method for manufacturing a Schottky diode element according to claim 7, wherein: An oxide protective layer is formed on the surface of the epitaxial layer; The step of forming the N-type heavily doped region and the N-type lightly doped region further includes: Etching and removing the oxide protection layer in the cathode region to form a cathode pattern opening, so that the epitaxial layer is exposed in the cathode pattern opening; Performing high-concentration ion implantation doping of an N-type doping material on the substrate, so that the N-type doping material is implanted into the epitaxial layer exposed from the cathode pattern opening, so that the epitaxial layer forms a first implantation region; forming a first dielectric layer on the substrate, the first dielectric layer completely covering the oxidation protection layer and the first implantation region; Performing annealing on the substrate to make the N-type doping material of the first implantation region evenly distributed outward to form the N-type heavily doped region; removing the oxide protection layer and the first dielectric layer around the N-type heavily doped region to expose the epitaxial layer and the N-type heavily doped region; The substrate is doped with low-concentration ion implantation of an N-type doping material, and the N-type doping material is implanted into the epitaxial layer around the N-type heavily doped region to form the N-type lightly doped region.
9. The method for manufacturing a Schottky diode element according to claim 8, wherein: The step of forming the plurality of P-type doped regions further comprises: A second dielectric layer is covered on the surface of the substrate, wherein the material of the second dielectric layer is the same as that of the first dielectric layer, wherein the second dielectric layer covers the first dielectric layer and the N-type lightly doped region, and the first dielectric layer and the second dielectric layer are combined into a dielectric protection layer; Performing a patterning step on the anode region so that the dielectric protection layer and the oxidation protection layer thereunder form a plurality of vertical gate-shaped barrier members, a trench is formed between adjacent gate-shaped barrier members, and the bottom of each trench exposes the epitaxial layer of the substrate; Performing high-concentration P-type doping implantation on the substrate, so that the P-type doping material is implanted into the epitaxial layer at the bottom of the trenches to form a plurality of adjacently spaced P-type doping regions; as well as The grid-like barrier in the anode region is removed by etching.
10. The method for manufacturing a Schottky diode element according to claim 9, wherein: The contact metal layer is a copper layer; Before forming the back metal film, a planarization process is performed on the back side of the substrate to reduce the thickness of the substrate; Prior to dicing the substrate, the backside protective layer is laser inscribed.