Method for manufacturing bipolar transistor
By using specific layer stacking and epitaxial growth techniques when manufacturing bipolar transistors, the non-planar layer problem caused by etching thick layer stacking is solved, the contact quality is improved and the formation of smaller cavity is achieved.
Patent Information
- Application Number
- CN202411395750.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-10-01
- Filing Date
- 2024-10-08
- Publication Date
- 2025-04-04
AI Technical Summary
In making bipolar transistors, etching a thick layer stack during the formation of the emitter may result in the formation of non-planar layers, affecting the quality of the contact.
By forming a first layer stack on the substrate, a first layer of base material, and forming a portion of the collector and base in the first cavity, the first and second portions are formed using epitaxial growth techniques, and an insulating layer and emitter layer are formed thereon, partially etching to form an appropriate cavity structure.
This method effectively avoids the formation of non-planar layers, improves the quality of contact, and makes the etching process easier, can form smaller cavity and meets stricter dimensional requirements.
Smart Images
Figure CN119767699A_ABST
Abstract
Description
[0001] Priority claim
[0002] This application claims the benefit of priority of French patent application No. 2310501 filed on October 2, 2023, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field
[0003] The present disclosure relates generally to electronic devices and methods of manufacturing the same, and more specifically to bipolar transistors and methods of manufacturing the same. Background Art
[0004] A bipolar transistor is a semiconductor-based electronic device in the transistor family. Its operating principle is based on two PN junctions, a forward junction and a reverse junction.
[0005] Bipolar transistor manufacturing methods can be problematic. For example, etching a thick layer stack during emitter formation can result in the formation of a non-planar layer. Such a layer can cause problems during contact formation. Summary of the invention
[0006] An embodiment provides a method for manufacturing a bipolar transistor, comprising: a) forming a first layer stack on a substrate, the first layer stack including a first layer made of a material of a base of the bipolar transistor between a second insulating layer and a third insulating layer; b) forming a first cavity passing through the first stack in such a way as to reach the substrate, wherein forming the first cavity includes not etching layers covering the first layer except the third layer; and c) forming a first portion of the collector of the bipolar transistor and a second portion of the base of the bipolar transistor in the first cavity.
[0007] According to an embodiment, the first portion and the second portion are formed by epitaxial growth.
[0008] According to an embodiment, the first portion is closer to the bottom of the first cavity than the second portion.
[0009] According to an embodiment, the method includes: after step c), d) forming a fourth insulating layer covering an upper surface of the third layer and an upper surface of the second portion, the fourth layer including an opening exposing a portion of the upper surface of the second portion.
[0010] According to an embodiment, the fourth layer is planar.
[0011] According to an embodiment, the method comprises, after step d), e) forming a second layer stack comprising a fifth layer made of a material of the emitter of the bipolar transistor and a sixth insulating layer covering the fifth layer.
[0012] According to an embodiment, the fifth layer contacts the fourth layer and fills the opening in the fourth layer.
[0013] According to an embodiment, the thickness of the fifth layer is substantially equal to ten times the thickness of the fourth layer.
[0014] According to an embodiment, the method includes partially etching the fourth layer, the fifth layer, and the sixth layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the remainder of this disclosure of specific embodiments, which are given by way of illustration and not limitation with reference to the accompanying drawings, in which:
[0016] Figure 1 shows a device resulting from the steps of a bipolar transistor fabrication method;
[0017] Figure 2 shows a device resulting from another step of the bipolar transistor manufacturing method;
[0018] Figure 3 shows a device resulting from another step of the bipolar transistor manufacturing method;
[0019] Figure 4 shows a device resulting from another step of the bipolar transistor manufacturing method;
[0020] Figure 5 shows a device resulting from another step of the bipolar transistor manufacturing method;
[0021] Figure 6 shows a device resulting from another step of the bipolar transistor manufacturing method;
[0022] Figure 7 shows a device resulting from another step of the bipolar transistor manufacturing method;
[0023] Figure 8 shows a device resulting from another step of the bipolar transistor manufacturing method;
[0024] Fig. 9 shows a device resulting from another step in the bipolar transistor manufacturing method; and
[0025] Fig.10 A device resulting from another step of the bipolar transistor manufacturing method is shown. DETAILED DESCRIPTION
[0026] In the various drawings, similar features are designated by similar reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals, and may be provided with the same structure, dimensions, and material properties.
[0027] For clarity, only the steps and elements that are useful for understanding the described embodiments are illustrated and described in detail.
[0028] Unless otherwise indicated, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.
[0029] In the following description, when reference is made to terms that modify absolute positions (such as terms “front”, “back”, “top”, “bottom”, “left side”, “right side”, etc.) or relative positions (such as terms “above”, “below”, “upper”, “lower”, etc.) or terms that modify directions (such as terms “horizontal”, “vertical”, etc.), unless otherwise specified, this refers to the orientation of the drawing.
[0030] Unless otherwise specified, the expressions "around", "approximately", "substantially" and "about" mean plus or minus 10%, preferably plus or minus 5%.
[0031] Unless otherwise specified, the expressions “conductive” and “insulating” mean “electrically conductive” or “electrically insulating”.
[0032] Figures 1 to 10 Steps, preferably consecutive steps, of a method of manufacturing a bipolar transistor 10 are shown.
[0033] Figure 1 The device resulting from the steps of the method of manufacturing a bipolar transistor 10 is shown.
[0034] During this step, a substrate 12 is formed. The substrate 12 forms a substrate inside and on top of which the transistor 10 will be formed. The substrate 12 is made of, for example, a semiconductor material, for example, silicon, for example, silicon doped with an N-type dopant. For example, a portion of the substrate corresponds to a portion of the collector of the bipolar transistor 10.
[0035] Figure 1 The step of forming the insulating trench 14 includes, for example, forming an insulating trench 14. The trench 14 is, for example, a simple shallow insulating trench (SSTI). The trench 14 corresponds to an insulating region located in the substrate 12, preferably at the surface of the substrate 12. Therefore, the upper surface of the trench 14 is coplanar with the upper surface of the substrate 12. The region 14 is preferably made of an oxide, such as silicon oxide.
[0036] Figure 1The step of forming the insulating layer 16 on the structure also comprises forming an insulating layer 16. More precisely, the layer 16 covers the substrate 12 and the upper surface of the trench 14. The layer 16 preferably completely covers the trench 14. The layer 16 is preferably in contact with the trench 14 and the substrate 12. The layer 16 is preferably made of the same material as the region 14. The sum of the thicknesses of the layer 14 and the trench 14 is preferably less than 70 nm, for example substantially equal to 50 nm.
[0037] Figure 1 The step of forming the layer 18 also includes forming the layer 18. The layer 18 is made of the base material of the transistor 10. The layer 18 is made of a semiconductor material, for example. The layer 18 is made of polysilicon, for example P-type doped. The layer 18 covers at least the trench 14. The layer 18 is preferably in contact with the layer 16. The layer 18 preferably extends over the entire layer 16.
[0038] Figure 1 The step of forming the layer 20 also includes forming the layer 20. The layer 20 is made of a single material (preferably a homogeneous material). The layer 20 is preferably a single layer and is preferably not formed by other layers. The layer 20 is an insulating layer. The layer 20 is made of, for example, silicon nitride. Advantages of using a single layer of homogeneous material for the layer 20 include: simplified integration; reduced cost; reduced variability in stack thickness because a single deposit can be used; improved uniformity when etching between different geometries (compared to a stack of layers that requires different etching chemistries with different etching rates depending on the component geometry); and no interface between different materials is required.
[0039] Layer 20 covers at least trench 14. Preferably, layer 20 extends over the entire layer 18. Layer 20 is located on and in contact with layer 18. Preferably, layer 20 is not separated from layer 18 by another layer or layer portion, even if only partially.
[0040] The sum of the thicknesses of trench 14 and layers 16, 18 and 20 is preferably less than 230 nm, preferably less than 200 nm, preferably less than or substantially equal to 150 nm.
[0041] Figure 2 A device resulting from another step of the method of manufacturing the bipolar transistor 10 is shown.
[0042] Figure 2 The step of etching the structure to reach the substrate 12 at the level of the trench 14. In other words, Figure 2 The step of forming the cavity 22 comprises forming a cavity 22. The cavity 22 passes through the stack including the layers 16, 18, 20 and the trench 14. Thus, the cavity reaches the substrate 12. Thus, the bottom of the cavity 22 is formed by a portion of the substrate 12. The bottom of the cavity 22 is preferably substantially coplanar with the lower surface of the trench 14.
[0043] The stack preferably comprises no further layers than the layers 16, 18, 20 and the trench 14. The stack comprises a single layer, namely the layer 20 above the layer 18. In other words, during the step of etching the stack, the layer 18 is only covered by the insulating layer 20, e.g. at least in front of the trench 14, e.g. at least in front of the location of the bipolar transistor. The etching step of step 2 comprises not etching the layers covering the layer 18 except the layer 20.
[0044] The height of the cavity 22 is preferably less than 230 nm, preferably less than 200 nm, preferably less than or substantially equal to 150 nm.
[0045] Figure 2 The step of forming the cavity 22 may optionally include forming spacers 24. The spacers 24 are located on the lateral walls of the cavity 22. The spacers cover the lateral walls of the layers in the cavity 22. Thus, the layers 16, 18, 20 forming the walls of the cavity 22 and the lateral walls of the trench 14 are covered by the spacers 24, for example completely covered.
[0046] Figure 3 A device resulting from another step of the bipolar transistor manufacturing method is shown.
[0047] Figure 3 The step includes the step of epitaxially growing the substrate 12 in the cavity 22. Therefore, Figure 3 The step of forming an epitaxial region 26 in the cavity 22 includes: forming an epitaxial region 26 in the cavity 22;
[0048] Region 26 preferably extends from the bottom of cavity 22 to a level above the upper surface of layer 18 and preferably below the upper surface of layer 20. Thus, the sidewalls of layer 18 at the same level as the sidewalls of cavity 22 are completely separated by region 26 and spacer 24.
[0049] Region 26 is in contact with substrate 12 and spacer 24. Thus, region 26 is separated from layers 16, 18, 20 and trench 14 by spacer 24.
[0050] The region 26 is made of a semiconductor material, such as silicon, for example N-type doped silicon. The region 26 is preferably made of the material of the substrate 12. The region 26 preferably corresponds to a portion of the collector of the bipolar transistor 10.
[0051] Figure 4 A device resulting from another step of the bipolar transistor manufacturing method is shown.
[0052] Figure 4 The step of parallel etching (ie, partially removing) spacer 24. More precisely, the portion of the spacer located above the upper surface of region 26 is etched. Thus, after etching, the upper surface of spacer 24 is preferably substantially coplanar with the upper surface of region 26.
[0053] Figure 4 The step of forming region 28 also includes forming region 28. For example, region 28 is formed by, for example, epitaxial growth from region 26. Epitaxial region 28 preferably fills cavity 22. Region 28 preferably extends from spacer 24 and the upper surface of region 26. Region 28 extends between the side surfaces of layer 20 located in cavity 22. Thus, region 28 is in lateral contact with layer 20, preferably only with layer 20. Preferably, region 28 is preferably not in contact with layer 18. Region 28 is in contact with region 26 and spacer 24.
[0054] The upper surface of the structure corresponding to the upper surface of region 28 and the upper surface of layer 20 is preferably planar.
[0055] Region 28 is made of a semiconductor material, such as silicon, for example P-type doped silicon. Region 28 corresponds to a portion of the base region of transistor 10.
[0056] Figure 5 A device resulting from another step of the bipolar transistor manufacturing method is shown.
[0057] During this step, layer 30 is formed on the structure. More precisely, layer 30 preferably covers the upper surface of layer 20 and the upper surface of region 28. For example, layer 30 completely covers layer 20 and region 28. Layer 30 is preferably in contact with region 28 and layer 20, preferably in contact with the entire upper surface of region 28 and layer 20. For example, layer 30 is made of the same material as layer 16. Layer 30 is made of silicon oxide, for example. For example, the thickness of layer 30 is in the range of 4 nm to 20 nm.
[0058] Figure 5 The step of forming layer 32 also includes forming layer 32. Layer 32 preferably covers layer 30, preferably completely covers layer 30. Layer 32 is preferably in contact with layer 30, preferably in contact with the entire layer 30. Layer 32 is preferably made of the same material as layer 20, such as silicon nitride. Layers 30 and 32 are preferably made of different materials. The material of layer 32 is preferably a material that is selectively etchable over the material of layer 30. By selective etching, it is meant that the material of layer 32 can be etched by an etching method at least twice faster than the material of layer 30, such as at least ten times faster. The thickness of layer 32 is, for example, in the range of 8nm to 40nm.
[0059] Figure 6 A device resulting from another step of the bipolar transistor manufacturing method is shown.
[0060] During this step, a cavity 34 is formed in layers 30 and 32, preferably only in layers 30 and 32. Cavity 34 is located in front of cavity 22. In other words, cavity 34 is located in front of regions 26 and 28. Cavity 34 extends along the entire height of layers 30 and 32. Thus, cavity 34 reaches region 28. The bottom of cavity 34 is formed by the upper surface of region 28, preferably only by the upper surface of region 28. The side walls of cavity 34 are formed by the side walls of layers 30 and 32. Layer 32 is physically etched, for example, by a series of photolithography and dry etching methods. Layer 32 is then used as a mask for a (isotropic) wet etching step of layer 30.
[0061] The dimensions of cavity 34 (particularly the horizontal dimensions, i.e., for example, the dimensions in a plane parallel to the plane of the upper surface of layer 20) are smaller than the dimensions of cavity 22, for example, in particular, smaller than the horizontal dimensions of cavity 22. Therefore, a portion of the upper surface of region 28 is not exposed by etching to form cavity 34. In other words, Figure 6 During the step of etch, a portion of the layers 30, 32 (preferably the portion located in front of the region 28 and surrounding the cavity 34) is not etched.
[0062] Figure 7 A device resulting from another step of the bipolar transistor manufacturing method is shown.
[0063] During this step, layer 32 is removed. Thus, layer 30 is exposed at least at the location of the transistor. Preferably, layer 32 is completely removed. Thus, layer 30 is preferably completely exposed.
[0064] Thus, cavity 34 is replaced by a cavity or opening 34 ′ that corresponds to the portion of cavity 34 defined by layer 30 and region 28 .
[0065] Figure 8 A device resulting from another step of the bipolar transistor manufacturing method is shown.
[0066] During this step, layer 36 is formed on the structure. More precisely, layer 36 preferably covers the upper surface of layer 30 and the bottom and walls of cavity 34'. Thus, layer 36 preferably covers the upper surface of layer 30, the side walls of layer 30 form the side walls of cavity 34', and a portion of the upper surface of region 28 forms the bottom of cavity 34'. For example, layer 36 completely covers layer 30 and the walls and bottom of cavity 34'. Layer 36 is preferably in contact with region 28 and layer 30 in cavity 34'. Layer 36 is made of the material of the emitter region of bipolar transistor 10. Layer 36 is made of polysilicon, for example of N-type doped polysilicon. For example, the thickness of layer 36 is in the range of 50 nm to 100 nm. For example, layer 30 is substantially ten times smaller than layer 36.
[0067] Figure 8 The step of forming further comprises forming layer 38. Layer 38 preferably covers layer 36, preferably completely covers layer 36. Layer 38 preferably contacts layer 36, preferably contacts the entire layer 36. Layer 38 is preferably made of the same material as layer 30, such as silicon oxide.
[0068] The thickness of layer 30 is small compared to the thickness of layer 36, the upper surface of which is substantially planar and does not include depressions.
[0069] As usual, you can choose Figure 1 A stack of a large number of insulating layers is formed in a step of forming an L-shaped insulating element on the upper surface of region 28 to define cavity 34'. Layers 36 and 38 will then not be planar and will form a depression in line with cavity 34'. Such a depression will cause problems in contacting the emitter of the bipolar transistor.
[0070] Fig. 9 A device resulting from another step of the bipolar transistor manufacturing method is shown.
[0071] During this step, layers 30, 36, 38 are partially etched. In other words, layers 30, 36, 38 are completely etched, except for the portion of each of layers 30, 36, 38 that is located in front of region 28. Layers 38 and 36 are etched, for example, by a series of photolithography and (anisotropic) dry etching. Layer 30 is used as a stop layer for this etching. Layer 30 is then etched by wet chemistry (isotropic).
[0072] Thus, after partially etching layers 30, 36, 38, a portion of each layer 30, 36, 38 remains in front of region 28. The portion of layer 30 surrounds and defines cavity 34'. The portion of layer 36 fills cavity 34' and preferably completely covers the portion of layer 30. The portion of layer 38 preferably completely covers layer 36. The portions of layers 30, 36, 38 preferably have coplanar sidewalls. Preferably, a portion of the upper surface of region 28 (e.g., a portion surrounding the portion covered by the portion of layer 30) is not covered by the portion of layers 30, 36, 38.
[0073] Fig. 9 The step of forming further includes forming a layer 40 made of an insulating material, such as the same material as layer 16, such as silicon oxide. Layer 40 covers the sidewalls of portions of layers 30, 36, 38 and a portion of the upper surface of layer 38. For example, layer 40 covers a portion of the upper surface of region 28 that surrounds portions of layers 30, 36, 38. Layer 40 does not cover layer 20.
[0074] Then, Fig. 9The step of removing layer 20 comprises, for example, removing layer 20 by etching. Layer 20 is preferably completely removed. At least a portion of layer 20 surrounding region 28 is removed. Thus, at least a portion of layer 18 surrounding region 26 is exposed.
[0075] Then, Fig. 9 The step of epitaxially growing layer 18 comprises epitaxial growth of layer 18. The growth of epitaxial layer 18 is maintained until layer 18 is in lateral contact with region 28. Thus, the upper surface of layer 18 is higher than the lower surface of region 28. Preferably, the upper surface of layer 18 is lower than the upper surface of region 28. For example, the upper surface of layer 18 and the upper surface of region 28 are coplanar.
[0076] Fig.10 A device resulting from another step of the bipolar transistor manufacturing method is shown.
[0077] During this step, layers 16 and 18 are partially etched. More precisely, layers 16 and 18 are partially etched to expose the upper surface of substrate 12. For example, layer 16 is etched so that a portion of layer 16 at least partially covers trench 14. Thus, the portion of layer 16 covering substrate 12 around trench 14 is removed. Further, layer 18 is partially etched so that a portion of layer 18 surrounding region 28 remains. Thus, said portion of layer 18 surrounds region 28 and is in lateral contact with region 28.
[0078] Fig.10 The step also includes forming a contact pad. In particular, Fig.10 The steps include: forming a contact pad 42, which is located on substrate 12 and corresponds to the collector contact pad; forming a contact pad 44, which is located on layer 18 and corresponds to the base contact pad; and forming a contact pad (not shown) which is located on layer 36 and corresponds to the emitter contact pad.
[0079] An advantage of the described embodiment is that etching the cavity 22 means etching a thinner stack, which is therefore easier to etch. Thus, smaller cavities can be formed, for example with a critical dimension of less than 200 nm.
[0080] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and those skilled in the art will readily recognize other variations.
[0081] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.
Claims
1. A method for manufacturing a bipolar transistor, comprising: a) forming a first layer stack on a substrate, the first layer stack comprising a first layer, the first layer being between a second insulating layer and a third insulating layer and being made of a material of a base of the bipolar transistor, wherein the third insulating layer is a single layer; b) forming a first cavity through the first stack in a manner to reach the substrate, wherein forming the first cavity includes not etching layers covering the first layer except the third insulating layer; as well as c) forming a first portion of a collector of the bipolar transistor and a second portion of the base of the bipolar transistor in the first cavity. The method according to claim 1 , wherein the first portion and the second portion are formed by epitaxial growth. The method of claim 1 , wherein the first portion is closer to the bottom of the first cavity than the second portion.
4. The method according to claim 1, further comprising: After c), d) forming a fourth insulating layer, the fourth insulating layer covering the upper surface of the third layer and the upper surface of the second portion, and forming an opening in the fourth layer to expose a portion of the upper surface of the second portion. The method of claim 4 , wherein the fourth layer is planar.
6. The method according to claim 4, further comprising: After d), e) forming a second layer stack comprising a fifth layer made of a material of the emitter of the bipolar transistor and a sixth insulating layer covering the fifth layer. 7 . The method of claim 6 , wherein the fifth layer contacts the fourth layer and fills the opening in the fourth layer.
8. The method of claim 6, wherein the thickness of the fifth layer is substantially equal to ten times the thickness of the fourth layer.
9. The method according to claim 6, further comprising: The fourth layer, the fifth layer and the sixth layer are partially etched.
10. A method for manufacturing a bipolar transistor, comprising: forming a first layer made of an insulating material on a substrate; forming a second layer made of polysilicon material on the first layer; forming a third layer made of an insulating material on the second layer; wherein the third layer is a single layer; forming a first cavity by not etching a layer covering the second layer except the third layer, the first cavity passing through the first layer, the second layer and the third layer cavity to reach the substrate; epitaxially growing a collector region of the bipolar transistor from an exposed portion of the substrate; epitaxially growing a first portion of a base region of the bipolar transistor from the collector region, the first portion of the base region being in contact with the second layer, the second layer providing a second portion of the base region of the bipolar transistor; forming a fourth layer made of an insulating material on the third layer and the first portion of the base region; forming an opening through the fourth layer; An emitter region of the bipolar transistor is formed in the opening.
11. The method according to claim 10, further comprising: forming a trench isolation region at an upper surface of the substrate; and Wherein forming the first cavity includes extending the first cavity through the trench isolation region. The method according to claim 10 , wherein the third layer is made of only silicon nitride.
13. The method of claim 10, wherein forming the first cavity is performed before covering the third layer with any other material layer.
Citation Information
Patent Citations
Bague de centrage et d'etancheite pour element filtrant tubulaire de cartouche filtrante
FR2310501A2