IGBT device and method for manufacturing the same

Abstract

The present invention provides an IGBT device and a preparation method thereof, comprising: forming a first trench of a first depth and a second trench of a second depth on a first surface of a substrate, wherein the first depth is greater than the second depth; performing ion implantation of a second conductive type to form first and second bottom doped regions; forming a gate oxide layer and a gate layer; forming a carrier storage layer in the substrate, making the second bottom doped region inverted to eliminate the second bottom doped region, the depth of the carrier storage layer being less than the depth of the top of the first bottom doped region, so as to retain the first bottom doped region; forming a body region and an active region in the substrate, wherein the depth of the body region is less than the depth of the second trench; forming an isolation layer and a metal interconnection layer on the first surface of the substrate; and forming a collector on the second surface of the substrate. The IGBT device of the present invention does not generate a large electric field at the bottom and sidewall of the trench, reduces the sensitivity to the trench etching process, and can effectively improve the stability of the IGBT device in an avalanche state.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit design and manufacture, and in particular relates to an IGBT device and a preparation method thereof. Background Art

[0002] With the development of the power industry, more requirements are being placed on semiconductor power devices that perform energy conversion. In many usage scenarios, smaller size, higher operating temperature, higher efficiency, and lower energy loss are required, so the power devices required to be used have higher junction temperatures and greater power density.

[0003] Existing power devices continuously reduce the minimum repetition period of the active area and increase the conductive channel per unit area to reduce the chip size and increase the switching speed of the power device. This approach will increase the gate drive requirements for MOSFET-type power devices, requiring stronger driving capabilities to provide the charge required during the gate switching process, so split-gate MOSFETs have emerged. However, for power devices such as IGBTs, the split-gate gate structure has brought about a rapid increase in process costs, as well as the gate reliability risks of high-voltage devices due to the complexity of the gate. Therefore, power devices such as IGBTs still mainly use conventional trench structures when the repetition period of the active area is reduced. For IGBTs, such a small minimum repetition period places very high requirements on the quality and angle of the oxide layer at the bottom and sidewalls of the trench, so it is easy to fail when encountering a strong electric field, which is manifested as the characteristics of avalanche negative resistance.

[0004] Existing traditional IGBT devices generally use a trench depth of 4 to 7 microns. The deeper the trench depth, the greater the challenge to the process control of the sidewalls and bottom of the trench, so reliability risks need to be improved.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an IGBT device and a method for manufacturing the same, so as to solve the problem that the IGBT device in the prior art is prone to avalanche negative resistance effect.

[0007] To achieve the above-mentioned purpose and other related purposes, the present invention provides a method for preparing an IGBT device for alleviating the avalanche negative resistance phenomenon, the preparation method comprising: forming a first trench of a first depth and a second trench of a second depth on a first surface of a first conductive type substrate, the first trench and the second trench being arranged at intervals, and the first depth being greater than the second depth; performing second conductive type ion implantation at the bottom of the first trench and the bottom of the second trench to form a first bottom doping region and a second bottom doping region respectively; forming a gate oxide layer in the first trench and the second trench, and filling a gate layer; performing first conductive type ion implantation on the substrate to form a carrier storage layer in the substrate, the doping concentration and depth of the carrier storage layer being greater than the doping concentration and depth of the second bottom doping region, making the second bottom doping region inverted to eliminate the second bottom doping region, the depth of the carrier storage layer being less than the depth of the top of the first bottom doping region, so as to retain the first bottom doping region; forming a body region and an active region in the substrate, the depth of the body region being less than the depth of the second trench; forming an isolation layer and a metal interconnect layer on the first surface of the substrate; and forming a collector on the second surface of the substrate.

[0008] Optionally, forming the first groove and the second groove includes: forming a hard mask pattern on the substrate, the hard mask pattern having a first window of a first width and a second window of a second width, the first width being greater than the second width; etching the substrate based on the first window and the second window to form a first groove below the first window and a second groove below the second window, and since the first width is greater than the second width, after the etching process, a first depth of the first groove is greater than a second depth of the second groove.

[0009] Optionally, the width of the first groove is 0.3 micrometers to 3 micrometers, the width of the second groove is 0.2 micrometers to 2 micrometers, and the first depth of the first groove is 1.2 times to 2 times the second depth of the second groove.

[0010] Optionally, forming a gate oxide layer in the first trench and the second trench includes:

[0011] A sacrificial oxide layer is grown on the sidewalls of the first trench and the second trench by using a thermal oxidation process, and then the sacrificial oxide layer is removed to repair the sidewalls of the first trench and the second trench; and a gate oxide layer is grown on the sidewalls of the first trench and the second trench by using a thermal oxidation process.

[0012] Optionally, forming a carrier storage layer includes: performing ion implantation of a first doping type and then performing annealing activation to form a carrier storage layer, wherein the depth of the carrier storage layer is greater than the bottom depth of the second bottom doping region and the distance between the bottom of the carrier storage layer and the bottom of the second bottom doping region is greater than 0.1 microns, and the depth of the carrier storage layer is less than the depth of the top of the first bottom doping region and the distance between the bottom of the carrier storage layer and the top of the first bottom doping region is greater than 0.3 microns.

[0013] Optionally, forming an isolation layer and a metal interconnection layer on the first side of the substrate includes: forming an isolation layer on the substrate, forming contact holes in the isolation layer and the substrate, the contact holes exposing an active area and a body area; forming a contact area with a second doping type and a high doping concentration at the bottom of the contact hole by ion implantation; depositing a metal bonding layer in the contact hole, and then depositing metal tungsten to form a tungsten plug in the contact hole; depositing a metal layer, and forming a circuit connection layer by photolithography and etching processes; depositing a passivation layer, and exposing a pad area by photolithography and etching processes.

[0014] Optionally, forming a collector on the second side of the substrate includes: thinning the substrate from the second side of the substrate; forming a field stop layer on the second side of the substrate by ion implantation; forming a collector region on the second side of the substrate by ion implantation; forming a back metal layer on the second side of the substrate, and annealing to form an ohmic contact.

[0015] Optionally, while forming the first bottom doped region, a lead-out doped region is also formed in the substrate, wherein the lead-out doped region extends from the first surface of the substrate to the interior of the substrate and is connected to the first bottom doped region, and the lead-out doped region is arranged on the side or end surface of the first groove; when a metal interconnection layer is formed on the first surface of the substrate, the metal interconnection layer is connected to the lead-out doped region.

[0016] The present invention also provides an IGBT device, comprising: a first conductive type substrate, a first surface of the first conductive type substrate is formed with a first groove of a first depth and a second groove of a second depth, the first groove and the second groove are arranged at intervals, the first depth is greater than the second depth, a gate oxide layer is arranged in the first groove and the second groove and is filled with a gate layer; a first bottom doping region and a second bottom doping region of the second conductive type are arranged at the bottom of the first groove and the bottom of the second groove, respectively; a first conductive type carrier storage layer is arranged in the substrate, the doping concentration and depth of the carrier storage layer are greater than the doping concentration and depth of the second bottom doping region, the second bottom doping region is inverted to eliminate the second bottom doping region, the depth of the carrier storage layer is less than the depth of the top of the first bottom doping region, so as to retain the first bottom doping region; a body region and an active region are arranged in the substrate, the depth of the body region is less than the depth of the second groove; an isolation layer and a metal interconnection layer are arranged on the first surface of the substrate; and a collector is arranged on the second surface of the substrate.

[0017] Optionally, the first width of the first groove is greater than the second width of the second groove, the width of the first groove is 0.3 microns to 3 microns, the width of the second groove is 0.2 microns to 2 microns, and the first depth of the first groove is 1.2 times to 2 times the second depth of the second groove.

[0018] Optionally, the depth of the carrier storage layer is greater than the bottom depth of the second bottom doping region and the distance between the bottom of the carrier storage layer and the bottom of the second bottom doping region is greater than 0.1 microns, and the depth of the carrier storage layer is less than the depth of the top of the first bottom doping region and the distance between the bottom of the carrier storage layer and the top of the first bottom doping region is greater than 0.3 microns.

[0019] Optionally, contact holes are provided in the isolation layer and the substrate, the contact holes exposing the active area and the body area; a contact area with a second doping type and a high doping concentration is provided at the bottom of the contact hole; a metal bonding layer is provided in the contact hole and filled with a tungsten plug; a circuit connection layer is provided on the isolation layer; a passivation layer is provided on the circuit connection layer, and the passivation layer exposes a pad area.

[0020] Optionally, a lead-out doping region is provided in the substrate, the lead-out doping region extends from the first surface of the substrate to the inside of the substrate and is connected to the first bottom doping region, the lead-out doping region is provided on the side or end surface of the first groove; the lead-out doping region is connected to the metal interconnection layer.

[0021] As described above, the IGBT device and the method for manufacturing the same of the present invention have the following beneficial effects:

[0022] The present invention provides a first trench and a second trench arranged at different depths and intervals, and provides a bottom doping region at the bottom of the deeper first trench, which can be used to shield the electric field peak of the gate, and the bottom doping region repeatedly arranged at the bottom of the first trench can also reduce the electric field at the bottom of the second trench at the same time. Therefore, the front structure of the IGBT device of the present invention does not generate a large electric field at the bottom and sidewall of the trench, reduces the sensitivity to the trench etching process, and can effectively improve the stability of the IGBT device in an avalanche state.

[0023] The present invention utilizes the difference in trench depths caused by different widths during trench etching to greatly reduce the preparation cost of trenches of different depths. On the other hand, a carrier storage layer is used to eliminate the bottom doping region at the bottom of the shallower second trench, which can effectively shield the electric field of the emitter and collector of the IGBT at the bottom of the trench gate. At the same time, during the layout, the charge of the gate can be effectively adjusted by reasonably setting the ratio of the first trench to the second trench.

[0024] In the IGBT device of the present invention, both the first trench and the second trench can be active trenches or inactive trenches, which can facilitate the adjustment of the gate charge of the device while still maintaining a very small minimum repetition period. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application.

[0026] Figure 1 to Figure 10 It is a schematic structural diagram showing each step of the method for preparing an IGBT device according to an embodiment of the present invention, wherein: Fig. 9 and Fig.10 They respectively show a cross-sectional structural schematic diagram and a three-dimensional structural schematic diagram of an IGBT device according to an embodiment of the present invention.

[0027] Description of component numbers: 101 substrate, 102 hard mask pattern, 103 photoresist pattern, 104 first window, 105 second window, 106 first trench, 107 second trench, 108 first bottom doped region, 109 second bottom doped region, 110 gate oxide layer, 111 gate layer, 112 carrier storage layer, 113 body region, 114 active region, 115 isolation layer, 116 contact hole, 117 tungsten plug, 118 metal interconnection layer, 119 passivation layer, 120 collector, 121 lead-out doped region. DETAILED DESCRIPTION

[0028] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0029] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0030] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0031] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0032] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0033] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0034] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0035] like Figure 1 to Figure 10 As shown, this embodiment provides a method for preparing an IGBT device for alleviating the avalanche negative resistance phenomenon, and the preparation method comprises the following steps:

[0036] like Figure 1~Figure 2 As shown, firstly, step 1 is performed to form a first trench 106 of a first depth and a second trench 107 of a second depth on a first surface of a first conductive type substrate 101. The first trench 106 and the second trench 107 are arranged alternately, and the first depth is greater than the second depth.

[0037] The substrate 101 is a semiconductor substrate of a first conductivity type (such as N-type or P-type), and the material includes but is not limited to: a single crystal silicon substrate, a silicon carbide (SiC) substrate, etc. For example, in this embodiment, the first conductivity type substrate is an N-type conductive single crystal silicon substrate, and its crystal orientation can be <100> or <111> , the resistivity can be 0.1Ω·cm ~10Ω·cm.

[0038] In one embodiment, forming the first trench 106 and the second trench 107 includes:

[0039] a) A hard mask pattern 102 is formed on a substrate 101 based on a photoresist pattern 103, wherein the hard mask pattern 102 has a first window 104 of a first width and a second window 105 of a second width, wherein the first width is greater than the second width; the material of the hard mask pattern 102 may be silicon nitride (Si3N4), silicon oxide (SiO2) or a multi-layer stack (such as SiO2 / Si3N4), etc.

[0040] A first window 104 is formed in the hard mask layer by photolithography and etching processes. The width of the first window 104 is 0.3 microns to 3 microns, and specifically 0.5 microns, 1.2 microns, 2.0 microns, etc. The width of the second window 105 can be 0.2 microns to 2 microns, and specifically 0.3 microns, 0.8 microns, 1.5 microns, etc.

[0041] b) etching the substrate 101 based on the first window 104 and the second window 105 to form a first trench 106 under the first window 104 and a second trench 107 under the second window 105. Since the first width is greater than the second width, after the etching process, the first depth of the first trench 106 is greater than the second depth of the second trench 107. For example, reactive ion etching (RIE) or inductively coupled plasma (ICP) may be used to etch the substrate 101, and the etching gas combination may be Cl2 / HBr / O2 (volume ratio of, for example, 1:2:0.5) or SF6 / C4F8 (ratio of, for example, 3:1), etc.

[0042] In one embodiment, the width of the first groove 106 is 0.3 microns to 3 microns, specifically 0.5 microns, 1.2 microns, 2.0 microns, etc., and the width of the second groove 107 is 0.2 microns to 2 microns, specifically 0.3 microns, 0.8 microns, 1.5 microns, etc.

[0043] In one embodiment, the first depth of the first trench 106 is 1.2 to 2 times, for example, 1.5 or 1.8 times, the second depth of the second trench 107 .

[0044] The present invention realizes different groove depth differences through different window widths, and completes the etching of grooves of different depths through one photolithography and etching step, which can effectively improve process efficiency and reduce process cost.

[0045] like Figure 3 As shown, step 2 is then performed to implant second conductive type ions at the bottom of the first trench 106 and the bottom of the second trench 107 to form a first bottom doped region 108 and a second bottom doped region 109. By controlling the bottom doped region, the electric field distribution can be regulated to reduce the electric field peak at the bottom of the trench.

[0046] In one embodiment, the second conductivity type may be a P-type conductivity type. The implanted element may be, for example, boron (B), the implantation energy may be 30-200 keV, and the dose may be 5e12-1e14 cm -2 , forming a depth of 0.5 micron to 2 microns (such as 0.8 micron, 1.5 micron, etc.). Then, rapid thermal annealing (RTA) activation is performed, the annealing temperature can be 900~1100℃, and the annealing time can be 10~120 seconds.

[0047] like Figure 4 As shown, step 3 is then performed to form a gate oxide layer 110 in the first trench 106 and the second trench 107, and fill the gate layer 111.

[0048] In one embodiment, forming the gate oxide layer 110 in the first trench 106 and the second trench 107 includes:

[0049] a) growing a sacrificial oxide layer on the sidewalls of the first trench 106 and the second trench 107 by a thermal oxidation process (the growth temperature is, for example, 800-950° C. and the time is 10-60 minutes) with a thickness of 100 angstroms to 500 angstroms, and then removing the sacrificial oxide layer. For example, the sacrificial oxide layer can be removed by wet etching (diluted HF solution) to repair the etching damage on the sidewalls of the first trench 106 and the second trench 107;

[0050] b) Using a thermal oxidation process, a gate oxide layer 110 is grown on the sidewalls of the first trench 106 and the second trench 107. For example, the thermal oxidation temperature may be 900-1050° C., the time may be 30-180 minutes, and the thickness of the gate oxide layer 110 may be, for example, 500 angstroms to 2000 angstroms, specifically 800 angstroms, 1200 angstroms, 1500 angstroms, etc.

[0051] The gate layer 111 may be doped polysilicon, metal or metal silicide, and may be formed by low pressure chemical vapor deposition (LPCVD) or sputtering (PVD), and then planarized by chemical mechanical polishing (CMP) after filling, to form the final gate layer 111 .

[0052] like Figure 5 As shown, step 4 is then performed), the first conductive type ion is implanted into the substrate 101 to form a carrier storage layer 112 in the substrate 101, the doping concentration and depth of the carrier storage layer 112 are greater than the doping concentration and depth of the second bottom doping region 109, so that the second bottom doping region 109 is inverted to eliminate the second bottom doping region 109, and the depth of the carrier storage layer 112 is less than the depth of the top of the first bottom doping region 108 to retain the first bottom doping region 108.

[0053] In one embodiment, forming the carrier storage layer 112 includes: performing ion implantation of a first doping type and then performing annealing activation to form the carrier storage layer 112, the depth of the carrier storage layer 112 is greater than the bottom depth of the second bottom doping region 109 and the distance between the bottom of the carrier storage layer 112 and the bottom of the second bottom doping region 109 is greater than 0.1 microns, the depth of the carrier storage layer 112 is less than the depth of the top of the first bottom doping region 108 and the distance between the bottom of the carrier storage layer 112 and the top of the first bottom doping region 108 is greater than 0.3 microns.

[0054] In one embodiment, the injection energy of the carrier storage layer 112 may be 200-600 keV, and the dose may be 1e13-1e15 cm -2 (e.g. 5e13 cm -2 、3e14 cm -2 ), and then RTA annealing is performed, the temperature is, for example, 1000~1150°C, and the time is, for example, 10~60 seconds. The depth of the carrier storage layer 112 is greater than the bottom depth of the second bottom doping region 109, and the spacing is preferably greater than or equal to 0.1 micron (such as 0.15 micron, 0.2 micron). The depth of the carrier storage layer 112 is less than the top depth of the first bottom doping region 108, and the spacing is preferably greater than or equal to 0.3 micron (such as 0.35 micron, 0.4 micron). The present invention eliminates the inversion of the second bottom doping region 109 through the high-concentration carrier storage layer 112, while retaining the first bottom doping region 108 to shield the electric field.

[0055] like Figure 6 As shown, step 5 is then performed to form a body region 113 and an active region 114 in the substrate 101 , wherein the depth of the body region 113 is less than the depth of the second trench 107 .

[0056] In one embodiment, the body region 113 is of the second conductivity type (P type), and its doping ions may be boron. The depth may be, for example, 0.5-2 microns (eg, 1.0 microns, 1.5 microns), and its depth must be less than the depth of the second trench 107 .

[0057] The active region 114 is of the first conductivity type (N type), and its doping ions may be phosphorus or arsenic. Specifically, a photolithography machine may be used for spin coating on the surface of the substrate 101, and the pattern of the active region 114 may be defined by a photolithography process, and then the active region 114 may be formed by ion implantation.

[0058] like Figure 7~Figure 8 As shown, step 6 is then performed to form an isolation layer 115 and a metal interconnection layer 118 on the first surface of the substrate 101.

[0059] In one embodiment, forming an isolation layer 115 and a metal interconnection layer 118 on the first surface of the substrate 101 includes: forming an isolation layer 115 (which may be silicon oxide or silicon nitride or a stacked layer, etc.) on the substrate 101, forming a contact hole 116 in the isolation layer 115 and the substrate 101, the contact hole 116 exposing the active area 114 and the body area 113; forming a contact area with a high doping concentration of a second doping type at the bottom of the contact hole 116 by ion implantation; depositing a metal bonding layer (such as titanium / titanium nitride, etc.) in the contact hole 116, and then depositing metal tungsten to form a tungsten plug 117 in the contact hole 116; depositing a metal layer (such as copper or aluminum, etc.), and forming a circuit connection layer by photolithography and etching processes; depositing a passivation layer 119 (such as silicon oxide, silicon nitride or polyimide, etc.), and exposing the pad area by photolithography and etching processes.

[0060] like Figure 9~Figure 10 As shown, step 7 is finally performed to form a collector electrode 120 on the second surface of the substrate 101.

[0061] In one embodiment, forming a collector electrode 120 on the second surface of the substrate 101 includes: thinning the substrate 101 from the second surface of the substrate 101, such as thinning the substrate 101 by grinding or chemical mechanical polishing (CMP); forming a field stop layer on the second surface of the substrate 101 by ion implantation; forming a collector region on the second surface of the substrate 101 by ion implantation; forming a back metal layer on the second surface of the substrate 101, and annealing to form an ohmic contact, the material of the back metal layer is, for example, an Al / Ti / Ni / Ag multilayer structure with a thickness of 1 to 5 microns, and annealing (such as 400 to 600°C for 10 to 30 minutes) to form an ohmic contact with the collector region.

[0062] like Fig.10 As shown, in one embodiment, while forming the first bottom doping region 108, it also includes forming an extraction doping region 121 in the substrate 101, the extraction doping region 121 extends from the first surface of the substrate 101 to the inside of the substrate 101 and is connected to the first bottom doping region 108, and the extraction doping region 121 is arranged on the side or end surface of the first trench 106; when the metal interconnection layer 118 is formed on the first surface of the substrate 101, the metal interconnection layer 118 is connected to the extraction doping region 121. In the layout of the present invention, by controlling the distribution of the interval, the first bottom doping region 108 can be short-circuited with the metal interconnection layer 118 through the extraction doping region 121, thereby preventing the gate from being out of control when the first bottom doping region 108 is floating.

[0063] like Figure 9~Figure 10As shown, this embodiment also provides an IGBT device, which can be prepared by the preparation method described in the above embodiment, and the IGBT device includes: a first conductive type substrate 101, a first groove 106 of a first depth and a second groove 107 of a second depth are formed on the first surface of the first conductive type substrate 101, the first groove 106 and the second groove 107 are arranged at intervals, the first depth is greater than the second depth, and a gate oxide layer 110 is arranged in the first groove 106 and the second groove 107 and is filled with a gate layer 111; a first bottom doped region 108 and a second bottom doped region 109 of the second conductive type are respectively arranged at the bottom of the first groove 106 and the bottom of the second groove 107 a first conductive type carrier storage layer 112, disposed in the substrate 101, wherein the doping concentration and depth of the carrier storage layer 112 are greater than the doping concentration and depth of the second bottom doping region 109, so that the second bottom doping region 109 is inverted to eliminate the second bottom doping region 109, and the depth of the carrier storage layer 112 is less than the depth of the top of the first bottom doping region 108 to retain the first bottom doping region 108; a body region 113 and an active region 114, disposed in the substrate 101, wherein the depth of the body region 113 is less than the depth of the second trench 107; an isolation layer 115 and a metal interconnection layer 118, disposed on the first surface of the substrate 101; and a collector 120, disposed on the second surface of the substrate 101.

[0064] In one embodiment, the first width of the first groove 106 is greater than the second width of the second groove 107 , the width of the first groove 106 is 0.3 microns to 3 microns, the width of the second groove 107 is 0.2 microns to 2 microns, and the first depth of the first groove 106 is 1.2 times to 2 times the second depth of the second groove 107 .

[0065] In one embodiment, the depth of the carrier storage layer 112 is greater than the bottom depth of the second bottom doping region 109 and the distance between the bottom of the carrier storage layer 112 and the bottom of the second bottom doping region 109 is greater than 0.1 microns, and the depth of the carrier storage layer 112 is less than the depth of the top of the first bottom doping region 108 and the distance between the bottom of the carrier storage layer 112 and the top of the first bottom doping region 108 is greater than 0.3 microns.

[0066] In one embodiment, a contact hole 116 is provided in the isolation layer 115 and the substrate 101, and the contact hole 116 exposes the active area 114 and the body area 113; a contact area with a second doping type and a high doping concentration is provided at the bottom of the contact hole 116; a metal bonding layer is provided in the contact hole 116 and is filled with a tungsten plug 117; a circuit connection layer is provided on the isolation layer 115; a passivation layer 119 is provided on the circuit connection layer, and the passivation layer 119 exposes a pad area.

[0067] In one embodiment, a lead-out doping region 121 is provided in the substrate 101, and the lead-out doping region 121 extends from the first surface of the substrate 101 to the interior of the substrate 101 and is connected to the first bottom doping region 108, and the lead-out doping region 121 is provided on the side or end surface of the first trench 106; the lead-out doping region 121 is connected to the metal interconnection layer 118.

[0068] As described above, the IGBT device and the method for manufacturing the same of the present invention have the following beneficial effects:

[0069] The present invention provides the first trench 106 and the second trench 107 with different depths and intervals, and provides a bottom doping region at the bottom of the deeper first trench 106, which can be used to shield the electric field peak of the gate, and the bottom doping region repeatedly arranged at the bottom of the first trench 106 can also simultaneously reduce the electric field at the bottom of the second trench 107. Therefore, the front structure of the IGBT device of the present invention does not generate a large electric field at the bottom and sidewall of the trench, reduces the sensitivity to the trench etching process, and can effectively improve the stability of the IGBT device in an avalanche state.

[0070] The present invention utilizes the difference in trench depth caused by different widths during trench etching to greatly reduce the preparation cost of trenches of different depths. On the other hand, the carrier storage layer 112 is used to eliminate the bottom doping region at the bottom of the shallower second trench 107, which can effectively shield the electric field of the IGBT at the emitter and collector 120 at the bottom of the trench gate. At the same time, during the layout, the charge of the gate can be effectively adjusted by reasonably setting the ratio of the first trench 106 to the second trench 107.

[0071] In the IGBT device of the present invention, the first trench 106 and the second trench 107 can be active trenches or inactive trenches, which can facilitate the adjustment of the gate charge of the device while still maintaining a very small minimum repetition period.

[0072] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0073] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing an IGBT device, characterized in that: The preparation method comprises: Forming a first trench of a first depth and a second trench of a second depth on a first surface of a first conductive type substrate, wherein the first trench and the second trench are arranged alternately, and the first depth is greater than the second depth; Performing second conductive type ion implantation at the bottom of the first trench and the bottom of the second trench to form a first bottom doped region and a second bottom doped region respectively; forming a gate oxide layer in the first trench and the second trench, and filling a gate layer; Performing first conductivity type ion implantation on the substrate to form a carrier storage layer in the substrate, wherein the doping concentration and depth of the carrier storage layer are greater than the doping concentration and depth of the second bottom doping region, so that the second bottom doping region is inverted to eliminate the second bottom doping region, and the depth of the carrier storage layer is less than the depth of the top of the first bottom doping region to retain the first bottom doping region; forming a body region and an active region in the substrate, wherein a depth of the body region is less than a depth of the second trench; forming an isolation layer and a metal interconnection layer on the first surface of the substrate; A collector is formed on the second surface of the substrate.

2. The method for preparing an IGBT device according to claim 1, characterized in that: Forming the first trench and the second trench includes: forming a hard mask pattern on the substrate, the hard mask pattern having a first window of a first width and a second window of a second width, wherein the first width is greater than the second width; The substrate is etched based on the first window and the second window to form a first groove below the first window and a second groove below the second window. Since the first width is greater than the second width, after the etching process, the first depth of the first groove is greater than the second depth of the second groove.

3. The method for preparing an IGBT device according to claim 1, characterized in that: The width of the first groove is 0.3 micrometers to 3 micrometers, the width of the second groove is 0.2 micrometers to 2 micrometers, and the first depth of the first groove is 1.2 times to 2 times the second depth of the second groove.

4. The method for preparing an IGBT device according to claim 1, characterized in that: Forming a gate oxide layer in the first trench and the second trench comprises: Growing a sacrificial oxide layer on the sidewalls of the first trench and the second trench by a thermal oxidation process, and then removing the sacrificial oxide layer to repair the sidewalls of the first trench and the second trench; A gate oxide layer is grown on the sidewalls of the first trench and the second trench by using a thermal oxidation process.

5. The method for preparing an IGBT device according to claim 1, characterized in that: Forming a carrier storage layer includes: performing ion implantation of a first doping type and then performing annealing activation to form a carrier storage layer, wherein the depth of the carrier storage layer is greater than the bottom depth of the second bottom doping region and the distance between the bottom of the carrier storage layer and the bottom of the second bottom doping region is greater than 0.1 microns, and the depth of the carrier storage layer is less than the depth of the top of the first bottom doping region and the distance between the bottom of the carrier storage layer and the top of the first bottom doping region is greater than 0.3 microns.

6. The method for preparing an IGBT device according to claim 1, characterized in that: Forming an isolation layer and a metal interconnection layer on the first surface of the substrate comprises: forming an isolation layer on the substrate, and forming contact holes in the isolation layer and the substrate, wherein the contact holes expose the active region and the body region; forming a contact region of a second doping type and a high doping concentration at the bottom of the contact hole by ion implantation; depositing a metal bonding layer in the contact hole, and then depositing metal tungsten to form a tungsten plug in the contact hole; Depositing a metal layer and forming a circuit link layer using photolithography and etching processes; A passivation layer is deposited, and the pad area is exposed using photolithography and etching processes.

7. The method for preparing an IGBT device according to claim 1, characterized in that: Forming a collector on the second surface of the substrate comprises: thinning the substrate from the second side of the substrate; forming a field stop layer on the second surface of the substrate by ion implantation; forming a collector region on the second surface of the substrate by ion implantation; A back metal layer is formed on the second surface of the substrate and annealed to form an ohmic contact.

8. The method for preparing an IGBT device according to claim 1, characterized in that: While forming the first bottom doping region, the method further includes forming an extraction doping region in the substrate, wherein the extraction doping region extends from the first surface of the substrate to the inside of the substrate and is connected to the first bottom doping region, and the extraction doping region is arranged on a side surface or an end surface of the first trench; When a metal interconnection layer is formed on the first surface of the substrate, the metal interconnection layer is connected to the lead-out doping region.

9. An IGBT device, characterized in that: include: A first conductive type substrate, wherein a first trench of a first depth and a second trench of a second depth are formed on a first surface of the first conductive type substrate, the first trench and the second trench are arranged alternately, the first depth is greater than the second depth, and a gate oxide layer is disposed in the first trench and the second trench and is filled with a gate layer; A first bottom doped region and a second bottom doped region of a second conductivity type, respectively disposed at the bottom of the first trench and the bottom of the second trench; a carrier storage layer of a first conductivity type, disposed in the substrate, wherein the doping concentration and depth of the carrier storage layer are greater than the doping concentration and depth of the second bottom doping region, so that the second bottom doping region is inverted to eliminate the second bottom doping region, and the depth of the carrier storage layer is less than the depth of the top of the first bottom doping region to retain the first bottom doping region; A body region and an active region are disposed in the substrate, wherein a depth of the body region is less than a depth of the second trench; An isolation layer and a metal interconnection layer are arranged on the first surface of the substrate; The collector is arranged on the second surface of the substrate.

10. The IGBT device according to claim 9, characterized in that: The first width of the first groove is greater than the second width of the second groove, the width of the first groove is 0.3 microns to 3 microns, the width of the second groove is 0.2 microns to 2 microns, and the first depth of the first groove is 1.2 times to 2 times the second depth of the second groove.

11. The IGBT device according to claim 9, characterized in that: The depth of the carrier storage layer is greater than the bottom depth of the second bottom doped region and the distance between the bottom of the carrier storage layer and the bottom of the second bottom doped region is greater than 0.1 microns, and the depth of the carrier storage layer is less than the depth of the top of the first bottom doped region and the distance between the bottom of the carrier storage layer and the top of the first bottom doped region is greater than 0.3 microns.

12. The IGBT device according to claim 9, characterized in that: Contact holes are provided in the isolation layer and the substrate, the contact holes exposing the active area and the body area; a contact area with a second doping type and a high doping concentration is provided at the bottom of the contact hole; a metal bonding layer is provided in the contact hole and filled with a tungsten plug; a circuit connection layer is provided on the isolation layer; a passivation layer is provided on the circuit connection layer, and the passivation layer exposing a pad area.

13. The IGBT device according to claim 9, characterized in that: The substrate is provided with a lead-out doping region, which extends from the first surface of the substrate to the inside of the substrate and is connected to the first bottom doping region, and is arranged on the side or end surface of the first groove; the lead-out doping region is connected to the metal interconnection layer.

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