Power semiconductor device and method of manufacturing power semiconductor device

Abstract

A power semiconductor device (1) comprising: a semiconductor body (10) having a vertically protruding fin (16) configured to conduct a portion of a nominal load current of the device; and a first load terminal (11) in contact with an upper portion of the fin portion (16). The electrode material (141) is arranged adjacent to the fin (16) and is electrically insulated from the fin (16) based on the insulating material (142). The electrode material (141) is electrically insulated from the first load terminal (11) on the basis of the isolation material (143). The power semiconductor device further includes an isolation sidewall spacer (144) on top of the electrode material (141) adjacent to the isolation material (143) and the insulating material (142), where the sidewall spacer (144) terminates at a pull-back distance (PBD) below the top of the fin (16), where the pull-back distance (PBD) is equal to at least 90% of a width of the fin (16) at the top of the fin (16).

Description

Technical Field

[0001] The present description relates to embodiments of a power semiconductor device and embodiments of a method of manufacturing a power semiconductor device. Background Art

[0002] Many functions of modern devices in automotive, consumer and industrial applications, such as converting electrical energy and driving electric motors or motors, rely on power semiconductor devices. For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and diodes, to name a few, have been used in a variety of applications including, but not limited to, switches in power supplies and power converters.

[0003] A power semiconductor device typically includes a semiconductor body configured to conduct a forward load current along a load current path between two load terminals of the device. The load current is typically conducted by means of an active region of the power semiconductor device. The active region is typically surrounded by an edge termination region that is terminated by the edge of the chip.

[0004] In the case of a controllable power semiconductor device, such as a transistor, the load current path can be controlled by means of an insulated electrode, usually referred to as a gate electrode. For example, upon receiving a corresponding control signal from a driver unit, for example via a control terminal of the device, the control electrode can set the power semiconductor device to one of a forward conducting state and a blocking state.

[0005] In addition, some devices provide reverse load current capability; that is, the active area of ​​the semiconductor body is also configured to conduct reverse load current along a reverse load current path between the two load terminals of the device. For example, the RC (reverse current) IGBT is a representative of such a device. In the RC IGBT, a single chip combines the IGBT structure and the diode structure.

[0006] Regardless of whether the device exhibits an RC configuration or not, a general goal is to design a power semiconductor device with high reliability and high efficiency. For example, in the case of a controllable device, reliability may be reduced due to the risk of breakdown caused by accidental electrical contact between one of the load terminals and the gate electrode. These accidental contacts may occur due to processing errors during device production and / or due to device degradation over time. Even for device configurations with relatively small structures, such accidental contacts must be avoided to ensure high device reliability. Summary of the invention

[0007] The subject matter of the independent claims is presented. Features of the exemplary embodiments are defined in the dependent claims.

[0008] According to an embodiment, a method for manufacturing a power semiconductor device comprises the following steps:

[0009] - providing a semiconductor body having vertically protruding fins covered by an insulation material, the insulation material being covered by an electrode material, wherein the insulation material at least partially covers the electrode material;

[0010] - exposing a portion of the electrode material arranged over the upper portion of the fin;

[0011] - removing the exposed portion of the electrode material to expose the upper portion of the fin covered by the insulating material, thereby forming a corresponding groove adjacent to both sides of the exposed upper portion of the fin, the groove being spatially confined by a) the insulating material, b) the electrode material and c) the isolation material;

[0012] - forming an isolation sidewall spacer in the recess and on top of the electrode material adjacent to the insulating material and the isolation material, wherein the sidewall spacer terminates at a pullback distance below the top of the fin, wherein the pullback distance is equal to at least 90% of the fin width at the top of the fin;

[0013] - forming an interlayer dielectric ILD on top of the exposed portion of the device by a) providing further insulating material and b) a subsequent removal process step to re-expose both the upper portion of the sidewall spacers and the upper portion of the fin by removing a portion of the isolation material covering the fin;

[0014] - forming a first load terminal configured to contact an upper portion of the fin.

[0015] According to another embodiment, a power semiconductor device includes: a semiconductor body having a vertically protruding fin configured to conduct a portion of a nominal load current of the device; a first load terminal in contact with an upper portion of the fin. An electrode material is arranged adjacent to the fin and is electrically insulated from the fin based on an insulating material. The electrode material is electrically insulated from the first load terminal based on an isolation material. The power semiconductor device further includes: an isolation sidewall spacer adjacent to the isolation material and the insulating material on top of the electrode material, wherein the sidewall spacer terminates at a pullback distance below the top of the fin, wherein the pullback distance is equal to at least 90% of the fin width at the top of the fin.

[0016] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The parts in the drawings are not necessarily drawn to scale, instead, emphasis is placed on illustrating the principles of the present invention. In addition, in the drawings, the same reference numerals designate corresponding parts. In the drawings:

[0018] Figure 1A -B both schematically and exemplarily illustrates a corresponding section of a vertical cross section of a power semiconductor device according to one or more embodiments;

[0019] Figure 2A -B both schematically and exemplarily illustrates a corresponding section of a vertical cross section of a power semiconductor device according to one or more embodiments;

[0020] Figure 3 schematically and exemplarily illustrates a section of a vertical cross-section of a power semiconductor device;

[0021] Figure 4 schematically and exemplarily illustrates a section of a vertical cross-section of a power semiconductor device according to one or more embodiments; and

[0022] Figure 5-13 A method of manufacturing a power semiconductor device according to some embodiments is schematically and exemplarily illustrated based on several sections of a vertical cross-section of the device being processed. DETAILED DESCRIPTION

[0023] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.

[0024] In this regard, directional terms, such as "top", "bottom", "below", "front", "rear", "back", "leading", "trailing", "above", etc., may be used with reference to the orientation of the figure being described. Since the components of the embodiments may be positioned in many different orientations, the directional terms are used for illustrative purposes and are in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be construed in a limiting sense, and the scope of the present invention is defined by the appended claims.

[0025] Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the drawings. Each example is provided by way of explanation and is not meant to be a limitation of the invention. For example, features illustrated or described as part of one embodiment may be used in other embodiments or used in conjunction with other embodiments to produce yet other embodiments. It is intended that the invention includes such modifications and variations. Examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. For clarity, if not otherwise stated, the same elements or manufacturing steps have been designated by the same reference numerals in different drawings.

[0026] The term "horizontal" as used in this specification is intended to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or semiconductor structure. This may be, for example, the surface of a semiconductor wafer or die or chip. For example, both the first lateral direction X and the second lateral direction Y mentioned below may be horizontal directions, wherein the first lateral direction X and the second lateral direction Y may be perpendicular to each other.

[0027] The term "vertical" as used in this specification is intended to describe an orientation that is generally arranged perpendicular to a horizontal surface, i.e. parallel to the normal direction of the surface of the semiconductor wafer / chip / die. For example, the extension direction Z mentioned below may be an extension direction perpendicular to both the first lateral direction X and the second lateral direction Y. The extension direction Z is also referred to herein as the "vertical direction Z".

[0028] In this specification, n-doping is referred to as the “first conductivity type” and p-doping is referred to as the “second conductivity type.” Alternatively, the opposite doping relationship may be adopted, such that the first conductivity type may be p-doped and the second conductivity type may be n-doped.

[0029] In the context of this specification, the terms "in ohmic contact", "in electrical contact", "in ohmic connection" and "electrically connected" are intended to describe the presence of a low-ohmic electrical connection or a low-ohmic current path between two regions, sections, areas, parts or components of a semiconductor device, or between different terminals of one or more devices, or between a terminal or metallization or electrode of a semiconductor device and a part or component thereof, where "low ohmic" may mean that the properties of the respective contact are substantially unaffected by ohmic resistance. Further, in the context of this specification, the term "in contact" is intended to describe the presence of a direct physical connection between two elements of the respective semiconductor device; for example, a transition between two elements in contact with each other may not include additional intermediate elements, etc.

[0030] Additionally, in the context of this specification, if not stated otherwise, the term "electrically insulated" is used in its generally reasonably understood context, and is thus intended to describe two or more components that are located separately from each other and there is no ohmic connection connecting those components. However, components that are electrically insulated from each other may nevertheless be coupled to each other, such as mechanically and / or capacitively and / or inductively and / or electrostatically (e.g., in the case of a "junction"). To give an example, two electrodes of a capacitor may be electrically insulated from each other and at the same time mechanically and capacitively coupled to each other, such as by means of an insulating portion, such as a dielectric.

[0031] The specific embodiments described in this specification relate to, but are not limited to, power semiconductor devices that can be used in power converters or power supplies. Therefore, in one embodiment, such a power semiconductor device can be configured to carry a load current to be fed to a load and / or provided by a power supply, respectively. For example, the power semiconductor device may include one or more active power semiconductor unit cells, such as a monolithic integrated diode cell, a derivative of a monolithic integrated diode cell, a monolithic integrated transistor cell, for example a monolithic integrated IGBT or MOSFET cell and / or its derivatives. Such a diode / transistor cell can be integrated in a single chip. A plurality of such cells can constitute a cell field arranged in an active region of the power semiconductor device.

[0032] The term "blocking state" of a power semiconductor device may refer to a situation when the power semiconductor device is in a state configured to block a load current when an external voltage is applied. More specifically, the power semiconductor device may be configured to prevent a forward load current from passing through the power semiconductor device when a forward bias is applied. In contrast, the power semiconductor device may be configured to conduct a forward load current in a "conducting state" of the power semiconductor device when a forward bias is applied. The transition between the blocking state and the conducting state may be controlled by a control electrode, or more specifically, by the potential of the control electrode. Of course, the electrical characteristics may only be applicable within a predetermined operating range of a current density and an external voltage within the power semiconductor device. Therefore, the term "blocking state" may refer to a situation where a power semiconductor device is in a blocking state when a forward bias is applied.

[0033] The term "power semiconductor device" as used in this specification is intended to describe a power semiconductor device on a single chip having a high voltage blocking and / or a high current carrying capability. In other words, such a power semiconductor device is intended for high currents, typically in the ampere range, such as up to tens or hundreds of amperes, and / or high voltages, typically above 15V, more typically 100V and above, such as up to at least 500V or even higher, such as up to at least 3kV, or even up to 10kV or more, depending on the respective application.

[0034] For example, the term "power semiconductor device" as used in this specification does not refer to a logic semiconductor device used for, for example, storing data, computing data, and / or other types of semiconductor-based data processing.

[0035] For example, the power semiconductor device described below may be a single semiconductor chip, for example, in a stripe cell configuration (or honeycomb / needle cell configuration), and may be configured for use as a power component in low, medium and / or high voltage applications.

[0036] Figure 1A -B illustrates both schematically and exemplarily a corresponding section of a vertical cross section of a power semiconductor device 1 according to one or more embodiments. According to these embodiments, the power semiconductor device 1 exhibits an IGBT configuration.

[0037] Figure 2A -B both schematically and exemplarily illustrates a corresponding section of a vertical cross section of a power semiconductor device 1 according to one or more further embodiments. According to these embodiments, the power semiconductor device 1 exhibits a MOSFET configuration.

[0038] The following description refers to Figures 1A to 2B Each one of them.

[0039] The power semiconductor device 1 (also referred to herein as “device”) comprises in a single chip a semiconductor body 10 configured to conduct a load current between a first load terminal 11 at a first side 110 of the semiconductor body 10 and a second load terminal 12 at a second side 120 of the semiconductor body 10 .

[0040] The first side 110 and the second side 120 may be arranged opposite to each other. For example, the first side 110 is the front side of the device 1 and the second side 120 is the back side of the device 1. Therefore, the device 1 may exhibit a vertical configuration according to which the load current in the device 1 follows a path parallel to the vertical direction Z.

[0041] The device 1 further comprises a drift region 100 of the first conductivity type within the semiconductor body 10. Herein, the term "drift region" is used in the sense that a skilled person usually associates with it in the field of power semiconductor devices. For example, the vertical extension of the drift region 100 affects the voltage blocking capability of the device 1.

[0042] The device 1 further comprises fins 16 protruding from the first side 110 opposite to the vertical direction Z. At least some of the fins 16 may be associated with corresponding control electrodes 141. When a corresponding control signal is provided to the control electrode, the device 1 may be set to a blocking state or a conducting state. For example, to this end, the control electrode 141 may be configured to induce a conducting channel in the fin 16 or to cut off the conducting channel, respectively.

[0043] Based on at least the insulating structures 142, 143, the control electrode 141 is electrically isolated from both the first load terminal 11 (and the second load terminal 12) and the semiconductor body 10. The insulating structure 142 includes a bottom insulating layer 142-1 that electrically insulates the control electrode 141 from the semiconductor body and a gate insulating layer 142-2 that electrically insulates the control electrode 141 from the fin 16. The gate insulating layer 142-2 may also be referred to as a gate dielectric (layer).

[0044] As in Figures 1A-2B As shown in FIG. 1 , the fin 16 is electrically connected to the first load terminal 11 , for example based on contacts 111 . These contacts 111 will be described in more detail below. In the region where the fin 16 adjoins the contacts 111 , the fin may include a first doped region 101 of the first conductivity type or a second doped region 102 of the second conductivity type. In the case of an IGBT configuration (see Figure 1A -B), two types (a first doping region 101 of a first conductivity type and a second doping region 102 of a second conductivity type) are realized; therefore, the device 1 exhibits a bipolar configuration. The ratio between the fins 16 of the first conductivity type (the fins 16 including the first doping region 101) and the fins 16 of the second conductivity type (the fins 16 including the second doping region 102) can be at least 1 to 1, at least 1 to 3, or even at least 1 to 6. In other words, for each fin 16 including one of the first doping regions 101, there can be at least 1, at least 3, or even at least 6 fins 16 including one of the second doping regions 102. In the case of a MOSFET configuration (see Figure 2A -B), the fin 16 is provided with only the first doping region 101 of the first conductivity type; therefore, the device 1 exhibits a unipolar configuration. Alternatively, in the case of a MOSFET configuration, it is also possible that the device 1 includes a fin 16 of the first conductivity type (the fin 16 including the first doping region 101) and a fin 16 of the second conductivity type (the fin 16 including the second doping region 102).

[0045] Furthermore, the device 1 may include a shielding region of the second conductivity type buried in the semiconductor body 10 and spaced apart from the front side 110. The shielding region may be directly connected to the first load terminal 11 or connected to the first load terminal 11 via one or more of the fins 16 of the second conductivity type (including the fins 16 of the second doped region 102). Two or more of the shielding regions may together form a JFET.

[0046] Each of the fins 16 may be connected in parallel between the first load terminal 11 and the second load terminal 12 , wherein each of the fins 16 may be configured to conduct a portion of a load current between the first load terminal 11 and the second load terminal 12 .

[0047] According to an embodiment, the drift region 100 is arranged below the fin 16; in other words, the drift region 100 is arranged below the front side 110 of the semiconductor body 10, while the fin 16 is arranged above the front side 110. At the front side 110, the fin may adjoin the drift region 100 or another doped region below the front side 110 of the semiconductor body 10.

[0048] Due to the protruding fins 16 (e.g., characterized by their width being less than the lithographic resolution used to form them), the device 1 (in both MOSFET and IGBT configurations) may also be referred to as a "FinFET controlled power transistor" due to the cell head including a "FinFET structure". However, the device 1 as a whole may also be referred to as a "FinFET". For example, the fins 16 may be characterized by a width less than 100 nm.

[0049] The semiconductor body 10 at the back side 120 can be designed accordingly: in the case of an IGBT configuration (see Figure 1A -B), the drift zone 100 may adjoin a field stop zone 107 of the first conductivity type, which may adjoin an emitter zone 108 of the second conductivity type arranged in electrical connection with the second load terminal 12. As illustrated, the field stop zone 107 of the first conductivity type exhibits a greater dopant concentration than the drift zone 100, but typically exhibits a smaller overall extension in the vertical direction Z than the drift zone 100. In the case of an IGBT configuration (see Figure 1A -B), the drift region 100 may be adjacent to a buffer region 105 of the first conductivity type, which may be adjacent to a contact region 106 of the first conductivity type arranged in electrical connection with the second load terminal 12. As illustrated, the buffer region 105 of the first conductivity type exhibits a greater dopant concentration than the drift region 100, but typically exhibits a smaller overall extension along the vertical direction Z than the drift region 100. Furthermore, as illustrated, the contact region 106 of the first conductivity type exhibits a greater dopant concentration than the buffer region 105, but typically exhibits a smaller overall extension along the vertical direction Z than the buffer region 105.

[0050] The present disclosure relates to the configuration of the fin 16 and corresponding processing techniques, and in particular to the region where the fin 16 abuts the first load terminal 11 .

[0051] For example, refer to Figure 3, the vertical FinFET pattern can be contacted by a contact hole 110 that is wider than the actual fin 16, so as to avoid problems with lateral misalignment and size variation of the pattern etched with the contact hole. Due to vertical tolerances in the contact hole etching, the bottom of the contact hole 110 may reach the control electrode 141, thus creating an electrical short circuit with the first load terminal 11. Even in the absence of a short circuit, variations in the depth of the contact hole 110 can lead to greater device scattering, variations in contact characteristics, or varying electrical characteristics.

[0052] For example, refer to Figure 4 , in the case where the top of the fin 16 embedded in the metal of the first load terminal 11 is fully silicided during the formation of the contact 111, the actual contact interface will be the bottom of the silicided region / contact 111. Therefore, any dispersion of the vertical distance d_C / K between the bottom of the silicided region / contact 111 and the upper end of the first (or second) doped region 101 (or 102) may result in dispersion of device performance.

[0053] To solve the reference Figure 3 and Figure 4 In view of the challenges described above, embodiments of device manufacturing methods are proposed herein. Figures 1A-2B The device 1 described can be based on the following Figures 5 to 13 The invention can be manufactured by one or more of the embodiments of the described methods.

[0054] For example, see Figure 5 In a first step 200 of an embodiment of the method, a semiconductor body 10 is provided with a vertically protruding fin 16 covered by an insulating material 142, which is covered by an electrode material 141, wherein an isolation material 143 at least partially covers the electrode material 141. For example, the starting point can thus be, for example, using as in Figure 5 Preparation of the control electrode 141 of the thin gate layer illustrated in FIG. The isolation material 143 (e.g., based on SiO2) can form a mask layer, which can be formed with an upper edge at the same level as the top of the gate layer. This can be achieved, for example, by using a thicker deposition and adopting a subsequent chemical mechanical polishing (CMP) processing step.

[0055] Then, see Figure 6 , a portion of the electrode material 141 disposed above the upper portion of the fin 16 is exposed (step 210). For example, the mask layer is correspondingly recessed to a level below the lower end of the gate layer on the top of the fin 16, as shown in Figure 6 After step 210, both the control electrode 141 and the mask layer / isolation material 143 may exhibit defined thicknesses h_M and d_G, respectively.

[0056] Subsequently, a step 220 of removing the exposed portion of the electrode material 141 may be performed (see Figure 7 ) to expose the upper portion of the fin 16 covered by the insulating material 142, thereby forming corresponding grooves 222 adjacent to both sides of the exposed upper portion of the fin 16, and the grooves 222 are spatially limited by a) the insulating material 142, b) the electrode material 141 and c) the isolation material 143. For example, an isotropic etching is used to recess the gate layer (electrode material 141) so as to achieve the desired channel length l_G. The etching time can depend on the initial thickness h_M of the mask layer (isolation material 143) because the etching can be isotropic. However, a combination of isotropic and anisotropic etching processes can also be applied as long as they are highly selective to the selected materials 142 and 143.

[0057] Therefore, according to an embodiment, the electrode material removal step 220 may define the channel length l_G in the fin 16. In addition, the electrode material removal step 220 may be based on an isotropic etching process step. The etching process step may be an isotropic etching process step, an anisotropic etching process step or a combination thereof.

[0058] Then, in step 230, see Fig. 8A and Figure 8B , an isolation sidewall spacer 144 adjacent to the isolation material 143 and the insulating material (142) is formed in the recess 222 and on top of the electrode material 141, wherein the sidewall spacer 144 terminates at a pullback distance PBD below the top of the fin 16, wherein at the top of the fin 16, the pullback distance PBD can be, for example, at least 15nm and at most 100nm. During step 230, the insulating material 142 can remain substantially intact. For example, step 230 can be a selective etching process that selectively removes the spacer 144 relative to the insulating material 142. As in Figure 8B As shown in , the previous step 220 of removing part of the electrode material 141 can be performed independently of the channel length l_G. Figure 8B , two different examples of channel length l_G are shown. It must be noted that on both sides of the vertical dotted line, two different embodiments of the device 1 are depicted. The channel length l_G of the left embodiment is different from the channel length l_G of the right embodiment. Figure 8B It is shown that the proposed method works independently of the desired channel length l_G.

[0059] When later forming the contact of the first doped region 101 or the second doped region 102 to the first load terminal 11, a stable process for defining the exposed fin height h_F of the fin 16 above the isolation material 142 is a prerequisite for stable contact characteristics. Therefore, the process variation with respect to the exposed fin height h_F must be kept low. Variations in the isolation thickness Dd need to be accounted for by appropriate device design measures of the device 1.

[0060] For example, in step 230, in order to produce the sidewall spacers 144, an insulator (e.g., Si3N4) is conformally deposited, which can be selectively etched to the isolation material 143 and the control electrode dielectric 142 (isolation material 142). In the next processing step, an anisotropic etching step for the insulator (e.g., Si3N4) is performed. By selecting the thickness of the layer and the etching time, a sidewall spacer 144 with a defined pullback distance PBD from the top of the fin 16 or the upper part of the control electrode dielectric 142, respectively, can be formed. For example, with the availability of sufficient conformal deposition (e.g., using LPCVD (low pressure chemical vapor deposition), PEALD (plasma enhanced atomic layer deposition) Si3N4 process) at a thickness greater than half the thickness of the electrode material 141 (i.e., the gate layer), the illustrated gap between the two sidewall spacers on both sides of the fin 16 can be closed. For less conformal layers (e.g., based on a PECVD (Plasma Enhanced Chemical Vapor Deposition) process) or layers with poor gap-filling capabilities, the maximum spacer width may be limited, as in Fig. 8A and Figure 8B The pullback distances PBD of the inner sidewall spacer 144-1 (adjacent to the fin 16) and the outer sidewall spacer 144-2 (adjacent to the isolation material 143) may be different depending on the relative heights of the isolation material 143 and the isolation material 142 above the fin 16. The pullback distance PBD of the inner sidewall spacer 144-1 is mainly relevant to the device 1 electrically.

[0061] According to an embodiment, the sidewall spacer forming step 230 may include a deposition process step and a subsequent anisotropic etching process step. The duration of the anisotropic etching process step determines the pullback distance PBD. Furthermore, the deposition process step may be an at least substantially conformal deposition process step.

[0062] Even in Figures 1A-2B Although not clearly shown, the isolation sidewall spacer 144 may also be present Figures 1A-2B in the structure.

[0063] refer to Fig.9A and Fig. 9BIn a subsequent step 240, an interlayer dielectric ILD is formed on top of the exposed portion of the device 1 by a) providing additional insulating material 145 and b) a subsequent removal process step to re-expose both the upper portion of the sidewall spacer 144 and the upper portion of the fin 16 by removing a portion of the isolation material 142 covering the fin 16. Fig.9A and Fig. 9B As shown in the figure, the width w can be selected to place the edge of the contact hole at a lateral position of the inner sidewall spacer 144-1 (adjacent to the fin 16) or the outer sidewall spacer 144-2 (adjacent to the isolation material 143). The resulting height h_F of the portion of the fin 16 protruding above the isolation material 142 can be at least 15nm and at most 100nm. A typical value can be about 50nm. For example, ILD 145 can be based on SiO2. For example, first, SiO2 is deposited to form ILD 145, and then a contact hole etch selective to the spacer material 144 can be performed to re-expose the upper portion of the fin 16 and the adjacent sidewall spacer 144. When the etching front reaches the upper edge of the sidewall spacer 144, the end point can be detected and the etching process can be stopped. Therefore, the overlap of the contact hole and the fin 16 is defined by the sidewall spacer 144.

[0064] In such Fig.9A In the embodiment depicted in FIG. 1 , the width w of the contact hole can be defined, for example, as less than (less than by a safety margin) the width of the fin 16 plus twice the thickness of the control electrode dielectric (isolation material) 142, 142-2 adjacent to the fin 16 and twice the thickness of the inner sidewall spacer 144-1. In providing a safety margin, even a process window can be provided for lateral alignment and width variation of the contact hole mask on the fin 16.

[0065] In such Fig. 9B In the embodiment depicted in FIG. 1 , the width w of the contact hole can be defined, for example, as less than (less than by a safety margin) the width of the fin 16 plus twice the thickness of the control electrode dielectric (isolation material) 142, 142-2 adjacent to the fin 16 plus twice the thickness of the control electrode 141. In providing a safety margin, a process window can even be provided for lateral alignment and width variation of the contact hole mask on the fin 16.

[0066] In another embodiment (not depicted), with Fig. 9B In comparison, the width w of the contact hole can be defined to be even larger. In this case, the reaching spacer pattern 144 can deliver an endpoint signal during the etching process of the contact hole. Fig.9A and Fig.9A ), the depth of the contact hole and the overlap with the fin 16 are defined by the spacer pullback PBD.

[0067] Therefore, in an embodiment, sub-step a) of the ILD formation step 240 may include a deposition process step to cover the recess 222, the upper portion of the fin 16, and the isolation material 143 with an additional insulating material 145. Sub-step b) of the ILD formation step 240 may be based on an etching process step. As described above, the etching process step may include detecting that the etching front reaches the sidewall spacer 144, in particular its upper edge.

[0068] Furthermore, as illustrated, the ILD formation step 240 may result in a contact hole where the fin 16 protrudes from the bottom of the contact hole, see Fig.9A -B. The contact hole may exhibit a width w that is less than the sum of the width of the fin 16 , twice the width of the isolation material 142 between the fin 16 and the electrode material 141 , and twice the width of one of the sidewall spacers 144 adjacent to the fin 16 .

[0069] refer to Fig.10 In the next step 250, a first load terminal 11 is formed, for example, above the ILD 145, wherein the first load terminal 11 is configured to contact the upper portion of the fin 16. Before forming the first load terminal 11, the upper portion of the fin 16 may be subjected to at least one silicide formation process step to form the contact 111. In addition, the first doped region 101 and / or the second doped region 102 may be formed in the fin 16 before forming the first load terminal 11, for example, by performing a contact implantation process step on the upper portion of the fin 16.

[0070] exist Figure 11-13 Another embodiment of the method is illustrated in FIG. Fig.11 The diagram is similar to Fig. 8A -B processing stage. Fig.11 , sidewall spacers 144 have been formed, and ILD 143 has been removed down to a level corresponding to the top of sidewall spacers 144; that is, both ILD 143 and sidewall spacers 144 terminate at the same vertical level. Figure 11-13 In an embodiment of the present invention, the material of the sidewall spacer 144 can be selected for better uniformity in order to allow thicker sidewall spacers 144 and allow a larger process window for overlay tolerance of the contact hole lithography for the fin 16. For example, a very conformal oxide film like TEOS (tetraethoxysilane) is selected as the material for the sidewall spacer 144. Since even a low densified PECVD-TEOS will be etched at the same etch rate as other masking oxides or pure SiO2 gate oxide during anisotropic etching, there will be a very uniform pullback of the device surface (such as in Fig.10 Furthermore, a subsequent ALD (atomic layer deposition) process can be used to deposit an oxide film with high precision.

[0071] refer to Fig.12 In step 245, a liner 146, for example based on Si3N4, is deposited. The liner 146 can be selectively etched relative to SiO2. The thickness of the liner can be selected so that the gaps between the sidewall spacers 144 can be covered. The small gaps (not shown) that eventually remain are less important because no high electric field strength occurs (i.e., in the gaps between adjacent sidewall spacers 144).

[0072] Afterwards, see Fig.13 In step 250, the first load terminal 11 may be formed, as described above with respect to Fig.10 Again, before forming the first load terminal 11, the upper portion of the fin 16 may be subjected to at least one silicide formation process step to form the contact 111. In addition, the first doped region 101 and / or the second doped region 102 may be formed in the fin 16 before forming the first load terminal 11, for example, by performing a contact implantation process step on the upper portion of the fin 16.

[0073] If, it is necessary to contact only the fin 16, only the photolithography process can be performed to Fig.12 The etch stop region is opened in the region 115 designated in FIG. 1. In this case, the topology in the contact hole is low and a simple metal stack can be used (e.g., AlSiCu or AlCu over a TiSi / TiN barrier). In case another interlayer dielectric is required for other purposes, a standard contact hole etch with an etch stop on the pad plus a subsequent break-through step through the pad can be used to open that layer.

[0074] Wet chemical cleaning can have a high etch rate for undensified or weakly densified sidewall spacers. Fig.10 and Fig.11 The sidewall spacers 144 in the embodiment cause the resistance to defects during deposition. Fig.10 An optional thin nitride liner (not shown) may be deposited before the (e.g. SiO2-based) sidewall spacers. Since it is intended only as a redundant layer, it can be kept thin and is therefore not critical with respect to non-conformal deposition process steps.

[0075] Also presented herein is a power semiconductor device 1 produced according to one of the exemplary methods described above. That is, as indicated above, Figures 1A to 2B The device illustrated in FIG. 1 may be provided with the sidewall spacer 144 .

[0076] For example, a power semiconductor device 1 according to the present disclosure includes: a semiconductor body 10 having a vertically protruding fin 16 configured to conduct a portion of a nominal load current of the device; a first load terminal 11 in contact with an upper portion of the fin 16. An electrode material 141 is arranged adjacent to the fin 16 and is electrically insulated from the fin 16 based on an insulating material 142. The electrode material 141 is electrically insulated from the first load terminal 11 based on an isolation material 143. The power semiconductor device further includes: an isolation sidewall spacer 144 adjacent to the isolation material 143 and the insulating material 142 on top of the electrode material 141, wherein the sidewall spacer 144 terminates at a pullback distance PBD below the top of the fin 16, wherein the pullback distance PBD is equal to at least 90% of the width of the fin 16 at the top of the fin 16.

[0077] For all embodiments, each of the fins 16 may have a width (along the first lateral direction X) of at least 20 nm, wherein the width may be present at the top of the respective fin 16, and a height (along the vertical direction Z) of at least 0.25 μm. Furthermore, each of the fins 16 may have a width of at most 100 nm and a height of at most 1 μm. The width of the fins 16 may be less than the lithographic resolution used during fabrication of the device 1.

[0078] The height h_F of the portion of the fin 16 protruding above the isolation material 142 may be at least 15 nm and at most 100 nm. A typical value may be about 50 nm.

[0079] Still with respect to all embodiments, provision can be made that, at the vertical level at which contact is established between a first load terminal 11 and a corresponding fin 16, the lateral area of ​​the first load terminal 11 is greater than the lateral area of ​​the contacted fin 16. This optional feature is for example Figures 1A-2B , Figure 4 , Fig.10 and Fig.13 Each of the diagrams is shown in Figure 2.

[0080] Furthermore, the device 1 is not intended for logic processing such as performing computational and / or storage functions, but is intended for use as a power semiconductor device in power applications, such as a power converter, for example. To this end, the nominal load current of the device may be equal to at least 5A.

[0081] In each of the described embodiments, the power semiconductor device 1 may be configured with a forward blocking voltage of at least 500V.

[0082] Furthermore, in each of the described embodiments, the semiconductor body 10 of the power semiconductor device 1 may be based on silicon. In other embodiments, the semiconductor body 10 of the power semiconductor device 1 may be based on silicon carbide SiC or another wide bandgap semiconductor material.

[0083] In the above, embodiments concerning a power semiconductor device and a corresponding manufacturing method were explained.

[0084] For example, these power semiconductor devices are based on silicon (Si). Accordingly, a single-crystal semiconductor region or layer, such as a semiconductor body and its regions / areas, such as regions, etc., may be a single-crystal Si region or Si layer. In other embodiments, polycrystalline or amorphous silicon may be used.

[0085] However, it should be understood that the semiconductor body and its regions / areas can be made of any semiconductor material suitable for manufacturing semiconductor devices. Examples of such materials include, but are not limited to, the following: elemental semiconductor materials, such as silicon (Si) or germanium (Ge); Group IV compound semiconductor materials, such as silicon carbide (SiC) or silicon germanium (SiGe); binary, ternary or quaternary III-V semiconductor materials, such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or gallium arsenide phosphide (InGaAsP); and binary or ternary II-VI semiconductor materials, such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name a few. The previously mentioned semiconductor materials are also referred to as "homojunction semiconductor materials". When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, the following: aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x) and silicon-SiGe heterojunction semiconductor materials. For power semiconductor switch applications, Si, SiC, GaAs and GaN materials are currently used.

[0086] Spatially relative terms such as "below," "below," "lower," "above," "upper," and the like are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the corresponding devices in addition to those different orientations depicted in the figures. Further, terms such as "first," "second," and the like are also used to describe various elements, regions, sections, and the like, and are also not intended to be limiting. Throughout this description, the same terms may refer to the same elements.

Claims

1. A method for manufacturing a power semiconductor device (1), - providing (200) a semiconductor body (10) having a vertically protruding fin (16) covered by an insulating material (142), the insulating material (142) being covered by an electrode material (141), wherein an isolation material (143) at least partially covers the electrode material (141); - exposing (210) a portion of the electrode material (141) arranged above an upper portion of the fin (16); - removing (220) the exposed portion of the electrode material (141) to expose the upper portion of the fin (16) covered by the insulating material (142), thereby forming corresponding grooves (222) adjacent to both sides of the exposed upper portion of the fin (16), the grooves (222) being spatially limited by a) the insulating material (142), b) the electrode material (141) and c) the isolation material (143); - forming (230; 235) an isolation sidewall spacer (144) in the recess (222) and on top of the electrode material (141) adjacent to the isolation material (143) and the insulating material (142), wherein the sidewall spacer (144) terminates at a pullback distance (PBD) below the top of the fin (16), wherein the pullback distance (PBD) is equal to at least 90% of the width of the fin (16) at the top of the fin (16); - forming (240) an interlayer dielectric ILD on top of the exposed portion of the device (1) by a) providing further insulating material (145) and b) a subsequent removal processing step to re-expose both the upper portion of the sidewall spacer (144) and the upper portion of the fin (16) by removing a portion of the isolation material (142) covering the fin (16); - forming (250) a first load terminal (11) configured to contact an upper portion of the fin (16).

2. The method according to claim 1, wherein: Sub-step a) of the ILD formation step (240) includes a deposition process step to cover the recess (222), the upper portion of the fin (16) and the isolation material (143) with a further insulating material (145).

3. The method according to claim 1 or 2, wherein: Sub-step b) of the ILD forming step (240) is based on an etching process step.

4. The method according to claim 4, wherein: The etching process step includes detecting that the etch front reaches the sidewall spacers (144).

5. The method according to one or more of the preceding claims, wherein: The ILD forming step (240) results in a contact hole, wherein the fin (16) protrudes from a bottom of the contact hole.

6. The method according to claim 5, wherein: The contact hole exhibits a width (w) that is less than the sum of the width of the fin (16), twice the width of the isolation material (142) between the fin (16) and the electrode material (141), and twice the width of one of the sidewall spacers (144) adjacent to the fin (16).

7. The method according to one or more of the preceding claims, wherein: The sidewall spacer forming step (230) includes a deposition process step and a subsequent anisotropic etching process step.

8. The method according to claim 7, wherein: The duration of the anisotropic etch process step determines the pullback distance (PBD).

9. The method according to claim 7 or 8, wherein: The deposition process step is a conformal deposition process step.

10. The method according to one or more of the preceding claims, wherein: The electrode material removal step is based on an isotropic etching process step.

11. The method according to one or more of the preceding claims, further comprising: - Subjecting the upper part of the fin (16) to a contact implantation process step.

12. The method according to one or more of the preceding claims, further comprising: - subjecting the upper portion of the fin (16) to at least one silicide formation process step.

13. The method according to one or more of the preceding claims, wherein: The fin (16) has a width of at least 20 nm and a height of at least 0.25 μm.

14. A power semiconductor device (1), wherein: The power semiconductor device (1) has been produced according to the method as claimed in one or more of the preceding claims.

15. A power semiconductor device (1), comprising - a semiconductor body (10) having a vertically protruding fin (16) configured to conduct a portion of a nominal load current of the device; - a first load terminal (11) in contact with the upper portion of the fin (16); - an electrode material (141) arranged adjacent to the fin (16), and o being electrically insulated from the fin (16) by an insulating material (142); o being electrically insulated from the first load terminal (11) by means of an isolating material (143); - On top of the electrode material (141), an isolation sidewall spacer (144) adjacent to the isolation material (143) and the insulating material (142), wherein the sidewall spacer (144) terminates at a pullback distance (PBD) below the top of the fin (16), wherein the pullback distance (PBD) is equal to at least 90% of the width of the fin (16) at the top of the fin (16).

16. The power semiconductor device (1) according to claim 15, wherein: The nominal load current of the device is equal to at least 5A.

17. The power semiconductor device (1) according to one of the preceding claims 14 to 16, wherein: The power semiconductor device (1) is configured with a forward blocking voltage of at least 500V.

18. The power semiconductor device (1) according to one of the preceding claims 14 to 17, wherein: The power semiconductor device (1) has a MOSFET or IGBT configuration.

19. The power semiconductor device (1) according to one of the preceding claims 14 to 18, wherein: The semiconductor body (10) is based on silicon carbide SiC.

20. The power semiconductor device (1) according to one of the preceding claims 15 to 19, wherein: The semiconductor body (10) comprises a front side (110) and a back side (120), wherein the fin (16) protrudes from the front side (110), and wherein the power semiconductor device (1) comprises a second load terminal (12) at the back side (12) of the semiconductor body (10).

21. The power semiconductor device (1) according to claim 20, wherein: The semiconductor body (10) further comprises a drift region (100) between the first load terminal (11) and the second load terminal (12).

22. The power semiconductor device (1) according to one of the preceding claims 20 to 21, wherein: The fin (16) is one of a plurality of fins (16) protruding from the front side, - each of the plurality of fins (16) is connected in parallel between the first load terminal (11) and the second load terminal (12), and Each of the fins (16) is configured to conduct a portion of a load current between the first load terminal (11) and the second load terminal (12).

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