Thyristor and method for manufacturing the same

Abstract

The present invention discloses a thyristor and a preparation method thereof, wherein the thyristor comprises: an anode structure, comprising an anode emission region; a drift region, located at one side of the anode emission region; a cathode structure, located at a side of the drift region away from the anode structure, comprising at least one base region, at least one cathode emission region and at least one cathode turn-off region, wherein the cathode emission region is located in the base region, and the area of ​​the cathode emission region is greater than the area of ​​the cathode turn-off region; and a gate structure layer, located at a side of the drift region away from the anode structure, wherein the gate structure layer covers a part of the drift region, a part of the base region, a part of the cathode emission region and a part of the cathode turn-off region. By increasing the area of ​​the cathode emission region, the current carrying capacity of the thyristor can be improved while ensuring the turn-off performance of the thyristor, thereby improving the peak pulse current that the device can carry when the thyristor is turned on, which is conducive to further improving the turn-on pulse characteristics of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a thyristor and a preparation method thereof. Background Art

[0002] MOS gate-controlled thyristor (Metal-Oxide-Semiconductor-Controlled Thyristor, MCT for short) is a voltage-controlled solid-state pulse power device. MCT combines the Metal-Oxide-Semiconductor Field-Effect Transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET for short) structure with the thyristor structure, so that it has the advantages of voltage drive, high input impedance, low drive power consumption of MOS gate-controlled devices and high voltage, large current, and low on-state voltage drop of thyristor devices. It has broad application prospects in fields such as pulse switching.

[0003] However, the existing MOS gate-controlled thyristors have the problem that the peak pulse current of the device is not large enough when turned on, so that the turn-on pulse characteristics of the device cannot be further improved. Summary of the invention

[0004] In view of the above problems, the present invention is proposed to provide a thyristor and a preparation method thereof that overcome the above problems or at least partially solve the above problems. By increasing the area of ​​the cathode emission region, the current carrying capacity of the thyristor can be improved while ensuring the turn-off performance of the thyristor, thereby increasing the peak pulse current that the device can carry when the thyristor is turned on, which is beneficial to further improve the turn-on pulse characteristics of the device.

[0005] In a first aspect, a thyristor is provided, comprising:

[0006] an anode structure, including an anode emission region;

[0007] A drift region, located on one side of the anode emission region;

[0008] a cathode structure, located on a side of the drift region away from the anode structure, comprising at least one base region, at least one cathode emission region and at least one cathode shut-off region, wherein the cathode emission region is located in the base region, and an area of ​​the cathode emission region is larger than an area of ​​the cathode shut-off region;

[0009] The gate structure layer is located on a side of the drift region away from the anode structure, and covers a portion of the drift region, a portion of the base region, a portion of the cathode emission region, and a portion of the cathode turn-off region.

[0010] In some implementations, along the length direction of the drift region, the length of the cathode emission region is greater than the length of the cathode turn-off region.

[0011] In some implementations, the gate structure layer includes at least two gate structures spaced apart along the length direction of the drift region, the at least two gate structures include a first gate structure and a second gate structure; the at least one base region includes a first base region, the at least one cathode emitter region includes a first cathode emitter region, and the at least one cathode turn-off region includes a first cathode turn-off region;

[0012] The first base region is disposed between the first gate structure and the second gate structure, and the first cathode emission region and the first cathode turn-off region are disposed in the first base region.

[0013] In some implementations, along the length direction of the drift region, the length of the first cathode emission region is greater than the length of the first cathode turn-off region.

[0014] In some implementations, the first gate structure covers a portion of the drift region, a portion of the first base region, and a portion of the first cathode emitter region, and the second gate structure covers a portion of the drift region, a portion of the first base region, and a portion of the first cathode turn-off region.

[0015] In some implementations, the at least two gate structures further include a third gate structure, and the third gate structure is located on a side of the second gate structure away from the first gate structure;

[0016] The at least one base region further includes a second base region disposed between the second gate structure and the third gate structure, and the at least one cathode emitter region further includes a second cathode emitter region disposed in the second base region.

[0017] In some implementations, along the length direction of the drift region, the length of the second cathode emitter region is greater than the spacing between the second gate structure and the third gate structure, the second gate structure also covers a portion of the second base region and a portion of the second cathode emitter region, and the third gate structure covers a portion of the drift region, a portion of the second base region, and a portion of the second cathode emitter region.

[0018] In some implementations, the at least one cathode shut-off region further includes a second cathode shut-off region, and the second cathode shut-off region is disposed in the second base region;

[0019] The second cathode turn-off region is located on a side of the second cathode emitter region close to the second gate structure, the second gate structure also covers a portion of the second base region and a portion of the second cathode turn-off region, and the third gate structure covers a portion of the drift region, a portion of the second base region, and a portion of the second cathode emitter region; or

[0020] The second cathode turn-off region is located on a side of the second cathode emitter region close to the third gate structure, the second gate structure also covers a portion of the second base region and a portion of the second cathode emitter region, and the third gate structure covers a portion of the drift region, a portion of the second base region and a portion of the second cathode turn-off region.

[0021] In some implementations, along the length direction of the drift region, the length of the second cathode emission region is greater than the length of the second cathode turn-off region.

[0022] In some implementations, the gate structure is a planar gate structure or a trench gate structure.

[0023] In some implementations, the gate structure layer includes a polysilicon layer and a gate oxide layer that are stacked, the gate oxide layer wraps the polysilicon layer, and the polysilicon layer is connected to the gate of the thyristor.

[0024] In some implementations, the anode structure further comprises:

[0025] A buffer layer is located between the anode emission region and the drift region.

[0026] In some implementations, the thyristor further includes:

[0027] an anode, located at a side of the anode structure away from the drift region and connected to the anode emission region;

[0028] The cathode is located at a side of the cathode structure away from the drift region and is connected to the at least one cathode emission region and the at least one cathode shutdown region.

[0029] In a second aspect, a method for preparing a thyristor is provided, the method comprising:

[0030] Providing a semiconductor substrate, wherein a drift region is formed in the semiconductor substrate;

[0031] forming an anode structure on one side of the drift region, the anode structure comprising an anode emitter region;

[0032] A cathode structure is formed on a side of the drift region away from the anode structure, wherein the cathode structure includes at least one base region, at least one cathode emission region and at least one cathode shut-off region, wherein the cathode emission region is located in the base region, and an area of ​​the cathode emission region is larger than an area of ​​the cathode shut-off region;

[0033] A gate structure layer is formed on a side of the drift region away from the anode structure, and the gate structure layer covers a portion of the drift region, a portion of the base region, a portion of the cathode emitter region, and a portion of the cathode turn-off region.

[0034] The technical solution provided in the embodiments of the present invention has at least the following technical effects or advantages:

[0035] The thyristor and its preparation method provided by the embodiment of the present invention, the thyristor has an anode structure, a drift region, a cathode structure and a gate structure layer, wherein the cathode structure includes at least one base region, at least one cathode emission region and at least one cathode turn-off region, the cathode emission region is located in the base region, and the area of ​​the cathode emission region is larger than the area of ​​the cathode turn-off region. When the gate applies a forward voltage, at least one cathode emission region in the cathode structure can be activated, so that the electrons in the cathode emission region are injected into the drift region. Since the area of ​​the cathode emission region is larger than the area of ​​the cathode turn-off region, the area of ​​the cathode emission region per unit area can be increased, and the peak pulse current capacity of the thyristor in the on state is enhanced under the premise of ensuring the turn-off performance of the thyristor, thereby increasing the peak pulse current that the thyristor can carry when it is turned on. At the same time, since the diffusion and drift process of the carriers in the emission region will consume a certain amount of time, the large-area emission region can make these processes more fully carried out, so that the thyristor can reach the on state faster, reduce the turn-on time of the device, and improve the turn-on pulse characteristics of the device.

[0036] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0038] Figure 1 It is a structural cross-sectional view of a base resistance controlled thyristor provided by the related technology;

[0039] Figure 2 yes Figure 1 The current distribution diagram when the thyristor is turned on is shown;

[0040] Figure 3 yes Figure 1 The current distribution diagram when the thyristor is turned off is shown;

[0041] Figure 4 is a structural cross-sectional view of a thyristor provided by an embodiment of the present invention;

[0042] Figure 5 is a structural cross-sectional view of another thyristor provided by an embodiment of the present invention;

[0043] Figure 6 yes Figure 5 The current distribution diagram when the thyristor is turned on is shown;

[0044] Figure 7 yes Figure 5 The current distribution diagram when the thyristor is turned off is shown;

[0045] Figure 8 is a structural cross-sectional view of another thyristor provided by an embodiment of the present invention;

[0046] Fig. 9 yes Figure 8 The current distribution diagram when the thyristor is turned on is shown;

[0047] Fig.10 yes Figure 8 The current distribution diagram when the thyristor is turned off is shown;

[0048] Fig.11 is a structural cross-sectional view of another thyristor provided by an embodiment of the present invention;

[0049] Fig.12 is a structural cross-sectional view of another thyristor provided by an embodiment of the present invention;

[0050] Fig.13 yes Fig.12 The current distribution diagram when the thyristor is turned on is shown;

[0051] Fig.14 yes Fig.12 The current distribution diagram when the thyristor is turned off is shown;

[0052] Fig.15 is a pulse characteristic curve diagram of different thyristors provided by an embodiment of the present invention;

[0053] Figures 16 to 18 is a structural cross-sectional view of a thyristor with a trench gate structure provided by an embodiment of the present invention;

[0054] Fig.19 The present invention provides a flow chart of a method for preparing a thyristor. DETAILED DESCRIPTION

[0055] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0056] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0057] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intervening layer / element therebetween. Additionally, if a layer / element is "on" another layer / element in one orientation, the layer / element may be "below" the other layer / element when the orientation is reversed. In the context of the present disclosure, similar or identical components may be denoted by the same or similar reference numerals.

[0058] In order to better understand the above-mentioned technical scheme, the above-mentioned technical scheme will be described in detail below in combination with specific implementation methods. It should be understood that the embodiments of the present disclosure and the specific features in the embodiments are detailed descriptions of the technical scheme of the present application, rather than limitations on the technical scheme of the present application. In the absence of conflict, the embodiments of the present application and the technical features in the embodiments can be combined with each other.

[0059] MOS gate-controlled thyristor (MCT for short) is a voltage-controlled solid-state pulse power device. MCT combines the MOSFET structure with the thyristor structure, making it have the advantages of voltage drive, high input impedance, low drive power consumption of MOS gate-controlled devices and high voltage, high current, and low conduction voltage drop of thyristor devices. It has broad application prospects in fields such as pulse switches. In the 1990s, BJ Baliga et al. first proposed the MCT device structure. Later, in order to further simplify the process, the MCT structure was improved and the base resistance controlled thyristor (BRT for short) structure was proposed.

[0060] Figure 1 It is a structural cross-sectional view of a base resistance controlled thyristor provided by the related technology, such as Figure 1As shown, the BRT structure in the related art includes an anode emitter region 1, a buffer layer 2, a drift region 3 and a plurality of gate structure layers arranged in sequence from bottom to top, and a base region 4, a cathode emitter region 5 and a cathode turn-off region 6 are formed in the drift region 3. Among them, the cathode emitter region 5 is located in the base region 4, and the cathode turn-off region 6 is located outside the base region 4 and is spaced from the base region 4. The gate structure layer includes a gate oxide layer 7 and a polysilicon layer 8 located in the gate oxide layer 7, and the gate of the device is led out by the polysilicon layer 8. An anode connected to the anode emitter region 1 is provided at the bottom of the anode emitter region 1, and a cathode connected to the cathode emitter region 5 and the cathode turn-off region 6 is provided on the cathode emitter region 5 and the cathode turn-off region 6.

[0061] The BRT also includes a PNPN thyristor structure consisting of a cathode emitter region 5, a base region 4, a drift region 3 and an anode emitter region 1, and a PNP parasitic triode structure consisting of a cathode turn-off region 6, a drift region 3 and an anode emitter region 1. The BRT has two MOSFET regions: a PMOS for turning off the thyristor, including the cathode turn-off region 6, the base region 4 and the drift region 3; and an NMOS for turning on the device, including the cathode emitter region 5, the base region 4 and the drift region 3.

[0062] Figure 2 yes Figure 1 The current distribution diagram when the thyristor is turned on is shown in Figure 2 As shown, NMOS is used to provide a driving current for the opening of the thyristor. When a positive voltage is applied to the gate, NMOS is turned on, providing a channel for the electrons in the N+ cathode emitter region 5 to be injected into the N-drift region 3, and providing a base driving current for the PNP parasitic triode structure. If a positive voltage is applied to the anode, the P+ anode region 1 injects holes into the N-drift region 3, passing through the PN junction formed by the N-drift region 3 and the P-type base region 4, and finally triggering the PNP parasitic triode structure, and forming a positive feedback, and the PNPN thyristor is turned on.

[0063] Figure 3 yes Figure 1 The current distribution diagram when the thyristor is turned off is shown in Figure 3 As shown, when a negative voltage is applied to the gate, the PMOS is turned on, carriers in the P-type base region 4 are extracted and stored in the cathode, and the PNP parasitic triode structure is turned off, destroying the positive feedback inside the thyristor and turning off the device.

[0064] Because when in the on state, the current in the thyristor area is mainly determined by the area of ​​the N+ cathode emitter region 5, and the area of ​​the P+ cathode turn-off region 6 responsible for shutdown in the existing BRT structure is comparable to the area of ​​the N+ cathode emitter region 5 responsible for conduction, such a design will cause the peak pulse current of the thyristor device to be not large enough when it is turned on, which is not conducive to further improvement of the device's turn-on pulse characteristics.

[0065] In order to solve the above technical problems, the present invention provides a thyristor, which can be specifically a BRT thyristor. The area of ​​the cathode emitter region responsible for conduction in the thyristor is larger than the area of ​​the cathode turn-off region responsible for turn-off. By increasing the area of ​​the cathode emitter region, while ensuring the turn-off performance of the thyristor, the current carrying capacity of the thyristor can be improved, thereby increasing the peak pulse current that the device can carry when the thyristor is turned on, which is beneficial to further improve the turn-on pulse characteristics of the device.

[0066] Figure 4 is a cross-sectional view of a thyristor structure provided by an embodiment of the present invention, such as Figure 4 As shown, the thyristor includes an anode structure 10 , a drift region 20 , a cathode structure 30 and a gate structure layer 40 .

[0067] The anode structure 10 includes an anode emission region 11, and the drift region 20 is located on one side of the anode emission region 11. The cathode structure 30 is located on the side of the drift region 20 away from the anode structure 10, that is, the cathode structure 30 and the anode structure 10 are located on opposite sides of the drift region 20, and the cathode structure 30 includes at least one base region 31, at least one cathode emission region 32, and at least one cathode shut-off region 33. The cathode emission region 32 is located in the base region 31, and the area of ​​the cathode emission region 32 is larger than the area of ​​the cathode shut-off region 33. The gate structure layer 40 is located on the side of the drift region 20 away from the anode structure 10, and the gate structure layer 40 covers a partial area of ​​the drift region 20, a partial area of ​​the base region 31, a partial area of ​​the cathode emission region 32, and a partial area of ​​the cathode shut-off region 33.

[0068] The area of ​​the cathode emission region 32 is the maximum area of ​​the plane perpendicular to the thyristor current flow direction in the cathode emission region 32, and the area of ​​the cathode turn-off region 33 is the maximum area of ​​the plane perpendicular to the thyristor current flow direction. It should be noted that in the embodiment of the present invention, the area of ​​the cathode emission region and the area of ​​the cathode turn-off region need to be maintained at a certain ratio (the specific ratio is not limited in the embodiment of the present invention) to ensure that the area of ​​the cathode turn-off region is not too small, thereby achieving the improvement of the current carrying capacity of the thyristor while ensuring the turn-off performance of the thyristor.

[0069] In some implementations, along the length direction x of the drift region 20 , the length L1 of the cathode emission region 32 is greater than the length L2 of the cathode shutdown region 33 , so that the area of ​​the cathode emission region 32 is greater than the area of ​​the cathode shutdown region 33 .

[0070] In some implementations, the anode structure 10 further includes a buffer layer 12, which is located between the anode emission region 11 and the drift region 20. The buffer layer 12 can play a buffering role, preventing the anode emission region 11 from being impacted by the current in the drift region 20, thereby improving the stability and life of the anode emission region 11, and can also improve the electric field distribution and improve the voltage resistance of the device.

[0071] In some implementations, the base region 31, the cathode turn-off region 33 and the anode emitter region 11 are all of the first doping type, and the cathode emitter region 32, the drift region 20 and the buffer layer 12 are all of the second doping type. The first doping type may be P-type doping, and the second doping type may be N-type doping.

[0072] Exemplarily, the base region 31 is a P-base region, the cathode turn-off region 33 is a P+ cathode turn-off region, the anode emitter region 11 is a P+ cathode emitter region, the cathode emitter region 32 is an N+ cathode emitter region, the drift region 20 is an N-drift region, and the buffer layer 12 is an N+ buffer layer. Wherein, + and - represent the doping concentration, that is, the doping concentration of the N+ region is greater than the doping concentration of the N- region, and the doping concentration of the P+ region is greater than the doping concentration of the P- region.

[0073] In some implementations, the gate structure layer 40 includes a gate oxide layer 41 and a polysilicon layer 42 which are stacked, the gate oxide layer 41 wraps the polysilicon layer 42, and the polysilicon layer 42 is connected to the gate of the thyristor. Alternatively, the polysilicon layer 42 may also be formed on a side of the gate oxide layer 41 away from the cathode structure 30, and the gate oxide layer 41 may play an insulating role, isolating the polysilicon layer 42 from other conductive structures to improve the working stability of the thyristor. The material of the gate oxide layer 41 may be an insulating material such as silicon dioxide or silicon oxynitride.

[0074] In some implementations, the thyristor further includes an anode 50 and a cathode 60. The anode 50 is located on a side of the anode structure 10 away from the drift region 20, and is connected to the anode emitter region 11. The cathode 60 is located on a side of the cathode structure 30 away from the drift region 20, and is connected to at least one cathode emitter region 32 and at least one cathode turn-off region 33. The anode 50 can be made of a material with high conductivity and high thermal stability, such as aluminum and silicon, and the cathode 60 can be made of a material with high conductivity, such as germanium and silicon, which can provide stable electron injection when the thyristor is working.

[0075] Figure 5 is a cross-sectional view of another thyristor structure provided by an embodiment of the present invention, such as Figure 5 As shown, in some other implementations, the gate structure layer 40 includes at least two gate structures arranged at intervals along the length direction x of the drift region 20, and the at least two gate structures include a first gate structure 40a and a second gate structure 40b. At least one base region 31 includes a first base region 31a, at least one cathode emitter region 32 includes a first cathode emitter region 32a, and at least one cathode shut-off region 33 includes a first cathode shut-off region 33a. The first base region 31a is disposed between the first gate structure 40a and the second gate structure 40b, and the first cathode emitter region 32a and the first cathode shut-off region 33a are disposed in the first base region 31a.

[0076] Since in the related art, the cathode shutoff region and the cathode emission region are respectively arranged between different gate structures, when the BRT device is turned off, it is necessary to apply a negative bias to the gate to turn on the surface PMOS device to make the BRT device enter the shutdown mode, and the existing BRT structure has an extremely low turn-on voltage (usually less than 0.7V), and a small signal disturbance at the input end in the working state is easy to cause the BRT device to be falsely triggered, and it is necessary to add protection measures in the drive control circuit, which increases the complexity of the drive circuit in the pulse power device. Therefore, in the above implementation mode of this embodiment, by setting the cathode shutoff region and the cathode emission region in the same base region between the first gate structure and the second gate structure, the device can also generate a current discharge channel when the gate voltage is 0V, so as to achieve shutdown at 0V, and it is not necessary to apply a negative bias to the gate to turn off the BRT device. At the same time, by introducing the cathode shutoff region in the base region, the forward conduction voltage drop of the BRT device in the forward conduction can also be increased, the probability of false triggering caused by the input end signal disturbance is reduced, the working reliability of the pulse system is improved, and the complexity of the pulse system drive circuit is reduced.

[0077] In some implementations, along the length direction x of the drift region 20 , the length L1 of the first cathode emission region 32a is greater than the length L2 of the first cathode shutdown region 33a , so that the area of ​​the cathode emission region is greater than the area of ​​the cathode shutdown region.

[0078] In some implementations, the first gate structure 40a covers a portion of the drift region 20, a portion of the first base region 31a, and a portion of the first cathode emitter region 32a, and the second gate structure 40b covers a portion of the drift region 20, a portion of the first base region 31a, and a portion of the first cathode turn-off region 33a. At this time, the drift region 20, the first base region 31a, the first cathode emitter region 32a, and the first gate structure 40a constitute an NMOS for turning on the thyristor; the drift region 20, the first base region 31a, the first cathode turn-off region 33a, and the second gate structure 40b constitute a PMOS for turning off the thyristor. Both the NMOS and the PMOS are controlled by the gates derived from their respective gate structures.

[0079] Figure 6 yes Figure 5 The current distribution diagram when the thyristor is turned on is shown in Figure 6 As shown, when a forward voltage is applied to the gate, the NMOS is turned on, and electrons are injected from the first cathode emission region 32a to the first base region 31a. These electrons diffuse through the first base region 31a and gather at the junction between the first base region 31a and the drift region 20. When electrons enter the drift region 20, a forward voltage is applied to the anode, and they act as the base drive current of the PNP parasitic transistor, causing holes to be strongly injected from the junction between the anode emission region 11 and the drift region 20, establishing a positive feedback regeneration behavior, and the PNPN thyristor is turned on.

[0080] Figure 7 yes Figure 5 The current distribution diagram when the thyristor is turned off is shown in Figure 7 As shown, when the device is turned off, the current in the drift region 20 is collected by the junction of the reverse biased drift region 20 and the first base region 31a, and then flows into the cathode through the first cathode turn-off region 33a, the PN junction of the first cathode emitter region 32a and the first base region 31a is short-circuited, the positive feedback of the PNPN thyristor is destroyed, and the device is turned off. At this time, due to the existence of the first cathode turn-off region 33a, a current discharge channel can also be generated when the gate voltage is 0V, so that the device can be turned off at normal voltage.

[0081] In some implementations, see below Figures 8 to 14 At least two gate structures further include a third gate structure 40c, which is located on a side of the second gate structure 40b away from the first gate structure 40a. At least one base region 31 further includes a second base region 31b, which is disposed between the second gate structure 40b and the third gate structure 40c. At least one cathode emission region 32 further includes a second cathode emission region 32b, which is disposed in the second base region 31b.

[0082] In the above implementation, at least two base regions are formed in each thyristor, and a cathode emission region is provided in each base region. The density of the cathode emission regions per unit area is increased compared with that of conventional BRT, so that the thyristor has a larger peak pulse current and a higher pulse current change rate in the forward conduction state, thereby having better pulse discharge characteristics.

[0083] Figure 8 is a structural cross-sectional view of another thyristor provided by an embodiment of the present invention, such as Figure 8 As shown, the at least one cathode turn-off region 33 further includes a second cathode turn-off region 33b, and the second cathode turn-off region 33b is disposed in the second base region 31b.

[0084] The second cathode turn-off region 33b is located on a side of the second cathode emitter region 32b close to the second gate structure 40b, and the second gate structure 40b covers a portion of the drift region 20, a portion of the first base region 31a, a portion of the first cathode turn-off region 33a, a portion of the second base region 31b, and a portion of the second cathode turn-off region 33b, and the third gate structure 40c covers a portion of the drift region 20, a portion of the second base region 31b, and a portion of the second cathode emitter region 32b.

[0085] In the above implementation, the thyristor includes at least two base regions, and each base region is provided with a cathode emission region. Compared with the BRT structure in the related art, the density of the cathode emission region is increased, and while ensuring the thyristor turn-off performance, the current carrying capacity of the thyristor can be further improved, thereby increasing the peak pulse current that the thyristor can carry when the device is turned on, which is conducive to further improving the device turn-on pulse characteristics. And at least one base region is provided with a cathode turn-off region, which can realize the device to be turned off at normal voltage, and improve the forward conduction voltage drop of the BRT device in forward conduction.

[0086] exist Figure 8 In the thyristor structure shown, the drift region 20, the first base region 31a, the first cathode emitter region 32a and the first gate structure 40a form an NMOS; the drift region 20, the first base region 31a, the first cathode turn-off region 33a and the second gate structure 40b form a PMOS; the drift region 20, the second base region 31b, the second cathode turn-off region 33b and the second gate structure 40b form a PMOS; the drift region 20, the second base region 31b, the second cathode emitter region 32b and the third gate structure 40c form an NMOS. In this embodiment, the first cathode emitter region 32a and the second cathode emitter region 32b are both N+ cathode emitter regions, the first base region 31a and the second base region 31b are both P-base regions, the drift region 20 is an N-drift region, and the anode emitter region 11 is a P+ anode emitter region. A PN junction is formed between the first cathode emitter region 32a (N+ cathode emitter region) and the first base region 31a (P-base region), and a PN junction is formed between the second cathode emitter region 32b (N+ cathode emitter region) and the second base region 31b (P-base region). The first cathode emitter region 32a (N+ cathode emitter region), the first base region 31a (P-base region), the drift region 20 (N-drift region) and the anode emitter region 11 (P+ anode emitter region) form a PNPN thyristor.

[0087] Fig. 9 yes Figure 8 The current distribution diagram when the thyristor is turned on is shown in Fig. 9 As shown, when a forward voltage is applied to the gate, the NMOS is turned on, and electrons are injected from the first cathode emission region 32a to the first base region 31a, and from the second cathode emission region 32b to the second base region 31b. These electrons diffuse through the first base region 31a and the second base region 31b, and gather at the junction between the first base region 31a, the second base region 31b and the drift region 20. When electrons enter the drift region 20, a forward voltage is applied to the anode, and they act as the base drive current of the PNP parasitic transistor, causing holes to be strongly injected from the junction between the anode emission region 11 and the drift region 20, establishing a positive feedback regeneration behavior, and the PNPN thyristor is turned on.

[0088] Fig.10 yes Figure 8The current distribution diagram when the thyristor is turned off is shown in Fig.10 As shown, when the device is turned off, the current in the drift region 20 is collected by the junction of the reverse biased drift region 20 and the first base region 31a and the second base region 31b, and then flows into the cathode through the first cathode turn-off region 33a and the second cathode turn-off region 33b, and the PN junction between the first cathode emitter region 32a and the first base region 31a, and the PN junction between the second cathode emitter region 32b and the second base region 31b are short-circuited, the positive feedback of the PNPN thyristor is destroyed, and the device is turned off. At this time, due to the existence of the first cathode turn-off region 33a and the second cathode turn-off region 33b, a current discharge channel can also be generated when the gate voltage is 0V, so that the device can be turned off at 0V.

[0089] Fig.11 is a structural cross-sectional view of another thyristor provided by an embodiment of the present invention, such as Fig.11 As shown, in some implementations, the second cathode turn-off region 33b is located on a side of the second cathode emitter region 32b close to the third gate structure 40c, the second gate structure 40b covers a portion of the drift region 20, a portion of the first base region 31a, a portion of the first cathode turn-off region 33a, a portion of the second base region 31b, and a portion of the second cathode emitter region 32b, and the third gate structure 40c covers a portion of the drift region 20, a portion of the second base region 31b, and a portion of the second cathode turn-off region 33b.

[0090] Fig.11 The thyristor shown with Figure 8 The difference between the thyristors shown in the figure is that the second cathode emission region 32b and the second cathode turn-off region 33b in the second base region 32a are arranged at different positions, and the corresponding gate structure covers different areas. The current distribution of the thyristor when it is turned on and off can be referred to. Fig. 9 and Fig.10 .exist Fig.11 In the thyristor structure shown, the drift region 20, the first base region 31a, the first cathode emitter region 32a and the first gate structure 40a form an NMOS; the drift region 20, the first base region 31a, the first cathode turn-off region 33a and the second gate structure 40b form a PMOS; the drift region 20, the second base region 31b, the second cathode emitter region 32a and the second gate structure 40b form an NMOS; the drift region 20, the second base region 31b, the second cathode turn-off region 33b and the third gate structure 40c form a PMOS.

[0091] Fig.12 is a structural cross-sectional view of another thyristor provided by an embodiment of the present invention, such as Fig.12As shown, in some implementations, along the length direction x of the drift region 20, the length of the second cathode emitter region 32b is greater than the spacing between the second gate structure 40b and the third gate structure 40c, the second gate structure 40b covers a portion of the drift region 20, a portion of the first base region 31a, a portion of the first cathode turn-off region 33a, a portion of the second base region 31b, and a portion of the second cathode emitter region 32b, and the third gate structure 40c covers a portion of the drift region 20, a portion of the second base region 31b, and a portion of the second cathode emitter region 32b.

[0092] exist Fig.12 In the thyristor structure shown, the drift region 20, the first base region 31a, the first cathode emitter region 32a and the first gate structure 40a form an NMOS; the drift region 20, the first base region 31a, the first cathode turn-off region 33a and the second gate structure 40b form a PMOS; the drift region 20, the second base region 31b, the second cathode emitter region 32b and the second gate structure 40b form an NMOS; the drift region 20, the second base region 31b, the second cathode emitter region 32b and the third gate structure 40c form an NMOS. Figure 8 and Fig.11 Compared to the thyristor shown, Fig.12 In the second base region 31 b of the thyristor shown, only one second cathode emitter region 32 b is provided. The area of ​​the second cathode emitter region 32 b can be set larger, and the number of NMOS can be larger.

[0093] Fig.13 yes Fig.12 The current distribution diagram when the thyristor is turned on is shown in Fig.13 As shown, when a forward voltage is applied to the gate, the NMOS on the left side of the first base region 31a and the NMOS on both sides of the second base region 31b are turned on at the same time. Compared with other thyristor structures, the current path when the device is turned on is increased, the turn-on speed of the device is accelerated, and the area of ​​the cathode emission region is increased. The thyristor area increases when turned on, and the pulse peak current is further increased.

[0094] Fig.14 yes Fig.12 The current distribution diagram when the thyristor is turned off is shown in Fig.14 As shown, when the thyristor is turned off, the current in the drift region 20 is collected by the junction between the reverse biased drift region 20 and the first base region 31a and the second base region 31b, and then flows into the cathode through the first cathode turn-off region 33a, the NPN transistor is turned off, the positive feedback of the PNPN thyristor is destroyed, and the thyristor is turned off.

[0095] In some implementations, along the length direction of the drift region 20, the length of the second cathode emission region 32b is greater than the length of the second cathode shutdown region 33b, so that the area of ​​the cathode emission region is greater than the area of ​​the cathode shutdown region.

[0096] Fig.15 is a pulse characteristic curve diagram of different thyristors provided by the embodiment of the present invention, such as Fig.15 As shown in the figure, the horizontal axis represents the opening time t of the thyristor, and the vertical axis represents the pulse peak current I peak The first thyristor represents a thyristor in the related art, and the second thyristor is Figure 8 The thyristors shown, the third thyristor represents Fig.12 The thyristor shown. Compared with the first thyristor, the area of ​​the cathode emission region of the second thyristor is increased, so the pulse peak current obtained by the second thyristor during pulse discharge is increased compared with the first thyristor; compared with the second thyristor, the area of ​​the cathode emission region of the third thyristor is increased, so the pulse peak current obtained by the third thyristor during pulse discharge is increased compared with the second thyristor. In addition, since the number of NMOS in the third thyristor is increased compared with the second thyristor, the turn-on time of the third thyristor is also shortened compared with the second thyristor, and the turn-on delay time is reduced. It can be seen that the pulse peak current of the thyristor proposed in the present invention is increased and the turn-on time is shortened compared with the conventional BRT thyristor structure. Therefore, the thyristor of the present invention has a greater turn-on speed, a greater pulse current rise rate during pulse discharge, and the pulse characteristics of the thyristor are improved.

[0097] In some implementations, the gate structure is a planar gate structure or a trench gate structure. Figures 4 to 14 Each gate structure (including the first gate structure 40 a , the second gate structure 40 b and the third gate structure 40 c ) in the thyristor shown is a planar gate structure, that is, each gate structure is formed on a side of the drift region 30 away from the anode structure. Figures 16 to 18 is a cross-sectional view of a thyristor having a trench gate structure provided by an embodiment of the present invention, wherein Fig.16 The thyristor shown with Figure 5 The thyristor structure shown is the same, Fig.17 The thyristor shown with Figure 8 The thyristor structure shown is the same, Fig.18 The thyristor shown with Fig.12 The thyristors shown have the same structure, differing only in that Figures 16 to 18 Each gate structure in the thyristor shown is a trench gate structure. Along the thickness direction z of the drift region 20, the trench gate structure penetrates the cathode structure 30 and a part of the drift region 20. Fig.17For example, along the thickness direction z of the drift region 20, the first trench gate structure 40a penetrates the first cathode emitter region 32a, the first base region 31a and part of the drift region 20, the second trench gate structure 40b penetrates the first cathode turn-off region 33a, the second cathode turn-off region 33b, the first base region 31a, the second base region 31b and part of the drift region 20, and the third trench gate structure 40c penetrates the second cathode emitter region 32b, the second base region 31b and part of the drift region 20.

[0098] Fig.19 is a flow chart of a method for preparing a thyristor provided by an embodiment of the present invention, such as Fig.19 As shown, the preparation method is used to prepare the thyristor described in the above embodiment, and the preparation method comprises:

[0099] Step S1901: provide a semiconductor substrate, wherein a drift region is formed in the semiconductor substrate.

[0100] In some embodiments, the semiconductor substrate may be a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, a silicon germanium substrate or a germanium substrate. The drift region is a region doped with a certain concentration of N-type impurities such as phosphorus. The doping concentration and thickness of the drift region may be set according to actual needs.

[0101] Step S1902: forming an anode structure on one side of the drift region, wherein the anode structure includes an anode emitter region.

[0102] In some implementations, a process such as ion implantation may be used to dope one side of the drift region to form a P+ anode emitter region. As described above, when the anode structure includes a buffer layer, before forming the P+ anode emitter region, a process such as ion implantation may be used to form an N+ buffer layer on one side of the drift region, and then a P+ anode emitter region is formed on the side of the N+ buffer layer away from the drift region.

[0103] In some implementations, after executing step S1902 and before executing step S1903, the preparation method may further include: performing metallization treatment on a side of the P+ anode emitter region away from the drift region to form an anode.

[0104] Step S1903, forming a cathode structure on a side of the drift region away from the anode structure, the cathode structure including at least one base region, at least one cathode emitter region and at least one cathode shut-off region, the cathode emitter region is located in the base region, and the area of ​​the cathode emitter region is larger than the area of ​​the cathode shut-off region.

[0105] In some implementations, step S1903 includes:

[0106] An ion implantation process is used to dope the side of the drift region away from the anode structure to form at least one P-base region, at least one N+ cathode emitter region and at least one P+ cathode turn-off region, and the N+ cathode emitter region is located in the P-base region.

[0107] It should be noted that, during the preparation process, the area of ​​the cathode emission region can be made larger than the area of ​​the cathode turn-off region by controlling the relevant parameters of the ion implantation process. In the preparation process, according to the actual thyristor structure to be manufactured, the relevant parameters of the ion implantation process can be controlled to form the above-mentioned thyristor embodiment on the side of the drift region away from the anode structure. Figures 4 to 14 The various cathode structures shown are not described in detail in this embodiment.

[0108] In some implementations, after executing step S1903 and before executing step S1904, the preparation method may further include: metallizing the side of the cathode structure away from the drift region to form an anode connected to at least one cathode emission region and at least one cathode shutdown region.

[0109] Step S1904 , forming a gate structure layer on a side of the drift region away from the anode structure, the gate structure layer covering a portion of the drift region, a portion of the base region, a portion of the cathode emitter region and a portion of the cathode turn-off region.

[0110] In some implementations, the gate structure layer includes a stacked gate oxide layer and a polysilicon layer, the gate oxide layer wraps the polysilicon layer, and the polysilicon layer is connected to the gate of the thyristor. Chemical vapor deposition, photolithography, etching and other processes can be used to form the required gate oxide layer and polysilicon layer on the side of the drift region away from the anode structure.

[0111] As mentioned above, the gate structure layer includes a plurality of gate structures, and the plurality of gate structures are planar gate structures or trench gate structures. In some implementations, when the plurality of gate structures are planar gate structures, chemical vapor deposition, photolithography, and etching processes can be used to sequentially form the gate structures on the side of the drift region away from the anode structure as shown in the above thyristor embodiment. Figures 4 to 14 When the multiple gate structures are trench gate structures, multiple trenches can be first formed on the side of the drift region away from the anode structure by using processes such as photolithography and etching, and then chemical vapor deposition and other processes can be used to sequentially form the above-mentioned thyristor embodiments in the multiple trenches. Figures 16 to 18 Multiple trench gate structures are shown.

[0112] It should be noted that the formation order of each structure in the above preparation method can be determined according to actual needs, as long as the thyristor structures described in the above embodiments can be prepared. The thyristor prepared by the preparation method can be a BRT thyristor.

[0113] The technical solutions provided in the above embodiments of the present application have at least the following technical effects or advantages:

[0114] A thyristor and a preparation method thereof provided in an embodiment of the present invention, wherein the thyristor has an anode structure, a drift region, a cathode structure and a gate structure layer, wherein the cathode structure includes at least one base region, at least one cathode emission region and at least one cathode turn-off region, the cathode emission region is located in the base region, and the area of ​​the cathode emission region is larger than the area of ​​the cathode turn-off region. When a forward voltage is applied to the gate, at least one cathode emission region in the cathode structure can be activated, so that electrons in the cathode emission region are injected into the drift region. Since the area of ​​the cathode emission region is larger than the area of ​​the cathode turn-off region, the area of ​​the cathode emission region per unit area can be increased, and the peak pulse current capacity of the thyristor in the on state is enhanced while ensuring the turn-off performance of the thyristor, thereby increasing the peak pulse current that the thyristor can carry when it is turned on. At the same time, since the diffusion and drift process of carriers in the emission region consumes a certain amount of time, a large-area emission region can make these processes more fully carried out, so that the thyristor can reach the on state faster, reduce the turn-on time of the device, and improve the turn-on pulse characteristics of the device.

[0115] In the base resistance controlled thyristor disclosed in the present application, the cathode emitter region and the cathode turn-off region are directly located in the base region (i.e., in direct contact with the base region), and at the same time, the cathode turn-off region has two functions as a PMOS source region and as a direct hole path when turned off. Therefore, the base resistance controlled thyristor in the present application is smaller in size and has a simpler structure.

[0116] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0117] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the intention that the claimed invention requires more features than those explicitly recited in each claim. More specifically, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Therefore, the claims that follow the specific embodiment are hereby expressly incorporated into the specific embodiment, with each claim itself serving as a separate embodiment of the present invention.

[0118] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims.

Claims

1. A thyristor, characterized in that: include: an anode structure, including an anode emission region; A drift region, located on one side of the anode emission region; a cathode structure, located on a side of the drift region away from the anode structure, comprising at least one base region, at least one cathode emission region and at least one cathode shut-off region, wherein the cathode emission region is located in the base region, and an area of ​​the cathode emission region is larger than an area of ​​the cathode shut-off region; The gate structure layer is located on a side of the drift region away from the anode structure, and covers a portion of the drift region, a portion of the base region, a portion of the cathode emission region, and a portion of the cathode turn-off region.

2. The thyristor according to claim 1, characterized in that: Along the length direction of the drift region, the length of the cathode emission region is greater than the length of the cathode turn-off region.

3. The thyristor according to claim 1, characterized in that: The gate structure layer includes at least two gate structures arranged at intervals along the length direction of the drift region, and the at least two gate structures include a first gate structure and a second gate structure; the at least one base region includes a first base region, the at least one cathode emitter region includes a first cathode emitter region, and the at least one cathode turn-off region includes a first cathode turn-off region; The first base region is disposed between the first gate structure and the second gate structure, and the first cathode emission region and the first cathode turn-off region are disposed in the first base region.

4. The thyristor according to claim 3, characterized in that: Along the length direction of the drift region, the length of the first cathode emission region is greater than the length of the first cathode turn-off region.

5. The thyristor according to claim 3, characterized in that: The first gate structure covers a portion of the drift region, a portion of the first base region, and a portion of the first cathode emitter region, and the second gate structure covers a portion of the drift region, a portion of the first base region, and a portion of the first cathode turn-off region.

6. The thyristor according to claim 3, characterized in that: The at least two gate structures further include a third gate structure, and the third gate structure is located on a side of the second gate structure away from the first gate structure; The at least one base region further includes a second base region disposed between the second gate structure and the third gate structure, and the at least one cathode emitter region further includes a second cathode emitter region disposed in the second base region.

7. The thyristor according to claim 6, characterized in that: Along the length direction of the drift region, the length of the second cathode emitter region is greater than the spacing between the second gate structure and the third gate structure, the second gate structure also covers a portion of the second base region and a portion of the second cathode emitter region, and the third gate structure covers a portion of the drift region, a portion of the second base region, and a portion of the second cathode emitter region.

8. The thyristor according to claim 6, characterized in that: The at least one cathode shut-off region further comprises a second cathode shut-off region, wherein the second cathode shut-off region is disposed in the second base region; The second cathode turn-off region is located on a side of the second cathode emitter region close to the second gate structure, the second gate structure also covers a portion of the second base region and a portion of the second cathode turn-off region, and the third gate structure covers a portion of the drift region, a portion of the second base region, and a portion of the second cathode emitter region; or, The second cathode turn-off region is located on a side of the second cathode emitter region close to the third gate structure, the second gate structure also covers a portion of the second base region and a portion of the second cathode emitter region, and the third gate structure covers a portion of the drift region, a portion of the second base region and a portion of the second cathode turn-off region.

9. The thyristor according to claim 8, characterized in that: Along the length direction of the drift region, the length of the second cathode emission region is greater than the length of the second cathode turn-off region.

10. The thyristor according to any one of claims 3 to 9, characterized in that: The gate structure is a planar gate structure or a trench gate structure.

11. The thyristor according to claim 1, characterized in that: The gate structure layer comprises a gate oxide layer and a polysilicon layer which are stacked, the gate oxide layer wraps the polysilicon layer, and the polysilicon layer is connected to the gate of the thyristor.

12. The thyristor according to claim 1, characterized in that: The anode structure further comprises: A buffer layer is located between the anode emission region and the drift region.

13. The thyristor according to claim 1, characterized in that: The thyristor further comprises: an anode, located at a side of the anode structure away from the drift region and connected to the anode emission region; The cathode is located at a side of the cathode structure away from the drift region and is connected to the at least one cathode emission region and the at least one cathode shutdown region.

14. A method for preparing a thyristor, characterized in that: The preparation method comprises: Providing a semiconductor substrate, wherein a drift region is formed in the semiconductor substrate; forming an anode structure on one side of the drift region, the anode structure comprising an anode emitter region; A cathode structure is formed on a side of the drift region away from the anode structure, wherein the cathode structure includes at least one base region, at least one cathode emission region and at least one cathode shut-off region, wherein the cathode emission region is located in the base region, and an area of ​​the cathode emission region is larger than an area of ​​the cathode shut-off region; A gate structure layer is formed on a side of the drift region away from the anode structure, and the gate structure layer covers a portion of the drift region, a portion of the base region, a portion of the cathode emitter region, and a portion of the cathode turn-off region.

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