Semiconductor device and forming method thereof

Abstract

A semiconductor device and a method of fabricating the same are provided. The method includes forming a first gate on a first fin and forming a first spacer layer on a sidewall of the first gate, and forming a second gate on a second fin and forming a second spacer layer on a sidewall of the second gate. The epitaxial layer of the second composition in the first fin is replaced by a disposable interposer disposed below the first gate and first internal spacer layers located at opposite ends of the disposable interposer. And etching back two opposite transverse end parts of the epitaxial layer of the second composition in the second fin part to form a groove below the second gap wall layer and between adjacent epitaxial layers of the first composition. A second internal spacer layer is formed within the second fin sheet within each recess on opposite lateral ends of the second composition epitaxial layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor technology, and more particularly to a semiconductor device and a method for forming the same. Background Art

[0002] The electronics industry is experiencing an ever-increasing demand for smaller and faster electronic devices that are simultaneously capable of supporting more and more increasingly complex and sophisticated functions. As a result, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been achieved in large part by shrinking the size (e.g., minimum feature size) of semiconductor integrated circuits (ICs), thereby increasing production efficiency and reducing associated costs. However, this miniaturization has also increased the complexity of semiconductor manufacturing processes. Therefore, achieving continued advancements in semiconductor integrated circuits and devices requires similar advancements in semiconductor manufacturing processes and technologies.

[0003] Recently, multi-gate devices have been introduced in an attempt to improve gate control, reduce off-state current, and reduce short-channel effects (SCE) by increasing gate-channel coupling. One such multi-gate device that has been introduced is the FinFET. FinFETs are named after the fin structures that extend from a substrate formed on the structure to form the FET channel. Another multi-gate device is the gate-all-around (GAA) transistor, which was introduced in part to address performance challenges associated with FinFETs. GAA transistors are named for their gate structure that extends completely around the channel, providing better electrostatic control than FinFETs. FinFETs and GAA transistors are compatible with conventional complementary metal oxide semiconductor (CMOS) processes, and their three-dimensional structures allow them to be scaled significantly while maintaining gate control and reducing short channel effects (SCE).

[0004] Generally speaking, when, for example, FinFETs can no longer meet performance requirements, gate-all-around (GAA) transistors can be used. However, the manufacture of gate-all-around (GAA) transistors introduces new challenges to the semiconductor manufacturing process and leads to related device reliability issues. Therefore, the prior art has not proven to be completely satisfactory in all respects. Summary of the invention

[0005] In some embodiments, a method for forming a semiconductor device is provided, comprising: providing a first fin in a first type device region and providing a second fin in a second type device region. The first fin comprises a first epitaxial layer stack having a plurality of first semiconductor channel layers sandwiched by a plurality of first dummy layers; and the second fin comprises a second epitaxial layer stack having a plurality of second semiconductor channel layers sandwiched by a plurality of second dummy layers. The method further comprises: covering the second fin, and when the second fin is covered, the method further comprises: removing the first dummy layer from the first type device region to form a first gap between two adjacent ones of the first semiconductor channel layers; forming a dielectric layer in a first channel region in the first gap between two adjacent ones of the first semiconductor channel layers; and forming a plurality of first internal spacer layers in the first gap between two adjacent ones of the first semiconductor channel layers and on opposite sides of the dielectric layer.

[0006] In some embodiments, a method for forming a semiconductor device is provided, comprising: providing a first fin structure having a plurality of epitaxial layers consisting of a first component sandwiched between a plurality of epitaxial layers consisting of a second component, and providing a second fin structure having a plurality of epitaxial layers consisting of a first component sandwiched between a plurality of epitaxial layers consisting of a second component; forming a first dummy gate above the first fin structure and forming a first spacer layer on the sidewall of the first dummy gate, and forming a second dummy gate above the second fin structure and forming a second spacer layer on the sidewall of the second dummy gate; using a first dummy gate disposed on the first dummy gate structure to form a first spacer layer on the sidewall of the second dummy gate; The epitaxial layer composed of the second component in the first fin structure is replaced by a plurality of disposable interlayers below the fin and a plurality of first internal spacer layers located on two opposite ends of the disposable interlayer and below the first spacer layer; the two opposite lateral ends of the epitaxial layer composed of the second component in the second fin structure are etched back to form a plurality of grooves arranged below the second spacer layer and between adjacent epitaxial layers composed of the first component; and a plurality of second internal spacer layers are formed in the second fin structure and in each of the grooves at the two opposite lateral ends of the epitaxial layer composed of the second component.

[0007] In some embodiments, a semiconductor device is provided, comprising: a first fin extending from a substrate in a P-type device region and a second fin extending from a substrate in an N-type device region, wherein the first fin includes a plurality of first semiconductor channel layers, and the second fin includes a plurality of second semiconductor channel layers; a plurality of first internal spacer layers disposed between two adjacent ones of the first semiconductor channel layers and located on either side of a first channel region; and a plurality of second internal spacer layers disposed between two adjacent ones of the second semiconductor channel layers and located on either side of a second channel region. Each of the first semiconductor channel layers has a substantially rectangular shape, and each of the second semiconductor channel layers has a dog-bone structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A simplified top-down layout diagram of a multi-gate device according to some embodiments is shown;

[0009] Figure 2 A flow chart of a method for manufacturing a semiconductor device 300 according to one or more aspects of the present disclosure is shown, wherein the semiconductor device 300 includes a P-type device 300A and an N-type device 300B;

[0010] Figure 3A , 4A , 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A and 19A illustrate various stages of the process of method 200 according to some embodiments, providing a P-type device 300A along a substantially parallel Figure 1 A schematic cross-sectional view of a planar embodiment of the plane defined by the section AA'; and

[0011] Figure 3B , 4B , 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B and 19B illustrate various stages of the process of method 200 according to some embodiments, providing an N-type device 300B along a substantially parallel Figure 1 A schematic cross-sectional view of a planar embodiment of the invention is shown in FIG.

[0012] Description of reference numerals:

[0013] 100: Multi-gate device

[0014] 104: fin; fin part

[0015] 105,107: Source / drain region

[0016] 108: Gate structure

[0017] 200: Method; Semiconductor manufacturing method

[0018] 202,204,206,208,210,212,214,216,218,220,222,224,226: Step area 300: Device

[0019] 300A: P type device

[0020] 300B: N-type device

[0021] 304: Base

[0022] 304A: Base

[0023] 306: Fins

[0024] 308: epitaxial layer; epitaxial layer formed by the first component

[0025] 310: epitaxial layer; epitaxial layer formed by the second composition

[0026] 316: Gate Stack

[0027] 320,502,1902: Dielectric layer

[0028] 322: Electrode layer

[0029] 325,327: Spacer layer

[0030] 330,1706: Groove

[0031] 404,1004: Patterned photoresist layer; Patterned resist layer

[0032] 604,1104: Groove

[0033] 702,1202: Internal spacer material

[0034] 702A,1202A: Internal spacer

[0035] 902,1402: Source / drain feature parts

[0036] 902A,1402A: First epitaxial layer

[0037] 902B, 1402B: Second epitaxial layer

[0038] 1602: Contact Etch Stop Layer (CESL)

[0039] 1604: Interlayer dielectric (ILD) layer

[0040] 1708,1808: Gap

[0041] 1904: Metal layer

[0042] 1916: Gate structure DETAILED DESCRIPTION

[0043] The following disclosure provides many different embodiments or examples to implement different characteristic components of the present disclosure. The following disclosure describes specific examples of various components and their arrangement in order to simplify the present disclosure. Of course, these are only examples and are not used to define the present disclosure. For example, if the following disclosure describes that a first characteristic component is formed on or above a second characteristic component, it means that it includes an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and also includes an embodiment in which additional characteristic components can be formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact. In addition, the present disclosure will repeat numbers and / or text in various different examples. Repetition is for the purpose of simplification and clarification, rather than listing and specifying the relationship between the various different embodiments and / or configurations discussed.

[0044] Furthermore, spatially related terms such as "under", "below", "lower", "over", "upper", etc. are used herein to easily express the relationship between a device or feature in the drawings shown in this specification and another device or feature. These spatially related terms not only cover the orientation shown in the drawings, but also cover different orientations of the device during use or operation. The device can have different orientations (rotated 90 degrees or other orientations) and the spatially related symbols used herein are also interpreted accordingly.

[0045] Additionally, in the following description, the dimensions (e.g., thickness, width, length, etc.) of a given layer or other feature may sometimes be described using terms such as "substantially equal," "equal," or "about," where such terms should be understood to mean within + / -10% of the referenced value or between the comparative values. For example, if dimension A is described as being "substantially equal to" dimension B, it should be understood that dimension A is within + / -10% of dimension B. In another example, if a film layer is described as having a thickness of approximately 100 nm, it should be understood that the thickness of the film layer may be within a range between 90-110 nm.

[0046] It should also be noted that the present disclosure proposes embodiments in the form of multi-gate transistors. Multi-gate transistors include those transistors whose gate structures are formed on at least two sides of the channel region. These multi-gate devices may include P-type transistors or N-type transistors. Specific examples may be presented herein and referred to as gate-all-around (GAA) transistors. A gate-all-around (GAA) transistor includes any device whose gate structure or a portion thereof is formed on four sides of the channel region (e.g., surrounding a portion of the channel region). The devices proposed herein also include embodiments having a channel region disposed within a semiconductor channel layer. In various embodiments, the semiconductor channel layer may include a nanosheet channel, a nanowire channel, a strip channel, and / or other appropriate channel configurations. The device embodiments proposed herein are those having one or more channel regions (e.g., a semiconductor channel layer) and a single continuous gate structure. However, it is known to those skilled in the art that the above teachings may be applied to a single channel (e.g., a single semiconductor channel layer) or any number of channels. Other examples of semiconductor devices of various forms that may benefit from the present disclosure may be known to those skilled in the art.

[0047] A silicon / silicon germanium (Si / SiGe) superlattice (including a Si channel layer sandwiched by a sacrificial SiGe layer (or SiGe interposer)) may be formed as part of a gate-all-around (GAA) transistor fabrication process. In one example, the SiGe interposer (or portion thereof) is removed after a source / drain epitaxial growth process and subsequently replaced by a gate structure disposed in a channel region between adjacent Si channel layers. Additionally, an internal spacer layer is formed between lateral ends of adjacent Si channel layers and between the epitaxial source / drain features and the gate structure disposed in the channel region. Prior to removal of the SiGe interposer, and due to dopant diffusion (e.g., diffusion of Ge) that occurs as a result of the process, an unwanted SiGe / Si intermixed layer may be formed at the interface between the Si interposer and the Si channel layer and along the interface adjacent to the internal spacer layer. The high built-in stress that may result from the presence of the above intermixed layer and the SiGe layer may negatively impact gate-all-around (GAA) transistor performance. Even after the SiGe interposer is replaced by the gate structure, Ge residues may still exist in the corners between the gate structure, Si channel layer, and the internal spacer layer, which can cause interface traps and reduce device mobility. The dog-bone structure formed by the Si channel layer adjacent to the internal spacer layer also leads to higher fringing capacitance, which further reduces device performance. Therefore, the prior art has not proven to be completely satisfactory in all forms.

[0048] Embodiments of the present disclosure provide advantages over the prior art, although it should be understood that other embodiments may provide different advantages, but not all advantages are necessarily discussed herein, nor are all embodiments required to have a particular advantage. For example, the embodiments discussed herein include methods and structures for sandwiching a disposable interposer between semiconductor channel layers of a gate-all-around (GAA) transistor to address existing challenges. As described above, the difficulties associated with SiGe interposers primarily affect P-type gate-all-around (GAA) transistors (or PFETs). In some cases, for N-type gate-all-around (GAA) transistors (or NFETs), the use of SiGe interposers can provide enhanced tensile stress in the Si channel layer, thereby improving device performance. Therefore, according to some embodiments, for P-type gate-all-around (GAA) transistors (but not for N-type gate-all-around (GAA) transistors), the SiGe interposer can be replaced with a disposable interposer (e.g., such as an oxide or other dielectric material). Of course, in some cases, for both P-type gate-all-around (GAA) transistors and N-type gate-all-around (GAA) transistors, the SiGe interposer can be replaced with a disposable interposer. In other examples, for N-type gate all around (GAA) transistors (but not for P-type gate all around (GAA) transistors), the SiGe interposer may be replaced with a disposable interposer.

[0049] In some embodiments, a method for sandwiching a disposable interposer between semiconductor channel layers of a gate all-around (GAA) transistor includes first removing (e.g., by a wet etching process) a SiGe layer (sandwiched between adjacent semiconductor channel layers) and re-depositing an oxide or other dielectric material layer to conformally fill the cavity (formed by removing the SiGe layer). Thereafter, a recessing process is performed to recess the deposited oxide or other dielectric material layer to form an internal spacer layer groove between lateral ends of adjacent semiconductor channel layers. In some embodiments, the recessing process includes vapor dilute hydrofluoric acid (dHF) acid etching (which can be performed using a gas chemical etching system from Tokyo Electron Limited, Japan). Afterwards, the inner spacer material is deposited and etched back (e.g., using a dry etching process) to complete the inner spacer. After the inner spacer is formed, the epitaxial source / drain features are formed and the remaining oxide or other dielectric material layer is removed to form a gap between adjacent semiconductor channel layers, and then a metal gate structure is formed in the gap.

[0050] By replacing the SiGe interposer with a disposable interposer (e.g., oxide or other dielectric material), the embodiments of the gate-all-around (GAA) transistor disclosed herein prevent the formation of a SiGe / Si mixed layer (e.g., by removing a Ge diffusion source), reduce interface traps (e.g., by avoiding the formation of Ge residues at the corners between the gate structure, the Si channel layer, and the internal spacer layer), provide higher mobility and drive current, reduce edge capacitance (e.g., by minimizing the formation of dog-bone structures formed by the Si channel layer), provide enhanced control of short channel effects (SCE), and provide enhanced compressive stress in the Si channel layer (e.g., for a P-type gate-all-around (GAA) transistor), thereby improving device performance. In some embodiments, for an N-type gate-all-around (GAA) transistor, and as described above, the SiGe interposer can continue to be used to provide enhanced tensile stress in the Si channel layer. Other embodiments and advantages will become apparent to those skilled in the art after reading this disclosure.

[0051] For the following illustrative purposes, Figure 1 A simplified top-down layout diagram of a multi-gate device 100 is provided. In various embodiments, the multi-gate device 100 may include a gate all-around (GAA) transistor. The multi-gate device 100 may include a plurality of fin members 104 extending from a substrate, a gate structure 108 disposed above and around the fin members 104, and source / drain regions 105, 107, wherein the source / drain regions 105, 107 are formed within, on, and / or around the fin members 104. A channel region of the multi-gate device 100 (which may include a plurality of semiconductor channel layers) is disposed within the fin members 104, below the gate structure 108, and along a plane (which is substantially parallel to the plane formed by the substrate). Figure 1 In some embodiments, the sidewall spacers may also be formed on the sidewalls of the gate structure 108. Figure 2 Various other features of the multi-gate device 100 are described in more detail.

[0052] Please refer to Figure 2 , which shows a semiconductor manufacturing method 200 according to various embodiments, including the manufacture of a semiconductor device 300 (e.g., including a multi-gate device), wherein a disposable interposer is used instead of a SiGe interposer. The method 200 is described below with reference to the manufacture of a gate-all-around (GAA) transistor. However, it should be understood that various aspects of the method 200 may be equally applicable to other types of multi-gate devices, or to other types of devices implemented with multi-gate devices, without departing from the scope of the present disclosure. In some embodiments, the method 200 may be used to manufacture the above-referenced Figure 1The multi-gate device 100 is shown. Therefore, one or more aspects described above with reference to the multi-gate device 100 may also be applicable to the method 200. It should be understood that the method 200 includes steps that are characteristic of complementary metal oxide semiconductor (CMOS) technology. Therefore, only a brief description of the process flow is provided herein. In addition, additional steps may be performed before, after, and / or during the method 200.

[0053] It should also be noted that in some embodiments, the semiconductor device 300 may include various other devices and features, such as other types of devices (e.g., additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses and / or other logic circuits, etc.), but are simplified for a better understanding of the inventive concepts of the present disclosure. In some embodiments, the semiconductor device 300 may include multiple semiconductor devices (e.g., transistors) that may be interconnected. In addition, it should be noted that the process steps of the method 200, including any description given with reference to the accompanying drawings, are exemplary only and are not intended to limit what is specifically described in the appended claims.

[0054] Method 200 begins in step area 202, where a substrate including a partially fabricated device is provided. Figure 3A In the example of step 202, a locally manufactured device 300 is provided. In the example shown, the locally manufactured device 300 includes a P-type device 300A formed in a P-type device region and an N-type device 300B formed in an N-type device region. Specifically, Figure 3A-19A For each stage of the process according to method 200, along a substantially parallel path formed by Figure 1 The plane defined by the plane of the cross section AA' provides an embodiment of a P-type device 300A. Similarly, Figure 3B-19B For each stage of the process according to method 200, along a substantially parallel path formed by Figure 1 The plane defined by the cross section AA' provides an embodiment of an N-type device 300B.

[0055] Device 300 includes both a P-type device 300A and an N-type device 300B, and is formed on a substrate 304. In some embodiments, substrate 304 may be a semiconductor substrate, such as a silicon substrate. Substrate 304 may include different film layers, including a conductive layer or an insulating layer formed on a semiconductor substrate. As known in the art, substrate 304 may include various doping configurations depending on design requirements. Substrate 304 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, substrate 304 may include a compound semiconductor and / or an alloy semiconductor. Furthermore, substrate 304 may selectively include an epitaxial layer (epi-layer), may be strained to enhance performance, may include a silicon-on-insulator (SOI) structure, and / or have other suitable enhanced feature components.

[0056] like Figure 3A As shown in FIG. 3B, each of the P-type device 300A and the N-type device 300B includes a fin 306 having a base portion 304A (formed by a substrate 304), an epitaxial layer 308 formed by a first composition, and an epitaxial layer 310 formed by a second composition (which is sandwiched between the epitaxial layer 308 formed by the first composition). In some cases, a shallow trench isolation (STI) component may be formed to isolate the fin 306 from an adjacent fin. For illustrative purposes, the epitaxial layer 308 formed by the first composition includes a dummy layer (also referred to as a sacrificial layer or an interposer), and the epitaxial layer 310 formed by the second composition includes a semiconductor channel layer. In one embodiment, the epitaxial layer 308 formed by the first composition includes SiGe (e.g., to provide a SiGe interposer), and the epitaxial layer 310 formed by the second composition includes silicon (Si) (e.g., to provide a Si channel layer). It is also noted that while the epitaxial layers 308, 310 are shown as having a particular stacking order within the fin 306, wherein the epitaxial layer 310 is the topmost layer of the stack of epitaxial layers 308, 310 for each of the P-type device 300A and the N-type device 300B, other configurations are possible. For example, in some cases, the epitaxial layer 308 may also be the topmost layer of the stack of epitaxial layers 308, 310 for one or both of the P-type device 300A and the N-type device 300B. In other words, the growth order of the epitaxial layers 308, 310 and their stacking order may be interchanged or different from that shown in the figure and also be included in the scope of the present disclosure.

[0057] In various embodiments, the epitaxial layer 310 (e.g., including the second composition) or a portion thereof may form a channel region for a gate-all-around (GAA) transistor for the P-type device 300A and the N-type device 300B. For example, the epitaxial layer 310 may be referred to as a semiconductor channel layer for forming a channel region for a gate-all-around (GAA) transistor. In various embodiments, the semiconductor channel layer (e.g., the epitaxial layer 310 or a portion thereof) may include a nanosheet channel, a nanowire channel, a strip channel, and / or other appropriate channel configurations. In some embodiments, the semiconductor channel layer may also be used to form a local source / drain feature component of a gate-all-around (GAA) transistor for the P-type device 300A and the N-type device 300B.

[0058] It should be noted that although the fin 306 is shown as including three (3) epitaxial layers 308 and three (3) epitaxial layers 310, this is for illustrative purposes only and is not intended to limit the content specifically described in the claims. It is understood that any number of epitaxial layers can be formed, where, for example, the number of epitaxial layers depends on the desired number of semiconductor channel layers of the gate-all-around (GAA) transistors of the P-type device 300A and the N-type device 300B. In some embodiments, the number of epitaxial layers 310 and the number of semiconductor channel layers are between 3 and 10. In some examples, the number of epitaxial layers 308 and the number of epitaxial layers 310 can be different for each of the P-type device 300A and the N-type device 300B. In some examples, the number of epitaxial layers 308 and the number of epitaxial layers 310 can be the same for each of the P-type device 300A and the N-type device 300B.

[0059] In some embodiments, the epitaxial layer 308 (dummy layer / sacrificial layer / intermediary layer) each has a thickness in the range of about 3-8 nanometers (nm). In some cases, the epitaxial layer 310 (semiconductor channel layer) each has a thickness in the range of about 8-12nm. As described above, the epitaxial layer 310 can be used as a channel region of a subsequently formed multi-gate device (e.g., a gate all-around (GAA) transistor), and its thickness can be selected at least in part based on device performance considerations. The epitaxial layer 308 can be used to define the gap distance between adjacent channel regions of the subsequently formed multi-gate device, and its thickness can also be selected at least in part based on device performance considerations. In some examples, the thickness of the epitaxial layer 308 and the epitaxial layer 310 can be different for each of the P-type device 300A and the N-type device 300B. In other examples, the thickness of the epitaxial layer 308 and the epitaxial layer 310 can be the same for each of the P-type device 300A and the N-type device 300B.

[0060] The P-type device 300A and the N-type device 300B also include a gate stack 316 formed above the fin 306. In one embodiment, the gate stack 316 is a dummy (sacrificial) gate stack that is subsequently removed and replaced in the final gate stack of the subsequent process stage of the P-type device 300A and the N-type device 300B. For example, the gate stack 316 can be replaced by a high-K dielectric layer (HK) and a metal gate electrode (MG) in a subsequent process stage. Although the present description relates to a replacement gate (gate-last) process in which a dummy gate structure is formed and then replaced, other configurations (e.g., a gate-first process) are possible. The portion of the fin 306 located below the gate stack 316 can be referred to as the channel region of the P-type device 300A and the N-type device 300B. The gate stack 316 can also define the source / drain region of the fin 306, such as the fin 306 region adjacent to the channel region and located on two opposite sides of the channel region.

[0061] In some embodiments, the gate stack 316 includes a dielectric layer 320 and an electrode layer 322 located above the dielectric layer 320. In some embodiments, the dielectric layer 320 includes silicon oxide. Alternatively or additionally, the dielectric layer 320 may include silicon nitride, a high-K dielectric material, or other suitable materials. In some embodiments, the electrode layer 322 may include polysilicon. In some embodiments, after forming the gate stack 316, one or more spacer layers 325, 327 may be formed on the sidewalls of the gate stack 316. In some cases, the one or more spacer layers 325, 327 may include a dielectric material (e.g., silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, a low-K material (e.g., a dielectric constant 'k' <7) and / or a combination thereof. In some embodiments, the one or more spacer layers 325, 327 include multiple film layers, such as a main spacer layer, a liner layer, or a similar film layer.

[0062] Next, the method 200 proceeds to step area 204, where a source / drain etching process is performed. Figure 3A In the embodiment of step area 204, a source / drain etching process is performed on each of the P-type device 300A and the N-type device 300B. In some embodiments, the source / drain etching process is performed to remove the exposed epitaxial layers 308, 310 in the source / drain regions of each of the P-type device 300A and the N-type device 300B to form a trench 330, which exposes a portion of the substrate 304 located below. The source / drain etching process (and the trench 330) is also used to expose the side surfaces of the epitaxial layers 308, 310, such as Figure 3A / 3B. In some embodiments, the source / drain etching process may also remove part of one or more spacer layers 325, 327. In some embodiments, the source / drain etching process may include a dry etching process, a wet etching process and / or a combination thereof.

[0063] The method proceeds to step area 206, where the dummy epitaxial layer is removed from the P-type device region. Figure 3A / 3B and Figure 4A In the example of step 206, a patterned photoresist layer 404 is first formed on the N-type device region (including the N-type device 300B), while exposing the P-type device region (including the P-type device 300A). For example, the formation of the patterned resist layer 404 may include forming a resist layer on the device 300 (including on each of the P-type device 300A and the N-type device 300B), exposing the resist to form a pattern (for example, defined by a mask), performing a post-exposure bake process, and developing the exposed resist to form the patterned resist layer 404.

[0064] In some embodiments, after forming the patterned resist layer 404, and in another embodiment of step area 206, the dummy epitaxial layer (e.g., epitaxial layer 308 or SiGe interposer) is selectively removed (e.g., using a selective etching process) from the P-type device 300A, but the semiconductor channel layer (epitaxial layer 310) of the P-type device 300A remains substantially unetched, and the N-type device 300B remains covered by the patterned resist layer 404. In various examples, the selective removal of the dummy epitaxial layer (or SiGe interposer) from the P-type device 300A completely removes the epitaxial layer 308, thereby eliminating the possibility of Ge diffusion and / or Ge residue after subsequent device processing. However, in some embodiments, the above-mentioned Ge diffusion and / or Ge residue can remain in the N-type device 300B, and the N-type device 300B can still use the SiGe interposer. The selective etching process (step area 204) to remove the epitaxial layer 308 from the P-type device 300A can be performed through the trench 330 provided by the source / drain etching process. In some embodiments, the selective etching process may include a selective wet etching process. In some cases, the selective wet etching includes ammonia (NH3) and / or ozone (O3). In just one example, the selective wet etching process includes tetra-methyl ammonium hydroxide (TMAH). In some embodiments, the selective etching process may include using a gas chemical etching system from Tokyo Electron Limited, Japan. to perform a dry plasma-free etching process. In some examples, the selective etching process may include etching using a standard clean 1 (SC-1) solution, ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and water (H2O), hydrofluoric acid (HF), a buffered HF solution and / or a fluorine (F2)-based etch. In some examples, the fluorine (F2)-based etch may include fluorine (F2) remote plasma etching. It should be noted that due to the selective removal of the dummy epitaxial layer or SiGe interposer (epitaxial layer 308), a gap (or cavity) 402 is formed between adjacent semiconductor channel layers (epitaxial layer 310) of the P-type device 300A. In some embodiments, and after removing the dummy epitaxial layer (step area 206) from the P-type device area, the epitaxial layer 310 can maintain a substantially rectangular shape. In this way, the formation of a dog-bone structure of the epitaxial layer 310 (semiconductor channel layer) can be reduced, and the associated edge capacitance can be reduced.

[0065] After removing the dummy epitaxial layer from the P-type device region (step area 206), the method 200 then proceeds to step area 208 where a dielectric layer is deposited in the P-type device region. Figure 4A / 4B and Figure 5A / 5B, in an embodiment of step region 208, a dielectric layer 502 is conformally deposited over the device 300. Specifically, the dielectric layer 502 is conformally deposited within the trench 330 of the P-type device 300A and within the gap (or cavity) 402 (which was previously formed between adjacent semiconductor channel layers (epitaxial layers 310) of the P-type device 300A). In some embodiments, the dielectric layer 502 can be deposited so that it completely fills the gap (or cavity) 402. As shown and in some cases, the dielectric layer 502 can also be deposited over the patterned resist layer 404, which is used to cover and protect the N-type device 300B.

[0066] In some embodiments, the dielectric layer 502 may include an oxygen-containing layer (e.g., an oxide layer such as SiO2), a nitrogen-containing layer (e.g., a nitride layer such as SiN), an oxygen- and nitrogen-containing layer (e.g., silicon oxynitride (SiON)), a metal oxide (e.g., aluminum oxide (Al2O3), a carbon-containing layer (e.g., silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), or silicon oxycarbonitride (SiOCN)), a low-K value material (e.g., a dielectric constant "k" <7), and / or a combination thereof. In some cases, the dielectric layer 502 may be conformally deposited using a process (e.g., an ALD process, a CVD process, or other suitable process). In various examples, the dielectric layer 502 may have a thickness in the range of 3-8 nm. According to embodiments of the present disclosure, the dielectric layer 502 may serve as a disposable interposer, as further described herein.

[0067] Next, the method 200 proceeds to step area 210, where the dielectric layer previously deposited in the P-type device area is recessed. Figure 5A / 5B and Fig. 6A / 6B, in an embodiment of step region 210, a recess process is performed on the device 300. Specifically, and in a different example, the recess process etches the dielectric layer 502 from above the upper surface of the P-type device 300A, and from above the upper surface of the patterned resist layer 404 disposed above the N-type device 300B (the N-type device 300B is protected by the patterned resist layer 404). Furthermore, the recess process etches the dielectric layer 502 from the sidewalls of the trench 330 along the P-type device 300A, and at least partially etches the dielectric layer 502 from between the lateral ends of the adjacent semiconductor channel layers (epitaxial layers 310) of the P-type device 300A to form a groove 604, while the dielectric layer 502 is still at least partially disposed between the adjacent semiconductor channel layers (epitaxial layers 310) of the P-type device 300A. The portion of dielectric layer 502 remaining between adjacent semiconductor channel layers will serve as a disposable interlayer, effectively replacing the SiGe interlayer (epitaxial layer 308) previously disposed between the semiconductor channel layers (epitaxial layer 310) of the P-type device 300A. During subsequent stages of the process, as described below, the disposable interlayer will be removed and replaced by a portion of the gate structure (e.g., a metal gate structure) that is connected to the corresponding adjacent internal interlayer. In some examples, when the dielectric layer 502 includes an oxide layer, the recess process (step area 210) includes using a gas chemical etching system from Tokyo Electron Limited, Japan. To perform vapor diluted hydrofluoric acid (dHF) acid etching. In some embodiments, a wet etching process (e.g., phosphoric acid (H3PO4) chemical etching) can be used to recess the dielectric layer 502 (step area 210). In some other examples, a high temperature sulfuric peroxide mixture (HTSPM) cycle with dilute hydrofluoric acid (dHF), ozone (O3) and dilute hydrofluoric acid (dHF), or a combination thereof can be used to perform the above-mentioned recessing process.

[0068] Next, the method 200 proceeds to step area 212, where an inner spacer layer is formed in the P-type device region. Fig. 6A / 6B and Fig. 7A / 7B, in the embodiment of step area 212, first, the inner spacer material 702 is conformally deposited over the device 300. Specifically, the inner spacer material 702 is conformally deposited in the trench 330 of the P-type device 300A and in the recess 604 of the P-type device 300A (e.g., formed by recessing the dielectric layer 502 in step area 210). The conformally deposited inner spacer material 702 may substantially fill the recess 604 and contact the side surface of the recessed dielectric layer 502 (disposable interposer). In some embodiments, the inner spacer material 702 may include amorphous silicon. In some examples, the inner spacer material 702 may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, a low-K material (e.g., having a dielectric constant 'k' <7), and / or a combination thereof. For example, the inner spacer material 702 may be formed by conformally depositing the inner spacer material 702 over the device 300 using a process (e.g., an ALD process, a CVD process, or other suitable process). As shown and in some cases, the inner spacer material 702 may also be deposited over the patterned resist layer 404 to cover and protect the N-type device 300B.

[0069] Please refer to Fig. 7A / 7B and Fig. 8A / 8B, in another embodiment of step area 212, an internal spacer etch back process is performed. Specifically, and in some embodiments, the internal spacer etch back process etches the internal spacer material 702 from the upper surface of the P-type device 300A and from the upper surface of the patterned resist layer 404 disposed above the N-type device 300B (the N-type device 300B is protected by the patterned resist layer 404). Furthermore, the internal spacer etch back process etches the internal spacer material 702 from the sidewalls of the trench 330 along the P-type device 300A, while the internal spacer material remains disposed in the recess 604, thereby providing the P-type device 300A with an internal spacer 702A. The internal spacer etch back process for forming the internal spacer 702A may include a wet etching process, a dry etching process, or a combination thereof. In some cases, any remaining portions of the internal spacer material 702 remaining on the upper surface of the P-type device 300A and / or remaining on the sidewalls or lower surfaces of the trench 330 of the P-type device 300A, such as after an internal spacer etch-back process, can be removed during a subsequent cleaning process (e.g., prior to epitaxial growth of source / drain features). In various examples, the internal spacer 702A can extend below one or more spacer layers 325, 327 (which are formed on the sidewalls of the gate stack 316 of the P-type device 300A) while being disposed adjacent to subsequently formed source / drain features, as described below. In some cases, the internal spacer 702A can extend at least partially below the gate stack 316 of the P-type device 300A.

[0070] Next, the method 200 proceeds to step area 214 where source / drain features are formed in the P-type device region. Fig. 8A / 8B and Fig. 8A / 8B and Fig.9A / 9B, in the embodiment of step region 214 and after forming the internal spacer layer 702A, a source / drain feature 902 is formed in the source / drain region adjacent to and on both sides of the gate stack 316 of the P-type device 300A. In one embodiment, the source / drain feature 902 may include a first epitaxial layer 902A, the first epitaxial layer 902A is formed in the trench 330 of the P-type device 300A, is located above the exposed portion of the substrate 304, and is in contact with the adjacent internal spacer layer 702A and the channel layer (epilayer 310) of the P-type device 300A. Furthermore, the source / drain feature 902 may include a second epitaxial layer 902B, the second epitaxial layer 902B is formed in the trench 330 of the P-type device 300A and is not above the first epitaxial layer 902A. In some embodiments, as previously described, a cleaning process may be performed to remove any remaining portions of the internal spacer material immediately prior to forming the source / drain features 902. The cleaning process may include wet etching, hot etching, or a combination thereof.

[0071] In some embodiments, the source / drain feature 902 including the first epitaxial layer 902A and the second epitaxial layer 902B is formed by epitaxially growing one or more semiconductor material layers in the source / drain region. Generally speaking, the one or more semiconductor material layers used to grow the formed source / drain feature 902 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiB, SiGeBx, SiAs, SiPAsx, SiC, SiCP or other suitable materials. The source / drain feature 902 may be formed by one or more epitaxial (epi) processes, and in some cases, in-situ doping may be performed during the epitaxial growth process. For example, and in some embodiments, a P-type source / drain feature (e.g., source / drain feature 902) formed in a P-type device region may include a SiGe or boron doped epitaxial layer (e.g., SiB or SiGeBx). In some embodiments, the source / drain features 902 are not doped in situ, but an implantation process is performed to dope the source / drain features 902. In different examples, the first epitaxial layer 902A and the second epitaxial layer 902B may include different semiconductor material layers and / or their respective semiconductor material layers include different doping configurations. In at least some cases, the first epitaxial layer 902A and the second epitaxial layer 902B may include substantially similar (or identical) semiconductor material layers and / or their respective semiconductor material layers include substantially similar (or identical) doping configurations.

[0072] Next, the method 200 proceeds to step area 216, where an internal spacer layer is formed in the N-type device region. First, after forming the source / drain feature 902 and referring to Fig.9A / 9B and Fig. 10A / 10B, the patterned resist layer 404 can be removed (for example, by a solvent, a resist stripper, ashing or other suitable techniques). Thereafter, a patterned photoresist (resist) layer 1004 is formed over the P-type device region (including the P-type device 300A), while exposing the N-type device region (including the N-type device 300B). Fig. 10B As shown, the exposure of the N-type device 300B exposes the trench 330 in the N-type device region, including the portion of the substrate 304 located below and the side surfaces of the epitaxial layers 308 and 310. The formation of the patterned resist layer 1004 may include forming a resist layer above the device 300 (including above each of the P-type device 300A and the N-type device 300B), exposing the resist layer to form a pattern (e.g., a pattern defined by a mask), performing a post-exposure bake process, and developing the exposed resist, thereby forming the patterned resist layer 1004.

[0073] Please refer to Fig. 10A / 10B and 11A / 11B, after forming the patterned resist layer 1004 and in the embodiment of step area 216, a dummy layer recessing process is performed on the N-type device 300B. The dummy layer recessing process includes lateral etching of the epitaxial layer 308 to form a groove 1104 along the sidewalls of the trench 330 of the N-type device 300B, while the epitaxial layer 308 remains at least partially disposed between adjacent semiconductor channel layers (epilayer 310) of the N-type device 300B. The portion of the epitaxial layer 308 remaining between the adjacent semiconductor channel layers will serve as a SiGe interposer (epilayer 308). During subsequent stages of the process, as described below, the SiGe interposer will be removed and replaced by a portion of a gate structure (e.g., a metal gate structure) connected to the corresponding adjacent internal spacer layer. In some embodiments, the dummy layer recessing process is performed using a dry etching process, a wet etching process, and / or a combination thereof. In some cases, the dummy layer recessing process may include performing etching and using a standard clean 1 (SC-1) solution, ozone (O3), ammonium hydroxide (NH4OH) solution, hydrogen peroxide (H2O2) and water (H2O), hydrofluoric acid (HF), buffered hydrofluoric acid (HF) and / or fluorine (F2) based etching. In some examples, the fluorine (F2) based etching may include fluorine (F2) remote plasma etching.

[0074] Please refer to Fig.11A / 11B and Fig. 12A / 12B, after the dummy layer recess process and in another embodiment of step area 216, an inner spacer layer material 1202 is conformally deposited over the device 300. Specifically, the inner spacer layer material 1202 is conformally deposited in the trench 330 of the N-type device 300B and in the recess 1104 (e.g., formed by the dummy layer recess process, as described above). The conformally deposited inner spacer layer material 1202 can substantially fill the recess 1104 and contact the side surface of the recessed epitaxial layer 308 (SiGe interposer). In some embodiments, the inner spacer layer material 1202 can include amorphous silicon. In some examples, the inner spacer layer material 1202 can include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, a low-K material (e.g., having a dielectric constant "k" <7) and / or a combination thereof. For example, the internal spacer material 1202 can be formed by using a process (e.g., an ALD process, a CVD process, or other suitable process) to conformally deposit the internal spacer material 1202 over the device 300. As shown and in some cases, the internal spacer material 1202 can also be deposited over the patterned resist layer 1004 to cover and protect the P-type device 300A.

[0075] Please refer to Fig. 12A / 12B and Fig.13A / 13B, in another embodiment of step area 216, an internal spacer etch back process is performed. Specifically, in some embodiments, the internal spacer etch back process etches the internal spacer material 1202 from above the upper surface of the N-type device 300B and from above the upper surface of the patterned resist layer 1004 disposed on the P-type device 300A (the P-type device 300A is protected by the patterned resist layer 1004). Furthermore, the internal spacer etch back process etches the internal spacer material 1202 from the sidewalls of the trench 330 along the N-type device 300B, while the internal spacer material remains disposed in the recess 1104, thereby providing the N-type device 300B with an internal spacer 1202A. The internal spacer etch back process for forming the internal spacer 1202A may include a wet etching process, a dry etching process, or a combination thereof. In some cases, any remaining portions of the inner spacer material 1202 remaining on the upper surface of the N-type device 300B and / or remaining on the sidewalls or lower surfaces of the trench 330 of the N-type device 300B, such as after the inner spacer etch-back process, can be removed during a subsequent cleaning process (e.g., prior to epitaxial growth of source / drain features). In various examples, the inner spacer 1202A can extend below one or more spacer layers 325, 327 formed on the sidewalls of the gate stack 316 of the N-type device 300B while being disposed adjacent to subsequently formed source / drain features, as described below. In some cases, the inner spacer 1202A can partially extend below the gate stack 316 of the N-type device 300B.

[0076] Next, the method 200 proceeds to step area 218 where source / drain features are formed in the N-type device region. Fig.13A / 13B and Fig.14A / 14B, in the embodiment of step area 218 and after forming the inner spacer layer 1202A, the source / drain feature 1402 is formed in the source / drain region adjacent to and on both sides of the gate stack 316 of the N-type device 300B. In one embodiment, the source / drain feature 1402 may include a first epitaxial layer 1402A formed in the trench 330 of the N-type device 300B, located above the exposed portion of the substrate 304, and in contact with the adjacent inner spacer layer 1202A and the semiconductor layer (epilayer 310) of the N-type device 300B. Furthermore, the source / drain feature 1402 may include a second epitaxial layer 1402B formed in the trench 330 of the N-type device 300B and formed above the first epitaxial layer 1402A. In some embodiments, as previously described, a cleaning process may be performed immediately before forming the source / drain feature 1402 to remove any remaining portions of the inner spacer layer material. The cleaning process may include wet etching, dry etching, or a combination thereof.

[0077] In some embodiments, the source / drain feature 1402 including the first epitaxial layer 1402A and the second epitaxial layer 1402B is formed by epitaxially growing one or more semiconductor material layers in the source / drain region. In general, the one or more semiconductor material layers grown to form the source / drain feature 1402 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiB, SiGeBx, SiAs, SiPAsx, SiC, SiCP or other suitable materials. The source / drain feature 1402 may be formed by one or more epitaxial (epi) processes, and in some cases, in-situ doping may be performed during the epitaxial growth process. For example, and in some embodiments, an N-type source / drain feature (e.g., source / drain feature 1402) formed in an N-type device region may include SiP or an arsenic-doped epitaxial layer (e.g., SiAs or SiPAsx). In some embodiments, the source / drain feature 1402 is not doped in situ, but an implantation process is performed to dope the source / drain feature 1402. In different examples, the first epitaxial layer 1402A and the second epitaxial layer 1402B may include different semiconductor material layers and / or each semiconductor material layer includes a different doping configuration. In at least some cases, the first epitaxial layer 1402A and the second epitaxial layer 1402B may include substantially similar (or identical) semiconductor material layers and / or each semiconductor material layer includes substantially similar (or identical) doping configuration. After forming the source / drain feature 1402, refer to Figures 14A-14B and Fig.15A / 15B, the patterned resist layer 1004 may be removed (eg, by solvent, resist stripper, ashing, or other suitable technique).

[0078] Thereafter, the method 200 proceeds to step region 220 where a contact etch stop layer (CESL) and an inter-layer dielectric (ILD) layer are formed. Fig.15A / 15B and Fig.16A / 16B, after forming the source / drain feature 1402 and removing the patterned resist layer 1004, and in the embodiment of step area 220, a contact etch stop layer (CESL) 1602 may be conformally formed over the device 300 (including the P-type device 300A and the N-type device 300B). Specifically, the contact etch stop layer (CESL) 1602 may be formed in the opening (disposed above each of the source / drain feature 902 and the source / drain feature 1402, and located between adjacent gate stacks 316 in the corresponding P-type device 300A and the corresponding N-type device 300B). In some examples, the contact etch stop layer (CESL) 1602 may include a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other materials known in the art. In some embodiments, and in another embodiment of step area 220 , an interlayer dielectric (ILD) layer 1604 for each of the P-type device 300A and the N-type device 300B may be formed on the contact etch stop layer (CESL) 1602 . In different cases, the interlayer dielectric (ILD) layer 1604 may include tetraethylorthosilicate (TEOS) oxide, undoped silicate glass or doped silicon oxide materials (e.g., borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. In some embodiments, after forming the interlayer dielectric (ILD) layer 1604, the device 300 may undergo a high thermal budget process to anneal the interlayer dielectric (ILD) layer 1604. In some embodiments, after forming the contact etch stop layer (CESL) 1602 and the interlayer dielectric (ILD) layer 1604, a chemical mechanical polishing (CMP) process may be performed. A CMP (conductively coupled membrane polishing) process is performed to remove a portion of the interlayer dielectric (ILD) layer 1604 and a portion of the contact etch stop layer (CESL) 1602 located above the gate stack 316 and any hard mask layer that may exist above the gate stack 316, so as to planarize the upper surface of the device 300 and expose the upper surface of the electrode layer 322 of the gate stack 316 of each of the P-type device 300A and the N-type device 300B.

[0079] Next, the method 200 proceeds to step area 222 where the dummy gate stacks (gate stack 316) are removed from the P-type and N-type device regions, and the disposable interposer is removed from the P-type device region. Fig.16A / 16B and Fig.17A / 17B example, in the embodiment of step area 222, the electrode layer 322 of the gate stack 316 of each of the P-type device 300A and the N-type device 300B (for example, exposed by a chemical mechanical polishing (CMP) process, as described above) can be removed by a suitable etching process to form a trench 1706 (which exposes the dielectric layer 320 of the gate stack 316 of each of the P-type device 300A and the N-type device 300B). In some examples, the etching process for removing the electrode layer 322 can include wet etching, dry etching, or a combination thereof. Thereafter, in some embodiments, an etching process can be performed to remove the exposed dielectric layer 320 from the trench 1706 of each of the P-type device 300A and the N-type device 300B. In some examples, the etching process for removing the dielectric layer 320 can include wet etching, dry etching, or a combination thereof. In some examples, the removal of dielectric layer 320 may be performed using vapor dilute hydrofluoric acid (dHF) etching and may be performed using a gas chemical etching system from Tokyo Electron Limited, Japan. In some embodiments, the removal of dielectric layer 320 may be performed using a wet etching process (e.g., phosphoric acid (H3PO4) chemical etching of dielectric layer 320). In some other examples, cycles of high temperature sulfur peroxide mixture (HTSPM) with dilute hydrofluoric acid (dHF), ozone (O3) and dilute hydrofluoric acid (dHF), or a combination thereof may be used to remove dielectric layer 320.

[0080] It is noted that because the dielectric layer 320 and the portion of the dielectric layer 502 that remains between the adjacent semiconductor channel layers (disposable interposer) disposed within the channel region of the P-type device 300A may be composed of the same or similar materials (e.g., the dielectric layer 320 and the disposable interposer may both include an oxide layer, a nitride layer, or other similar dielectric layer), the process of removing the dielectric layer 320 may also selectively remove the disposable interposer (e.g., during the same etching process) while the semiconductor channel layer (epitaxial layer 310) and the internal spacer layer 702A remain substantially unetched. However, the SiGe interposer of the N-type device 300B (e.g., including the portion of the epitaxial layer 308 that remains between the adjacent semiconductor channel layers) may remain unetched by the process of removing the dielectric layer 320. It is also noted that the removal of the electrode layer 322 and the dielectric layer 320 provides for the removal of the dummy gate (gate stack 316) (e.g., as part of a replacement gate process). Therefore, in just one example, if both the dielectric layer 320 and the disposable interposer of the P-type device 300A include oxide layers (or nitride layers or other similar dielectric layers), the disposable interposer will be removed along with the dielectric layer 320 (as part of the replacement gate process).

[0081] Due to the selective removal of the remaining portion of the dielectric layer 502 (disposable interposer), a gap 1708 is formed between adjacent semiconductor channel layers (epitaxial layer 310) in the channel region of the P-type device 300A. For example, the gap 1708 is used to expose a first portion of the epitaxial layer 310 between the opposing internal spacer layers 702A, while a second portion of the epitaxial layer 310 remains covered by the internal spacer layer 702A. As described in more detail below, a portion of the gate structure (e.g., including a metal gate stack having an interface layer, a high-K dielectric layer, and one or more metal electrode layers) will be formed within the gap 1708 between adjacent semiconductor channels (epitaxial layer 310) and in contact with the internal spacer layer 702A.

[0082] The method 200 then proceeds to step area 224 where the SiGe interposer is removed from the N-type device region. Fig.17A / 17B and Fig.18A / 18B, in the embodiment of step area 224, the SiGe interposer (the portion of the epitaxial layer 308 remaining between adjacent semiconductor channel layers, which may also be referred to as a dummy layer) in the channel region of the N-type device 300B may be selectively removed (e.g., using a selective etching process). The selective etching of the SiGe interposer may be performed by removing the trench provided by the dummy gate (gate stack 316). In some embodiments, the selective etching process may include a selective wet etching process. In some cases, the selective wet etching process includes tetramethylammonium hydroxide (TMAH). In some embodiments, the selective etching process may include using a gas chemical etching system from Tokyo Electron Limited, Japan. In some examples, the selective etching process may include using a standard clean 1 (SC-1) solution, an ammonium hydroxide (NH4OH) solution, hydrogen peroxide (H2O2) and water (H2O), hydrofluoric acid (HF), buffered hydrofluoric acid (HF) and / or fluorine (F2) based etching. In some examples, the fluorine (F2) based etching may include fluorine (F2) remote plasma etching.

[0083] It is noted that due to the selective removal of the SiGe interposer, a gap 1808 is formed between adjacent semiconductor channel layers (epitaxial layer 310) in the channel region of the N-type device 300B. For example, the gap 1808 is used to expose a first portion of the epitaxial layer 310 located between the opposing inner spacer layers 1202A, while a second portion of the epitaxial layer 310 remains covered by the inner spacer layer 1202A. As described in more detail below, a portion of the gate structure (e.g., including a metal gate stack having an interface layer, a high-K dielectric layer, and one or more metal electrode layers) will be formed within the gap 1808 between adjacent semiconductor channels (epitaxial layer 310) and in contact with the inner spacer layer 1202A.

[0084] In some cases, dopant diffusion (e.g., diffusion of Ge) from the SiGe interposer may form a SiGe / Si mixed layer at the interface between the SiGe interposer and the semiconductor channel layer (epitaxial layer 310) in the channel region of the N-type device 300B. As such, removal of the SiGe interposer may also at least partially etch the upper and / or lower surfaces (e.g., including at least a portion of the SiGe / Si mixed layer) of the epitaxial layer 310 (semiconductor channel layer) in the channel region of the N-type device 300B, such that the semiconductor channel layer (epitaxial layer 310) in the channel region is slightly thinner than the LDD region, thereby forming a dog-bone structure of the epitaxial layer 310 in the N-type device 300B. In contrast, the semiconductor channel layer (epitaxial layer 310) of the P-type device 300A (where the SiGe interposer is replaced with a disposable interposer as described below) may maintain a substantially rectangular shape. Of course, in some examples, the upper and / or lower surfaces of the epitaxial layer 310 (semiconductor channel layer) in the channel region of the P-type device 300A will be very slightly etched (at step area 206 and / or step area 222). However, even in this case, any consumption of the upper and / or lower surfaces of the epitaxial layer 310 of the P-type device 300A will be less than the consumption of the upper and / or lower surfaces of the epitaxial layer 310 of the N-type device 300B (e.g., due to the SiGe / Si mixed layer in the N-type device 300B). In addition, in some embodiments (and due to the use of a disposable interposer or SiGe interposer), the internal spacer layers 702A, 1202A of each of the P-type device 300A and the N-type device 300B can also have different shapes.

[0085] Next, the method 200 proceeds to step area 226 where a final gate structure is formed in the P-type and N-type device regions. Fig.18A / 18B and Fig.19AIn the example of step area 226, a final gate structure 1916 is formed for each of the P-type device 300A and the N-type device 300B. The gate structure 1916 may include a high-K value / metal gate stack, but other compositions are also possible. In some embodiments, the gate structure 1916 may form a gate associated with multiple channels provided by multiple exposed semiconductor channel layers (exposed epitaxial layer 310, previously having gaps 1708 or gaps 1808 therebetween) in the channel regions of the P-type device 300A and the N-type device 300B. In some embodiments, the gate structure 1916 includes a dielectric layer 1902 formed on the first exposed surface of the epitaxial layer 310 (semiconductor channel layer), the epitaxial layer 310 including the exposed first portion of the epitaxial layer 310 located in the gap 1708 between the opposite surfaces of the inner spacer layer 702A (and on the surface of the inner spacer layer 702A itself), and the exposed first portion of the epitaxial layer 310 located in the gap 1808 between the opposite surfaces of the inner spacer layer 1202A (and on the surface of the inner spacer layer 1202A itself). In some embodiments, the dielectric layer 1902 includes an interfacial layer (IL) and a high-K dielectric layer formed above the interfacial layer (IL). In different embodiments, the interfacial layer (IL) and the high-K dielectric layer together define the gate dielectric layer of the gate structure of the P-type device 300A and the N-type device 300B. In some embodiments, the gate dielectric layer has a total thickness of about 1-5 nm. As used and described herein, a high-K gate dielectric layer includes a dielectric material having a high dielectric constant, such as a dielectric constant greater than that of thermal silicon oxide (-3.9).

[0086] In some embodiments, the interfacial layer (IL) may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). In some examples, the high-K dielectric layer may include hafnium oxide (HfO2). Alternatively, the high-K dielectric layer may include other high-K dielectric materials such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO3 (BST), Al2O3, Si3N4, oxynitride (SiON), combinations thereof, or other suitable materials. In various embodiments, the gate dielectric may be formed by thermal oxidation, ALD, physical vapor deposition (PVD), pulsed laser deposition (PLD), CVD, and / or other suitable methods.

[0087] Please still refer to Fig.19A In the example of / 19B, a metal gate including a metal layer 1904 is formed above a gate dielectric layer (e.g., above an interface layer (IL) and a high-K dielectric layer). The metal layer 1904 may include a metal, a metal alloy, or a metal silicide. In addition, the formation of the gate dielectric layer / metal gate stack may include depositing different gate materials, one or more liner layers, and one or more chemical mechanical polishing (CMP) processes to remove excess gate material and thereby planarize the upper surface of the device 300 (including the P-type device 300A and the N-type device 300B).

[0088] In some embodiments, the metal layer 1904 may include a single layer or a multilayer structure, such as various combinations of metal layers having a selected work function to enhance device performance (work function metal layers), a liner, a wetting layer, an adhesion layer, a metal alloy, or a metal silicide. For example, the metal layer 1904 may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials, or combinations thereof. In different embodiments, the metal layer 1904 may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. Furthermore, the metal layer 1904 may be formed separately for each of the P-type device 300A and the N-type device 300B, and the metal layer 1904 may use different metal layers. In addition, the metal layer 1904 can provide an N-type or P-type work function for each of the P-type device 300A and the N-type device 300B, can be used as a gate electrode of a transistor (e.g., a gate all-around (GAA) transistor), and in at least some embodiments, the metal layer 1904 can include a polysilicon layer. For the device shown and described, the gate structure 1916 includes a portion sandwiched between each epitaxial layer 310, and each epitaxial layer 310 provides a semiconductor channel layer for the P-type device 300A and the N-type device 300B.

[0089] In general, the semiconductor device 300 including the P-type device 300A and the N-type device 300B may undergo further processing to form various features and regions known in the art. For example, further processing may form various contacts / vias / lines and multi-layer interconnect features (e.g., metal layers and interlayer dielectric layers) on the substrate 304 to connect different features to form functional circuits (which may include one or more gate devices (e.g., one or more gate all-around (GAA) transistors), such as the P-type device 300A and the N-type device 300B. In a further example, the multi-layer interconnect may include vertical interconnects (e.g., vias or contacts) and horizontal interconnects (e.g., metal lines). Different interconnect features may use different conductive materials, including copper, tungsten and / or silicide. In one example, a damascene and / or dual damascene process is used to form a multi-layer interconnect structure associated with copper. Furthermore, additional process steps may be performed before, during, and after the method 200, and some of the above process steps may be modified, replaced, or removed according to various embodiments of the method 200.

[0090] In relation to the description provided herein, a method and structure for replacing a SiGe interposer with a disposable interposer between semiconductor channel layers of a gate-all-around (GAA) transistor (e.g., particularly a P-type gate-all-around (GAA) transistor) is disclosed. In some embodiments, a method for sandwiching a disposable interposer between semiconductor channel layers of a gate-all-around (GAA) transistor includes: first removing a SiGe layer sandwiched between adjacent semiconductor channel layers (e.g., by a wet etching process), and re-depositing an oxide or other dielectric material. The layer conformally fills the cavity formed by removing the SiGe layer. Thereafter, a recessing process is performed to recess the deposited oxide or other dielectric material layer to form an internal spacer layer groove between the lateral ends of the adjacent semiconductor channel layers. Thereafter, the internal spacer layer material is deposited and etched back (e.g., using a dry etching process) to complete the formation of the internal spacer layer. After forming the internal spacer layer, an epitaxial source / drain feature is formed, and the remaining oxide or other dielectric material layer (e.g., disposable interposer) is removed to form a gap between adjacent semiconductor channel layers, and then a metal gate structure is formed in the gap.

[0091] By replacing the SiGe interposer with a disposable interposer (e.g., oxide or other dielectric material), the embodiments of the gate-all-around (GAA) transistor disclosed herein prevent the formation of a SiGe / Si mixed layer (e.g., by removing the Ge diffusion source), reduce interface traps (e.g., by avoiding the formation of Ge residues at the corners between the gate structure, the Si channel layer, and the internal spacer layer), provide higher mobility and drive current, reduce edge capacitance (e.g., by minimizing the formation of dog-bone structures in the Si channel layer), provide enhanced control of short channel effects (SCE), and provide enhanced compressive stress in the Si channel layer (e.g., for P-type gate-all-around (GAA) transistors), thereby improving device performance. For N-type gate-all-around (GAA) transistors, in some embodiments, the SiGe interposer can continue to be used to provide enhanced tensile stress in the Si channel layer. Other embodiments and advantages will be apparent to those skilled in the art after reading this disclosure.

[0092] Therefore, one of the embodiments of the present disclosure provides a method for forming a semiconductor device, the method comprising: providing a first fin in a first type device region and providing a second fin in a second type device region. In some embodiments, the first fin comprises a first epitaxial layer stack having a plurality of first semiconductor channel layers sandwiched by a plurality of first dummy layers; and the second fin comprises a second epitaxial layer stack having a plurality of second semiconductor channel layers sandwiched by a plurality of second dummy layers. In some examples, the method further comprises covering the second fin. In some embodiments, and when the second fin is covered, the method further comprises removing the first dummy layer from the first type device region to form a first gap between two adjacent ones of the first semiconductor channel layer. In some examples, when the second fin remains covered, the method further comprises forming a dielectric layer in a first channel region in the first gap between two adjacent ones of the first semiconductor channel layer. In some cases, when the second fin remains covered, the method further includes forming a plurality of first inner spacer layers in the first gap between two adjacent ones of the semiconductor channel layers and on opposite sides of the dielectric layer.

[0093] In some embodiments, before covering the second fin, a portion of the first epitaxial layer stack in the first source / drain regions of the first fin is removed to expose the side surfaces of the first semiconductor channel layer and the first dummy layer, and a portion of the second epitaxial layer stack in the second source / drain regions of the second fin is removed to expose the side surfaces of the second semiconductor channel layer and the second dummy layer. In some embodiments, the dielectric layer includes an oxide layer or a nitride layer. In some embodiments, the dielectric layer provides a disposable interposer. In some embodiments, forming a dielectric layer in the first channel region includes conformally depositing a dielectric layer in the first gap, the dielectric layer substantially filling the first gap; and recessing the dielectric layer to form a plurality of grooves between the ends of two adjacent ones of the first semiconductor channel layer; and a first internal spacer layer is formed in the grooves between the ends of two adjacent ones in the first semiconductor channel layer. In some embodiments, recessing the dielectric layer includes performing vapor dilute hydrofluoric acid etching. In some embodiments, the method further comprises, after forming the first internal spacer layer and while the second fin remains covered, epitaxially growing a plurality of first source / drain features in a plurality of first source / drain regions of the first fin. In some embodiments, the method further comprises, after epitaxially growing the first source / drain features, exposing the second fin and covering the first fin, wherein while covering the first fin, the method further comprises recessing the second dummy layer from the second type device region to form a plurality of grooves between a plurality of ends of two adjacent ones in the second semiconductor channel layer; and forming a plurality of second internal spacer layers in the grooves between the ends of two adjacent ones in the second semiconductor channel layer. In some embodiments, the method further comprises, after forming the second internal spacer layer and while the first fin remains covered, epitaxially growing a plurality of second source / drain features in a plurality of second source / drain regions of the second fin. In some embodiments, the method further includes exposing the first fin after epitaxially growing the second source / drain feature; removing the dielectric layer from the first channel region to form a second gap between two adjacent ones in the first semiconductor channel layer; and removing the recessed second dummy layer from a second channel region of the second type device region to form a third gap between two adjacent ones in the second semiconductor channel layer. In some embodiments, the method further includes forming a first metal gate structure in the second gap between two adjacent ones in the first semiconductor channel layer, adjacent to the first internal spacer layer; and forming a second metal gate structure in the third gap between two adjacent ones in the second semiconductor channel layer, adjacent to the second internal spacer layer.

[0094] In another embodiment, a method for forming a semiconductor device is provided, the method comprising: providing a first fin structure having a plurality of epitaxial layers consisting of a first composition sandwiched by a plurality of epitaxial layers consisting of a second composition, and providing a second fin structure having a plurality of epitaxial layers consisting of a first composition sandwiched by a plurality of epitaxial layers consisting of a second composition. In some embodiments, the method further comprises forming a first dummy gate above the first fin structure and forming a first spacer layer on the sidewall of the first dummy gate, and forming a second dummy gate above the second fin structure and forming a second spacer layer on the sidewall of the second dummy gate. In some examples, the method further comprises replacing the epitaxial layers consisting of the second composition located in the first fin structure with a plurality of disposable interlayers disposed below the first dummy gate and a plurality of first internal spacer layers located on two opposite ends of the disposable interlayer and below the first spacer layer. In some embodiments, the method further includes etching back two opposite lateral ends of the epitaxial layer formed of the second composition and located in the second fin structure to form a plurality of grooves disposed below the second spacer layer and located between adjacent epitaxial layers formed of the first composition. In some cases, the method further includes forming a plurality of second internal spacer layers in the second fin structure and in each of the grooves at two opposite lateral ends of the epitaxial layer formed of the second composition.

[0095] In some embodiments, the disposable interposer includes an oxide layer or a nitride layer. In some embodiments, the epitaxial layer composed of the second composition after etching back in the second fin provides multiple SiGe interposers. In some embodiments, the P-type device includes a first fin structure, and the N-type device includes a second fin structure. In some embodiments, the above method also includes removing a first dummy gate located above the first fin structure and a second dummy gate located above the second fin structure after forming the first internal spacer layer and the second internal spacer layer, wherein the disposable interposer is removed at the same time as the first dummy gate is removed to form a first gap between adjacent epitaxial layers composed of the first composition in the first fin structure; and after removing the second dummy gate, the epitaxial layer composed of the second composition after etching back is removed to form a second gap between adjacent epitaxial layers composed of the first composition in the second fin structure. In some embodiments, the above method also includes forming a first metal gate structure in the first gap and adjacent to the first internal spacer layer; and forming a second metal gate structure in the second gap and adjacent to the second internal spacer layer.

[0096] In yet another embodiment, a semiconductor device is provided, comprising: a first fin extending from a substrate in a P-type device region and a second fin extending from a substrate in an N-type device region. In some embodiments, the first fin comprises a plurality of first semiconductor channel layers, and the second fin comprises a plurality of second semiconductor channel layers. In some examples, the semiconductor device further comprises a plurality of first internal spacer layers disposed between adjacent semiconductor channel layers in the first semiconductor channel layers and located on either side of a first channel region. In some cases, the semiconductor device further comprises a plurality of second internal spacer layers disposed between adjacent semiconductor channel layers in the second semiconductor channel layers and located on either side of a second channel region. In some embodiments, each of the first semiconductor channel layers has a substantially rectangular shape, and each of the second semiconductor channel layers has a dog-bone structure.

[0097] In some embodiments, the first internal isolation layer and the second internal isolation layer have different shapes. In some embodiments, the semiconductor device further comprises a first portion of a first metal gate structure disposed between two adjacent ones of the first semiconductor channel layer, and a second portion of a second metal gate structure disposed between two adjacent ones of the second semiconductor channel layer, wherein the first internal isolation layer is disposed on either side of the first portion of the first metal gate structure, and wherein the second internal isolation layer is disposed on either side of the second portion of the second metal gate structure.

[0098] The above briefly describes the characteristic components of several embodiments of the present disclosure, so that those skilled in the art can more easily understand the form of the present disclosure. Any person skilled in the art should understand that the present disclosure can be easily used as a basis for the change or design of other processes or structures to achieve the same purpose and / or obtain the same advantages as the embodiments described herein. Any person skilled in the art can also understand that structures equivalent to the above do not depart from the concept and scope of protection of the present disclosure, and can be changed, replaced and modified without departing from the concept and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: Providing a first fin in a first type device region and providing a second fin in a second type device region, the first fin comprising a first epitaxial layer stack having a plurality of first semiconductor channel layers sandwiched by a plurality of first dummy layers, and the second fin comprising a second epitaxial layer stack having a plurality of second semiconductor channel layers sandwiched by a plurality of second dummy layers; Covering the second fin, and when the second fin is covered, the method further includes: Removing the plurality of first dummy layers from the first type device region to form a first gap between two adjacent ones of the plurality of first semiconductor channel layers; forming a dielectric layer in a first channel region in the first gap between two adjacent ones of the plurality of first semiconductor channel layers; and A plurality of first inner spacer layers are formed in the first gap between two adjacent ones of the plurality of first semiconductor channel layers and on two opposite sides of the dielectric layer.

2. The method for forming a semiconductor device according to claim 1, further comprising: Before covering the second fin, a portion of the first epitaxial layer stack within the multiple first source / drain regions of the first fin is removed to expose the side surfaces of the multiple first semiconductor channel layers and the multiple first dummy layers, and a portion of the second epitaxial layer stack within the multiple second source / drain regions of the second fin is removed to expose the side surfaces of the multiple second semiconductor channel layers and the multiple second dummy layers. 3 . The method for forming a semiconductor device as claimed in claim 1 , wherein the dielectric layer provides a disposable interposer.

4. The method for forming a semiconductor device as claimed in claim 1, wherein forming the dielectric layer in the first channel region comprises: Conformally depositing the dielectric layer in the first gap, wherein the dielectric layer substantially fills the first gap; as well as Recessing the dielectric layer to form a plurality of grooves between ends of two adjacent ones of the plurality of first semiconductor channel layers; The plurality of first internal spacer layers are formed in the plurality of grooves between the plurality of end portions of two adjacent ones of the plurality of first semiconductor channel layers.

5. A method for forming a semiconductor device, comprising: Providing a first fin structure, comprising a plurality of epitaxial layers consisting of a first composition sandwiched between a plurality of epitaxial layers consisting of a second composition, and providing a second fin structure, comprising a plurality of epitaxial layers consisting of the first composition sandwiched between a plurality of epitaxial layers consisting of the second composition; Forming a first dummy gate above the first fin structure and forming a first spacer layer on the sidewall of the first dummy gate, and forming a second dummy gate above the second fin structure and forming a second spacer layer on the sidewall of the second dummy gate; Replacing the plurality of epitaxial layers composed of the second composition in the first fin structure with a plurality of disposable interlayers disposed under the first dummy gate and a plurality of first internal spacer layers located on two opposite ends of the plurality of disposable interlayers and under the first spacer layer; Etching back two opposite lateral ends of the plurality of epitaxial layers formed of the second composition and located in the second fin structure to form a plurality of grooves disposed below the second spacer layer and located between the plurality of adjacent epitaxial layers formed of the first composition; and A plurality of second internal spacer layers are formed in the second fin structure and in each of the plurality of recesses at two opposite lateral ends of the plurality of epitaxial layers composed of the second composition. 6 . The method for forming a semiconductor device as claimed in claim 5 , wherein the plurality of disposable interposers comprise an oxide layer or a nitride layer. 7 . The method for forming a semiconductor device as claimed in claim 5 , wherein a P-type device comprises the first fin structure, and an N-type device comprises the second fin structure.

8. A semiconductor device comprising: A first fin extending from a substrate in a P-type device region and a second fin extending from a substrate in an N-type device region, wherein the first fin includes a plurality of first semiconductor channel layers and the second fin includes a plurality of second semiconductor channel layers; A plurality of first internal spacer layers are disposed between two adjacent ones of the plurality of first semiconductor channel layers and are located on either side of a first channel region; as well as A plurality of second inner spacer layers are disposed between two adjacent ones of the plurality of second semiconductor channel layers and are located on either side of a second channel region; The first semiconductor channel layers each have a substantially rectangular shape, and the second semiconductor channel layers each have a dog-bone structure. 9 . The semiconductor device as claimed in claim 8 , wherein the plurality of first internal isolation layers and the plurality of second internal isolation layers have different shapes.

10. The semiconductor device according to claim 8, further comprising: A first portion of a first metal gate structure disposed between two adjacent layers of the plurality of first semiconductor channel layers; as well as A second portion of a second metal gate structure disposed between two adjacent layers of the plurality of second semiconductor channel layers; The plurality of first internal spacer layers are disposed on either side of the first portion of the first metal gate structure, and the plurality of second internal spacer layers are disposed on either side of the second portion of the second metal gate structure.

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