Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof, the semiconductor device comprises a substrate, a channel layer, a barrier layer and a source drain function part, and the channel layer is located at one side of the substrate; the barrier layer is located on the side, away from the substrate, of the channel layer; the source-drain function part is located on the side, away from the substrate, of the barrier layer and makes contact with the barrier layer, the source-drain function part comprises a source part and a drain part which are arranged in a spaced mode, and the source-drain function part comprises a titanium metal layer, an aluminum metal layer and a titanium nitride layer which are arranged in a stacked mode in the direction away from the barrier layer. The yield and the reliability of the semiconductor device provided by the invention are remarkably improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Ohmic contact mainly forms the source and drain of the High Electron Mobility Transistor (HEMT), and its performance will directly affect the output source-drain current and knee voltage of the transistor. Currently, most n-GaN-based ohmic contacts contain 4 layers of metal, and the most common case is gold ohmic contact. The yield of gold ohmic contact is poor, which seriously affects the yield and performance of the transistor. Summary of the invention

[0003] The purpose of this application is to at least solve the problem of poor yield of semiconductor devices. This purpose is achieved through the following technical solutions:

[0004] The first aspect of the present application provides a semiconductor device, comprising:

[0005] substrate;

[0006] A channel layer, located on one side of the substrate;

[0007] A barrier layer, located on a side of the channel layer facing away from the substrate;

[0008] The source-drain functional part is located on the side of the barrier layer away from the substrate and contacts the barrier layer. The source-drain functional part includes a source part and a drain part arranged at intervals. The source-drain functional part includes a titanium metal layer, an aluminum metal layer and a titanium nitride layer stacked in a direction away from the barrier layer.

[0009] In the semiconductor device provided by the present application, the source-drain functional part includes a titanium metal layer, an aluminum metal layer and a titanium nitride layer stacked in a direction away from the barrier layer. The titanium nitride layer has very good conductivity and low resistance, and therefore has strong metallic properties. Titanium nitride is also a controllable material, and its work function can be controlled by controlling the atomic number ratio of nitrogen atoms to titanium atoms in titanium nitride, so that it can better match other metals in the source-drain functional part. The titanium nitride layer is relatively stable in nature and can be used as a protective layer for the outermost layer of the source-drain functional part. The titanium nitride layer has a good surface morphology, and can also protect the titanium metal layer and the aluminum metal layer from reacting during annealing, preventing the overflow of titanium metal and aluminum metal from causing contact between the source and the drain, thereby causing leakage or even short circuit, thereby helping to improve the yield and reliability of semiconductor devices. The source-drain functional part of the semiconductor device provided by the present application does not contain gold (Au), so that a gold-free ohmic contact can be formed with the barrier layer. Compared with the ohmic contact containing gold, the material cost of the source-drain functional part of the semiconductor device provided by the present application is low, thereby reducing the manufacturing cost of the semiconductor device and avoiding the problem of contact degradation caused by the easy diffusion of gold at high temperatures. The source-drain functional part in the present application has strong contact stability, is resistant to high temperatures, and is not easy to diffuse at high temperatures, thereby improving the reliability of the semiconductor device.

[0010] The second aspect of the present application also provides a method for preparing a semiconductor device, comprising:

[0011] providing a substrate;

[0012] forming a channel layer on one side of the substrate;

[0013] forming a barrier layer on a side of the channel layer facing away from the substrate;

[0014] A titanium metal material layer, an aluminum metal material layer and a titanium nitride material layer are sequentially formed on the surface of the barrier layer on the side away from the channel layer, and patterning and annealing are performed to form a source-drain functional portion, wherein the drain functional portion includes a source portion and a drain portion that are spaced apart, and the source-drain functional portion includes a titanium metal layer, an aluminum metal layer and a titanium nitride layer that are stacked in a direction away from the barrier layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Moreover, the same reference numerals are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0016] Figure 1 It is a structural schematic diagram of the first semiconductor device provided by the present application;

[0017] Figure 2 is a schematic structural diagram of a second semiconductor device provided by the present application;

[0018] Figure 3 is a schematic structural diagram of a third semiconductor device provided by the present application;

[0019] Figure 4 is a schematic structural diagram of a fourth semiconductor device provided by the present application;

[0020] Figure 5 is a schematic structural diagram of a fifth semiconductor device provided by the present application;

[0021] Figure 6 It is a flow chart of a method for preparing a semiconductor device provided by the present application;

[0022] Figures 7 to 13 It is a schematic diagram of the film layer structure in a method for preparing a semiconductor device provided in the present application.

[0023] The reference numerals are as follows:

[0024] 1. Semiconductor device; 11. Substrate; 12. Channel layer; 13. Barrier layer; 131. Accommodating hole; 132. Accommodating groove; 14. Source-drain functional part; 141. Source part; 142. Drain part; 143. Titanium metal layer; 144. Aluminum metal layer; 145. Titanium nitride layer; 146. Titanium nitride connecting layer; 147. Titanium-aluminum alloy layer; 15. Cap layer; 16. Titanium metal material layer; 17. Aluminum metal material layer; 18. Titanium nitride material layer; 19. Mask layer; 191. Blocking area; 192. Hole area; 20. Isolation mask layer; 21. Isolation structure. DETAILED DESCRIPTION

[0025] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0026] It should be understood that the terms used herein are only for the purpose of describing specific example embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive, and therefore specify the existence of stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not interpreted as necessarily requiring them to be performed in the specific order described or illustrated, unless the execution order is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0027] Although the terms first, second, third, etc. can be used in the text to describe multiple elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can only be used to distinguish an element, component, region, layer or section from another region, layer or section. Unless the context clearly indicates, terms such as "first", "second" and other numerical terms do not imply order or sequence when used in the text. Therefore, the first element, component, region, layer or section discussed below can be referred to as the second element, component, region, layer or section without departing from the teaching of the example embodiments.

[0028] For ease of description, spatial relative terms may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figure, such as "inside", "outside", "inner side", "outer side", "below", "below", "above", "above", etc. Such spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure is turned over, then the elements described as "below other elements or features" or "below other elements or features" will subsequently be oriented as "above other elements or features" or "above other elements or features". Therefore, the example term "below..." can include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or in other directions) and the spatial relative descriptors used in the text are interpreted accordingly.

[0029] Research has found that ohmic contacts mainly form the source and drain of high electron mobility transistors (HEMTs), and their performance will directly affect the output source-drain current and knee voltage of the transistor. At present, most n-GaN-based ohmic contacts contain 4 layers of metal. The most common case is a gold ohmic contact, including four layers of metal, Ti, Al, Ni, and Au, which are stacked in sequence on one side of the barrier layer. After the four layers of metal are deposited, a rapid thermal annealing (RTA) process is required to form ohmic characteristics. In the process corresponding to the gold ohmic contact, the annealing temperature is high, and the negative impact of high-temperature annealing is large. On the one hand, it will cause mechanical damage inside the device, thereby affecting the yield and reliability of the device; on the other hand, it will cause damage to the surface layer of the film layer in the device, thereby affecting the preparation yield of subsequent film layers. Therefore, high-temperature annealing requires precise control of temperature, time, and annealing environment to avoid introducing new defects or undesirable chemical components, which greatly increases the difficulty of the process.

[0030] Specifically, at high temperatures, due to the different thermal expansion coefficients of GaN and metal materials, thermal stress is easily generated during high temperature annealing, resulting in mechanical damage inside the device, thereby affecting the reliability of the device. At the same time, high temperatures can cause GaN surface degradation, such as increased surface roughness or changes in surface chemical composition, thereby affecting the subsequent process steps, which may include the step of depositing a passivation layer.

[0031] Therefore, the present application provides a semiconductor device and a method for manufacturing the same, so as to improve the yield and performance of the semiconductor device and reduce the difficulty and cost of manufacturing.

[0032] like Figure 1 As shown, according to an embodiment of the present application, a semiconductor device 1 is proposed, which includes a substrate 11, a channel layer 12, a barrier layer 13 and a source-drain functional portion 14. The channel layer 12 is located on one side of the substrate 11. The barrier layer 13 is located on the side of the channel layer 12 away from the substrate 11. The source-drain functional portion 14 is located on the side of the barrier layer 13 away from the substrate 11 and is in contact with the barrier layer 13, and the source-drain functional portion 14 includes a source portion 141 and a drain portion 142 arranged at intervals, and the source-drain functional portion 14 includes a titanium metal layer 143, an aluminum metal layer 144 and a titanium nitride layer 145 stacked in a direction away from the barrier layer 13.

[0033] In the semiconductor device 1 provided by the present application, the source-drain functional part 14 includes a titanium metal layer 143, an aluminum metal layer 144 and a titanium nitride layer 145 stacked in a direction away from the barrier layer 13. The titanium nitride layer 145 has very good conductivity and low resistance, and therefore has strong metallic properties. Titanium nitride is also a controllable material, and its work function can be controlled by controlling the atomic number ratio of nitrogen atoms to titanium atoms in titanium nitride, so that it can better match other metals in the source-drain functional part 14. The titanium nitride layer 145 is relatively stable in nature and can be used as a protective layer for the outermost layer of the source-drain functional part 14. The titanium nitride layer 145 has a good surface morphology, and can also protect the titanium metal layer 143 and the aluminum metal layer 144 from reacting during annealing, preventing the overflow of titanium metal and aluminum metal from causing contact between the source part 141 and the drain part 142, thereby causing leakage or even short circuit, thereby helping to improve the yield and reliability of the semiconductor device 1. The source-drain functional portion 14 in the semiconductor device 1 provided in the present application does not contain gold (Au), so that a gold-free ohmic contact can be formed with the barrier layer 13. Compared with the ohmic contact containing gold, the material cost of the source-drain functional portion 14 in the semiconductor device 1 provided in the present application is low, thereby reducing the manufacturing cost of the semiconductor device 1 and avoiding the problem of contact degradation caused by the easy diffusion of gold at high temperatures. The source-drain functional portion 14 in the present application has strong contact stability, is resistant to high temperatures, and is not easy to diffuse at high temperatures, thereby improving the reliability of the semiconductor device 1.

[0034] In the above embodiment, the resistance of the gold-free ohmic contact can be as low as 0.4Ω, which helps to further improve the performance of the semiconductor device 1.

[0035] As an integrated circuit manufacturing process, the CMOS process has the characteristics of high integration, low power consumption and high reliability, and is widely used in the manufacturing process of various electronic products. The source-drain functional part 14 and the barrier layer 13 in the semiconductor device 1 provided in the present application can form a gold-free ohmic contact, and the material of the source-drain functional part 14 can be compatible with the existing CMOS manufacturing process. This compatibility allows GaN devices to be integrated into the CMOS process to form mixed signal and high-power integrated circuits, thereby further improving the overall performance and adding more functions, promoting the generation of new devices and expanding their application scenarios. For example, the new devices can be used in high-frequency communications, radar systems, power electronic devices and other fields. Since the production line of the CMOS process is very mature and large-scale, the use of GaN devices without gold ohmic contact can use the existing CMOS process to mass-produce silicon-based gallium nitride devices, while reducing production costs, it is also conducive to the large-scale production and application of gallium nitride devices.

[0036] In the semiconductor device 1 provided in the present application, the metal material used in the source-drain functional part 14 can adopt an anhydrous process throughout the entire preparation process, and can be well combined with the CMOS process.

[0037] In the above implementation mode, if Figure 2 As shown, the source-drain functional portion 14 further includes a titanium nitride connection layer 146 located between the barrier layer 13 and the titanium metal layer 143 and a titanium-aluminum alloy layer 147 located between the titanium metal layer 143 and the aluminum metal layer 144 .

[0038] The material of the barrier layer 13 in the semiconductor device 1 is AlGaN. In the process of preparing the source-drain functional part 14, annealing treatment is required. The titanium metal layer 143 reacts at the interface where the barrier layer 13 contacts, thereby forming a titanium nitride connection layer 146 between the titanium metal layer 143 and the barrier layer 13. The titanium nitride connection layer 146 is used to connect the titanium metal layer 143 and the barrier layer 13 to eliminate the interface barrier. After annealing, a titanium-aluminum alloy layer 147 is formed between the titanium metal layer 143 and the aluminum metal layer 144.

[0039] In a feasible implementation manner, the thickness of the titanium metal layer 143 is in the range of 5 nm to 25 nm.

[0040] Specifically, the thickness of the titanium metal layer 143 may be 5 nm, 6 nm, 9 nm, 10 nm, 13 nm, 15 nm, 18 nm, 25 nm, etc. The titanium metal layer 143 within the above thickness range can form a good ohmic contact between the source / drain functional part 14 and the barrier layer 13 .

[0041] In one feasible implementation, the thickness of the aluminum metal layer 144 is in the range of 120 nm to 180 nm.

[0042] Specifically, the thickness of the aluminum metal layer 144 may be 120 nm, 125 nm, 130 nm, 143 nm, 158 nm, 166 nm, 179 nm, 180 nm, etc. The aluminum metal layer 144 within the above thickness range can form a good ohmic contact between the source / drain functional part 14 and the barrier layer 13 .

[0043] In one feasible implementation, the thickness of the titanium nitride layer 145 is in the range of 80 nm to 120 nm.

[0044] Specifically, the thickness of the titanium nitride layer 145 may be 80 nm, 88 nm, 90 nm, 93 nm, 101 nm, 115 nm, 117 nm, 120 nm, etc. The titanium nitride layer 145 within the above thickness range can form a good ohmic contact between the source / drain functional part 14 and the barrier layer 13 .

[0045] In one feasible implementation, the atomic number ratio of nitrogen atoms to titanium atoms in the titanium nitride layer 145 is in a range of 0.8-1.2.

[0046] In the above embodiment, the atomic number ratio of nitrogen atoms to titanium atoms in the titanium nitride layer 145 can be 1:1, and can fluctuate within the above range according to the accuracy of the actual preparation process. When the atomic number ratio of nitrogen atoms to titanium atoms in the titanium nitride layer 145 is within the above range, its work function can be exactly matched with other metals in the source-drain functional portion 14.

[0047] In a possible implementation, Figure 3 As shown, the thickness of the barrier layer 13 is greater than the preset thickness value, and the barrier layer 13 includes an accommodation hole 131, which penetrates the barrier layer 13 and exposes the channel layer 12. The source portion 141 is located in the accommodation hole 131, the source portion 141 corresponds to the accommodation hole 131 one by one, the source portion 141 contacts the sidewall of the accommodation hole 131, and the source portion 141 contacts the channel layer 12 exposed through the accommodation hole 131; the drain portion 142 is located in the accommodation hole 131, the drain portion 142 corresponds to the accommodation hole 131 one by one, the drain portion 142 contacts the sidewall of the accommodation hole 131, and the source portion 141 contacts the channel layer 12 exposed through the accommodation hole 131.

[0048] In the above implementation, the preset thickness value may be 6 nm.

[0049] In the above embodiment, a receiving hole 131 is formed in the barrier layer 13, and the receiving hole 131 penetrates the barrier layer 13 along the thickness direction of the barrier layer 13. The receiving hole 131 is used to accommodate the source part 141 and the drain part 142. The circumference of the source part 141 contacts the side wall of one receiving hole 131, that is, the circumference of the source part 141 contacts the barrier layer 13, and the bottom of the source part 141 contacts the channel layer 12. The circumference of the drain part 142 contacts the side wall of one receiving hole 131, that is, the circumference of the drain part 142 contacts the barrier layer 13, and the bottom of the drain part 142 contacts the channel layer 12.

[0050] The side walls of the source-drain functional portion 14 are in contact with the barrier layer 13 and annealed to form an ohmic contact. The bottom wall of the source-drain functional portion 14 is in contact with the barrier layer 13 and annealed to form an ohmic contact. It is easier to form an ohmic contact between the side walls of the source-drain functional portion 14 and the barrier layer 13 than between the bottom wall and the barrier layer 13. Therefore, in the above embodiment, by forming a receiving hole 131 in the barrier layer 13, the contact area between the barrier layer 13 and the side walls of the source-drain functional portion 14 is increased, which helps to enhance the formation of ohmic contact and improve the stability of the semiconductor device 1.

[0051] In another possible implementation, if Figure 4As shown, the thickness of the barrier layer 13 is greater than the preset thickness value, and the barrier layer 13 includes a receiving groove 132, and the receiving groove 132 includes a side wall and a bottom wall. The source-drain functional part 14 includes a source part 141 and a drain part 142, the source part 141 is located in the receiving groove 132, the source part 141 corresponds to the receiving groove 132 one by one, and the source part 141 contacts the side wall and the bottom wall of the receiving groove 132; the drain part 142 is located in the receiving hole 131, and the drain part 142 corresponds to the receiving groove 132 one by one, and the drain part 142 contacts the side wall and the bottom wall of the receiving groove 132.

[0052] In the above implementation, the preset thickness value may be 6 nm.

[0053] In the above embodiment, a receiving groove 132 is formed in the barrier layer 13. The receiving groove 132 is formed by a side surface of the barrier layer 13 facing away from the substrate 11 and concave toward the substrate 11. The receiving groove 132 includes a side wall and a bottom wall. The receiving groove 132 is used to receive the source part 141 and the drain part 142. The circumference of the source part 141 contacts the side wall of one receiving groove 132, and the side of the source part 141 close to the substrate 11 contacts the bottom wall of the receiving groove 132, that is, the circumference and bottom wall of the source part 141 are both in contact with the barrier layer 13. The circumference of the drain part 142 contacts the side wall of one receiving groove 132, and the side of the drain part 142 close to the substrate 11 contacts the bottom wall of the receiving groove 132, that is, the circumference and bottom wall of the drain part 142 are both in contact with the barrier layer 13.

[0054] In the above embodiment, the side wall of the source-drain functional portion 14 contacts the barrier layer 13 and is annealed to form an ohmic contact, and the bottom wall of the source-drain functional portion 14 contacts the barrier layer 13 and is annealed to form an ohmic contact. Therefore, in the above embodiment, by forming a receiving groove 132 in the barrier layer 13, the total contact area between the barrier layer 13 and the source-drain functional portion 14 is increased, which helps to enhance the formation of ohmic contact and improve the stability of the semiconductor device 1.

[0055] Specifically, the thickness of the bottom wall of the receiving groove 132 is less than or equal to 2 nm, that is, the thickness of a portion of the barrier layer 13 located on a side of the receiving groove 132 close to the substrate 11 is less than or equal to 2 nm.

[0056] In a possible implementation, Figure 1 As shown, when the thickness of the barrier layer 13 is less than or equal to the preset thickness value, that is, when the barrier layer 13 is relatively thin, the barrier layer 13 does not need to be grooved or drilled. After the barrier layer 13 is formed, the source and drain functional parts 14 can be directly formed on the surface of the side of the barrier layer 13 away from the substrate 11.

[0057] In a possible implementation, Figure 4As shown, a cap layer 15 is further included. The cap layer 15 is located on a side of the barrier layer 13 away from the channel layer 12 , and the cap layer 15 is disposed around at least a portion of the circumference of the source / drain functional portion 14 .

[0058] In the above embodiment, by providing the cap layer 15 on the side of the barrier layer 13 away from the channel layer 12, it helps to reduce the current collapse effect, increase the barrier height, improve the electrostatic balance, increase the breakdown voltage, modulate the surface electric field, etc., thereby helping to improve the overall performance of the semiconductor device 1.

[0059] In a feasible implementation, the material of the cap layer 15 includes one of gallium nitride and silicon nitride.

[0060] In the above embodiment, when the cap layer 15 is made of gallium nitride, the material of the cap layer 15 is the same as that of the channel layer 12, which can be easily prepared. Silicon nitride is grown in situ, thereby simplifying the process flow and saving production costs. The silicon nitride layer has the characteristics of high dielectric constant, low loss, high thermal stability, excellent corrosion resistance and mechanical strength, and can be used as an effective protective layer, thereby protecting the semiconductor device 1 to extend the service life of the semiconductor device 1.

[0061] like Figure 5 As shown, when the thickness of the barrier layer 13 is less than or equal to the preset thickness value, the cap layer 15 is preferably provided. Figure 1 When the thickness of the barrier layer 13 is greater than the preset thickness value, the cap layer 15 may not be set, such as Figure 5 Alternatively, when the thickness of the barrier layer 13 is greater than the preset thickness value, a cap layer 15 may also be provided, such as Figures 2 to 4 shown.

[0062] In a feasible implementation manner, the material of the substrate 11 includes one of silicon carbide, silicon, and sapphire.

[0063] In a possible implementation, Figures 1 to 5 As shown, the semiconductor device 1 includes transistors and other devices, and an isolation structure 21 for device isolation may be formed around the transistor. The isolation structure 21 may include a shallow trench isolation structure or an ion implantation isolation structure, and the like.

[0064] The present application also provides a method for preparing a semiconductor device 1, such as Figure 6 As shown, including:

[0065] S200, such as Figure 7 As shown, a substrate 11 is provided.

[0066] Specifically, the substrate 11 may be any one of a silicon carbide substrate 11 , a silicon substrate 11 , and a sapphire substrate 11 .

[0067] S400, such as Figure 7 As shown, a channel layer 12 is formed on one side of a substrate 11 .

[0068] Specifically, the material of the channel layer 12 may be gallium nitride.

[0069] Specifically, a buffer layer may be further formed before forming the channel layer 12 on the substrate 11 .

[0070] S600, such as Figure 7 As shown, a barrier layer 13 is formed on a side of the channel layer 12 facing away from the substrate 11 .

[0071] Specifically, the material of the barrier layer 13 includes AlGaN, and the thickness of the barrier layer 13 is in the range of 20 nm to 23 nm.

[0072] S800, such as Figures 8 to 11 As shown, a titanium metal material layer 16, an aluminum metal material layer 17 and a titanium nitride material layer 18 are formed in sequence on the surface of the barrier layer 13 on the side away from the channel layer 12, and patterning and annealing are performed to form a source-drain functional portion 14, wherein the drain functional portion includes a source portion 141 and a drain portion 142 that are spaced apart, and the source-drain functional portion 14 includes a titanium metal layer 143, an aluminum metal layer 144 and a titanium nitride layer 145 that are stacked in a direction away from the barrier layer 13.

[0073] Specifically, the thickness of the titanium metal layer 143 is in the range of 5 nm to 25 nm; the thickness of the aluminum metal layer 144 is in the range of 120 nm to 180 nm; and the thickness of the titanium nitride layer 145 is in the range of 80 nm to 120 nm.

[0074] In the above-mentioned preparation method provided in the present application, a titanium metal material layer 16, an aluminum metal material layer 17 and a titanium nitride material layer 18 are sequentially formed on the surface of the barrier layer 13 on one side away from the channel layer 12, and patterning and annealing are performed to form a source-drain functional portion 14. The titanium nitride material layer 18 is relatively stable in nature. During the annealing process, the titanium metal material layer 16 and the aluminum metal material layer 17 can be protected to prevent the titanium metal material layer 16 and the aluminum metal material layer 17 from overflowing and causing contact between the source portion 141 and the drain portion 142, thereby causing leakage or even a short circuit, thereby helping to improve the yield and reliability of the semiconductor device 1. Since no gold material is used when forming the source-drain functional portion 14, a gold-free ohmic contact can be formed with the barrier layer 13. Compared with the gold-containing ohmic contact, the preparation method provided by the present application has a low material cost, thereby reducing the manufacturing cost of the semiconductor device 1 and avoiding the problem of contact degradation caused by the easy diffusion of gold at high temperatures. That is, the preparation method of the semiconductor device 1 provided by the present application can manufacture a semiconductor device 1 with greater stability, higher temperature resistance, and greater reliability.

[0075] In a feasible implementation manner, step S800 includes:

[0076] S810, such as Figure 7 and Figure 8 As shown, a mask layer 19 is formed on the surface of the barrier layer 13 facing away from the channel layer 12 . The mask layer 19 includes a blocking region 191 and a hole region 192 . The hole region 192 is used to form a source portion 141 and a drain portion 142 .

[0077] Specifically, the material of the mask layer 19 may include photoresist. The specific steps of forming the mask layer 19 include: coating, exposure, and development. The coating speed may be 6000 r / min, and the photoresist thickness may be 1.1 μm. In the mask layer 19, the hole area 192 penetrates the mask layer 19 along the thickness direction of the mask layer 19.

[0078] S820, such as Fig. 9 As shown, a titanium metal material layer 16 disposed over the entire surface is formed on the side of the mask layer 19 facing away from the substrate 11 and the side of the barrier layer 13 facing away from the substrate 11 .

[0079] Specifically, the titanium metal material layer 16 may be formed by a magnetron sputtering process, and the gas atmosphere may be argon.

[0080] S830, such as Fig. 9 As shown, an aluminum metal material layer 17 is formed on the side of the titanium metal material layer 16 facing away from the substrate 11 and is disposed over the entire surface.

[0081] Specifically, the aluminum metal material layer 17 may be formed by a magnetron sputtering process, and the gas atmosphere may be argon.

[0082] S840, such as Fig. 9 As shown, a titanium nitride material layer 18 is formed on the side of the aluminum metal material layer 17 facing away from the substrate 11 and is disposed over the entire surface.

[0083] Specifically, titanium is sputtered in a mixed gas with a ratio of argon to nitrogen of 40:7 to form a titanium nitride metal layer 143. The atomic number ratio of nitrogen atoms to titanium atoms in the formed titanium nitride metal layer 143 is in the range of 0.8-1.2. Titanium nitride is a controllable material, and its work function can be controlled by controlling the atomic number ratio of nitrogen atoms to titanium atoms in titanium nitride, so that it can better match the titanium metal material layer 16 and the aluminum metal material layer 17.

[0084] S850, such as Fig.10 As shown, the mask layer 19 is removed and the portions of the titanium metal material layer 16 , the aluminum metal material layer 17 and the titanium nitride material layer 18 located on the side of the mask layer 19 away from the substrate 11 are removed.

[0085] Specifically, the mask layer 19 and the titanium metal material layer 16, the aluminum metal material layer 17 and the titanium nitride material layer 18 located on the side of the mask layer 19 facing away from the substrate 11 can be stripped off, leaving only the portions of the titanium metal material layer 16, the aluminum metal material layer 17 and the titanium nitride material layer 18 located in the hole area 192, thereby achieving patterning of the titanium metal material layer 16, the aluminum metal material layer 17 and the titanium nitride material layer 18.

[0086] S860, performing annealing treatment, the temperature range of the annealing treatment is 600°C-680°C.

[0087] Specifically, the source-drain functional part 14 is formed by stacking a titanium metal material layer 16, an aluminum metal material layer 17 and a titanium nitride material layer 18, and no gold material is used. Therefore, in the process of annealing to form an alloy to achieve ohmic contact, the annealing temperature is lower than that of the source-drain functional part 14 made of gold material, thereby avoiding damage to the semiconductor device 1 caused by high temperature, for example: mechanical damage caused by different thermal expansion coefficients between different material film layers under the influence of high temperature, or high temperature may cause the surface of gallium nitride to degrade and affect its own surface roughness or surface chemical composition changes, etc. After the annealing temperature is reduced, the damage to the semiconductor device 1 can be reduced while ensuring the ohmic contact yield, thereby improving the comprehensive performance and yield of the semiconductor device 1, and at the same time helping to reduce the difficulty and cost of preparation.

[0088] In the above embodiment, the titanium metal material layer 16 and the aluminum metal material layer 17 can be formed by magnetron sputtering or electron beam evaporation. The above preparation process is mature and highly controllable, and can improve the preparation yield of the titanium metal material layer 16 and the aluminum metal material layer 17.

[0089] In a feasible implementation manner, between steps S810 and S820, the following is further included:

[0090] like Fig.11 As shown, the portion of the barrier layer 13 exposed by the hole region 192 is etched to form an accommodating hole 131 or an accommodating groove 132 .

[0091] Specifically, a dry etching process may be used to etch the portion of the barrier layer 13 exposed through the hole region 192 .

[0092] In the above embodiment, after the barrier layer 13 is etched by dry etching, the morphology of the surface formed by etching is conducive to the formation of ohmic contact, thereby further improving the stability of the ohmic contact.

[0093] In a feasible implementation, the semiconductor device 1 may further include an isolation structure 21 for isolating adjacent device regions. The device region may be used to form a transistor or a capacitor, etc., wherein the transistor prepared in the above implementation of the present application may be located in one of the device regions. Between steps S850 and S860, the following may be included: Fig.12 and Fig.13 As shown, an isolation structure 21 is formed. The isolation structure 21 is arranged around the source-drain functional portion 14 . The isolation structure 21 penetrates the barrier layer 13 along the thickness direction of the substrate 11 and penetrates at least a portion of the channel layer 12 .

[0094] In the above-mentioned implementation, the isolation structure 21 may be formed by using shallow trench isolation technology or ion implantation to perform device isolation.

[0095] The specific steps of forming the isolation structure 21 include:

[0096] like Fig.12 As shown, an isolation mask layer 20 is formed on the side of the titanium nitride layer 145 and the barrier layer 13 facing away from the substrate 11. The isolation mask layer 20 forms a mask portion covering the device region where the transistor is located and exposes the region around the device region for forming the isolation structure 21. Fig.13 As shown, the isolation structure 21 is formed in the area not covered by the mask portion, that is, the area for forming the isolation structure 21, by shallow trench isolation technology or ion implantation. Then, the isolation mask layer 20 is removed.

[0097] Specifically, the material of the isolation mask layer 20 may include photoresist. The specific steps of forming the isolation mask layer 20 include: coating, exposure, and development. The coating speed may be 1800 / min, and the thickness of the photoresist may be 3 μm.

[0098] In a feasible embodiment, a cap layer 15 is further formed between steps S600 and S800, and the material of the cap layer 15 includes gallium nitride. When the barrier layer 13 includes a receiving groove 132 or a receiving hole 131, the cap layer 15 can be patterned synchronously with the barrier layer 13, and this application will not repeat it. When the barrier layer 13 does not include a receiving groove 132 or a receiving hole 131, the cap layer 15 can be patterned separately to expose the area in the barrier layer 13 for forming the source part 141 and the drain part 142, so as to facilitate the source part 141 and the drain part 142 to form ohmic contact with the barrier layer 13 respectively.

[0099] The preparation method provided in the present application also includes forming a gate insulating layer and a gate (not shown in the figure) on the surface of the cap layer facing away from the substrate, and the gate is located between the source and the drain.

[0100] The above are only preferred specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A channel layer, located on one side of the substrate; A barrier layer, located on a side of the channel layer facing away from the substrate; The source-drain functional part is located on the side of the barrier layer away from the substrate and contacts the barrier layer. The source-drain functional part includes a source part and a drain part arranged at intervals. The source-drain functional part includes a titanium metal layer, an aluminum metal layer and a titanium nitride layer stacked in a direction away from the barrier layer.

2. The semiconductor device according to claim 1, wherein: The thickness of the titanium metal layer is in the range of 5nm-25nm; and / or, The thickness of the aluminum metal layer is in the range of 120nm-180nm; and / or, The thickness of the titanium nitride layer is in the range of 80nm-120nm.

3. The semiconductor device according to claim 1, wherein: The atomic number ratio of nitrogen atoms to titanium atoms in the titanium nitride layer is in the range of 0.8-1.

2.

4. The semiconductor device according to claim 1, wherein: The barrier layer has a thickness greater than a preset thickness value, and the barrier layer includes a receiving hole, wherein the receiving hole penetrates the barrier layer and exposes the channel layer; The source portion is located in the accommodating hole, the source portion corresponds to the accommodating hole one-to-one, the source portion contacts the side wall of the accommodating hole, and the source portion contacts the channel layer exposed through the accommodating hole; the drain portion is located in the accommodating hole, the drain portion corresponds to the accommodating hole one-to-one, the drain portion contacts the side wall of the accommodating hole, and the source portion contacts the channel layer exposed through the accommodating hole.

5. The semiconductor device according to claim 1, wherein: The thickness of the barrier layer is greater than a preset thickness value, the barrier layer comprises a receiving groove, and the receiving groove comprises a side wall and a bottom wall; The source portion is located in the receiving groove, the source portion corresponds to the receiving groove one-to-one, and the source portion contacts the side wall and the bottom wall of the receiving groove; the drain portion is located in the receiving hole, the drain portion corresponds to the receiving groove one-to-one, and the drain portion contacts the side wall and the bottom wall of the receiving groove.

6. The semiconductor device according to claim 1, wherein: The invention also includes a cap layer, which is located on a side of the barrier layer away from the channel layer, and the cap layer is disposed around at least a portion of the circumference of the source / drain functional portion.

7. The semiconductor device according to claim 6, characterized in that The material of the cap layer includes one of gallium nitride and silicon nitride; and / or, The material of the substrate includes one of silicon carbide, silicon, and sapphire.

8. The semiconductor device according to claim 1, wherein: The source-drain functional part further includes a titanium nitride connection layer located between the barrier layer and the titanium metal layer and a titanium-aluminum alloy layer located between the titanium metal layer and the aluminum metal layer.

9. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; forming a channel layer on one side of the substrate; forming a barrier layer on a side of the channel layer facing away from the substrate; A titanium metal material layer, an aluminum metal material layer and a titanium nitride material layer are sequentially formed on the surface of the barrier layer on the side away from the channel layer, and patterning and annealing are performed to form a source-drain functional portion, wherein the drain functional portion includes a source portion and a drain portion that are spaced apart, and the source-drain functional portion includes a titanium metal layer, an aluminum metal layer and a titanium nitride layer that are stacked in a direction away from the barrier layer.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: The steps of sequentially forming a titanium metal material layer, an aluminum metal material layer and a titanium nitride material layer on the surface of the barrier layer facing away from the channel layer, and performing patterning and annealing treatments include: Forming a mask layer on a surface of the barrier layer facing away from the channel layer, wherein the mask layer comprises a blocking region and a hole region, and the hole region is used to form the source portion and the drain portion; Forming a titanium metal material layer disposed entirely on the mask layer facing away from the substrate and on the barrier layer facing away from the substrate; Forming an aluminum metal material layer disposed entirely on a side of the titanium metal material layer away from the substrate; Forming a titanium nitride material layer disposed entirely on a side of the aluminum metal material layer away from the substrate; removing the mask layer and removing the titanium metal material layer, the aluminum metal material layer and the portion of the titanium nitride material layer located on a side of the mask layer away from the substrate; An annealing treatment is performed, wherein the temperature range of the annealing treatment is 600° C.-680° C.

11. The method for preparing a semiconductor device according to claim 9, characterized in that: The titanium metal material layer and the aluminum metal material layer can be formed by a magnetron sputtering process or an electron beam evaporation process.

12. The method for preparing a semiconductor device according to claim 9, characterized in that: The titanium nitride metal layer is formed by sputtering metal titanium in a mixed gas having an argon gas and a nitrogen gas ratio of 40:

7.

13. The method for preparing a semiconductor device according to claim 10, characterized in that: After the step of forming a mask layer on a surface of the barrier layer away from the channel layer, wherein the mask layer includes a blocking area and a hole area, and the hole area is used to form the source portion and the drain portion, the method further includes: The portion of the barrier layer exposed by the hole region is etched to form an accommodation hole or an accommodation groove.

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