GaN-based HEMT device structure and manufacturing method thereof

Abstract

The invention provides a GaN-based HEMT (High Electron Mobility Transistor) device structure and a manufacturing method thereof, a gate pattern layer comprises a gate ring array and a gate line group, the gate ring array comprises a plurality of hexagonal gate rings arranged in a hexagonal array, the gate line group comprises a gate main line and a plurality of gate sub-lines, any two adjacent hexagonal gate rings in the gate ring group are connected through a gate sub-line unit, the source-drain pattern layer comprises a hexagonal electrode plate and hexagonal electrode rings, and the hexagonal electrode rings are provided with gaps above passing paths of the gate sub-line units. According to the invention, on one hand, the source electrode and the drain electrode are completely separated by the closed hexagonal gate ring, so that the drain-source leakage of the transistor can be reduced; and on the other hand, the hexagonal electrode rings around the hexagonal gate rings are provided with the notches and are non-closed, so that the hexagonal gate rings can be led out when layers of the hexagonal gate rings are manufactured, the complexity and difficulty of subsequent wiring can be reduced, the size of a chip can be reduced, and the cost can be saved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a GaN-based HEMT device structure and a manufacturing method thereof. Background Art

[0002] Gallium nitride (GaN) high electron mobility transistor (HEMT) is an advanced power semiconductor device based on gallium nitride materials, which has the characteristics of high electron mobility, high power density, small size and high integration. GaN HEMT uses the AlGaN / GaN heterostructure. Through the piezoelectric effect generated when growing AlGaN film on GaN, a large number of electrons gather at the interface to form a high-mobility two-dimensional electron gas (2DEG) layer, which serves as a current path. Due to the high mobility of the two-dimensional electron gas, the on-resistance of GaN HEMT is smaller, and the output capacitance and gate capacitance are also smaller, which enables it to have higher switching speed and lower switching loss in high-frequency applications.

[0003] There are two main layouts of GaN HEMT, one is the strip layout and the other is the hexagonal unit cell layout. In the standard strip layout, the gate, drain and source are parallel strips that end near the boundary of the active area or extend beyond the boundary of the active area. In the hexagonal unit cell layout, the source (or drain), gate, drain (or source) are arranged in sequence from the inside to the outside, where the source (or drain) in the center is in the shape of a hexagonal plate, the middle gate and the outer drain (or source) are both in the shape of a hexagonal ring, and the gate completely separates the source and drain. Compared with the strip layout, the hexagonal unit cell layout can reduce the drain-source leakage of the transistor. Because the hexagonal unit cell layout uses a closed geometry, that is, a closed unit cell, it has higher requirements for metal interconnection.

[0004] Therefore, how to provide a GaN-based HEMT device structure and a manufacturing method thereof to reduce the complexity of metal interconnection, reduce chip size and save costs while reducing transistor drain-source leakage has become an important technical problem that needs to be urgently solved by technical personnel in this field.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a GaN-based HEMT device structure and a manufacturing method thereof, so as to solve the problems existing in the existing GaN HEMT, such as drain-source leakage, high complexity of metal interconnection, large chip size, etc.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing a GaN-based HEMT device structure, comprising the following steps:

[0008] Providing a substrate, wherein a GaN-AlGaN heterojunction layer is provided in the substrate;

[0009] A gate pattern layer is formed on the substrate, wherein the gate pattern layer includes a gate ring array and a gate line group, wherein the gate ring array includes a plurality of hexagonal gate rings arranged in a hexagonal array, wherein the gate line group includes a gate main line extending along a first direction and a plurality of gate sub-lines arranged in parallel and extending in a second direction, wherein the first direction and the second direction are both parallel to the plane where the substrate is located, and the first direction and the second direction intersect each other, wherein the gate ring array and the plurality of gate sub-lines are located on the same side of the gate main line, wherein the plurality of hexagonal gate rings are divided into a plurality of parallel gate ring groups, wherein each gate ring group includes a plurality of hexagonal gate rings arranged sequentially and at intervals along the second direction, wherein the plurality of gate sub-lines are connected to the plurality of gate ring groups in a one-to-one correspondence, wherein each gate sub-line includes a plurality of gate sub-line units arranged intermittently, wherein any two adjacent hexagonal gate rings in the gate ring group are connected by a gate sub-line unit, and a hexagonal gate ring in the gate ring group closest to the gate main line is connected to the gate main line by a gate sub-line unit;

[0010] forming a first dielectric layer covering the gate pattern layer;

[0011] A source-drain electrode pattern layer is formed on the first dielectric layer, the source-drain electrode pattern layer includes a plurality of hexagonal electrode plates arranged in a hexagonal array and a plurality of hexagonal electrode rings arranged in a hexagonal array, one of the hexagonal electrode plates and the hexagonal electrode ring serves as a source, and the other serves as a drain, a vertical projection of each of the hexagonal electrode plates on the plane where the gate pattern layer is located is correspondingly arranged at the center of a hexagonal gate ring, a vertical projection of each of the hexagonal electrode rings on the plane where the gate pattern layer is located is correspondingly arranged around a hexagonal gate ring, any two adjacent hexagonal electrode rings share a side edge, and a vertical projection of the hexagonal electrode ring on the plane where the gate pattern layer is located has a gap on the passing path of the gate sub-line unit.

[0012] Optionally, the width of the gap is greater than the width of the gate sub-line unit.

[0013] Optionally, the first direction and the second direction are perpendicular to each other, or the first direction and the second direction are at 60°.

[0014] Optionally, the method further comprises the following steps:

[0015] forming a second dielectric layer covering the source and drain electrode pattern layer;

[0016] A plurality of first contact portions, a plurality of second contact portions and a plurality of third contact portions are formed to penetrate the second dielectric layer, each of the hexagonal electrode plates is provided with a plurality of the first contact portions, each of the hexagonal electrode rings is provided with a plurality of the second contact portions, and the gate main line is provided with a plurality of the third contact portions;

[0017] A first metal layer is formed on the second dielectric layer, and the first metal layer is patterned to obtain a plurality of first metal lines extending along the second direction, a plurality of second metal lines extending along the second direction, and a gate metal line extending along the first direction. The plurality of first metal lines and the plurality of second metal lines are alternately arranged in an ABAB manner, a plurality of first contact portions are correspondingly provided under each of the first metal lines, a plurality of second contact portions are correspondingly provided under each of the second metal lines, and a plurality of third contact portions are correspondingly provided under the gate metal lines.

[0018] Optionally, at least one first gate block is extended from the gate main line toward one side of the gate ring array, and a plurality of the third contact portions are arranged on the first gate block.

[0019] Optionally, the width of the first metal line and the width of the second metal line are both greater than the width of the gate sub-line, and the width of the gate metal line is greater than the width of the gate main line.

[0020] Optionally, the method further comprises the following steps:

[0021] forming a third dielectric layer covering the first metal layer;

[0022] Forming a plurality of first conductive vias, a plurality of second conductive vias and a plurality of third conductive vias penetrating the third dielectric layer, wherein each of the first metal lines is provided with a plurality of the first conductive vias, each of the second metal lines is provided with a plurality of the second conductive vias, and the gate metal lines are provided with a plurality of the third conductive vias;

[0023] Forming a second metal layer on the third dielectric layer, patterning the second metal layer to obtain at least one first metal block, at least one second metal block and at least one gate metal block, wherein a plurality of the first conductive vias are correspondingly disposed under each of the first metal blocks, a plurality of the second conductive vias are correspondingly disposed under each of the second metal blocks, and a plurality of the third conductive vias are correspondingly disposed under each of the gate metal blocks;

[0024] A fourth dielectric layer covering the second metal layer is formed, and the fourth dielectric layer is patterned to obtain at least one first pad hole exposing the first metal block, at least one second pad hole exposing the second metal block, and at least one third pad hole exposing the gate metal block.

[0025] Optionally, the first metal blocks and the second metal blocks are alternately arranged one or more times in the second direction.

[0026] Optionally, at least one second gate block extends from the gate metal line toward one side of the first metal line or the second metal line, a plurality of the third conductive through holes are arranged on the second gate block, and the gate metal block covers the second gate block.

[0027] Optionally, an opening area of ​​the first pad hole, an opening area of ​​the second pad hole, and an opening area of ​​the third pad hole are all larger than an area enclosed by the hexagonal gate ring.

[0028] The present invention also provides a GaN-based HEMT device structure, comprising:

[0029] A substrate, wherein a GaN-AlGaN heterojunction layer is provided in the substrate;

[0030] a gate pattern layer, located on the substrate, the gate pattern layer comprising a gate ring array and a gate line group, the gate ring array comprising a plurality of hexagonal gate rings arranged in a hexagonal array, the gate line group comprising a gate main line extending along a first direction and a plurality of gate sub-lines arranged in parallel and extending in a second direction, the first direction and the second direction are both parallel to the plane where the substrate is located, and the first direction and the second direction intersect each other, the gate ring array and the plurality of gate sub-lines are located on the same side of the gate main line, the plurality of hexagonal gate rings are divided into a plurality of parallel gate ring groups, each of the gate ring groups comprises a plurality of hexagonal gate rings arranged sequentially and at intervals along the second direction, a plurality of gate sub-lines are connected to the plurality of gate ring groups in a one-to-one correspondence, wherein each of the gate sub-lines comprises a plurality of gate sub-line units arranged discontinuously, any two adjacent hexagonal gate rings in the gate ring group are connected by a gate sub-line unit, and a hexagonal gate ring in the gate ring group closest to the gate main line is connected to the gate main line by a gate sub-line unit;

[0031] A first dielectric layer covering the gate pattern layer;

[0032] A source-drain electrode graphic layer is located on the first dielectric layer and includes a plurality of hexagonal electrode plates arranged in a hexagonal array and a plurality of hexagonal electrode rings arranged in a hexagonal array, wherein one of the hexagonal electrode plates and the hexagonal electrode ring serves as a source, and the other serves as a drain, and a vertical projection of each of the hexagonal electrode plates on the plane where the gate graphic layer is located is correspondingly arranged at the center of a hexagonal gate ring, and a vertical projection of each of the hexagonal electrode rings on the plane where the gate graphic layer is located is correspondingly arranged around a hexagonal gate ring, and any two adjacent hexagonal electrode rings share a side edge, and a vertical projection of the hexagonal electrode ring on the plane where the gate graphic layer is located has a gap on the passing path of the gate sub-line unit.

[0033] Optionally, the width of the gap is greater than the width of the gate sub-line unit.

[0034] Optionally, the first direction and the second direction are perpendicular to each other, or the first direction and the second direction are at 60°.

[0035] Optionally, the GaN-based HEMT device structure further includes:

[0036] A second dielectric layer covering the source and drain electrode pattern layer;

[0037] A plurality of first contact portions, a plurality of second contact portions and a plurality of third contact portions penetrating the second dielectric layer, a plurality of the first contact portions being correspondingly provided on each of the hexagonal electrode plates, a plurality of the second contact portions being correspondingly provided on each of the hexagonal electrode rings, and a plurality of the third contact portions being correspondingly provided on the gate main line;

[0038] A first metal layer is located on the second dielectric layer and includes a plurality of first metal wires extending along the second direction, a plurality of second metal wires extending along the second direction, and a gate metal wire extending along the first direction. The plurality of first metal wires and the plurality of second metal wires are alternately arranged in an ABAB manner. A plurality of first contact portions are correspondingly arranged under each of the first metal lines, a plurality of second contact portions are correspondingly arranged under each of the second metal lines, and a plurality of third contact portions are correspondingly arranged under the gate metal lines.

[0039] Optionally, at least one first gate block is extended from the gate main line toward one side of the gate ring array, and a plurality of the third contact portions are arranged on the first gate block.

[0040] Optionally, the width of the first metal line and the width of the second metal line are both greater than the width of the gate sub-line, and the width of the gate metal line is greater than the width of the gate main line.

[0041] Optionally, the GaN-based HEMT device structure further includes:

[0042] a third dielectric layer covering the first metal layer;

[0043] A plurality of first conductive vias, a plurality of second conductive vias and a plurality of third conductive vias penetrating the third dielectric layer, a plurality of the first conductive vias being correspondingly provided on each of the first metal lines, a plurality of the second conductive vias being correspondingly provided on each of the second metal lines, and a plurality of the third conductive vias being correspondingly provided on the gate metal line;

[0044] A second metal layer is located on the third dielectric layer and includes at least one first metal block, at least one second metal block and at least one gate metal block, wherein a plurality of the first conductive vias are correspondingly provided under each of the first metal blocks, a plurality of the second conductive vias are correspondingly provided under each of the second metal blocks, and a plurality of the third conductive vias are correspondingly provided under each of the gate metal blocks;

[0045] a fourth dielectric layer, covering the second metal layer,

[0046] At least one first pad hole, at least one second pad hole and at least one third pad hole penetrate the fourth dielectric layer, the first pad hole exposes the first metal block, the second pad hole exposes the second metal block, and the third pad hole exposes the gate metal block.

[0047] Optionally, the first metal blocks and the second metal blocks are alternately arranged one or more times in the second direction.

[0048] Optionally, at least one second gate block extends from the gate metal line toward one side of the first metal line or the second metal line, a plurality of the third conductive through holes are arranged on the second gate block, and the gate metal block covers the second gate block.

[0049] Optionally, an opening area of ​​the first pad hole, an opening area of ​​the second pad hole, and an opening area of ​​the third pad hole are all larger than an area enclosed by the hexagonal gate ring.

[0050] As described above, in the GaN-based HEMT device structure and the manufacturing method thereof of the present invention, a gate pattern layer is provided including a gate ring array and a gate line group, the gate ring array includes a plurality of hexagonal gate rings arranged in a hexagonal array, the gate line group includes a gate main line extending in a first direction and a plurality of gate sub-lines arranged in parallel and extending in a second direction, each gate sub-line includes a plurality of gate sub-line units arranged discontinuously, any two adjacent hexagonal gate rings in the gate ring group are connected by a gate sub-line unit, a hexagonal gate ring in the gate ring group closest to the gate main line is connected to the gate main line by a gate sub-line unit, the source-drain pattern layer includes a plurality of hexagonal electrode plates arranged in a hexagonal array and a plurality of hexagonal electrode rings arranged in a hexagonal array, one of the hexagonal electrode plates and the hexagonal electrode ring is used as a source, and the other is used as a drain, and the vertical projection of the hexagonal electrode ring on the plane where the gate pattern layer is located has a gap on the path through which the gate sub-line unit passes. In the present invention, on the one hand, since the closed hexagonal gate ring completely isolates the source and the drain, the drain-source leakage of the transistor can be reduced and the device performance can be improved; on the other hand, since the hexagonal electrode rings around the hexagonal gate ring have gaps and are non-closed, the hexagonal gate ring can be led out when the layer of the hexagonal gate ring is made, which is conducive to reducing the complexity and difficulty of subsequent wiring and is conducive to using fewer metal layers to complete the wiring. In addition, since the area available for wiring is more abundant and flexible, in some optional embodiments of the present invention, the second metal layer can be used to make the pad, and the pad can be directly set above the active area instead of being led to the periphery of the active area, thereby reducing the chip size to a certain extent and saving costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1Shown is an electrode layout for a GaN HEMT hexagonal unit cell.

[0052] Figure 2 Shown is an alternative electrode layout for a GaN HEMT hexagonal unit cell.

[0053] Figure 3 The process flow chart shows the method for manufacturing the GaN-based HEMT device structure of the present invention.

[0054] Figure 4 A planar layout diagram showing a gate pattern layer formed by the method for manufacturing a GaN-based HEMT device structure of the present invention.

[0055] Figure 5 The plan layout diagram of the structure obtained after the source and drain pattern layers are formed on the first dielectric layer according to the manufacturing method of the GaN-based HEMT device structure of the present invention is shown.

[0056] Figure 6 The electrode layout of a unit cell in the GaN-based HEMT device structure manufactured according to the present invention is shown.

[0057] Figure 7 The plan layout diagram of the structure obtained after the first contact portion, the second contact portion and the third contact portion are formed according to the method for manufacturing the GaN-based HEMT device structure of the present invention is shown.

[0058] Figure 8 The planar layout diagram of the structure obtained after patterning the first metal layer in the method for manufacturing the GaN-based HEMT device structure of the present invention is shown.

[0059] Fig. 9 It is a planar layout diagram of the structure obtained after forming the first conductive via, the second conductive via and the third conductive via according to the manufacturing method of the GaN-based HEMT device structure of the present invention.

[0060] Fig.10 The planar layout diagram of the structure obtained after patterning the second metal layer in the method for manufacturing the GaN-based HEMT device structure of the present invention is shown.

[0061] Fig.11 It is a planar layout diagram of the structure obtained after forming the first pad hole, the second pad hole and the third pad hole according to the manufacturing method of the GaN-based HEMT device structure of the present invention.

[0062] Description of Reference Numerals

[0063] 101 Source

[0064] 102 gate

[0065] 103 Drain

[0066] 201 Drain

[0067] 202 gate

[0068] 203 Source

[0069] Steps S1 to S4

[0070] 301 gate pattern layer

[0071] 3011 Hexagonal Gate Ring

[0072] 3012 grid main line

[0073] 3012a first gate block

[0074] 3013 gate sub-line

[0075] 3013a Gate sub-line unit

[0076] 302 Source and drain pattern layer

[0077] 3021 hexagonal electrode plate

[0078] 3022 Hexagonal Electrode Ring

[0079] 3022a gap

[0080] 3031 first contact part

[0081] 3032 second contact part

[0082] 3033 Third contact part

[0083] 304 first metal layer

[0084] 3041 First Metal Wire

[0085] 3042 Second Metal Wire

[0086] 3043 Gate Metal Line

[0087] 3043a Second gate block

[0088] 3051 first conductive via

[0089] 3052 second conductive via

[0090] 3053 third conductive via

[0091] 306 Second Metal Layer

[0092] 3061 First Metal Block

[0093] 3062 Second Metal Block

[0094] 3063 Gate Metal Block

[0095] 307 Fourth dielectric layer

[0096] 3071 first pad hole

[0097] 3072 Second pad hole

[0098] 3073 third pad hole

[0099] 3081 first pad

[0100] 3082 Second pad

[0101] 3083 Gate pad

[0102] A1~A9 gate ring group

[0103] X first direction

[0104] Y second direction DETAILED DESCRIPTION

[0105] See also Figure 1 and Figure 2 ,in, Figure 1 The figure shows an electrode layout of a GaN HEMT hexagonal unit cell, which includes a source 101, a gate 102, and a drain 103 from the inside to the outside. Figure 2 Another electrode layout of the GaN HEMT hexagonal unit cell is shown, which is a drain 201, a gate 202 and a source 203 from the inside out. In these two electrode layouts, the outermost hexagonal electrode ring is a closed design, which places higher requirements on metal interconnection. The inventor of the present application has improved the electrode layout of the GaN HEMT through a lot of analysis and research, which can reduce the complexity of metal interconnection while reducing the drain-source leakage of the transistor, and is conducive to reducing chip size and saving costs.

[0106] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0107] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0108] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0109] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0110] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0111] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0112] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0113] The present invention provides a method for manufacturing a GaN-based HEMT device structure. Figure 3 , shown as a process flow chart of the method, comprising the following steps:

[0114] S1: providing a substrate, wherein a GaN-AlGaN heterojunction layer is provided in the substrate;

[0115] S2: forming a gate pattern layer on the substrate, the gate pattern layer comprising a gate ring array and a gate line group, the gate ring array comprising a plurality of hexagonal gate rings arranged in a hexagonal array, the gate line group comprising a gate main line extending along a first direction and a plurality of gate sub-lines arranged in parallel and extending in a second direction, the first direction and the second direction are both parallel to the plane where the substrate is located, and the first direction and the second direction intersect each other, the gate ring array and the plurality of gate sub-lines are located on the same side of the gate main line, the plurality of hexagonal gate rings are divided into a plurality of parallel gate ring groups, each of the gate ring groups comprises a plurality of hexagonal gate rings arranged sequentially and at intervals along the second direction, a plurality of gate sub-lines are connected to the plurality of gate ring groups in a one-to-one correspondence, wherein each of the gate sub-lines comprises a plurality of gate sub-line units arranged intermittently, any two adjacent hexagonal gate rings in the gate ring group are connected by a gate sub-line unit, and a hexagonal gate ring in the gate ring group closest to the gate main line is connected to the gate main line by a gate sub-line unit;

[0116] S3: forming a first dielectric layer covering the gate pattern layer;

[0117] S4: forming a source-drain electrode pattern layer on the first dielectric layer, wherein the source-drain electrode pattern layer comprises a plurality of hexagonal electrode plates arranged in a hexagonal array and a plurality of hexagonal electrode rings arranged in a hexagonal array, wherein one of the hexagonal electrode plates and the hexagonal electrode ring serves as a source, and the other serves as a drain, wherein a vertical projection of each of the hexagonal electrode plates on the plane where the gate pattern layer is located is correspondingly arranged at the center of a hexagonal gate ring, and a vertical projection of each of the hexagonal electrode rings on the plane where the gate pattern layer is located is correspondingly arranged around a hexagonal gate ring, and any two adjacent hexagonal electrode rings share a side edge, and a vertical projection of the hexagonal electrode ring on the plane where the gate pattern layer is located has a gap on a passing path of the gate sub-line unit.

[0118] The above steps will be further described in detail below in conjunction with the structure diagram.

[0119] First, the step S1 is performed: providing a substrate (not shown), wherein a GaN-AlGaN heterojunction layer is disposed in the substrate.

[0120] Specifically, a plurality of transistors arranged in a hexagonal array are prefabricated in the base layer, and the transistors include at least a GaN-AlGaN heterojunction layer, wherein a high-mobility two-dimensional electron gas (2DEG) layer can be generated at the interface between the GaN layer and the AlGaN layer.

[0121] In addition, other functional layers may be introduced into the transistor as required to achieve the required electrical parameters, and the protection scope of the present invention should not be excessively limited here.

[0122] See next Figure 4 , performing the step S2: forming a gate pattern layer 301 on the substrate, wherein, Figure 4 The plan layout diagram of the gate pattern layer 301 is shown.

[0123] As an example, a gate material layer may be deposited on the substrate, and the gate material layer may be patterned using semiconductor processes such as photolithography and etching to obtain the gate pattern layer 301. The gate material layer may be made of one or a combination of several metals selected from gold, aluminum, titanium, and titanium nitride, or other suitable materials.

[0124] Specifically, the gate pattern layer 301 includes a gate ring array and a gate line group, the gate ring array includes a plurality of hexagonal gate rings 3011 arranged in a hexagonal array, the gate line group includes a gate main line 3012 extending along a first direction X and a plurality of gate sub-lines 3013 arranged in parallel and extending in a second direction Y, the first direction X and the second direction Y are both parallel to the plane where the substrate is located, and the first direction X and the second direction Y intersect each other.

[0125] As an example, the first direction X and the second direction Y are perpendicular to each other, for example Figure 4 What is shown.

[0126] In some other embodiments of the present invention, the first direction X and the second direction Y may also be at other angles, such as 60°.

[0127] Specifically, the gate ring array and the plurality of gate sub-lines 3013 are located on the same side of the gate main line 3012, and the plurality of hexagonal gate rings 3011 are divided into a plurality of gate ring groups arranged in parallel, for example Figure 4The first gate ring group A1, the second gate ring group A2, the third gate ring group A3, the fourth gate ring group A4, the fifth gate ring group A5, the sixth gate ring group A6, the seventh gate ring group A7, the eighth gate ring group A8 and the ninth gate ring group A9, each of the gate ring groups includes a plurality of hexagonal gate rings 3011 arranged sequentially and at intervals along the second direction Y, and a plurality of gate sub-lines 3013 are connected to the plurality of gate ring groups in a one-to-one correspondence, wherein each of the gate sub-lines 3013 includes a plurality of gate sub-line units 3013a arranged intermittently, any two adjacent hexagonal gate rings 3011 in the gate ring group are connected by a gate sub-line unit 3013a, and a hexagonal gate ring 3011 in the gate ring group closest to the gate main line 3012 is connected to the gate main line 3012 by a gate sub-line unit 3013a.

[0128] As an example, the gate main line 3012 can be in a straight line, a curve, or other suitable linear shape, and the gate sub-line 3013 can be in a straight line, a curve, a broken line, or other suitable linear shape.

[0129] Next, the step S3 is performed: forming a first dielectric layer (not shown) covering the gate pattern layer 301 .

[0130] As an example, the material of the first dielectric layer can be selected from silicon oxide, silicon nitride, or a combination of some dielectric materials, or other suitable dielectric materials.

[0131] See next Figure 5 , perform the step S4: forming a source-drain pattern layer 302 on the first dielectric layer.

[0132] As an example, a source-drain material layer may be deposited on the first dielectric layer, and the source-drain material layer may be patterned using semiconductor processes such as photolithography and etching to obtain the source-drain pattern layer 302. The source-drain material layer may be made of one or a combination of several metals selected from gold, aluminum, titanium, and titanium nitride, or other suitable materials.

[0133] Specifically, the source-drain electrode pattern layer 302 includes a plurality of hexagonal electrode plates 3021 arranged in a hexagonal array and a plurality of hexagonal electrode rings 3022 arranged in a hexagonal array, one of the hexagonal electrode plates 3021 and the hexagonal electrode rings 3022 serves as a source, and the other serves as a drain.

[0134] Specifically, the vertical projection of each hexagonal electrode plate 3021 on the plane where the gate graphic layer 301 is located is correspondingly arranged at the center of a hexagonal gate ring 3011, and the vertical projection of each hexagonal electrode ring 3022 on the plane where the gate graphic layer 301 is located is correspondingly arranged around a hexagonal gate ring 3011, and any two adjacent hexagonal electrode rings 3022 share a side edge.

[0135] For details, please refer to Figure 6 , showing the electrode layout of a unit cell in the GaN-based HEMT device structure manufactured by the present invention, wherein the vertical projection of the hexagonal electrode ring 3022 on the plane where the gate pattern layer 301 is located has a gap 3022a on the passing path of the gate sub-line unit 3013a, that is, the hexagonal electrode ring 3022 is non-closed.

[0136] As an example, the width of the gap 3022a is greater than the width of the gate sub-line unit 3013a.

[0137] In the present invention, on the one hand, since the closed hexagonal gate ring 3011 completely isolates the hexagonal electrode plate 3021 and the hexagonal electrode ring 3022, that is, completely isolates the source and the drain, the drain-source leakage of the transistor can be reduced and the device performance can be improved; on the other hand, since the hexagonal electrode ring 3022 is non-closed, the hexagonal gate ring 3011 can be led out through the gate line group when the layer of the hexagonal gate ring 3011 is manufactured, which is beneficial to reduce the complexity and difficulty of subsequent wiring, and is beneficial to using fewer metal layers to complete the wiring.

[0138] Some key steps of subsequent wiring are described below through some embodiments.

[0139] As an example, see Figure 7 , further forming a second dielectric layer (not shown) covering the source-drain pattern layer 302, and forming a plurality of first contact portions 3031, a plurality of second contact portions 3032 and a plurality of third contact portions 3033 penetrating the second dielectric layer, each of the hexagonal electrode plates 3021 is provided with a plurality of the first contact portions 3031, each of the hexagonal electrode rings 3022 is provided with a plurality of the second contact portions 3032, and the gate main line 302 is provided with a plurality of the third contact portions 3033.

[0140] As an example, the material of the second dielectric layer can be selected from silicon oxide, silicon nitride, or a combination of some dielectric materials, or other suitable dielectric materials.

[0141] As an example, at least one first gate block 3012 a is extended from the gate main line 3012 toward one side of the gate ring array, and a plurality of the third contact portions 3033 are arranged on the first gate block 3012 a .

[0142] As an example, the first gate block 3012 a is trapezoidal in shape to adapt to the shape of the hexagonal electrode rings 3022 and fully utilize the space on one side of the plurality of hexagonal electrode rings 3022 .

[0143] As an example, the material of the first contact portion 3031 , the second contact portion 3032 , and the third contact portion 3033 may be tungsten or other suitable conductive materials.

[0144] As an example, see Figure 8 , further forming a first metal layer 304 on the second dielectric layer, and patterning the first metal layer 304 using semiconductor processes such as photolithography and etching to obtain a plurality of first metal wires 3041 extending along the second direction Y, a plurality of second metal wires 3042 extending along the second direction Y, and a gate metal wire 3043 extending along the first direction X, wherein one of the first metal wire 3041 and the second metal wire 3042 serves as a source metal wire, and the other serves as a drain metal wire.

[0145] Specifically, multiple first metal wires 3041 and multiple second metal wires 3042 are alternately arranged in an ABAB manner, and multiple first contact portions 3031 are correspondingly provided under each first metal wire 3041 to electrically connect to the hexagonal electrode plate 3021, and multiple second contact portions 3032 are correspondingly provided under each second metal wire 3042 to electrically connect to the hexagonal electrode ring 3022, and multiple third contact portions 3033 are correspondingly provided under the gate metal line 3043 to electrically connect to the gate main line 302.

[0146] As an example, the width of the first metal line 3041 and the width of the second metal line 3042 are both greater than the width of the gate sub-line 3013 so as to completely cover the gate sub-line 3013 , and the width of the gate metal line 3043 is greater than the width of the gate main line 302 so as to completely cover the gate main line 302 .

[0147] As an example, at least one second gate block 3043 a is extended from one side of the gate metal line 3043 toward the first metal line 3041 or the second metal line 3042 to cover the first gate block 3012 a .

[0148] As an example, see Fig. 9, further forming a third dielectric layer (not shown) covering the first metal layer 304, and forming a plurality of first conductive vias 3051, a plurality of second conductive vias 3052 and a plurality of third conductive vias 3053 penetrating the third dielectric layer, each of the first metal lines 3041 is provided with a plurality of the first conductive vias 3051, each of the second metal lines 3042 is provided with a plurality of the second conductive vias 3052, and the gate metal line 3043 is provided with a plurality of the third conductive vias 3053.

[0149] Specifically, the third dielectric layer is used as an interlayer dielectric layer, and is used as an insulating layer between the upper and lower metal layers. The material of the third dielectric layer can be selected from silicon oxide, silicon nitride, or a combination of several dielectrics, or other suitable dielectric materials.

[0150] As an example, the material of the first conductive via 3051 , the second conductive via 3052 , and the third conductive via 3053 may be tungsten or other suitable conductive materials.

[0151] As an example, there are a plurality of the third conductive vias 3053 disposed on the second gate block 3043a.

[0152] As an example, see Fig.10 , further forming a second metal layer 306 on the third dielectric layer, and patterning the second metal layer 306 by using semiconductor processes such as photolithography and etching to obtain at least one first metal block 3061, at least one second metal block 3062 and at least one gate metal block 3063, each of the first metal blocks 3061 is provided with a plurality of first conductive vias 3051 to electrically connect the first metal line 3041, each of the second metal blocks 3062 is provided with a second conductive via 3052 to electrically connect the second metal line 3042, and each of the gate metal blocks 3063 is provided with a plurality of third conductive vias 3053 to electrically connect the gate metal line 3043.

[0153] As an example, the first metal block 3061 and the second metal block 3062 are alternately arranged one or more times in the second direction Y, for example Fig.10 What is shown in FIG. 3 is that the first metal block 3061 and the second metal block 3062 are alternately arranged twice in the second direction Y.

[0154] As an example, the gate metal block 3063 covers the second gate block 3043a.

[0155] As an example, see Fig.11, further forming a fourth dielectric layer 307 covering the second metal layer 306, and patterning the fourth dielectric layer 307 using semiconductor processes such as photolithography and etching to obtain at least one first pad hole 3071 exposing the first metal block 3061, at least one second pad hole 3072 exposing the second metal block 306, and at least one third pad hole 3073 exposing the gate metal block 3063.

[0156] Specifically, the fourth dielectric layer 307 is used as a passivation layer to protect the device surface. The material of the fourth dielectric layer 307 can be selected from silicon oxide, silicon nitride, or a combination of several dielectrics, or other suitable dielectric materials.

[0157] Specifically, the first metal block 3061 exposed by the first pad hole 3071 serves as a first pad 3081, the second metal block 3062 exposed by the second pad hole 3072 serves as a second pad 3082, and the gate metal block 3063 exposed by the third pad hole 3073 serves as a gate pad 3083, wherein one of the first pad 3081 and the second pad 3082 serves as a source pad, and the other serves as a drain pad.

[0158] As an example, the opening area of ​​the first pad hole 3071 , the opening area of ​​the second pad hole 3072 , and the opening area of ​​the third pad hole 3073 are all larger than the area enclosed by the hexagonal gate ring 3011 .

[0159] In the present invention, since the hexagonal gate ring 3011 is led out through the gate line group when the layer of the hexagonal gate ring 3011 is manufactured, the complexity and difficulty of subsequent wiring are reduced, and the wiring can be completed with fewer metal layers. Since the area available for wiring is more abundant and flexible, the second metal layer 306 can be used to make a pad, and the pad can be directly set above the active area instead of being led to the periphery of the active area, thereby reducing the chip size to a certain extent and saving costs.

[0160] In some embodiments of the present invention, a GaN-based HEMT device structure is also provided, comprising a substrate, a gate pattern layer, a first dielectric layer and a source-drain pattern layer, wherein a GaN-AlGaN heterojunction layer is provided in the substrate, the gate pattern layer is located on the substrate and comprises a gate ring array and a gate line group, the first dielectric layer covers the gate pattern layer, the source-drain pattern layer is located on the first dielectric layer and comprises a plurality of hexagonal electrode plates arranged in a hexagonal array and a plurality of hexagonal electrode rings arranged in a hexagonal array, one of the hexagonal electrode plate and the hexagonal electrode ring serves as a source, and the other serves as a drain.

[0161] Specifically, the gate ring array includes a plurality of hexagonal gate rings arranged in a hexagonal array, the gate line group includes a gate main line extending along a first direction and a plurality of gate sub-lines arranged in parallel and extending in a second direction, the first direction and the second direction are both parallel to the plane where the substrate is located, and the first direction and the second direction intersect with each other, the gate ring array and the plurality of gate sub-lines are located on the same side of the gate main line, the plurality of hexagonal gate rings are divided into a plurality of parallel arranged gate ring groups, each of the gate ring groups includes a plurality of hexagonal gate rings arranged sequentially and at intervals along the second direction, a plurality of gate sub-lines are connected to the plurality of gate ring groups in a one-to-one correspondence, wherein each of the gate sub-lines includes a plurality of gate sub-line units arranged intermittently, any two adjacent hexagonal gate rings in the gate ring group are connected by a gate sub-line unit, and a hexagonal gate ring in the gate ring group closest to the gate main line is connected to the gate main line by a gate sub-line unit.

[0162] Specifically, the vertical projection of each hexagonal electrode plate on the plane where the gate graphic layer is located is correspondingly arranged at the center of a hexagonal gate ring, the vertical projection of each hexagonal electrode ring on the plane where the gate graphic layer is located is correspondingly arranged around a hexagonal gate ring, any two adjacent hexagonal electrode rings share a side edge, and the vertical projection of the hexagonal electrode ring on the plane where the gate graphic layer is located has a gap on the passing path of the gate sub-line unit.

[0163] As an example, the width of the gap is greater than the width of the gate sub-line unit.

[0164] As an example, the first direction and the second direction are perpendicular to each other, or the first direction and the second direction are 60° apart.

[0165] As an example, the GaN-based HEMT device structure also includes a second dielectric layer, a first metal layer and a plurality of first contacts, a plurality of second contacts, and a plurality of third contacts, wherein the second dielectric layer covers the source and drain graphic layer, the first contact, the second contact and the third contact all penetrate the second dielectric layer, the first metal layer is located on the second dielectric layer and includes a plurality of first metal wires extending along the second direction, a plurality of second metal wires extending along the second direction and a gate metal wire extending along the first direction.

[0166] Specifically, each of the hexagonal electrode plates is correspondingly provided with a plurality of the first contact portions, each of the hexagonal electrode rings is correspondingly provided with a plurality of the second contact portions, and the gate main line is correspondingly provided with a plurality of the third contact portions.

[0167] Specifically, multiple first metal lines and multiple second metal lines are alternately arranged in an ABAB manner, multiple first contact portions are correspondingly provided under each first metal line, multiple second contact portions are correspondingly provided under each second metal line, and multiple third contact portions are correspondingly provided under the gate metal line.

[0168] As an example, at least one first gate block is extended from the gate main line toward one side of the gate ring array, and a plurality of the third contact portions are arranged on the first gate block.

[0169] As an example, the width of the first metal line and the width of the second metal line are both greater than the width of the gate sub-line, and the width of the gate metal line is greater than the width of the gate main line.

[0170] As an example, the GaN-based HEMT device structure also includes a third dielectric layer, a second metal layer, a fourth dielectric layer, a plurality of first conductive vias, a plurality of second conductive vias, a plurality of third conductive vias, at least one first pad hole, at least one second pad hole and at least one third pad hole, wherein the third dielectric layer covers the first metal layer, the first conductive via, the second conductive via and the third conductive via all pass through the third dielectric layer, the second metal layer is located on the third dielectric layer and includes at least one first metal block, at least one second metal block and at least one gate metal block, the fourth dielectric layer covers the second metal layer, and the first pad hole, the second pad hole and the third pad hole all pass through the fourth dielectric layer.

[0171] Specifically, each of the first metal lines is correspondingly provided with a plurality of the first conductive vias, each of the second metal lines is correspondingly provided with a plurality of the second conductive vias, and the gate metal line is correspondingly provided with a plurality of the third conductive vias.

[0172] Specifically, a plurality of the first conductive vias are correspondingly provided under each of the first metal blocks, a plurality of the second conductive vias are correspondingly provided under each of the second metal blocks, and a plurality of the third conductive vias are correspondingly provided under each of the gate metal blocks.

[0173] Specifically, the first pad hole exposes the first metal block to obtain a first pad, the second pad hole exposes the second metal block to obtain a second pad, the third pad hole exposes the gate metal block to obtain a gate pad, and one of the first pad and the second pad serves as a source pad, and the other serves as a drain pad.

[0174] As an example, the first metal blocks and the second metal blocks are alternately arranged one or more times in the second direction.

[0175] As an example, at least one second gate block extends from the gate metal line toward one side of the first metal line or the second metal line, a plurality of the third conductive through holes are arranged on the second gate block, and the gate metal block covers the second gate block.

[0176] As an example, an opening area of ​​the first pad hole, an opening area of ​​the second pad hole, and an opening area of ​​the third pad hole are all larger than an area enclosed by the hexagonal gate ring.

[0177] The GaN-based HEMT device structure of the present invention can complete metal interconnection with only two layers of metal, and the pad can be made above the active area, which can reduce the chip size to a certain extent and save costs.

[0178] In summary, in the GaN-based HEMT device structure and the manufacturing method thereof of the present invention, a gate pattern layer is provided including a gate ring array and a gate line group, the gate ring array includes a plurality of hexagonal gate rings arranged in a hexagonal array, the gate line group includes a gate main line extending in a first direction and a plurality of gate sub-lines arranged in parallel and extending in a second direction, each gate sub-line includes a plurality of gate sub-line units arranged discontinuously, any two adjacent hexagonal gate rings in the gate ring group are connected by a gate sub-line unit, a hexagonal gate ring in the gate ring group closest to the gate main line is connected to the gate main line by a gate sub-line unit, the source-drain pattern layer includes a plurality of hexagonal electrode plates arranged in a hexagonal array and a plurality of hexagonal electrode rings arranged in a hexagonal array, one of the hexagonal electrode plates and the hexagonal electrode ring is used as a source, and the other is used as a drain, and the vertical projection of the hexagonal electrode ring on the plane where the gate pattern layer is located has a gap on the path through which the gate sub-line unit passes. In the present invention, on the one hand, since the closed hexagonal gate ring completely isolates the source and the drain, the drain-source leakage of the transistor can be reduced and the device performance can be improved; on the other hand, since the hexagonal electrode rings around the hexagonal gate ring have gaps and are non-closed, the hexagonal gate ring can be led out when the layer of the hexagonal gate ring is made, which is conducive to reducing the complexity and difficulty of subsequent wiring and is conducive to using fewer metal layers to complete the wiring. In addition, since the area available for wiring is more abundant and flexible, in some optional embodiments of the present invention, the second metal layer can be used to make the pad, and the pad can be directly set above the active area instead of being led to the periphery of the active area, so that the chip size can be reduced to a certain extent and the cost can be saved. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0179] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a GaN-based HEMT device structure, characterized in that: The following steps are involved: Providing a substrate, wherein a GaN-AlGaN heterojunction layer is provided in the substrate; A gate pattern layer is formed on the substrate, wherein the gate pattern layer includes a gate ring array and a gate line group, wherein the gate ring array includes a plurality of hexagonal gate rings arranged in a hexagonal array, wherein the gate line group includes a gate main line extending along a first direction and a plurality of gate sub-lines arranged in parallel and extending in a second direction, wherein the first direction and the second direction are both parallel to the plane where the substrate is located, and the first direction and the second direction intersect each other, wherein the gate ring array and the plurality of gate sub-lines are located on the same side of the gate main line, wherein the plurality of hexagonal gate rings are divided into a plurality of parallel gate ring groups, wherein each gate ring group includes a plurality of hexagonal gate rings arranged sequentially and at intervals along the second direction, wherein the plurality of gate sub-lines are connected to the plurality of gate ring groups in a one-to-one correspondence, wherein each gate sub-line includes a plurality of gate sub-line units arranged intermittently, wherein any two adjacent hexagonal gate rings in the gate ring group are connected by a gate sub-line unit, and a hexagonal gate ring in the gate ring group closest to the gate main line is connected to the gate main line by a gate sub-line unit; forming a first dielectric layer covering the gate pattern layer; A source-drain electrode pattern layer is formed on the first dielectric layer, the source-drain electrode pattern layer includes a plurality of hexagonal electrode plates arranged in a hexagonal array and a plurality of hexagonal electrode rings arranged in a hexagonal array, one of the hexagonal electrode plates and the hexagonal electrode ring serves as a source, and the other serves as a drain, a vertical projection of each of the hexagonal electrode plates on the plane where the gate pattern layer is located is correspondingly arranged at the center of a hexagonal gate ring, a vertical projection of each of the hexagonal electrode rings on the plane where the gate pattern layer is located is correspondingly arranged around a hexagonal gate ring, any two adjacent hexagonal electrode rings share a side edge, and a vertical projection of the hexagonal electrode ring on the plane where the gate pattern layer is located has a gap on the passing path of the gate sub-line unit.

2. The method for manufacturing a GaN-based HEMT device structure according to claim 1, characterized in that: The width of the notch is greater than the width of the gate sub-line unit.

3. The method for manufacturing a GaN-based HEMT device structure according to claim 1, characterized in that: The first direction and the second direction are perpendicular to each other, or the first direction and the second direction are 60 degrees apart.

4. The method for manufacturing a GaN-based HEMT device structure according to claim 1, characterized in that: The following steps are also included: forming a second dielectric layer covering the source and drain electrode pattern layer; A plurality of first contact portions, a plurality of second contact portions and a plurality of third contact portions are formed to penetrate the second dielectric layer, each of the hexagonal electrode plates is provided with a plurality of the first contact portions, each of the hexagonal electrode rings is provided with a plurality of the second contact portions, and the gate main line is provided with a plurality of the third contact portions; A first metal layer is formed on the second dielectric layer, and the first metal layer is patterned to obtain a plurality of first metal lines extending along the second direction, a plurality of second metal lines extending along the second direction, and a gate metal line extending along the first direction. The plurality of first metal lines and the plurality of second metal lines are alternately arranged in an ABAB manner, a plurality of first contact portions are correspondingly provided under each of the first metal lines, a plurality of second contact portions are correspondingly provided under each of the second metal lines, and a plurality of third contact portions are correspondingly provided under the gate metal lines.

5. The method for manufacturing a GaN-based HEMT device structure according to claim 4, characterized in that: The gate main line extends toward one side of the gate ring array to form at least one first gate block, and a plurality of the third contact portions are arranged on the first gate block.

6. The method for manufacturing a GaN-based HEMT device structure according to claim 4, characterized in that: The width of the first metal line and the width of the second metal line are both greater than the width of the gate sub-line, and the width of the gate metal line is greater than the width of the gate main line.

7. The method for manufacturing a GaN-based HEMT device structure according to any one of claims 4 to 6, characterized in that: The following steps are also included: forming a third dielectric layer covering the first metal layer; Forming a plurality of first conductive vias, a plurality of second conductive vias and a plurality of third conductive vias penetrating the third dielectric layer, wherein each of the first metal lines is provided with a plurality of the first conductive vias, each of the second metal lines is provided with a plurality of the second conductive vias, and the gate metal lines are provided with a plurality of the third conductive vias; Forming a second metal layer on the third dielectric layer, patterning the second metal layer to obtain at least one first metal block, at least one second metal block and at least one gate metal block, wherein a plurality of the first conductive vias are correspondingly disposed under each of the first metal blocks, a plurality of the second conductive vias are correspondingly disposed under each of the second metal blocks, and a plurality of the third conductive vias are correspondingly disposed under each of the gate metal blocks; A fourth dielectric layer covering the second metal layer is formed, and the fourth dielectric layer is patterned to obtain at least one first pad hole exposing the first metal block, at least one second pad hole exposing the second metal block, and at least one third pad hole exposing the gate metal block.

8. The method for manufacturing a GaN-based HEMT device structure according to claim 7, characterized in that: The first metal blocks and the second metal blocks are alternately arranged one or more times in the second direction.

9. The method for manufacturing a GaN-based HEMT device structure according to claim 7, characterized in that: At least one second gate block is extended from the gate metal line toward one side of the first metal line or the second metal line, a plurality of the third conductive through holes are arranged on the second gate block, and the gate metal block covers the second gate block.

10. The method for manufacturing a GaN-based HEMT device structure according to claim 7, characterized in that: An opening area of ​​the first pad hole, an opening area of ​​the second pad hole, and an opening area of ​​the third pad hole are all larger than an area surrounded by the hexagonal gate ring.

11. A GaN-based HEMT device structure, characterized in that: include: A substrate, wherein a GaN-AlGaN heterojunction layer is provided in the substrate; a gate pattern layer, located on the substrate, the gate pattern layer comprising a gate ring array and a gate line group, the gate ring array comprising a plurality of hexagonal gate rings arranged in a hexagonal array, the gate line group comprising a gate main line extending along a first direction and a plurality of gate sub-lines arranged in parallel and extending in a second direction, the first direction and the second direction are both parallel to the plane where the substrate is located, and the first direction and the second direction intersect each other, the gate ring array and the plurality of gate sub-lines are located on the same side of the gate main line, the plurality of hexagonal gate rings are divided into a plurality of parallel gate ring groups, each of the gate ring groups comprises a plurality of hexagonal gate rings arranged sequentially and at intervals along the second direction, a plurality of gate sub-lines are connected to the plurality of gate ring groups in a one-to-one correspondence, wherein each of the gate sub-lines comprises a plurality of gate sub-line units arranged discontinuously, any two adjacent hexagonal gate rings in the gate ring group are connected by a gate sub-line unit, and a hexagonal gate ring in the gate ring group closest to the gate main line is connected to the gate main line by a gate sub-line unit; A first dielectric layer covering the gate pattern layer; A source-drain electrode graphic layer is located on the first dielectric layer and includes a plurality of hexagonal electrode plates arranged in a hexagonal array and a plurality of hexagonal electrode rings arranged in a hexagonal array, wherein one of the hexagonal electrode plates and the hexagonal electrode ring serves as a source, and the other serves as a drain, and a vertical projection of each of the hexagonal electrode plates on the plane where the gate graphic layer is located is correspondingly arranged at the center of a hexagonal gate ring, and a vertical projection of each of the hexagonal electrode rings on the plane where the gate graphic layer is located is correspondingly arranged around a hexagonal gate ring, and any two adjacent hexagonal electrode rings share a side edge, and a vertical projection of the hexagonal electrode ring on the plane where the gate graphic layer is located has a gap on the passing path of the gate sub-line unit.

12. The GaN-based HEMT device structure according to claim 11, characterized in that: The width of the notch is greater than the width of the gate sub-line unit.

13. The GaN-based HEMT device structure according to claim 11, characterized in that: The first direction and the second direction are perpendicular to each other, or the first direction and the second direction are 60 degrees apart.

14. The GaN-based HEMT device structure according to claim 11, characterized in that: The GaN-based HEMT device structure further includes: A second dielectric layer covering the source and drain electrode pattern layer; A plurality of first contact portions, a plurality of second contact portions and a plurality of third contact portions penetrating the second dielectric layer, a plurality of the first contact portions being correspondingly provided on each of the hexagonal electrode plates, a plurality of the second contact portions being correspondingly provided on each of the hexagonal electrode rings, and a plurality of the third contact portions being correspondingly provided on the gate main line; A first metal layer is located on the second dielectric layer and includes a plurality of first metal wires extending along the second direction, a plurality of second metal wires extending along the second direction, and a gate metal wire extending along the first direction. The plurality of first metal wires and the plurality of second metal wires are alternately arranged in an ABAB manner. A plurality of first contact portions are correspondingly arranged under each of the first metal lines, a plurality of second contact portions are correspondingly arranged under each of the second metal lines, and a plurality of third contact portions are correspondingly arranged under the gate metal lines.

15. The GaN-based HEMT device structure according to claim 14, characterized in that: The gate main line extends toward one side of the gate ring array to form at least one first gate block, and a plurality of the third contact portions are arranged on the first gate block.

16. The GaN-based HEMT device structure according to claim 14, characterized in that: The width of the first metal line and the width of the second metal line are both greater than the width of the gate sub-line, and the width of the gate metal line is greater than the width of the gate main line.

17. The GaN-based HEMT device structure according to any one of claims 14 to 16, characterized in that: The GaN-based HEMT device structure further includes: a third dielectric layer covering the first metal layer; A plurality of first conductive vias, a plurality of second conductive vias and a plurality of third conductive vias penetrating the third dielectric layer, a plurality of the first conductive vias being correspondingly provided on each of the first metal lines, a plurality of the second conductive vias being correspondingly provided on each of the second metal lines, and a plurality of the third conductive vias being correspondingly provided on the gate metal line; A second metal layer is located on the third dielectric layer and includes at least one first metal block, at least one second metal block and at least one gate metal block, wherein a plurality of the first conductive vias are correspondingly provided under each of the first metal blocks, a plurality of the second conductive vias are correspondingly provided under each of the second metal blocks, and a plurality of the third conductive vias are correspondingly provided under each of the gate metal blocks; a fourth dielectric layer, covering the second metal layer, At least one first pad hole, at least one second pad hole and at least one third pad hole penetrate the fourth dielectric layer, the first pad hole exposes the first metal block, the second pad hole exposes the second metal block, and the third pad hole exposes the gate metal block.

18. The GaN-based HEMT device structure according to claim 17, characterized in that: The first metal blocks and the second metal blocks are alternately arranged one or more times in the second direction.

19. The GaN-based HEMT device structure according to claim 17, characterized in that: At least one second gate block is extended from the gate metal line toward one side of the first metal line or the second metal line, a plurality of the third conductive through holes are arranged on the second gate block, and the gate metal block covers the second gate block.

20. The GaN-based HEMT device structure according to claim 17, characterized in that: An opening area of ​​the first pad hole, an opening area of ​​the second pad hole, and an opening area of ​​the third pad hole are all larger than an area surrounded by the hexagonal gate ring.

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