GaN-based enhanced field effect transistor realized by argon ion implantation and manufacturing method thereof

Abstract

The invention discloses a GaN-based enhanced field effect transistor realized by argon ion implantation and a manufacturing method of the GaN-based enhanced field effect transistor. The manufacturing method of the GaN-based enhanced field effect transistor comprises the following steps: selecting proper injection energy and injection dosage, injecting a barrier layer under a gate without influencing other positions, ensuring that injection occurs on the barrier layer without damaging a GaN channel layer, enabling a part of the barrier layer to be polycrystallized and non-shaped through an injection damage mode, destroying the orderliness of crystals, and improving the reliability of the GaN-based enhanced field effect transistor. And the spontaneous polarization and piezoelectric polarization of the damaged part are reduced or eliminated, so that the two-dimensional electron gas does not exist in the channel layer under the gate, thereby forming the enhanced device, and the enhanced device is simple in structure and easy in manufacturing process, and has important practical value and wide market prospect.

Description

Technical Field

[0001] The present invention particularly relates to a GaN-based enhanced field effect transistor obtained by a low-energy ion shallow implantation method and a manufacturing method thereof, belonging to the technical field of semiconductors. Background Art

[0002] The working principle of GaN-based HEMT devices is that due to the spontaneous polarization and piezoelectric polarization of III-V nitride materials, a two-dimensional electron gas is formed at the interface of the heterostructure, which has an extremely high electron concentration (up to 10 13 / cm 2 ), the electron concentration can be controlled by gate voltage, thereby achieving control of current and forming a field effect transistor. The presence of two-dimensional electron gas makes the conventional GaN-based heterostructure HEMT a normally-on (depletion-type) field effect transistor. In actual operation, this transistor requires a negative voltage power supply to turn it off, which has a failure safety problem; in addition, the need for unipolar power supply in the application of RF microwaves and the need for integration of enhancement and depletion devices in digital logic circuits urgently require the successful development of enhancement devices, which is also one of the technical problems that need to be solved urgently. Summary of the invention

[0003] The main purpose of the present invention is to provide a GaN-based enhancement mode field effect transistor implemented by argon ion implantation and a manufacturing method thereof, thereby overcoming the deficiencies in the prior art.

[0004] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention includes: A first aspect of an embodiment of the present invention provides a GaN-based enhancement mode field effect transistor, comprising an epitaxial structure and a source, a drain and a gate matched with the epitaxial structure, wherein the gate is arranged between the source and the drain, The epitaxial structure includes a channel layer, a barrier layer and an ion implantation region, wherein the barrier layer is stacked on the channel layer, a two-dimensional electron gas is present at an interface between the channel layer and the barrier layer, the source electrode and the drain electrode are electrically connected to the two-dimensional electron gas, the ion implantation region is located in the barrier layer in the region under the gate, and the two-dimensional electron gas in the region under the gate is depleted by the ion implantation region, wherein the ion implantation region is formed by injecting argon ions into the barrier layer in the region under the gate, and the barrier layer material in the region under the gate is converted from a single crystal to a polycrystalline.

[0005] A second aspect of an embodiment of the present invention provides a method for manufacturing a GaN-based enhancement mode field effect transistor, comprising the steps of manufacturing an epitaxial structure and manufacturing a source, a drain and a gate matching the epitaxial structure, wherein the gate is arranged between the source and the drain, wherein the step of manufacturing the epitaxial structure comprises: Manufacturing a heterojunction, wherein the heterojunction includes a stacked channel layer and a barrier layer, wherein a two-dimensional electron gas is present at an interface between the channel layer and the barrier layer, and the source electrode and the drain electrode are electrically connected to the two-dimensional electron gas; Argon ions are injected into the barrier layer in the area below the gate, and the barrier layer material in the area below the gate is converted from single crystal to polycrystalline, thereby forming an ion implantation area, and the two-dimensional electron gas below the ion implantation area is depleted.

[0006] Compared with the prior art, the advantages of the present invention include: the present invention utilizes a method of shallow low-energy argon ion implantation, selects appropriate implantation energy, and implants into the barrier layer under the gate without affecting other positions, thereby ensuring that the implantation occurs in the barrier layer without damaging the GaN channel layer, and partially polycrystallizes and amorphizes the barrier layer by way of implantation damage, destroying the orderliness of the crystal, reducing or eliminating the spontaneous polarization and piezoelectric polarization of the damaged portion, so that no two-dimensional electron gas exists in the channel layer under the gate, thereby forming an enhanced device.

[0007] Compared with fluorine ion implantation, which generates a negative electric field due to its negative charge, leading to the improvement of the energy band to achieve enhancement mode, argon ions, due to their inert stability, simply convert the barrier layer single crystal into polycrystalline, thereby weakening the polarization. The argon ions used in the present invention are relatively large and shallowly implanted, and are less likely to damage the channel. In addition, argon ion implantation to achieve enhancement mode of GaN-based field effect transistors solves the failure safety problem of normally-on transistors, the problem of unipolar power supply in applications in the field of radio frequency microwaves, and the integration problem of enhancement and depletion devices in digital logic circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a structural schematic diagram of a GaN-based enhancement mode field effect transistor without forming an isolation structure provided in a typical implementation case of the present invention; Figure 2 It is a schematic structural diagram of a GaN-based enhancement mode field effect transistor after forming an isolation structure in a typical implementation case of the present invention; Figure 3 It is a structural schematic diagram of another GaN-based enhancement mode field effect transistor provided in a typical implementation case of the present invention without forming an isolation structure; Figure 4 It is a schematic structural diagram of another GaN-based enhancement mode field effect transistor provided in a typical implementation case of the present invention after forming an isolation structure; Figure 5 2 are transfer characteristic curves of different GaN-based field effect transistors obtained in the embodiments and comparative examples. DETAILED DESCRIPTION

[0009] In view of the deficiencies in the prior art, the inventor of this case has proposed the technical solution of the present invention after long-term research and extensive practice. The technical solution, its implementation process and principle will be further explained as follows.

[0010] A first aspect of an embodiment of the present invention provides a GaN-based enhancement mode field effect transistor, including an epitaxial structure and a source, a drain and a gate matching the epitaxial structure, wherein the gate is arranged between the source and the drain.

[0011] The epitaxial structure includes a channel layer, a barrier layer and an ion implantation region, wherein the barrier layer is stacked on the channel layer, a two-dimensional electron gas is present at an interface between the channel layer and the barrier layer, the source electrode and the drain electrode are electrically connected to the two-dimensional electron gas, the ion implantation region is located in the barrier layer in the region under the gate, and the two-dimensional electron gas in the region under the gate is depleted by the ion implantation region, wherein the ion implantation region is formed by injecting argon ions into the barrier layer in the region under the gate, and the barrier layer material in the region under the gate is converted from a single crystal to a polycrystalline.

[0012] Furthermore, the implantation energy of the argon ions in the ion implantation region is 10keV-30keV.

[0013] Furthermore, the epitaxial structure further includes an insulating dielectric layer, the insulating dielectric layer is arranged on the barrier layer, and the gate is arranged on the insulating dielectric layer.

[0014] Furthermore, the material of the insulating dielectric layer includes SiN, but is not limited thereto.

[0015] Furthermore, the material of the channel layer includes GaN, but is not limited thereto.

[0016] Furthermore, the thickness of the channel layer is 100nm-300nm.

[0017] Furthermore, the material of the barrier layer includes AlGaN, AlInN, AlInGaN, AlGaN / AlN, AlInN / AlN or AlInGaN / AlN, but is not limited thereto.

[0018] Furthermore, the thickness of the barrier layer is 10nm-50nm.

[0019] Furthermore, the material of the source and drain can be a combination of one or more of titanium, aluminum, nickel, gold, and platinum, but not limited thereto, and the material of the gate includes a combination of one or more of nickel, gold, platinum, and palladium, but not limited thereto.

[0020] A second aspect of an embodiment of the present invention provides a method for manufacturing a GaN-based enhancement mode field effect transistor, comprising the steps of manufacturing an epitaxial structure and manufacturing a source, a drain and a gate matching the epitaxial structure, wherein the gate is arranged between the source and the drain, wherein the step of manufacturing the epitaxial structure comprises: Manufacturing a heterojunction, wherein the heterojunction includes a stacked channel layer and a barrier layer, wherein a two-dimensional electron gas is present at an interface between the channel layer and the barrier layer, and the source electrode and the drain electrode are electrically connected to the two-dimensional electron gas; Argon ions are injected into the barrier layer in the area below the gate, and the barrier layer material in the area below the gate is converted from single crystal to polycrystalline, thereby forming an ion implantation area, and the two-dimensional electron gas below the ion implantation area is depleted.

[0021] Furthermore, the argon ion implantation energy in the ion implantation region is 10keV-30keV.

[0022] Furthermore, the step of making the epitaxial structure includes: injecting argon ions into the barrier layer by ion implantation or plasma treatment, the ion implantation energy is 10keV-30keV, the dose is 1e13-1e14, and the ion implantation process also includes a thermal annealing process, the annealing atmosphere is N2, the annealing temperature is 400℃-450℃, and the annealing time is 10min-15min.

[0023] Furthermore, the manufacturing method of the GaN-based enhancement mode field effect transistor further includes: forming an insulating dielectric layer in the non-ohmic region of the barrier layer, and the gate is disposed on the insulating dielectric layer. Furthermore, the insulating dielectric layer can be formed by low pressure chemical vapor deposition (LPCVD), magnetron sputtering, plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD).

[0024] Furthermore, the material of the insulating dielectric layer includes SiN, but is not limited thereto.

[0025] Furthermore, the material of the channel layer includes GaN, but is not limited thereto.

[0026] Furthermore, the thickness of the channel layer is 100nm-300nm.

[0027] Furthermore, the material of the barrier layer includes AlGaN, AlInN, AlInGaN, AlGaN / AlN, AlInN / AlN or AlInGaN / AlN, but is not limited thereto.

[0028] Furthermore, the thickness of the barrier layer is 10nm-50nm.

[0029] Furthermore, the channel layer is stacked on the buffer layer, and the buffer layer is stacked on the substrate.

[0030] Furthermore, the material of the buffer layer includes GaN, but is not limited thereto.

[0031] Furthermore, the thickness of the buffer layer is 1 μm-4 μm.

[0032] Furthermore, the material of the substrate includes GaN, sapphire, Si or silicon carbide, but is not limited thereto.

[0033] Furthermore, the material of the source and drain can be a combination of one or more of titanium, aluminum, nickel, gold, and platinum, but not limited thereto, and the material of the gate includes a combination of one or more of nickel, gold, platinum, and palladium, but not limited thereto.

[0034] The technical solution, its implementation process and principles, etc. will be further explained below in conjunction with the accompanying drawings and specific implementation cases. Unless otherwise specified, the semiconductor epitaxial equipment and processes, metal deposition equipment and processes, device isolation processes, annealing equipment and processes, etc. used in the embodiments of the present invention are all known to those skilled in the art.

[0035] In a more specific implementation case, please refer to Figure 1-Figure 4 A GaN-based enhancement field effect transistor includes an epitaxial structure and a source, a drain and a gate matched with the epitaxial structure, the epitaxial structure includes a substrate, a buffer layer, a channel layer, a barrier layer, and an insulating dielectric layer (i.e., an insulating layer) stacked in sequence from bottom to top, a two-dimensional electron gas is provided at the interface between the channel layer and the barrier layer, the source and the drain are arranged on the barrier layer and are electrically connected to the two-dimensional electron gas, the gate is located between the source and the drain and is arranged on the insulating dielectric layer, and the epitaxial structure also has an ion implantation region in the region under the gate, and the two-dimensional electron gas below the ion implantation region is depleted.

[0036] Specifically, the ion implantation region can be formed only in the barrier layer in the region below the gate. The ion implantation region is formed by implanting argon ions into the barrier layer in the region below the gate, and the barrier layer material in the region below the gate is converted from single crystal to polycrystalline. Figure 1 , Figure 2 The ion implantation region can also be formed in the insulating dielectric layer and the barrier layer in the region below the gate. The ion implantation region is formed by implanting argon ions into the insulating dielectric layer and the barrier layer in the region below the gate, and the barrier layer material in the region below the gate is converted from single crystal to polycrystalline, as shown in FIG. Figure 3 , Figure 4 shown.

[0037] Specifically, the material of the substrate includes GaN, sapphire, Si or silicon carbide, the material of the buffer layer includes GaN, the thickness of the buffer layer is 1μm-4μm, the material of the channel layer includes GaN, the thickness of the channel layer is 100nm-300nm, the material of the barrier layer includes AlGaN, AlInN, AlInGaN, AlGaN / AlN, AlInN / AlN or AlInGaN / AlN, the thickness of the barrier layer is 10nm-50nm. The material of the insulating dielectric layer includes SiN Specifically, the material of the source and drain can be a combination of one or more of titanium, aluminum, nickel, gold, and platinum, but not limited thereto. The material of the gate includes a combination of one or more of nickel, gold, platinum, and palladium, but not limited thereto.

[0038] Example 1 A method for manufacturing a GaN-based enhancement mode field effect transistor comprises the following steps: 1) A 3.5μm GaN buffer layer, a 200nm GaN channel layer, and a 25nm AlGaN barrier layer are grown sequentially on a GaN substrate to form the epitaxial structure of a GaN-based HEMT device.

[0039] 2) Photolithography is used to protect the device surface, and then etching is used to achieve isolation between devices.

[0040] 3) Photolithography is performed to pattern the gate and ion implantation is performed into the barrier layer. The implantation energy range is 10keV-30keV and the implanted ions are argon ions. In this step, the energy and dose of the ion implantation are changed to regulate the implantation concentration and damage degree of the ions so that the damage occurs only in the barrier layer and no two-dimensional electron gas exists in the channel layer under the gate, thereby realizing an enhanced device.

[0041] 4) A SiN insulating dielectric layer with a thickness of 10 nm is deposited on the AlGaN barrier layer.

[0042] 5) Photolithography of the source and drain patterns is performed on the SiN insulating dielectric layer, and then the SiN insulating dielectric layer located in the source and drain regions is etched by dry etching to open holes for the source and drain.

[0043] 6) 20nm titanium / 130nm aluminum / 50nm nickel / 50nm gold were deposited as source and drain electrodes in the source and drain regions of the AlGaN barrier layer by electron beam evaporation, and then heated at 875℃, N 2 The ohmic contact was formed by rapid thermal annealing for 30 seconds under atmosphere.

[0044] 7) Photolithography of the gate pattern is performed, and 50nm nickel / 100nm gold is deposited on the SiN insulating dielectric layer by electron beam evaporation as the gate. The length of the gate is greater than the length of the ion implantation area; 8) At 450℃, N 2 Rapid thermal annealing was performed under atmosphere for 10 min.

[0045] Example 2 A method for manufacturing a GaN-based enhancement mode field effect transistor comprises the following steps: 1) A 3.5μm GaN buffer layer, a 200nm GaN channel layer, and a 25nm AlGaN barrier layer are grown sequentially on a GaN substrate to form the epitaxial structure of a GaN-based HEMT device.

[0046] 2) Photolithography is used to protect the device table, and then ion implantation is used to achieve isolation between devices.

[0047] 3) Photolithography is performed to pattern the gate and ion implantation is performed into the barrier layer. The implantation energy range is 10keV-30keV and the implanted ions are argon ions. In this step, the energy and dose of the ion implantation are changed to regulate the implantation concentration and damage degree of the ions so that the damage occurs only in the barrier layer and no two-dimensional electron gas exists in the channel layer under the gate, thereby realizing an enhanced device.

[0048] 4) A SiN insulating dielectric layer with a thickness of 10 nm is deposited on the AlGaN barrier layer by LPCVD.

[0049] 5) Photolithography of the source and drain patterns is performed on the SiN insulating dielectric layer, and then the SiN insulating dielectric layer located in the source and drain regions is etched by dry etching to open holes for the source and drain.

[0050] 6) 20nm titanium / 130nm aluminum / 50nm nickel / 50nm gold were deposited as source and drain electrodes in the source and drain regions of the AlGaN barrier layer by electron beam evaporation, and then heated at 875℃, N 2 The ohmic contact was formed by rapid thermal annealing for 30 seconds under atmosphere.

[0051] 7) Photolithography of the gate pattern is performed, and 50nm nickel / 100nm gold is deposited on the SiN insulating dielectric layer by electron beam evaporation as the gate. The length of the gate is greater than the length of the ion implantation area; 8) At 450℃, N 2 Rapid thermal annealing was performed under atmosphere for 10 min.

[0052] Example 3 A method for manufacturing a GaN-based enhancement mode field effect transistor comprises the following steps: 1) A 3.5μm GaN buffer layer, a 200nm GaN channel layer, and a 25nm AlGaN barrier layer are grown sequentially on a GaN substrate to form the epitaxial structure of a GaN-based HEMT device.

[0053] 2) A SiN insulating dielectric layer with a thickness of 10 nm is deposited on the AlGaN barrier layer.

[0054] 3) Photolithography is used to protect the device surface, and then etching is used to achieve isolation between devices.

[0055] 4) Photolithography of the source and drain patterns is performed on the SiN insulating dielectric layer, and then the SiN insulating dielectric layer located in the source and drain regions is etched by dry etching to open holes for the source and drain electrodes.

[0056] 5) 20nm titanium / 130nm aluminum / 50nm nickel / 50nm gold were deposited as the source and drain regions of the AlGaN barrier layer by electron beam evaporation, and then heated at 875℃, N 2 The ohmic contact was formed by rapid thermal annealing for 30 seconds under atmosphere.

[0057] 6) Photolithography is performed to pattern the gate and ion implantation is performed into the barrier layer. The implantation energy range is 10keV-30keV and the implanted ions are argon ions. In this step, the energy and dose of the ion implantation are changed to regulate the implantation concentration and damage degree of the ions so that the damage occurs only in the barrier layer and no two-dimensional electron gas exists in the channel layer under the gate, thereby realizing an enhanced device.

[0058] 7) Deposit 50nm nickel / 100nm gold as gate on the SiN insulating dielectric layer by electron beam evaporation 8) At 450℃, N 2 Rapid thermal annealing was performed in a gas atmosphere for 10 min.

[0059] Example 4 A method for manufacturing a GaN-based enhancement mode field effect transistor comprises the following steps: 1) A 3.5μm GaN buffer layer, a 200nm GaN channel layer, and a 25nm AlGaN barrier layer are grown sequentially on a GaN substrate to form the epitaxial structure of a GaN-based HEMT device.

[0060] 2) Photolithography is used to protect the device table, and then ion implantation is used to achieve isolation between devices.

[0061] 3) A SiN insulating dielectric layer with a thickness of 10 nm is deposited on the AlGaN barrier layer.

[0062] 4) Photolithography of the source and drain patterns is performed on the SiN insulating dielectric layer, and then the SiN insulating dielectric layer located in the source and drain regions is etched by dry etching to open holes for the source and drain electrodes.

[0063] 5) 20nm titanium / 130nm aluminum / 50nm nickel / 50nm gold were deposited as the source and drain regions of the AlGaN barrier layer by electron beam evaporation, and then heated at 875℃, N 2 The ohmic contact was formed by rapid thermal annealing for 30 seconds under atmosphere.

[0064] 6) Photolithography is performed to pattern the gate and ion implantation is performed into the barrier layer. The implantation energy range is 10keV-30keV and the implanted ions are argon ions. In this step, the energy and dose of the ion implantation are changed to regulate the implantation concentration and damage degree of the ions so that the damage occurs only in the barrier layer and no two-dimensional electron gas exists in the channel layer under the gate, thereby realizing an enhanced device.

[0065] 7) Deposit 50nm nickel / 100nm gold as the gate on the SiN insulating dielectric layer by electron beam evaporation.

[0066] 8) At 450℃, N 2 Rapid thermal annealing was performed in a gas atmosphere for 10 min.

[0067] Comparative Example 1 A method for manufacturing a GaN-based enhancement mode field effect transistor comprises the following steps: 1) A 3.5μm GaN buffer layer, a 200nm GaN channel layer, and a 25nm AlGaN barrier layer are grown sequentially on a GaN substrate to form the epitaxial structure of a GaN-based HEMT device.

[0068] 2) Photolithography is used to protect the device table, and then ion implantation is used to achieve isolation between devices.

[0069] 3) A SiN insulating dielectric layer with a thickness of 10 nm is deposited on the AlGaN barrier layer.

[0070] 4) Photolithography of the source and drain patterns is performed on the SiN insulating dielectric layer, and then the SiN insulating dielectric layer located in the source and drain regions is etched by dry etching to open holes for the source and drain electrodes.

[0071] 5) 20nm titanium / 130nm aluminum / 50nm nickel / 50nm gold were deposited as the source and drain regions of the AlGaN barrier layer by electron beam evaporation, and then heated at 875℃, N 2 The ohmic contact was formed by rapid thermal annealing for 30 seconds under atmosphere.

[0072] 6) Photolithography of the gate pattern is performed without performing ion implantation under the gate. 50nm nickel / 100nm gold is directly deposited on the SiN insulating dielectric layer by electron beam evaporation as the gate; Comparative Example 2 A method for manufacturing a GaN-based enhancement mode field effect transistor comprises the following steps: 1) A 3.5μm GaN buffer layer, a 200nm GaN channel layer, and a 25nm AlGaN barrier layer are grown sequentially on a GaN substrate to form the epitaxial structure of a GaN-based HEMT device.

[0073] 2) Photolithography is used to protect the device table, and then ion implantation is used to achieve isolation between devices.

[0074] 3) A SiN insulating dielectric layer with a thickness of 10 nm is deposited on the AlGaN barrier layer.

[0075] 4) Photolithography of the source and drain patterns is performed on the SiN insulating dielectric layer, and then the SiN insulating dielectric layer located in the source and drain regions is etched by dry etching to open holes for the source and drain electrodes.

[0076] 5) 20nm titanium / 130nm aluminum / 50nm nickel / 50nm gold were deposited as the source and drain regions of the AlGaN barrier layer by electron beam evaporation, and then heated at 875℃, N 2 The ohmic contact was formed by rapid thermal annealing for 30 seconds under atmosphere.

[0077] 6) Photolithography is performed to pattern the gate, and ion implantation is performed on the AlGaN barrier layer under the gate using ion implantation equipment. The implanted ions are argon ions, the implantation energy is 15keV, and the implantation dose is 5e13.

[0078] 7) Deposit 50nm nickel / 100nm gold as the gate on the SiN insulating dielectric layer by electron beam evaporation.

[0079] 8) At 450℃, N 2 Rapid thermal annealing was performed under atmosphere for 10 min.

[0080] Comparative Example 3 A method for manufacturing a GaN-based enhancement mode field effect transistor comprises the following steps: 1) A 3.5μm GaN buffer layer, a 200nm GaN channel layer, and a 25nm AlGaN barrier layer are grown sequentially on a GaN substrate to form the epitaxial structure of a GaN-based HEMT device.

[0081] 2) Photolithography is used to protect the device table, and then ion implantation is used to achieve isolation between devices.

[0082] 3) A SiN insulating dielectric layer with a thickness of 10 nm is deposited on the AlGaN barrier layer.

[0083] 4) Photolithography of the source and drain patterns is performed on the SiN insulating dielectric layer, and then the SiN insulating dielectric layer located in the source and drain regions is etched by dry etching to open holes for the source and drain electrodes.

[0084] 5) 20nm titanium / 130nm aluminum / 50nm nickel / 50nm gold were deposited as the source and drain regions of the AlGaN barrier layer by electron beam evaporation, and then rapid thermal annealing was performed at 875°C in a N2 atmosphere for 30 seconds to form an ohmic contact.

[0085] 6) The gate pattern is photolithographically produced, and ion implantation is performed on the AlGaN barrier layer in the area below the gate using ion implantation equipment. The implanted ions are argon ions, the implantation energy is 20keV, and the implantation dose is 3e13.

[0086] 7) Deposit 50nm nickel / 100nm gold as the gate on the SiN insulating dielectric layer by electron beam evaporation.

[0087] 8) Rapid thermal annealing at 450°C in N2 atmosphere for 10 minutes.

[0088] Figure 5 1 is the transfer characteristic curve of the GaN-based field effect transistor obtained under different injection conditions in Example 4, Comparative Example 1, Comparative Example 2 and Comparative Example 3 of the present invention. Figure 5 It can be seen that compared with conventional devices without ion implantation, the threshold voltage of the device with argon ion implantation is greatly improved. Under the same device size, the threshold voltage of the GaN-based HEMT device in Comparative Example 1 is about -6V (taken at Id=10μA / mm), while the threshold voltage of the devices in Comparative Examples 2 and 3 is greatly improved. In combination with argon ion implantation, the device threshold can be further improved by growing a low-component thick barrier layer.

[0089] Compared with Example 1 and Example 2, since Example 3 and Example 4 place the argon ion implantation under the gate after the growth of the insulating dielectric layer, the insulating dielectric layer can be used as an energy absorption layer, which can reduce the damage caused by a part of the implantation process, so that the damage does not occur in the channel layer as much as possible. Moreover, Example 3 and Example 4 can be directly implanted after the gate lithography, and then the gate metal is evaporated, which reduces one lithography process and saves costs.

[0090] In the embodiment of the present invention, argon ions are selected as the implanted ions for forming the ion implantation region. Argon ions are inert elements and are more stable. Unlike fluorine ions, they will not affect the device material itself due to their negative charge. In addition, the present invention adjusts the implantation concentration and damage degree of the ions by changing the energy, dosage and heat treatment conditions of the ion implantation, so that the damage only occurs in the barrier layer and no two-dimensional electron gas exists in the channel layer under the gate, thereby realizing an enhanced device.

[0091] The present invention utilizes a method of shallow low-energy ion implantation of argon ions to implant the barrier layer under the gate without affecting other regions, thereby ensuring that the implanted argon ions are in the barrier layer without damaging the channel layer, and partially making the barrier layer polycrystalline and amorphous by way of implantation damage, thereby destroying the orderliness of the crystal, reducing or eliminating the spontaneous polarization and piezoelectric polarization of the damaged portion, thereby eliminating the two-dimensional electron gas in the channel layer under the gate, thereby forming an enhanced device, solving the failure safety problem of normally-on transistors, the unipolar power supply problem in applications in the field of radio frequency microwaves, and the integration problem of enhanced and depletion devices in digital logic circuits.

[0092] It should be understood that the above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A GaN-based enhancement mode field effect transistor realized by argon ion implantation, comprising an epitaxial structure and a source, a drain and a gate matched with the epitaxial structure, wherein the gate is arranged between the source and the drain, characterized in that: The epitaxial structure includes a channel layer, a barrier layer and an ion implantation region, wherein the barrier layer is stacked on the channel layer, a two-dimensional electron gas is present at an interface between the channel layer and the barrier layer, the source electrode and the drain electrode are electrically connected to the two-dimensional electron gas, the ion implantation region is located in the barrier layer in the region under the gate, and the two-dimensional electron gas in the region under the gate is depleted by the ion implantation region, wherein the ion implantation region is formed by injecting argon ions into the barrier layer in the region under the gate, and the barrier layer material in the region under the gate is converted from a single crystal to a polycrystalline.

2. The GaN-based enhancement mode field effect transistor realized by argon ion implantation according to claim 1, characterized in that: The implantation energy of the argon ions in the ion implantation region is 10keV-30keV.

3. The GaN-based enhancement mode field effect transistor realized by argon ion implantation according to claim 1, characterized in that: The epitaxial structure further comprises an insulating dielectric layer, wherein the insulating dielectric layer is arranged on the barrier layer, and the gate is arranged on the insulating dielectric layer; Preferably, the material of the insulating dielectric layer includes SiN.

4. The GaN-based enhancement mode field effect transistor realized by argon ion implantation according to claim 1, characterized in that: The material of the channel layer includes GaN; preferably, the thickness of the channel layer is 100nm-300nm; And / or, the material of the barrier layer includes AlGaN, AlInN, AlInGaN, AlGaN / AlN, AlInN / AlN or AlInGaN / AlN; preferably, the thickness of the barrier layer is 10nm-50nm.

5. A method for manufacturing a GaN-based enhancement mode field effect transistor by argon ion implantation, comprising the steps of making an epitaxial structure and making a source, a drain and a gate matching the epitaxial structure, wherein the gate is arranged between the source and the drain, and characterized in that: The steps to make the epitaxial structure include: Manufacturing a heterojunction, wherein the heterojunction includes a stacked channel layer and a barrier layer, wherein a two-dimensional electron gas is present at an interface between the channel layer and the barrier layer, and the source electrode and the drain electrode are electrically connected to the two-dimensional electron gas; Argon ions are injected into the barrier layer in the area below the gate, and the barrier layer material in the area below the gate is converted from single crystal to polycrystalline, thereby forming an ion implantation area, and the two-dimensional electron gas below the ion implantation area is depleted.

6. The method for manufacturing a GaN-based enhancement mode field effect transistor by argon ion implantation according to claim 5, characterized in that: The concentration of argon ions in the ion implantation region is 1e13-1e14.

7. The method for manufacturing a GaN-based enhancement mode field effect transistor by argon ion implantation according to claim 5 or 6, characterized in that: include: Argon ions are injected into the barrier layer by ion implantation or plasma treatment. The energy of the ion implantation is 10keV-30keV and the dose is 1e13-1e14. The ion implantation process also includes a thermal annealing process. The annealing atmosphere is N2, the annealing temperature is 400℃-450℃, and the annealing time is 10min-15min.

8. The method for manufacturing a GaN-based enhancement mode field effect transistor by argon ion implantation according to claim 5, characterized in that: Also includes: forming an insulating dielectric layer in the non-ohmic region of the barrier layer, wherein the gate is disposed on the insulating dielectric layer; Preferably, the material of the insulating dielectric layer includes SiN.

9. The method for manufacturing a GaN-based enhancement mode field effect transistor by argon ion implantation according to claim 5, characterized in that: The material of the channel layer includes GaN; preferably, the thickness of the channel layer is 100nm-300nm; And / or, the material of the barrier layer includes AlGaN, AlInN, AlInGaN, AlGaN / AlN, AlInN / AlN or AlInGaN / AlN; preferably, the thickness of the barrier layer is 10nm-50nm.

10. The method for manufacturing a GaN-based enhancement mode field effect transistor by argon ion implantation according to claim 5, characterized in that: The channel layer is stacked on the buffer layer, and the buffer layer is stacked on the substrate; Preferably, the material of the buffer layer includes GaN; Preferably, the thickness of the buffer layer is 1 μm-4 μm; Preferably, the material of the substrate includes GaN, sapphire, Si or silicon carbide.

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