Semiconductor device and method for manufacturing the same

Abstract

The present application belongs to the field of semiconductor technology, and provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises a substrate, a buffer layer, a high resistance layer, a channel layer, a barrier layer and a gate cap layer stacked in sequence, as well as a gate electrode, a source electrode and a drain electrode, wherein the source electrode and the drain electrode are located on both sides of the gate electrode, the gate electrode is formed on the gate cap layer, the source electrode penetrates the barrier layer and contacts the channel layer, the drain electrode penetrates the barrier layer and the channel layer, and contacts the channel layer and the high resistance layer, when the semiconductor device is in a high voltage off state, a forward voltage is applied to the drain electrode, and a large number of holes can be injected into the buffer layer, effectively reducing the electron traps near the drain region in the off state, and reducing the dynamic on-resistance of the device. The manufacturing method of the semiconductor device provided in the present application is used to prepare the above-mentioned semiconductor device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Gallium nitride high electron mobility transistor (GaN HEMT) devices have excellent electron mobility and high critical breakdown electric field. Compared with silicon power devices, they have excellent characteristics such as high breakdown field strength, low on-resistance, and fast electron saturation drift speed, making them widely used in communications, automobiles, radars, power grid transmission, and aerospace. However, in practical applications, GaN power devices face the problem of dynamic on-resistance, that is, during the switching process, the on-resistance of the device will increase over time. This increased dynamic resistance is mainly caused by charge capture and hot electron injection, which seriously affects the performance and reliability of the device, and brings challenges to the further promotion and use of GaN power devices.

[0003] To solve the above problems, researchers have conducted extensive research and proposed a variety of solutions to the problem of dynamic on-resistance of GaN devices, including optimizing device structure design, improving epitaxial growth process, and using new passivation materials. Although the above methods can improve the problem of dynamic on-resistance of devices to a certain extent and improve the performance and reliability of devices, the improvement effect on the dynamic on-resistance of GaN devices still cannot meet the demand, and the problem of dynamic on-resistance still needs to be further solved. Based on this, in order to solve the above problems, it is necessary to provide a new technical solution to reduce the dynamic on-resistance of semiconductor devices. Summary of the invention

[0004] In view of the shortcomings of the prior art described above, the purpose of the present application is to provide a semiconductor device and a method for manufacturing the same, so as to solve the problem of large dynamic on-resistance of semiconductor devices in the prior art, thereby effectively reducing the dynamic on-resistance of semiconductor devices, especially gallium nitride devices, and improving device performance.

[0005] In order to achieve the above-mentioned object and other related objects, the present application provides a semiconductor device, comprising:

[0006] substrate;

[0007] A buffer layer, a high resistance layer, a channel layer, a barrier layer and a gate cap layer are sequentially formed on the substrate;

[0008] A gate electrode formed on the gate cap layer;

[0009] A source electrode, penetrating the barrier layer and contacting the channel layer;

[0010] The drain electrode penetrates the barrier layer and the channel layer and contacts the channel layer and the high resistance layer. The source electrode and the drain electrode are located on both sides of the gate electrode and are spaced apart from the gate electrode.

[0011] Optionally, the source electrode includes an ohmic source, and the drain electrode includes an ohmic drain in contact with the channel layer and a Schottky drain in contact with the high resistance layer.

[0012] Optionally, the width of the drain electrode penetrating the barrier layer is greater than the width of the drain electrode penetrating the channel layer, and the side walls of the ohmic drain and the Schottky drain away from the gate electrode are flush with each other.

[0013] Optionally, the semiconductor device further includes:

[0014] a nucleation layer, located between the substrate and the buffer layer;

[0015] A dielectric layer is formed on the barrier layer, and the source electrode and the drain electrode are formed above the dielectric layer and penetrate the dielectric layer;

[0016] The isolation region is arranged around the periphery of the semiconductor device in a direction of looking down at the semiconductor device to isolate adjacent semiconductor devices.

[0017] The present application also provides a method for manufacturing a semiconductor device, which is used to prepare any of the semiconductor devices described in the aforementioned embodiments, comprising the following steps:

[0018] providing a substrate;

[0019] A buffer layer, a high resistance layer, a channel layer, a barrier layer and a gate cap layer are sequentially grown on the substrate;

[0020] forming a gate layer on the gate cap layer, and etching the gate layer and the gate cap layer to form a gate electrode;

[0021] Etching the barrier layer and the channel layer on one side of the gate electrode to form a third opening, wherein the third opening exposes the high resistance layer;

[0022] Etching the barrier layer on both sides of the gate electrode to form a first opening and a second opening exposing the channel layer on both sides of the gate electrode respectively;

[0023] A source electrode and a drain electrode are formed respectively, wherein the source electrode is filled in the first opening and connected to the channel layer, and the drain electrode is filled in the second opening and the third opening and connected to the channel layer and the high resistance layer.

[0024] Optionally, the method for manufacturing the semiconductor device further includes:

[0025] Before growing and forming the buffer layer, growing and forming a nucleation layer on the substrate;

[0026] After forming the gate electrode, a dielectric layer covering the gate electrode and the barrier layer is formed on the barrier layer.

[0027] Optionally, the second opening and the third opening penetrate each other, and a spacing distance between the first opening and the gate electrode is smaller than a spacing distance between the second opening and the gate electrode.

[0028] Optionally, the forming of the source electrode and the drain electrode respectively comprises the following steps:

[0029] Filling the first opening, the second opening and the third opening with metal material, and making the metal material extend to cover a portion of the dielectric layer around the first opening and the second opening;

[0030] Annealing treatment is performed so that the metal material in the first opening that contacts the channel layer forms the ohmic source of the source electrode, the metal material in the second opening that contacts the channel layer forms the ohmic drain of the drain electrode, and the metal material in the third opening that contacts the high resistance layer forms the Schottky drain of the drain electrode.

[0031] Optionally, after forming a dielectric layer covering the gate electrode and the barrier layer above the barrier layer, and before etching the barrier layer and the channel layer on one side of the gate electrode, it also includes: forming an isolation region at the periphery of the semiconductor device to isolate the semiconductor device.

[0032] Optionally, after forming the source electrode and the drain electrode respectively, the method further includes: etching the dielectric layer to form a fourth opening exposing the gate electrode.

[0033] As described above, compared with the prior art, the semiconductor device and the manufacturing method thereof provided by the present application have at least the following beneficial effects:

[0034] In the semiconductor device of the present application, the drain electrode includes an ohmic drain and a Schottky drain. The ohmic drain penetrates the barrier layer and forms an ohmic contact with the channel layer, and the Schottky drain penetrates the barrier layer and the channel layer and forms a Schottky contact with the high carbon-doped gallium nitride high resistance layer. When the semiconductor device is in a high-voltage off state, a forward voltage is applied to the drain electrode, and a large number of holes can be injected into the buffer layer through the drain electrode, effectively reducing the electron traps near the drain region when the device is off. By cooperating with the ohmic drain, the dynamic on-resistance of the device can be effectively reduced while taking into account the on-resistance of the semiconductor device, thereby improving the overall performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 Shown is a schematic diagram of the structure of a semiconductor device provided in Example 1 of the present application.

[0037] Figure 2 Shown is a schematic structural diagram of a semiconductor device provided as an optional embodiment in Embodiment 1 of the present application.

[0038] Figure 3 Shown is a schematic flow chart of a method for manufacturing a semiconductor device provided in the second embodiment of the present application.

[0039] Figure 4 Shown is a schematic diagram of the structure obtained after a nucleation layer, a buffer layer, a channel layer, a barrier layer and a gate cap layer are grown on a substrate according to an optional embodiment of the second embodiment of the present application.

[0040] Figure 5 Shown is a schematic diagram of the structure obtained after forming a gate electrode in the manufacturing method of the semiconductor device provided in the second embodiment of the present application.

[0041] Figure 6 Shown is a schematic diagram of the structure obtained after a dielectric layer is formed in the method for manufacturing a semiconductor device provided in the second embodiment of the present application.

[0042] Figure 7 Shown is a schematic diagram of the structure obtained after forming an isolation region in the manufacturing method of the semiconductor device provided in the second embodiment of the present application.

[0043] Figure 8 Shown is a schematic diagram of the structure obtained after the third opening is formed in the method for manufacturing the semiconductor device provided in the second embodiment of the present application.

[0044] Fig. 9 Shown is a schematic diagram of the structure obtained after forming the first opening and the second opening in the manufacturing method of the semiconductor device provided in the second embodiment of the present application.

[0045] Fig.10 Shown is a schematic diagram of the structure obtained after forming a source electrode and a drain electrode in the manufacturing method of the semiconductor device provided in the second embodiment of the present application.

[0046] Reference numerals:

[0047] 11. Substrate; 12. Nucleation layer; 13. Buffer layer; 14. High resistance layer; 15. Channel layer; 16. Barrier layer; 17. Gate cap layer; 18. Dielectric layer; 191. Gate electrode; 192. Source electrode; 1921. Ohmic source; 193. Drain electrode; 1931. Ohmic drain; 1932. Schottky drain; 101. First opening; 102. Second opening; 103. Third opening; 104. Fourth opening; 105. Isolation region. DETAILED DESCRIPTION

[0048] In order to make the technical purpose, technical solution and technical effect of the present application clearer, the technical solution in the present application will be clearly and completely described in conjunction with the embodiments below. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0049] Therefore, the following detailed description of the embodiments of the present application is not intended to limit the scope of the present application for protection, but merely represents the selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of the present application. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0050] In the description of the present application, it should be noted that the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "example", "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the implementation or example are included in at least one implementation or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more implementations or examples in a suitable manner.

[0051] Embodiment 1

[0052] This embodiment provides a semiconductor device for solving the problem of large dynamic on-resistance of semiconductor devices in the prior art. Optionally, the semiconductor device may be, for example, a gallium nitride power device or other suitable devices. Figure 1 The semiconductor device of this embodiment includes a substrate 11 and a buffer layer 13 , a high resistance layer 14 , a channel layer 15 , a barrier layer 16 and a gate cap layer 17 formed on the substrate 11 .

[0053] The material of the substrate 11 may include, but is not limited to, silicon, silicon germanium, silicon carbide, gallium arsenide, sapphire or other suitable materials. The buffer layer 13 is located on the substrate 11. The material of the buffer layer 13 may include, but is not limited to, nitrides or Ш-V group compounds. For example, the material of the buffer layer 13 includes gallium nitride, gallium arsenide, indium nitride, aluminum nitride, aluminum gallium nitride, indium gallium nitride or other suitable materials and combinations. The buffer layer 13 helps to improve the crystal quality of the structural layer to be epitaxially grown on the buffer layer 13, reduce the problem of poor crystal quality, and also help to suppress the occurrence of leakage. The buffer layer 13 may be a single-layer structure, or a multi-layer structure, or may be formed by the same material grown under different conditions.

[0054] The high resistance layer 14 is formed on the buffer layer 13 to improve the leakage of the buffer layer 13. Specifically, for example, when the semiconductor device operates in the gate voltage pinch-off state and the voltage between the source electrode 192 and the drain electrode 193 is large, it can prevent the device from being completely turned off due to leakage of the buffer layer 13. The material of the high resistance layer 14 can be gallium nitride, aluminum gallium nitride, indium gallium nitride or other suitable materials and combinations thereof. The high resistance layer 14 can be doped with P-type impurities, and the P-type impurities can be, for example, iron, carbon, magnesium or other suitable materials. The thickness of the high resistance layer 14 can be set according to actual needs. In this embodiment, the high resistance layer 14 is a highly carbon-doped gallium nitride layer.

[0055] The channel layer 15 and the barrier layer 16 are sequentially formed on the high resistance layer 14. The materials of the channel layer 15 and the barrier layer 16 may include, but are not limited to, nitrides or Ш-V compounds. Specifically, the materials of the channel layer 15 and the barrier layer 16 may be, for example, gallium nitride, indium nitride, aluminum nitride, aluminum gallium nitride, aluminum indium gallium nitride or other suitable materials and combinations. Optionally, the band gap width of the barrier layer 16 is greater than the band gap width of the channel layer 15, so that the electron affinities of the barrier layer 16 and the channel layer 15 are different from each other, for example, the channel layer 15 is a gallium nitride layer, and the barrier layer 16 is an aluminum gallium nitride layer. A triangular potential well is generated at the bonding interface between the channel layer 15 and the barrier layer 16, so that electrons gather in the triangular potential well to form a two-dimensional electron gas.

[0056] The gate cap layer 17 is formed on the barrier layer 16 to improve the mobility of the two-dimensional electron gas in the channel layer 15 and increase the Schottky contact barrier on the heterojunction structure below, thereby reducing the gate leakage current and improving the gate withstand voltage capability. The material of the gate cap layer 17 can be, for example, P-type doped gallium nitride or other suitable materials. Optionally, the gate cap layer 17 is, for example, a magnesium-doped P-type gallium nitride layer.

[0057] Reference Figure 2 and Fig. 9, the semiconductor device of this embodiment further includes a gate electrode 191, a source electrode 192 and a drain electrode 193. The gate electrode 191 is formed on the gate cap layer 17 and is located on the side of the gate cap layer 17 away from the barrier layer 16. A first opening 101, a second opening 102 and a third opening 103 are formed in the semiconductor device; wherein the first opening 101 and the second opening 102 both penetrate the barrier layer 16 and expose the channel layer 15, and the third opening 103 penetrates the barrier layer 16 and the channel layer 15 and exposes the high resistance layer 14. The source electrode 192 is filled in the first opening 101, so that the source electrode 192 is in contact with the channel layer 15. Optionally, the source electrode 192 is formed on the side of the barrier layer 16 away from the channel layer 15 and is filled in the first opening 101. The drain electrode 193 is filled in the second opening 102 and the third opening 103 , so that the drain electrode 193 contacts the channel layer 15 and the high resistance layer 14 respectively. Optionally, the drain electrode 193 is formed on the side of the barrier layer 16 away from the channel layer 15 and is filled in the second opening 102 and the third opening 103 .

[0058] In an optional embodiment, the second opening 102 and the third opening 103 may be spaced apart from each other, or the second opening 102 and the third opening 103 may be interconnected. Optionally, in the thickness direction of the semiconductor device along the substrate 11, the second opening 102 and the third opening 103 are interconnected.

[0059] The material of the gate electrode 191 may be metal, alloy, doped semiconductor material or other suitable material. Optionally, the material of the gate electrode 191 may be titanium nitride, nickel, tungsten or other materials. The gate electrode 191 may be a single-layer structure or a multi-layer structure. Optionally, in the multi-layer structure of the gate electrode 191, each layer may have the same or similar material as other layers, or may have a different material from other layers.

[0060] The materials of the drain electrode 193 and the source electrode 192 can also be metals, alloys, doped semiconductor materials or other suitable materials and combinations. Optionally, the materials of the drain electrode 193 and the source electrode 192 can be titanium, aluminum, gold and other materials and combinations thereof. The drain electrode 193 and the source electrode 192 can be a single-layer structure or a multi-layer structure. Optionally, the source electrode 192 and the drain electrode 193 can be a multi-layer structure formed of metal materials such as titanium and aluminum. The material and structure of the drain electrode 193 can be the same as or different from that of the source electrode 192.

[0061] In this embodiment, the high resistance layer 14 of the semiconductor device is a gallium nitride layer doped with P-type impurities, such as a high-carbon doped layer. By making the drain electrode 193 contact the high resistance layer 14, when the semiconductor device is in a high-voltage off state, a forward voltage is applied to the drain electrode 193. The drain electrode 193 can be used to inject a large number of holes into the buffer layer 13, thereby effectively reducing the electron traps near the drain region when the device is in the off state, thereby reducing the dynamic on-resistance of the semiconductor device and improving the overall performance of the device.

[0062] In an optional embodiment, the gate electrode 191 is located between the source electrode 192 and the drain electrode 193, the source electrode 192 includes an ohmic source 1921, the drain electrode 193 includes an ohmic drain 1931, the ohmic source 1921 is filled in the first opening 101, and is in contact with the channel layer 15 and the barrier layer 16 respectively, and the ohmic drain 1931 is filled in the second opening 102, and is in contact with the channel layer 15 and the barrier layer 16 respectively. Optionally, the ohmic source 1921 is in ohmic contact with the channel layer 15 through the first opening 101, and the ohmic drain 1931 is in ohmic contact with the channel layer 15 through the second opening 102, which helps to reduce the on-resistance of the semiconductor device and improve the overall performance of the device.

[0063] In an optional embodiment, the drain electrode 193 further includes a Schottky drain 1932, which is filled in the third opening 103. The Schottky drain 1932 is in Schottky contact with the high resistance layer 14 through the third opening 103, which can generate a more uniform electric field distribution. By cooperating with the ohmic drain 1931, it can achieve interconnection with the high resistance layer 14 while taking into account the on-resistance of the device, so as to inject holes into the buffer layer 13, improve the problem of electron traps near the drain region when the device is turned off, and thus reduce the dynamic resistance of the device, thereby ensuring the improvement effect on the dynamic resistance of the device. In this embodiment, since the second opening 102 and the third opening 103 are interconnected, the drain electrode 193 forms a continuous structure in the second opening 102 and the third opening 103, wherein the portion in the third opening 103 that contacts the high resistance layer 14 forms the above-mentioned Schottky drain 1932; and the portion in the second opening 102 that contacts the channel layer 15 forms the ohmic drain 1931.

[0064] Furthermore, the source electrode 192 and the drain electrode 193 are located on both sides of the gate electrode 191, are spaced apart from the gate electrode 191, and are asymmetrically distributed with respect to the gate electrode 191. Figure 1As shown, there is a first spacing distance between the source electrode 192 and the gate electrode 191, and there is a second spacing distance between the drain electrode 193 and the gate electrode 191, and the first spacing distance is smaller than the second spacing distance. The above-mentioned arrangement of the source electrode 192 and the drain electrode 193 relative to the gate electrode 191 can prevent the semiconductor device from experiencing premature breakdown or saturation, which is beneficial to improving the blocking voltage capability of the device, reducing parasitic capacitance, etc., so as to improve the overall performance of the device.

[0065] Further, refer to Figure 1 , the width of the portion of the drain electrode 193 penetrating the barrier layer 16 is greater than the width of the portion of the drain electrode 193 penetrating the channel layer 15, that is, the width d1 is greater than the width d2. Furthermore, the side walls of the ohmic drain 1931 and the Schottky drain 1932 of the drain electrode 193 away from the gate electrode 191 are flush with each other, so that the ohmic drain 1931 can form an inverted L-shaped structure; on the side close to the gate electrode 191, the side wall of the ohmic drain 1931 is closer to the gate electrode 191 than the side wall of the Schottky drain 1932.

[0066] In an alternative embodiment, reference Figure 2 , the semiconductor device further includes a nucleation layer 12, a dielectric layer 18 and an isolation region 105. The nucleation layer 12 is located between the substrate 11 and the buffer layer 13. The nucleation layer 12 is formed on the substrate 11, and the buffer layer 13 is formed on the nucleation layer 12. The nucleation layer 12 helps to promote epitaxial growth, reduce the lattice mismatch problem between the buffer layer 13 and the substrate 11, and improve the stress condition of the structural layer grown on the substrate 11. The material of the nucleation layer 12 may include, but is not limited to, nitrides, Ш-V group compounds, and optionally, the material of the nucleation layer 12 may be, for example, aluminum gallium nitride, aluminum nitride or other suitable materials and combinations.

[0067] The dielectric layer 18 is formed above the barrier layer 16 and at least wraps around the sidewalls of the gate electrode 191 and the gate cap layer 17. The first opening 101, the second opening 102 and the third opening 103 also penetrate the dielectric layer 18. The source electrode 192 and the drain electrode 193 can be formed above the dielectric layer 18 around the first opening 101 and the second opening 102, respectively. Optionally, the dielectric layer 18 is provided with a fourth opening 104, which is formed above the gate electrode, penetrates the dielectric layer 18 and exposes the gate electrode 191, so as to facilitate subsequent testing of the semiconductor device. The material of the dielectric layer 18 can be, for example, aluminum nitride, aluminum oxide, silicon oxide, silicon nitride or other suitable materials, and the dielectric layer 18 can be a single-layer structure or a multi-layer structure. The dielectric layer 18 can be used as a passivation layer to protect the semiconductor device and reduce the influence of the surface state on the device performance.

[0068] In the direction of looking down at the semiconductor device, the isolation region 105 is arranged around the periphery of the semiconductor device, specifically, around the periphery of the source electrode 192 and the drain electrode 193, for isolating the semiconductor device from other devices to prevent mutual interference between the devices, and the isolation region 105 can adopt an implantation type isolation or a trench type isolation. Optionally, the isolation region 105 is an implantation type isolation, and the isolation region 105 can be formed by implanting materials such as helium ions and fluorine ions around the periphery of the semiconductor device.

[0069] In the present embodiment, the drain electrode 193 penetrates the barrier layer 16 and the channel layer 15 and contacts the high resistance layer 14. Ohmic contact and Schottky contact are formed between the drain electrode 193 and the channel layer 15 and the high resistance layer 14 respectively, so that the interconnection with the high resistance layer 14 can be achieved while taking into account the on-resistance of the device. When the semiconductor device is in a high-voltage off state, a forward voltage is applied to the drain electrode 193, and a large number of holes can be injected into the buffer layer 13 through the drain electrode 193, which effectively reduces the electron traps near the drain region when the device is in the off state, thereby reducing the dynamic on-resistance of the device and improving the overall performance of the device.

[0070] Embodiment 2

[0071] This embodiment provides a method for manufacturing a semiconductor device, which is used to manufacture any of the semiconductor devices in the above embodiments.

[0072] Reference Figure 3 The method for manufacturing a semiconductor device of this embodiment includes steps S1 to S6, specifically including:

[0073] Step S1: providing a substrate 11;

[0074] Step S2: sequentially growing a buffer layer 13, a high resistance layer 14, a channel layer 15, a barrier layer 16 and a gate cap layer 17 on the substrate 11;

[0075] Step S3: forming a gate layer on the gate cap layer 17, and etching the gate layer and the gate cap layer 17 to form a gate electrode 191;

[0076] Step S4: etching the barrier layer 16 and the channel layer 15 on one side of the gate electrode 191 to form a third opening 103 exposing the high resistance layer 14;

[0077] Step S5: etching the barrier layer 16 on both sides of the gate electrode 191 to form a first opening 101 and a second opening 102 exposing the channel layer 15 on both sides of the gate electrode 191 respectively;

[0078] Step S6: forming a source electrode 192 and a drain electrode 193 respectively, wherein the source electrode 192 is filled in the first opening 101 and contacts the channel layer 15 , and the drain electrode 193 is filled in the second opening 102 and the third opening 103 and contacts the channel layer 15 and the high resistance layer 16 .

[0079] The semiconductor device dispatching method of this embodiment will be described in detail below with reference to the accompanying drawings. It should be noted that the above sequence does not strictly represent the process sequence of the manufacturing method of the semiconductor device protected by this application, and those skilled in the art may change it according to the actual processing steps.

[0080] First, step S1 is performed to provide a pad. Optionally, the substrate 11 may be, for example, a silicon substrate 11 , a silicon carbide substrate 11 , a sapphire substrate 11 or other suitable substrates 11 .

[0081] Then, refer to Figure 4 , executing step S2 , sequentially growing a buffer layer 13 , a high resistance layer 14 , a channel layer 15 , a barrier layer 16 and a gate cap layer 17 on the substrate 11 .

[0082] In an optional embodiment, the buffer layer 13, the high resistance layer 14, the channel layer 15, the barrier layer 16 and the gate cap layer 17 may be formed respectively by atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD) or other suitable process methods. Optionally, the high resistance layer 14 and the gate cap layer 17 may be formed by ion implantation. For example, the high resistance layer 14 covering the buffer layer 13 and the gate cap layer 17 covering the barrier layer 16 may be formed by ALD, PVD, CVD or other suitable methods, and then ion implantation may be performed to form the high resistance layer 14 and the gate cap layer 17 respectively.

[0083] In an optional embodiment, the material of the buffer layer 13 may be, for example, gallium nitride, gallium arsenide, indium nitride, aluminum nitride, aluminum gallium nitride, indium gallium nitride or other suitable materials and combinations thereof, the material of the high resistance layer 14 may be, for example, gallium nitride, aluminum gallium nitride, indium gallium nitride or other suitable materials and combinations thereof with high P-type impurities, the material of the channel layer 15 and the barrier layer 16 may be, for example, gallium nitride, indium nitride, aluminum nitride, aluminum gallium nitride, aluminum indium gallium nitride or other suitable materials and combinations thereof, and the material of the gate cap layer 17 may be, for example, gallium nitride doped with P-type impurities or other suitable materials and combinations thereof. Further, in this embodiment, the high resistance layer 14 is a highly carbon-doped gallium nitride layer, the channel layer 15 is a gallium nitride layer, and the barrier layer 16 is an aluminum gallium nitride layer.

[0084] In an alternative embodiment, reference Figure 4 In step S2, before forming the buffer layer 13 on the substrate 11, the following steps are also included: forming a nucleation layer 12 on the substrate 11. The buffer layer 13, the high resistance layer 14, the channel layer 15 and the barrier layer 16 are sequentially formed on the nucleation layer 12. The material of the nucleation layer 12 can be, for example, aluminum nitride, aluminum nitride plus or other suitable materials, and the nucleation layer 12 can be formed on the substrate 11 by epitaxial growth technology, chemical vapor deposition process or other suitable methods.

[0085] Next, execute step S3, referring to Figure 5 , a gate layer is formed on the gate cap layer 17 , and the gate layer and the gate cap layer 17 are etched to form a gate electrode 191 .

[0086] In an optional embodiment, a gate material can be deposited on the gate cap layer 17 using a deposition process to form a gate layer. The gate material can be a metal, an alloy, a doped semiconductor material or other suitable material. The gate layer can be a single-layer structure or a multi-layer structure. Optionally, the gate material is, for example, titanium nitride, nickel, tungsten or other materials.

[0087] In an optional embodiment, after forming a gate layer on the gate cap layer 17, the gate layer and the gate cap layer 17 are patterned and etched to obtain a gate electrode 191. Optionally, the gate layer and the gate cap layer 17 can be etched to obtain the gate electrode 191, for example, by photolithography, exposure, development, etching or other suitable processes and combinations.

[0088] In an alternative embodiment, reference Figure 6In step S3, after forming the gate electrode 191, the following steps are further included: forming a dielectric layer 18 covering the gate electrode 191 on the barrier layer 16, and optionally, the dielectric layer 18 also covers the barrier layer 16. The material of the dielectric layer 18 may be, for example, aluminum nitride, aluminum oxide, silicon oxide, silicon nitride or other suitable materials, and the dielectric layer 18 may be a single-layer structure or a multi-layer structure, and may be deposited on the barrier layer 16 by vapor phase epitaxial deposition technology or other suitable methods to form the dielectric layer 18.

[0089] In an alternative embodiment, reference Figure 7 , after forming a dielectric layer 18 covering the gate electrode 191 on the barrier layer 16, the following step is also included: forming an isolation region 105 at the periphery of the semiconductor device to isolate the semiconductor device. The periphery of the semiconductor device means the periphery of the semiconductor device in the top view along the thickness direction of the substrate 11. The isolation region 105 can be formed before etching the barrier layer 16 and the channel layer 15 on one side of the gate electrode 191, or can be formed at other suitable nodes after etching the barrier layer 16 and the channel layer 15. Optionally, in this embodiment, the above-mentioned isolation region 105 is formed after forming the dielectric layer 18 covering the gate electrode 191 on the barrier layer 16 and before etching the barrier layer 16 and the channel layer 15 on one side of the gate electrode 191. The isolation region 105 can be an implantation type isolation or a trench type isolation. Optionally, ion implantation is performed on the periphery of the semiconductor device to form the isolation region 105.

[0090] Next, execute step S4, referring to Figure 8 and Fig. 9 , the barrier layer 16 and the channel layer 15 on one side of the gate electrode 191 are etched to form a third opening 103, and the third opening 103 exposes the high resistance layer 14. Specifically, for example, according to a preset drain pattern, the barrier layer 16 and the channel layer 15 can be etched to form the third opening 103, and the position of the third opening 103 corresponds to the position of the drain electrode 193. Optionally, a dielectric layer 18 is also formed on the barrier layer 16, and performing step S4 includes the following steps: etching the dielectric layer 18, the barrier layer 16 and the channel layer 15 to form the third opening 103 exposing the high resistance layer 14.

[0091] Next, step S5 is performed to etch the barrier layer 16 on both sides of the gate electrode 191, and form a first opening 101 and a second opening 102 respectively exposing the channel layer 15 on both sides of the gate electrode 191. Specifically, for example, the barrier layer 16 can be etched according to a preset source pattern and a drain pattern to form a first opening 101 and a second opening 102 respectively, and the position of the first opening 101 corresponds to the position of the source electrode 192, and the position of the second opening 102 corresponds to the position of the drain electrode 193.

[0092] In an optional embodiment, the spacing distance between the first opening 101 and the gate electrode 191 is smaller than the spacing distance between the second opening 102 and the gate electrode 191 , so that the first spacing distance between the source electrode 193 and the gate electrode 191 is smaller than the second spacing distance between the drain electrode 193 and the gate electrode 191 .

[0093] Finally, step S6 is performed to form a source electrode 192 and a drain electrode 193 , wherein the source electrode 192 is filled in the first opening 101 and contacts the channel layer 15 , and the drain electrode 193 is filled in the second opening 102 and the third opening 103 and contacts the channel layer 15 and the high resistance layer 16 .

[0094] The materials of the source electrode 192 and the drain electrode 193 can be metal materials such as titanium, aluminum, gold, or other suitable materials and combinations thereof. The drain electrode 193 and the source electrode 192 can be a single-layer structure or a multi-layer structure. For example, the source electrode 192 and the drain electrode 193 can be a multi-layer structure formed by stacking multiple layers of metal films. The source electrode 192 and the drain electrode 193 can be prepared by evaporation technology, magnetron sputtering technology, or other suitable methods.

[0095] In an alternative embodiment, reference Fig.10 , the source electrode 192 includes an ohmic source 1921, the drain electrode 193 includes an ohmic drain 1931 and a Schottky drain 1932, a dielectric layer 18 is formed on the barrier layer 16, and step S6 is performed, including the following steps: filling the first opening 101, the second opening 102 and the third opening 103 with metal material, and extending the metal material to cover part of the dielectric layer 18 around the first opening 101 and the second opening 102; performing an annealing process so that the metal material in the first opening 101 and the second opening 102 that contacts the channel layer 15 respectively forms the ohmic source 1921 of the source electrode and the ohmic drain 1931 of the drain electrode 193, and the metal material that contacts the high resistance layer 14 forms the Schottky drain 1932 of the drain electrode 193. It should be noted that the above order does not strictly represent the order of step S6 in this embodiment. The preparation of the ohmic drain 1931, the ohmic source 1921, and the Schottky drain 1932 and the order and method of forming the ohmic contact and the Schottky contact can be set according to actual needs, so that the ohmic drain 1931 and the ohmic source 1921 respectively form an ohmic contact with the channel layer 15, and the Schottky drain 1932 forms a Schottky contact with the high resistance layer 14.

[0096] In an alternative embodiment, reference Figure 2After forming a dielectric layer 18 covering the gate electrode 191 on the barrier layer 16, the following steps are also included: etching the dielectric layer 18 to form a fourth opening 104 exposing the gate electrode 191, so as to facilitate subsequent testing and other processes. Preferably, the dielectric layer 18 can be etched to form the fourth opening 104 after forming the source electrode 192 and the drain electrode 193.

[0097] The method for preparing a semiconductor device provided in this embodiment is used to manufacture any semiconductor device in the first embodiment, and therefore also has the beneficial effects of the first embodiment.

[0098] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify, change or combine the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A semiconductor device, characterized in that: include: substrate; A buffer layer, a high resistance layer, a channel layer, a barrier layer and a gate cap layer are sequentially formed on the substrate; A gate electrode formed on the gate cap layer; A source electrode, penetrating the barrier layer and contacting the channel layer; The drain electrode penetrates the barrier layer and the channel layer and contacts the channel layer and the high resistance layer. The source electrode and the drain electrode are located on both sides of the gate electrode and are spaced apart from the gate electrode.

2. The semiconductor device according to claim 1, wherein: The source electrode includes an ohmic source, and the drain electrode includes an ohmic drain in contact with the channel layer and a Schottky drain in contact with the high resistance layer.

3. The semiconductor device according to claim 2, characterized in that The width of a portion of the drain electrode penetrating the barrier layer is greater than the width of a portion of the drain electrode penetrating the channel layer, and side walls of the ohmic drain and the Schottky drain at a side away from the gate electrode are flush with each other.

4. The semiconductor device according to claim 1, wherein: Also includes: a nucleation layer, located between the substrate and the buffer layer; A dielectric layer is formed on the barrier layer, and the source electrode and the drain electrode are formed above the dielectric layer and penetrate the dielectric layer; The isolation region is arranged around the periphery of the semiconductor device in a direction of looking down at the semiconductor device to isolate adjacent semiconductor devices.

5. A method for manufacturing a semiconductor device, for preparing the semiconductor device according to any one of claims 1 to 4, characterized in that: The following steps are involved: providing a substrate; forming a buffer layer, a high resistance layer, a channel layer, a barrier layer and a gate cap layer in sequence on the substrate; forming a gate layer on the gate cap layer, and etching the gate layer and the gate cap layer to form a gate electrode; Etching the barrier layer and the channel layer on one side of the gate electrode to form a third opening exposing the high resistance layer; Etching the barrier layer on both sides of the gate electrode to form a first opening and a second opening exposing the channel layer on both sides of the gate electrode respectively; A source electrode and a drain electrode are formed respectively, wherein the source electrode is filled in the first opening and connected to the channel layer, and the drain electrode is filled in the second opening and the third opening and connected to the channel layer and the high resistance layer.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: Also includes: Before growing and forming the buffer layer, growing and forming a nucleation layer on the substrate; After forming the gate electrode, a dielectric layer covering the gate electrode and the barrier layer is formed on the barrier layer.

7. The method for manufacturing a semiconductor device according to claim 5, wherein: The second opening and the third opening penetrate each other, and a spacing distance between the first opening and the gate electrode is smaller than a spacing distance between the second opening and the gate electrode.

8. The method for manufacturing a semiconductor device according to claim 6, wherein: The forming of the source electrode and the drain electrode comprises the following steps: Filling the first opening, the second opening and the third opening with metal material, and making the metal material extend to cover a portion of the dielectric layer around the first opening and the second opening; Annealing treatment is performed so that the metal material in the first opening that contacts the channel layer forms the ohmic source of the source electrode, the metal material in the second opening that contacts the channel layer forms the ohmic drain of the drain electrode, and the metal material in the third opening that contacts the high resistance layer forms the Schottky drain of the drain electrode.

9. The method for preparing a semiconductor device according to claim 6, characterized in that: After forming a dielectric layer covering the gate electrode and the barrier layer above the barrier layer, and before etching the barrier layer and the channel layer on one side of the gate electrode, the method further includes: forming an isolation region at the periphery of the semiconductor device to isolate the semiconductor device.

10. The method for preparing a semiconductor device according to claim 6, characterized in that: After forming the source electrode and the drain electrode respectively, the method further includes: etching the dielectric layer to form a fourth opening exposing the gate electrode.

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