An epitaxial structure of a gallium nitride semiconductor chip

Abstract

The invention provides an epitaxial structure of a gallium nitride semiconductor chip, and relates to the technical field of semiconductor devices. A Si substrate is the basis of the epitaxial structure; an AlN nucleation layer is arranged on the Si substrate; a step-gradient AlGaN buffer layer is arranged on the AlN nucleation layer, and comprises four sub-buffer layers, wherein the Al component in each sub-buffer layer gradually increases, and transitions from the Al component close to the AlN nucleation layer at the bottom to the Al component close to the C-doped GaN buffer layer at the top; the C-doped GaN buffer layer is arranged on the step-gradient AlGaN buffer layer; an AlGaN back barrier layer is arranged on the C-doped GaN buffer layer; a GaN channel layer is arranged on the AlGaN back barrier layer for electron transmission; the AlGaN barrier layer is arranged on the GaN channel layer for forming a two-dimensional electron gas together with the GaN channel layer; and a Si passivation layer is arranged on the AlGaN barrier layer.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to an epitaxial structure of a gallium nitride semiconductor chip. Background Art

[0002] Gallium nitride (GaN) semiconductor chips are a semiconductor material widely used in high-power, high-frequency and high-temperature environments. Due to its wide bandgap, high thermal conductivity and electrical conductivity, GaN can work stably at higher voltages and frequencies, and is particularly suitable for high-efficiency, long-life power electronic devices and radio frequency (RF) applications.

[0003] The epitaxial structure is of vital importance in gallium nitride (GaN) semiconductor chips. By optimizing the epitaxial structure layer by layer, defects and dislocations caused by the lattice mismatch between the substrate and the material can be reduced.

[0004] Traditional epitaxial structures often introduce buffer layers to alleviate lattice mismatch. However, the Al component of the traditional buffer layer is often constant throughout the layer, which can easily cause stress concentration in the epitaxial structure, resulting in uneven GaN crystallization, thus affecting the performance and stability of the device. Summary of the invention

[0005] In order to solve the technical problem that the Al component of the traditional buffer layer is often constant throughout the layer, which easily causes stress concentration in the epitaxial structure, resulting in uneven GaN crystallization, thereby affecting the performance and stability of the device, the present invention provides an epitaxial structure of a gallium nitride semiconductor chip.

[0006] The technical solution provided by the embodiment of the present invention is as follows: An embodiment of the present invention provides an epitaxial structure of a gallium nitride semiconductor chip, comprising: a Si substrate (1), an AlN nucleation layer (2), a step-gradient AlGaN buffer layer (3), a C-doped GaN buffer layer (4), an AlGaN back barrier layer (5), a GaN channel layer (6), an AlGaN barrier layer (7), and a Si passivation layer (8); The Si substrate (1) is the basis of the epitaxial structure; The AlN nucleation layer (2) is arranged on the Si substrate (1); The step-gradient AlGaN buffer layer (3) is arranged on the AlN nucleation layer (2), and comprises four sub-buffer layers, wherein the Al component in each sub-buffer layer gradually increases, transitioning from the Al component at the bottom close to the AlN nucleation layer (2) to the Al component at the top close to the C-doped GaN buffer layer (4); The C-doped GaN buffer layer (4) is arranged on the step-gradient AlGaN buffer layer (3); The AlGaN back barrier layer (5) is arranged on the C-doped GaN buffer layer (4); The GaN channel layer (6) is arranged on the AlGaN back barrier layer (5) and is used for electron transmission; The AlGaN barrier layer (7) is arranged on the GaN channel layer (6) and is used to form a two-dimensional electron gas together with the GaN channel layer (6); The Si passivation layer (8) is arranged on the AlGaN barrier layer (7).

[0007] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least: In the present invention, the step-gradient AlGaN buffer layer effectively reduces the stress concentration and lattice mismatch in the GaN epitaxial layer by gradually increasing the Al component of each layer, from close to the AlN nucleation layer to close to the C-doped GaN buffer layer, and can smoothly alleviate the lattice constant difference between different materials, reduce the dislocation density, improve the crystal quality of the GaN epitaxial layer, and improve the performance and stability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0009] Figure 1 A schematic structural diagram of an epitaxial structure of a gallium nitride semiconductor chip provided in an embodiment of the present invention.

[0010] Figure 2 A schematic structural diagram of a stepped groove mask layer provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0011] The technical solution of the present invention is described below in conjunction with the accompanying drawings.

[0012] Reference Manual Attached Figure 1 , showing a schematic structural diagram of an epitaxial structure of a gallium nitride semiconductor chip provided by an embodiment of the present invention.

[0013] An embodiment of the present invention provides an epitaxial structure of a gallium nitride semiconductor chip, comprising: a Si substrate 1, an AlN nucleation layer 2, a step-gradient AlGaN buffer layer 3, a C-doped GaN buffer layer 4, an AlGaN back barrier layer 5, a GaN channel layer 6, an AlGaN barrier layer 7 and a Si passivation layer 8.

[0014] The Si substrate 1 is the basis of the epitaxial structure. The Si substrate has a significant cost advantage over other high-cost substrate materials (such as sapphire or silicon carbide). The price of silicon material is low, and the silicon substrate can produce large-sized wafers, which enables GaN semiconductor chips to be produced on a large scale and at low cost, thereby reducing the manufacturing cost of the overall device.

[0015] The AlN nucleation layer 2 is arranged on the Si substrate 1. During the epitaxial growth of GaN, since GaN has a high growth temperature, if there is no suitable buffer layer or nucleation layer, the GaN layer may undergo local melting and etching back at high temperature, resulting in surface unevenness and degradation of the epitaxial layer quality. The introduction of the AlN nucleation layer can effectively solve this problem, because AlN has a high melting point and good chemical stability, which can provide a stable growth surface for GaN during growth and prevent GaN from melting and etching back. In addition, the AlN nucleation layer can also alleviate the lattice mismatch and thermal expansion coefficient difference between GaN and Si, reduce the stress accumulation caused by these differences, thereby improving the quality of the GaN epitaxial layer, reducing the defect density, and improving the electronic properties of the GaN layer and the long-term stability of the device. In general, the AlN nucleation layer not only ensures the high-quality growth of the GaN layer, but also provides a solid foundation for the deposition of subsequent layers and the improvement of device performance.

[0016] The step-gradient AlGaN buffer layer 3 is arranged on the AlN nucleation layer 2, and includes four sub-buffer layers. The Al component in each sub-buffer layer gradually increases, and the Al component at the bottom close to the AlN nucleation layer 2 transitions to the Al component at the top close to the C-doped GaN buffer layer 4, reducing stress and gradually alleviating the lattice mismatch in the epitaxial layer. Through this gradient change, the step-gradient AlGaN buffer layer 3 can smoothly transition the lattice constant difference between GaN and the Si substrate and inside the GaN layer, reduce stress concentration, and avoid cracks and defects that may be caused by the traditional single-layer buffer layer. In addition, the layer-by-layer transition of the step-gradient AlGaN buffer layer 3 not only alleviates the internal stress caused by the lattice mismatch between different layers, but also improves the quality of the GaN layer, reduces the dislocation density, and further improves the electronic performance of the GaN layer, which is particularly important in high-power and high-frequency device applications. The design of the step-gradient AlGaN buffer layer effectively improves the quality and stability of the GaN epitaxial layer, allowing gallium nitride semiconductor devices to operate stably for a long time under harsh working environments.

[0017] The C-doped GaN buffer layer 4 is arranged on the step-gradient AlGaN buffer layer 3 to improve the crystal quality and obtain semi-insulating properties. By doping with carbon elements (C), the buffer layer not only effectively improves the crystal structure of GaN and reduces the dislocation density, but also provides semi-insulating properties by introducing controlled electronic defects. This semi-insulating property is crucial for high-power, high-frequency GaN devices (such as high electron mobility transistors HEMT) because it can reduce leakage current and improve the electrical performance of the device. The introduction of the C-doped GaN buffer layer not only helps to reduce defects caused by stress, but also optimizes the electronic structure of the GaN layer, providing higher carrier mobility and lower leakage current, thereby improving the overall performance and stability of the GaN epitaxial layer.

[0018] The AlGaN back barrier layer 5 is disposed on the C-doped GaN buffer layer 4 to improve carrier confinement and reduce the trap effect of the buffer layer, preventing electrons from transferring from the GaN channel layer 6 to the C-doped GaN buffer layer 4, thereby reducing leakage current and increasing breakdown voltage. The AlGaN back barrier layer has a higher energy band structure and can form a potential barrier, effectively limiting the flow of carriers, preventing electrons from entering the buffer layer or being lost through the back barrier layer, thereby reducing leakage current and increasing device efficiency. At the same time, the AlGaN back barrier layer 5 can also reduce the trap effect in the buffer layer and reduce the capture of carriers in the buffer layer, which helps to improve carrier mobility and the overall electrical performance of the device. By suppressing carrier leakage and reducing leakage current, the AlGaN back barrier layer 5 significantly improves the breakdown voltage of the GaN device, allowing the device to operate stably at a higher voltage, and is particularly suitable for high-power and high-frequency applications.

[0019] The GaN channel layer 6 is disposed on the AlGaN barrier layer 5 for electron transmission. The high electron mobility of the GaN channel layer 6 makes it an irreplaceable advantage in high-frequency and high-power electronic devices, and is widely used in the fields of radio frequency power amplifiers, high electron mobility transistors (HEMTs), etc.

[0020] The AlGaN barrier layer 7 is disposed on the GaN channel layer 6 to form a two-dimensional electron gas (2DEG) together with the GaN channel layer 6 to improve electron mobility. The AlGaN barrier layer 7 forms a quantum well with the GaN channel layer by providing a high potential barrier, which limits the vertical movement of electrons, so that electrons can flow freely only within the two-dimensional plane of the channel layer. This mechanism significantly improves electron mobility, allowing the device to achieve higher switching speeds and stronger current driving capabilities. The composition and thickness of the AlGaN barrier layer 7 directly affect the quality and density of the two-dimensional electron gas. Optimizing its structure can increase the carrier density and reduce the trap effect, thereby effectively improving the electron transmission efficiency.

[0021] The Si passivation layer 8 is disposed on the AlGaN barrier layer 7 and is the topmost layer of the epitaxial structure. It is used to protect the device surface, prevent surface trap effects, and reduce electron capture. The Si passivation layer 8 forms a stable barrier on the surface of the GaN epitaxial layer to prevent the adsorption of external impurities, oxides and other substances, thereby reducing the formation of surface defects and traps. By reducing the electron capture effect, the Si passivation layer 8 can improve the electron mobility and electrical performance of the device, ensuring high performance in high-frequency and high-power applications.

[0022] In one possible embodiment, the structural parameters of the step-gradient AlGaN buffer layer 3 include: total thickness, thickness of the first sub-buffer layer, thickness of the second sub-buffer layer, thickness of the third sub-buffer layer, thickness of the fourth sub-buffer layer, Al component in the first sub-buffer layer, Al component in the second sub-buffer layer, Al component in the third sub-buffer layer, and Al component in the fourth sub-buffer layer.

[0023] Optionally, the thickness of the first sub-buffer layer, the thickness of the second sub-buffer layer, the thickness of the third sub-buffer layer and the thickness of the fourth sub-buffer layer are equal.

[0024] In the present invention, by making the thickness of each sub-layer the same, the design of the step-gradient AlGaN buffer layer can be effectively simplified while ensuring the uniform distribution of stress in the epitaxial layer. The lattice transition and stress relief of each layer can be better controlled, making the growth of the epitaxial layer smoother and improving the overall quality of the GaN layer. The equal thickness design can also optimize the growth rate and crystallization quality of the GaN layer, avoid material defects caused by excessive or insufficient local stress, and thus improve the performance and stability of the device, especially in high-power and high-frequency applications.

[0025] Optionally, the Al component in each sub-buffer layer is specifically: ; Among them, e i represents the Al composition of the i-th sub-buffer layer, i = 1, 2, 3 or 4, e AlN represents the Al component of the AlN nucleation layer, e GaN represents the Al composition of the C-doped GaN buffer layer.

[0026] In the present invention, the Al component of each layer changes uniformly during the layer-by-layer transition, which can effectively achieve a smooth transition of the lattice and reduce stress and defects caused by lattice mismatch. The linear transition avoids stress mutations, making the stress changes between layers smoother, which helps to reduce dislocation density and crack generation.

[0027] Optionally, the structural parameters of the step-gradient AlGaN buffer layer 3 are optimized and determined by a bat optimization algorithm.

[0028] Optionally, the fitness function of the bat optimization algorithm when optimizing the step-gradient AlGaN buffer layer 3 is specifically: ; Where f represents the first fitness function, X represents the set of structural parameters of the step-gradient AlGaN buffer layer, f1 represents the device performance, μ represents the carrier mobility, ρ 2DEG represents the electron density of the two-dimensional electron gas, E br represents the breakdown voltage, λ1 represents the weight coefficient of device performance, f2 represents the interface quality, R represents the interface roughness, δ represents the lattice mismatch, λ2 represents the weight coefficient of interface quality, f3 represents the total stress of the step-gradient AlGaN buffer layer, σ i represents the stress of the i-th sub-buffer layer, and λ3 represents the weight coefficient of the total stress of the step-gradient AlGaN buffer layer.

[0029] Among them, those skilled in the art can set the weight coefficient λ1 of device performance, the weight coefficient λ2 of interface quality and the weight coefficient λ3 of total stress of the step-gradient AlGaN buffer layer according to actual conditions, and the present invention does not limit this.

[0030] Optionally, the weight coefficient λ1 of the device performance is set to 0.3, the weight coefficient λ2 of the interface quality is set to 0.3, and the weight coefficient λ3 of the total stress of the step-gradient AlGaN buffer layer is set to 0.4.

[0031] In the present invention, the fitness function comprehensively considers the device performance (carrier mobility, two-dimensional electron gas electron density and breakdown voltage), interface quality (interface roughness and lattice mismatch), and the total stress of the buffer layer (stress of each sub-buffer layer), and optimizes each target in the form of weighted summation. The bat optimization algorithm can quickly find the optimal structural parameters in a complex parameter space, reduce dislocation density, optimize stress distribution, and improve the electronic performance and stability of the epitaxial layer, thereby improving the working efficiency, reliability and long-term stability of GaN devices, especially for high-frequency and high-power applications.

[0032] Optionally, the constraints of the bat optimization algorithm specifically include: ; Where D represents the total thickness, d1 represents the thickness of the first sub-buffer layer, d2 represents the thickness of the second sub-buffer layer, d3 represents the thickness of the third sub-buffer layer, d4 represents the thickness of the fourth sub-buffer layer, e1 represents the Al component of the first sub-buffer layer, e AlN represents the Al component of the AlN nucleation layer, e4 represents the Al component of the fourth sub-buffer layer, and e GaN represents the Al composition of the C-doped GaN buffer layer.

[0033] Furthermore, the bat individuals are initialized, and each bat individual represents a feasible set of structural parameters of the step-gradient AlGaN buffer layer.

[0034] In the global search phase, update the flight speed and position of individual bats: ; Among them, f i represents the pulse emission frequency of the i-th bat individual, f min Indicates the minimum pulse transmission frequency, f max Indicates the maximum pulse emission frequency, β t represents the nonlinear arccosine acceleration factor at the tth iteration, represents the speed of the i-th bat individual at the t+1th iteration, r1 and r2 represent random numbers between 0 and 1, ω t represents the inertia weight factor at the tth iteration, represents the speed of the i-th bat individual at the t-th iteration, represents the individual optimal solution, c i represents the learning factor, x * represents the global optimal solution, represents the position of the i-th bat individual at the t-th iteration, represents the position of the i-th bat individual at the t+1th iteration, and Levy represents the Levy flight step.

[0035] In the present invention, by updating the flight speed and position of individual bats in the global search phase, combined with mechanisms such as pulse emission frequency, inertia weight factor, nonlinear arccosine acceleration factor and Levy flight step length, the search efficiency and accuracy can be significantly improved.

[0036] Optionally, the inertia weight factor is specifically: ; Among them, ω t represents the inertia weight factor at the tth iteration, ω min represents the minimum inertia weight factor, ω max represents the maximum inertia weight factor, t represents the current number of iterations, T m Indicates the maximum number of iterations.

[0037] In the present invention, in the early stage, a larger inertia weight factor promotes a wider search, allowing the bat to explore more areas in the solution space and avoid falling into the local optimal solution. As the number of iterations increases, the gradual reduction of the inertia weight factor enhances the convergence of the algorithm, allowing the bat to pay more attention to local search when approaching the optimal solution, and fine-tune the solution, thereby improving the accuracy and stability of the final solution.

[0038] Optionally, the nonlinear arccosine acceleration factor is specifically: ; Among them, arccos represents the arccosine function, t represents the current number of iterations, and T represents the maximum number of iterations, that is, .

[0039] In the present invention, the arccosine acceleration factor gradually decreases with the increase of the number of iterations, which makes the initial search more aggressive and can quickly explore the solution space; in the later stage of the optimization process, as the iterations proceed, the factor gradually decreases, the search process tends to be stable, and more emphasis is placed on local search and fine optimization.

[0040] Optionally, the learning factor is specifically: ; Among them, c i represents the learning factor of the i-th bat individual, c max represents the maximum learning factor, c min Represents the minimum learning factor.

[0041] In the present invention, in the early stage of optimization, a larger learning factor prompts individual bats to pay more attention to global search, quickly explore the solution space, and avoid falling into the local optimal solution; and as the iteration proceeds, the learning factor gradually decreases, causing the individual bats to gradually turn to local search and more finely adjust the current solution, thereby improving the accuracy and stability of the solution.

[0042] Optionally, the Levy flight step length is specifically: ; Where Γ represents the standard Gamma function, λ represents the exponential parameter, and s represents the size parameter.

[0043] A random number r3 between 0 and 1 is randomly generated, and it is determined whether the random number r3 is greater than the pulse rate. If so, the local search phase is entered. Otherwise, the pulse rate and the average loudness of the pulse are updated.

[0044] In the present invention, by introducing the Levy flight step to update the position of individual bats, more effective jumping exploration can be achieved in the solution space. The Levy flight step has a long-tail distribution, which means that it enables bats to jump out of the local optimal solution during the search process and conduct a wide global search, thereby improving the exploration ability.

[0045] In the local search phase, a solution is selected from the optimal solution set to generate a new local solution: ; in, represents the average loudness of the pulse emitted by the i-th bat individual at the t-th iteration, ε represents a random number between 0 and 1, represents the average loudness of the pulses emitted by the i-th bat individual at the tth iteration.

[0046] Calculate the fitness value of the new local solution, generate a random number r4 between 0 and 1, and determine whether it satisfies and If yes, accept the new local solution. Otherwise, do not accept the new local solution.

[0047] In the present invention, in the local search stage, by selecting a solution from the optimal solution set and generating a new local solution, the bat optimization algorithm can perform fine adjustment and optimization near the current optimal solution.

[0048] Update the pulse rate and average loudness of the pulses: ; in, represents the pulse rate emitted by the i-th bat individual at the t+1th iteration, represents the initial pulse rate emitted by the i-th bat individual, e represents the natural constant, γ represents the pulse rate enhancement coefficient, represents the average loudness of the pulse emitted by the i-th bat individual at the tth iteration, and α represents the pulse loudness attenuation coefficient.

[0049] Determine whether the current number of iterations has reached the maximum number of iterations. If so, output the set of structural parameters of the step-gradient AlGaN buffer layer represented by the bat individual with the highest current fitness. Otherwise, return to continue iteration.

[0050] In the present invention, by using the bat optimization algorithm to optimize the structural parameters of the step-gradient AlGaN buffer layer, the optimal solution can be efficiently found in a complex parameter space. The bat optimization algorithm simulates the echolocation behavior of bats in nature, and combines global search and local search capabilities to avoid falling into the local optimal solution and quickly find the optimal buffer layer structural parameters. By optimizing parameters, such as the thickness of the sub-buffer layer, the Al component, etc., the lattice mismatch can be effectively reduced, the stress can be relieved, and the quality of the GaN epitaxial layer can be improved, ultimately improving the performance and stability of GaN-based devices. In addition, the bat optimization algorithm has a strong global exploration capability and a high convergence accuracy, and can achieve a balance between multiple optimization objectives, ensuring that the final step-gradient AlGaN buffer layer design is in the best state in terms of comprehensive performance in all aspects.

[0051] Refer to the instruction manual Figure 2 , showing a schematic structural diagram of a stepped groove mask layer provided in an embodiment of the present invention.

[0052] In a possible implementation, the epitaxial structure of the gallium nitride semiconductor chip further includes: a Si3N4 stepped groove mask layer 9. The Si3N4 stepped groove mask layer 9 is disposed on the AlGaN barrier layer 5 or the AlN nucleation layer 2, and the Si3N4 stepped groove mask layer 9 has stepped irregular grooves, which are used to grow GaN and form a GaN channel layer 6.

[0053] It should be noted that this Si3N4 step-groove mask layer 9 causes GaN to undergo multiple turns during its growth to the area above the mask layer, effectively filtering out dislocations during the turning process, thereby forming a high-quality GaN channel layer 6 above the Si3N4 step-groove mask layer 9.

[0054] In the present invention, the growth direction and nucleation position of GaN are controlled by the geometric shape of the stepped groove, which effectively promotes the uniform growth of GaN crystals and reduces the generation of defects. The design of the special-shaped groove can improve the quality of the GaN layer by improving the nucleation and growth rate of GaN, while optimizing the surface flatness of the layer and reducing the surface roughness.

[0055] Optionally, the Si3N4 stepped trench mask layer 9 includes a first trench body 91 and a second trench body 92 .

[0056] The heights of the bottom, middle and upper parts of the first slot body 91 increase in sequence to form a three-stage stepped slot body. The heights of the bottom and upper parts of the second slot body 92 increase in sequence to form a two-stage stepped slot body.

[0057] A special-shaped groove 93 for GaN growth is formed by the first groove body 91 and the second groove body 92 .

[0058] In the present invention, this stepped groove mask layer uses Si as a substrate instead of expensive materials such as sapphire as a substrate, which greatly reduces the production cost. Silicon materials not only have a low cost, but can also be mass-produced through existing silicon semiconductor manufacturing technology. In addition, the use of silicon as a substrate also makes the entire epitaxial structure more economical and efficient in the production and application process. In contrast, expensive materials such as sapphire not only increase the production cost, but also increase the overall manufacturing complexity and cost of the device. At the same time, the stepped groove mask layer design in the present invention only uses two layers of homogeneous Si3N4 mask layers (i.e., the first trough body and the second trough body). This simplified design makes the structure more stable. Since the materials of the two mask layers are consistent, the stress problems that may be caused by material mismatch are reduced, and the mechanical properties and reliability of the entire structure are improved. This design not only optimizes cost-effectiveness, but also improves the stability of the device, ensuring the good performance and long-term reliability of the GaN epitaxial layer in high-frequency and high-power applications.

[0059] Optionally, the bat optimization algorithm is used to optimize and determine the structural parameters of the Si3N4 step-shaped groove mask layer 9. The structural parameters of the Si3N4 step-shaped groove mask layer 9 include: the length and height of the bottom, middle and upper parts of the first groove body 91, the length and height of the bottom and upper parts of the second groove body 92, and the spacing between the first groove body 91 and the second groove body 92.

[0060] Optionally, the fitness function of the bat optimization algorithm when optimizing the Si3N4 stepped groove mask layer 9 is specifically: ; Among them, g represents the second fitness function, Y represents the structural parameter set of the Si3N4 step-shaped groove mask layer, g1 represents the device performance, μ represents the carrier mobility, ρ 2DEG represents the electron density of the two-dimensional electron gas, E br represents the breakdown voltage, η1 represents the weight coefficient of device performance, g2 represents the dislocation density, η2 represents the weight coefficient of dislocation density, g3 represents the total stress of the Si3N4 step groove mask layer, and η3 represents the weight coefficient of the total stress of the Si3N4 step groove mask layer.

[0061] Among them, those skilled in the art can set the weight coefficient η1 of device performance, the weight coefficient η2 of dislocation density and the weight coefficient η3 of total stress of Si3N4 step-shaped groove mask layer according to actual conditions, and the present invention does not limit it.

[0062] Optionally, the weight coefficient η1 of the device performance is 0.3, the weight coefficient η2 of the dislocation density is 0.3, and the weight coefficient η3 of the total stress of the Si3N4 step-shaped groove mask layer is 0.4.

[0063] In the present invention, the fitness function comprehensively considers three key factors: device performance (such as carrier mobility, two-dimensional electron gas electron density and breakdown voltage), dislocation density and total stress. By optimizing these parameters, it is possible to reduce dislocation density and stress while improving device performance, thereby improving the quality and stability of the GaN epitaxial layer. The advantage of this method is that the bat optimization algorithm can quickly search for the global optimal solution, avoid the trap of the local optimal solution, and effectively improve the application efficiency of the Si3N4 stepped groove mask layer in GaN epitaxial growth.

[0064] Furthermore, how to optimize and determine the structural parameters of the Si3N4 step-groove mask layer 9 through the bat optimization algorithm can refer to the steps of optimizing and determining the structural parameters of the step-gradient AlGaN buffer layer 3 through the bat optimization algorithm mentioned above. To avoid repetition, the present invention will not go into details.

[0065] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least: In the present invention, the step-gradient AlGaN buffer layer effectively reduces the stress concentration and lattice mismatch in the GaN epitaxial layer by gradually increasing the Al component of each layer, from close to the AlN nucleation layer to close to the C-doped GaN buffer layer, and can smoothly alleviate the lattice constant difference between different materials, reduce the dislocation density, improve the crystal quality of the GaN epitaxial layer, and improve the performance and stability of the semiconductor device.

[0066] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. An epitaxial structure of a gallium nitride semiconductor chip, characterized in that: include: Si substrate (1), AlN nucleation layer (2), step-gradient AlGaN buffer layer (3), C-doped GaN buffer layer (4), AlGaN back barrier layer (5), GaN channel layer (6), AlGaN barrier layer (7) and Si passivation layer (8); The Si substrate (1) is the basis of the epitaxial structure; The AlN nucleation layer (2) is arranged on the Si substrate (1); The step-gradient AlGaN buffer layer (3) is arranged on the AlN nucleation layer (2), and comprises four sub-buffer layers, wherein the Al component in each sub-buffer layer gradually increases, transitioning from the Al component at the bottom close to the AlN nucleation layer (2) to the Al component at the top close to the C-doped GaN buffer layer (4); The C-doped GaN buffer layer (4) is arranged on the step-gradient AlGaN buffer layer (3); The AlGaN back barrier layer (5) is arranged on the C-doped GaN buffer layer (4); The GaN channel layer (6) is arranged on the AlGaN back barrier layer (5) and is used for electron transmission; The AlGaN barrier layer (7) is arranged on the GaN channel layer (6) and is used to form a two-dimensional electron gas together with the GaN channel layer (6); The Si passivation layer (8) is arranged on the AlGaN barrier layer (7).

2. The epitaxial structure of the gallium nitride semiconductor chip according to claim 1, characterized in that: The structural parameters of the step-gradient AlGaN buffer layer (3) include: total thickness, thickness of the first sub-buffer layer, thickness of the second sub-buffer layer, thickness of the third sub-buffer layer, thickness of the fourth sub-buffer layer, Al component in the first sub-buffer layer, Al component in the second sub-buffer layer, Al component in the third sub-buffer layer and Al component in the fourth sub-buffer layer.

3. The epitaxial structure of the gallium nitride semiconductor chip according to claim 2, characterized in that: The thickness of the first sub-buffer layer, the thickness of the second sub-buffer layer, the thickness of the third sub-buffer layer, and the thickness of the fourth sub-buffer layer are equal.

4. The epitaxial structure of the gallium nitride semiconductor chip according to claim 2, characterized in that: The Al components in each sub-buffer layer are specifically: ； Among them, e i represents the Al composition of the i-th sub-buffer layer, i = 1, 2, 3 or 4, e AlN represents the Al component of the AlN nucleation layer, e GaN represents the Al composition of the C-doped GaN buffer layer.

5. The epitaxial structure of the gallium nitride semiconductor chip according to claim 2, characterized in that: The structural parameters of the step-gradient AlGaN buffer layer (3) are optimized and determined by using a bat optimization algorithm.

6. The epitaxial structure of the gallium nitride semiconductor chip according to claim 5, characterized in that: The fitness function of the bat optimization algorithm when optimizing the step-gradient AlGaN buffer layer (3) is specifically: ； Where f represents the first fitness function, X represents the set of structural parameters of the step-gradient AlGaN buffer layer, f1 represents the device performance, μ represents the carrier mobility, ρ 2DEG represents the electron density of the two-dimensional electron gas, E br represents the breakdown voltage, λ1 represents the weight coefficient of device performance, f2 represents the interface quality, R represents the interface roughness, δ represents the lattice mismatch, λ2 represents the weight coefficient of interface quality, f3 represents the total stress of the step-gradient AlGaN buffer layer, σ i represents the stress of the i-th sub-buffer layer, λ3 represents the weight coefficient of the total stress of the step-gradient AlGaN buffer layer; The constraints of the bat optimization algorithm specifically include: ； Where D represents the total thickness, d1 represents the thickness of the first sub-buffer layer, d2 represents the thickness of the second sub-buffer layer, d3 represents the thickness of the third sub-buffer layer, d4 represents the thickness of the fourth sub-buffer layer, e1 represents the Al component of the first sub-buffer layer, e AlN represents the Al component of the AlN nucleation layer, e4 represents the Al component of the fourth sub-buffer layer, and e GaN represents the Al composition of the C-doped GaN buffer layer.

7. The epitaxial structure of the gallium nitride semiconductor chip according to claim 1, characterized in that: Also includes: Si3N4 stepped groove mask layer (9); The Si3N4 stepped groove mask layer (9) is arranged on the AlGaN barrier layer (5) or the AlN nucleation layer (2), and the Si3N4 stepped groove mask layer (9) has stepped irregular grooves, and the irregular grooves are used to grow GaN to form the GaN channel layer (6).

8. The epitaxial structure of the gallium nitride semiconductor chip according to claim 7, characterized in that: The Si3N4 stepped groove mask layer (9) comprises a first groove body (91) and a second groove body (92); The heights of the bottom, middle and upper parts of the first trough body (91) increase sequentially to form a three-step trough body; the heights of the bottom and upper parts of the second trough body (92) increase sequentially to form a two-step trough body; A special-shaped groove (93) for growing GaN is formed by the first groove body (91) and the second groove body (92).

9. The epitaxial structure of the gallium nitride semiconductor chip according to claim 8, characterized in that: Optimizing and determining the structural parameters of the Si3N4 stepped groove mask layer (9) by using a bat optimization algorithm; The structural parameters of the Si3N4 stepped groove mask layer (9) include: the length and height of the bottom, middle and upper parts of the first groove body (91), the length and height of the bottom and upper parts of the second groove body (92), and the distance between the first groove body (91) and the second groove body (92).

10. The epitaxial structure of the gallium nitride semiconductor chip according to claim 9, characterized in that: The fitness function of the bat optimization algorithm when optimizing the Si3N4 stepped groove mask layer (9) is specifically: ； Among them, g represents the second fitness function, Y represents the structural parameter set of the Si3N4 step-shaped groove mask layer, g1 represents the device performance, μ represents the carrier mobility, ρ 2DEG represents the electron density of the two-dimensional electron gas, E br represents the breakdown voltage, η1 represents the weight coefficient of device performance, g2 represents the dislocation density, η2 represents the weight coefficient of dislocation density, g3 represents the total stress of the Si3N4 step groove mask layer, and η3 represents the weight coefficient of the total stress of the Si3N4 step groove mask layer.

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