PMOS device and preparation method thereof

Abstract

The present invention provides a PMOS device and a preparation method thereof, wherein an embedded epitaxial structure is formed in a groove on the side of a gate structure, wherein the embedded epitaxial structure includes a germanium silicon buffer layer, a boron-doped germanium silicon main layer and a boron-doped cap layer from bottom to top, and the boron-doped germanium silicon main layer includes a first boron-doped germanium silicon main layer, a silicon layer and a second boron-doped germanium silicon main layer from bottom to top, and the silicon layer is in contact with the lower surface of the gate structure. The PMOS device of the present invention forms a silicon layer that is not doped with boron in the embedded epitaxial structure, and the silicon layer can be used as an isolation layer to block boron from diffusing into the channel, thereby reducing the probability of leakage, and can be used as a buffer layer between the second boron-doped germanium silicon main layer and the first boron-doped germanium silicon main layer to improve device performance control.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor preparation and relates to a PMOS device and a preparation method thereof. Background Art

[0002] As the technology node decreases, the size of components is getting smaller and smaller. Improving transistor performance by only reducing the gate dielectric layer is gradually approaching its physical limit, and it is difficult to continue to develop at the previous speed. For PMOS devices, embedded epitaxial layers usually use silicon germanium (SiGe) epitaxial layers added to the PMOS source and drain regions to generate compressive stress in the recesses, and for NMOS devices, embedded epitaxial layers usually use silicon phosphide (SiP) epitaxial layers to generate tensile stress in the recesses to change the stress in the channel region and increase carrier mobility.

[0003] The SiGe epitaxial layer of the PMOS device is generally doped with boron (B) to reduce the drain-source resistance and improve the device performance, including the process of forming a boron-doped buffer layer, a main layer and a cap layer from bottom to top in the groove. However, boron will diffuse in the subsequent annealing process. If there is too much boron, it may enter the channel region and produce a short channel effect.

[0004] Therefore, it is necessary to provide a PMOS device and a method for manufacturing the same. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a PMOS device and a method for manufacturing the same, so as to solve the problem of short channel effect caused by boron diffusion in the PMOS device in the prior art.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a PMOS device, the PMOS device comprising:

[0007] Silicon substrate;

[0008] A gate structure, wherein the gate structure is located on a surface of the silicon substrate;

[0009] a groove, the groove being located in the silicon substrate at a side of the gate structure;

[0010] An embedded epitaxial structure fills the groove, and includes, from bottom to top, a silicon germanium buffer layer, a boron-doped silicon germanium main layer and a boron-doped cap layer, wherein the boron-doped silicon germanium main layer includes, from bottom to top, a first boron-doped silicon germanium main layer, a silicon layer and a second boron-doped silicon germanium main layer, and the silicon layer is in contact with the lower surface of the gate structure.

[0011] Optionally, an upper surface of the first boron-doped silicon germanium main layer is lower than a lower surface of the gate structure or is flush with the lower surface of the gate structure.

[0012] Optionally, the thickness of the germanium silicon buffer layer includes The thickness of the first boron-doped silicon germanium main layer includes The thickness of the silicon layer includes The thickness of the second boron-doped silicon germanium main layer includes The thickness of the boron-doped capping layer includes

[0013] Optionally, the doping concentration of germanium located on the upper side of the first boron-doped silicon germanium main layer is greater than the doping concentration of germanium located on the lower side; the doping concentration of germanium located on the upper side of the second boron-doped silicon germanium main layer is less than the doping concentration of germanium located on the lower side; the starting doping concentration of germanium in the second boron-doped silicon germanium main layer is the ending doping concentration of germanium in the first boron-doped silicon germanium main layer.

[0014] Optionally, the boron doping concentration in the first boron-doped silicon germanium main layer includes 1E20 atoms / cm 3 ~9E20atoms / cm 3 The boron doping concentration in the second boron-doped silicon germanium main layer includes 1E19atoms / cm 3 ~9E20atoms / cm 3 The boron doping concentration in the boron doped capping layer includes 1E20atoms / cm 3 ~6E21atoms / cm 3 ; The starting doping concentration of boron in the second boron-doped silicon-germanium main layer is the ending doping concentration of boron in the first boron-doped silicon-germanium main layer.

[0015] Optionally, the germanium silicon buffer layer comprises a boron-doped germanium silicon buffer layer, and the boron doping concentration comprises 1E18 atoms / cm 3 ~9E19atoms / cm 3 ; The boron-doped capping layer includes a boron-doped silicon capping layer or a boron-doped germanium silicon capping layer.

[0016] Optionally, the atomic proportion of germanium in the germanium silicon buffer layer is 10% to 30%, and the atomic proportion of germanium includes a fixed atomic proportion of germanium or an atomic proportion of germanium located on the upper side that is greater than the atomic proportion of germanium located on the lower side; the atomic proportion of germanium in the first boron-doped germanium silicon main layer is 30% to 50%, and the atomic proportion of germanium located on the upper side is greater than the atomic proportion of germanium located on the lower side; the atomic proportion of germanium in the second boron-doped germanium silicon main layer is 20% to 50%, and the atomic proportion of germanium located on the upper side is less than the atomic proportion of germanium located on the lower side.

[0017] Optionally, the cross-sectional morphology of the groove includes a rectangle, a trapezoid, a U shape or a Σ shape.

[0018] The present invention also provides a method for preparing a PMOS device, comprising the following steps:

[0019] providing a silicon substrate;

[0020] forming a gate structure on the surface of the silicon substrate;

[0021] Patterning the silicon substrate to form a groove in the silicon substrate located on a side of the gate structure;

[0022] An embedded epitaxial structure is formed to fill the groove, wherein the embedded epitaxial structure includes, from bottom to top, a silicon germanium buffer layer, a boron-doped silicon germanium main layer and a boron-doped cap layer, wherein the boron-doped silicon germanium main layer includes, from bottom to top, a first boron-doped silicon germanium main layer, a silicon layer and a second boron-doped silicon germanium main layer, and the silicon layer is in contact with the lower surface of the gate structure.

[0023] Optionally, the starting doping concentration of germanium in the second boron-doped silicon germanium main layer is the ending doping concentration of germanium in the first boron-doped silicon germanium main layer; the starting doping concentration of boron in the second boron-doped silicon germanium main layer is the ending doping concentration of boron in the first boron-doped silicon germanium main layer.

[0024] As described above, the present invention provides a PMOS device and a preparation method thereof, wherein an embedded epitaxial structure is formed in a groove on the side of a gate structure, wherein the embedded epitaxial structure includes, from bottom to top, a germanium silicon buffer layer, a boron-doped germanium silicon main layer and a boron-doped cap layer, and the boron-doped germanium silicon main layer includes, from bottom to top, a first boron-doped germanium silicon main layer, a silicon layer and a second boron-doped germanium silicon main layer, and the silicon layer is in contact with the lower surface of the gate structure.

[0025] The PMOS device of the present invention forms a silicon layer not doped with boron in the embedded epitaxial structure. The silicon layer can be used as an isolation layer to prevent boron from diffusing into the channel, thereby reducing the probability of leakage, and can be used as a buffer layer between the second boron-doped silicon germanium main layer and the first boron-doped silicon germanium main layer to improve device performance control. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Shown is a schematic diagram of the process flow of preparing a PMOS device in an embodiment of the present invention.

[0027] Figure 2 to Figure 4 Shown is a schematic diagram of the structure presented in each step of preparing a PMOS device in an embodiment of the present invention.

[0028] Figure 5 The graph shows the variation of doping concentration with groove depth when preparing a PMOS device in an embodiment of the present invention.

[0029] Description of Reference Numerals

[0030] 100 Silicon substrate

[0031] 101 Groove

[0032] 200 Gate Structure

[0033] 300 Embedded epitaxial structure

[0034] 310 Germanium Silicon Buffer Layer

[0035] 320 Boron-doped SiGe main layer

[0036] 321 First boron-doped silicon germanium main layer

[0037] 322 Silicon layer

[0038] 323 Second boron-doped silicon germanium main layer

[0039] 330 Boron doped cap layer DETAILED DESCRIPTION

[0040] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0041] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0042] For ease of description, spatial relational terms such as “under”, “below”, “below”, “below”, “over”, etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other orientations of the device in use or operation in addition to the orientation depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, so that the first and second features may not be in direct contact. In addition, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or one or more intervening layers may also be present.

[0043] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0044] like Figure 1 This embodiment provides a method for preparing a PMOS device, comprising the following steps:

[0045] S1, providing a silicon substrate;

[0046] S2, forming a gate structure on the surface of the silicon substrate;

[0047] S3, patterning the silicon substrate to form a groove located on a side of the gate structure in the silicon substrate;

[0048] S4, forming an embedded epitaxial structure filling the groove, the embedded epitaxial structure including, from bottom to top, a silicon germanium buffer layer, a boron-doped silicon germanium main layer and a boron-doped cap layer, wherein the boron-doped silicon germanium main layer includes, from bottom to top, a first boron-doped silicon germanium main layer, a silicon layer and a second boron-doped silicon germanium main layer, and the silicon layer is in contact with the lower surface of the gate structure.

[0049] In the present embodiment, the silicon layer not doped with boron is formed in the embedded epitaxial structure, wherein the silicon layer can be used as an isolation layer to prevent boron from diffusing into the channel during the annealing process, thereby reducing the probability of leakage, and the buffer layer between the second boron-doped silicon germanium main layer and the first boron-doped silicon germanium main layer improves the device performance control.

[0050] The following is combined with Figure 2 to Figure 5 , further explanation is given on the preparation of the PMOS device.

[0051] First, see Figure 1 and Figure 2 , perform step S1 and provide a silicon substrate 100.

[0052] Specifically, in this embodiment, since a PMOS device is prepared, the silicon substrate 100 has a doped N well (not shown) in order to form a channel region corresponding to the source, drain, and gate. Further, the silicon substrate 100 may also have a P well as required to prepare for the formation of an NMOS device, which is not limited here. Among them, the N-type and P-type regions can be divided by a trench isolation structure (not shown) located in the silicon substrate 100. The size and thickness of the silicon substrate 100 are not limited here.

[0053] Next, see Figure 1 and Figure 2 , executing step S2 to form a gate structure 200 on the surface of the silicon substrate 100 .

[0054] Specifically, the gate structure 200 may be a gate structure 200 having sidewalls on the sides and a mask on the top, and being formed by stacking a gate dielectric layer and a polysilicon gate.

[0055] Furthermore, the gate structure 200 having a gate dielectric layer and a polysilicon gate can also be used as a dummy gate structure, that is, the dummy gate structure can be removed after the source region and the drain region are subsequently prepared, and then a metal gate structure (High-K Metal Gate, HKMG) with a high dielectric constant is formed in the area where the dummy gate structure is removed to improve the performance and reliability of the transistor, while reducing leakage current, thereby improving power consumption efficiency.

[0056] The specific structure and type of the gate structure 200 are not limited herein.

[0057] Next, see Figure 1 and Figure 3 , executing step S3 , patterning the silicon substrate 100 , and forming a groove 101 located on a side of the gate structure 200 in the silicon substrate 100 .

[0058] Specifically, the silicon substrate 100 at the side of the gate structure 200 may be opened by photolithography and etching processes to form the groove 101 to provide space for the subsequent formation of the embedded epitaxial structure 300 .

[0059] Among them, the cross-sectional morphology of the groove 101 may include rectangular, trapezoidal, U-shaped or Σ-shaped, etc. In this embodiment, the Σ-shaped is preferably adopted, but the cross-sectional morphology and preparation process of the groove 101 are not limited thereto and can be selected according to needs.

[0060] Next, see Figure 1 and Figure 4 , execute step S4 to form the embedded epitaxial structure 300 filling the groove 101, the embedded epitaxial structure 300 includes, from bottom to top, a silicon germanium buffer layer 310, a boron-doped silicon germanium main layer 320 and a boron-doped cap layer 330, wherein the boron-doped silicon germanium main layer 320 includes, from bottom to top, a first boron-doped silicon germanium main layer 321, a silicon layer 322 and a second boron-doped silicon germanium main layer 323, and the silicon layer 322 is in contact with the lower surface of the gate structure 200.

[0061] Specifically, Figure 4 When performing step S4 to form the embedded epitaxial structure 300 in the groove 101, step S4 may include the following steps:

[0062] First, perform step S4-1 to form the germanium silicon buffer layer 310 on the inner surface of the groove 101, wherein the germanium silicon buffer layer 310 can be used as a buffer layer between the silicon substrate 100 and the first boron-doped germanium silicon main layer 321 prepared subsequently, so as to improve the lattice mismatch problem between the silicon substrate 100 and the first boron-doped germanium silicon main layer 321 through the low concentration of germanium.

[0063] The atomic ratio of germanium in the germanium silicon buffer layer 310 may be 10% to 30%, such as 10%, 20%, 30%, etc. The atomic ratio of germanium may include a fixed ratio, such as Figure 5 In (a), that is, from top to bottom, as the depth (depth) of the groove 101 changes, the atomic ratio of germanium in the germanium silicon buffer layer 310 remains unchanged (Concentration, Con.).

[0064] In another embodiment, of course, the atomic ratio of germanium in the germanium silicon buffer layer 310 may also be such that the atomic ratio of germanium located on the upper side is greater than the atomic ratio of germanium located on the lower side, such as Figure 5 (b) illustrates the situation where the atomic proportion of germanium in the germanium silicon buffer layer 310 is gradually increasing, that is, from top to bottom, as the depth of the groove 101 changes, the atomic proportion of germanium in the germanium silicon buffer layer 310 gradually decreases linearly. Of course, the atomic proportion of germanium in the germanium silicon buffer layer 310 may also decrease in a step-by-step manner.

[0065] The thickness of the silicon germanium buffer layer 310 may include If wait.

[0066] In another embodiment, the silicon germanium buffer layer 310 may also be doped with boron to reduce the drain-source resistance, wherein the boron doping concentration may include, for example, 1E18 atoms / cm 3 ~9E19atoms / cm 3 , such as 5E18atoms / cm 3 、8E18atoms / cm 3 、9E19atoms / cm 3 wait.

[0067] Next, step S4 - 2 is performed to form the boron-doped silicon-germanium main layer 320 on the surface of the silicon-germanium buffer layer 310 .

[0068] The boron-doped germanium silicon main layer 320 mainly provides extrusion stress to the silicon substrate 100 on both sides of the groove 101 to change the stress in the channel region, increase carrier mobility, improve device performance, and reduce drain-source resistance by boron doping.

[0069] In the present embodiment, the boron-doped silicon germanium main layer 320 is divided into three layers, namely, from bottom to top, the first boron-doped silicon germanium main layer 321, the silicon layer 322 and the second boron-doped silicon germanium main layer 323, wherein, by setting the silicon layer 322 as a silicon layer not doped with boron, on the one hand, the silicon layer 322 can be used as a barrier layer to limit the diffusion of high boron doped in the silicon germanium layer and the cap layer into the gate channel in the subsequent annealing process, thereby reducing the probability of leakage, and can serve as a buffer layer between the second boron-doped silicon germanium main layer 323 and the first boron-doped silicon germanium main layer 321, so as to improve the device performance control.

[0070] The thickness of the first boron-doped silicon germanium main layer 321 includes like The thickness of the silicon layer 322 includes like The thickness of the second boron-doped silicon germanium body layer 323 may include like wait.

[0071] The thickness of the first boron-doped silicon germanium main layer 321, the silicon layer 322 and the second boron-doped silicon germanium main layer 323 can be selected as required. The thickness of the silicon layer 322 is preferably This is to avoid an increase in resistance due to the silicon layer 322 being too thick.

[0072] In this embodiment, the silicon layer 322 not doped with boron can effectively reduce the probability of a short channel effect in the channel region due to the diffusion of boron during the subsequent annealing process, thereby effectively reducing the leakage probability.

[0073] Among them, the position of the silicon layer 322 needs to be set corresponding to the channel region, that is, the silicon layer 322 needs to contact the lower surface of the gate structure 200, such as by adjusting the upper surface of the first boron-doped germanium silicon main layer 321 to be lower than or flush with the lower surface of the gate structure 200.

[0074] As an example, the atomic proportion of germanium in the first boron-doped silicon-germanium main layer 321 may be 30% to 50%, such as 30%, 40%, 50%, etc., and the atomic proportion of germanium located on the upper side is greater than the atomic proportion of germanium located on the lower side; the atomic proportion of germanium in the second boron-doped silicon-germanium main layer 323 may be 20% to 50%, such as 20%, 30%, 50%, etc., and the atomic proportion of germanium located on the upper side is less than the atomic proportion of germanium located on the lower side.

[0075] like Figure 5(b) illustrates the situation in which the atomic proportion of germanium in the first boron-doped silicon-germanium main layer 321 is gradually increasing, that is, from top to bottom, as the depth of the groove 101 changes, the atomic proportion of germanium in the first boron-doped silicon-germanium main layer 321 gradually decreases linearly. Of course, the atomic proportion of germanium in the first boron-doped silicon-germanium main layer 321 may also decrease in a step-by-step manner.

[0076] like Figure 5 (c) illustrates the situation in which the atomic proportion of germanium in the second boron-doped silicon germanium main layer 323 is gradually decreasing, that is, from top to bottom, as the depth of the groove 101 changes, the atomic proportion of germanium in the second boron-doped silicon germanium main layer 323 gradually increases linearly. Of course, the atomic proportion of germanium in the second boron-doped silicon germanium main layer 323 may also increase in a step-by-step manner.

[0077] It is preferred that the starting doping concentration of germanium in the second boron-doped silicon-germanium main layer 323 is the ending doping concentration of germanium in the first boron-doped silicon-germanium main layer 321 .

[0078] The boron doping concentration in the first boron-doped silicon germanium main layer 321 may include 1E20 atoms / cm 3 ~9E20atoms / cm 3 , such as 1E20atoms / cm 3 、5E20atoms / cm 3 、7E20atoms / cm 3 、9E20atoms / cm 3 etc.; the boron doping concentration in the second boron-doped silicon germanium main layer 323 includes 1E19atoms / cm 3 ~9E20atoms / cm 3 , such as 1E19atoms / cm 3 、5E19atoms / cm 3 、9E20atoms / cm 3 wait.

[0079] Preferably, the starting doping concentration of boron in the second boron-doped silicon-germanium main layer 323 is the ending doping concentration of boron in the first boron-doped silicon-germanium main layer 321 .

[0080] Then, step S4 - 3 is performed to form the boron-doped cap layer 330 on the surface of the boron-doped silicon-germanium main layer 320 .

[0081] The boron-doped capping layer 330 may include a boron-doped silicon capping layer or a boron-doped germanium silicon capping layer, which may be selected according to needs. In this embodiment, the boron-doped capping layer 330 is a boron-doped silicon capping layer, but is not limited thereto. In the boron-doped capping layer 330, the boron doping concentration may include 1E20 atoms / cm 3 ~6E21atoms / cm 3 , such as 1E20atoms / cm 3 、5E20atoms / cm 3 、1E21atoms / cm 3 、6E21atoms / cm 3 The thickness of the boron-doped capping layer 330 may include like wait.

[0082] There is no excessive restriction on the selection of doping concentration and thickness of each layer in the embedded epitaxial structure 300.

[0083] See also Figure 2 to Figure 4 This embodiment further provides a PMOS device, the PMOS device comprising:

[0084] Silicon substrate 100;

[0085] A gate structure 200, wherein the gate structure 200 is located on a surface of the silicon substrate 100;

[0086] A groove 101, wherein the groove 101 is located in the silicon substrate 100 at a side of the gate structure 200;

[0087] An embedded epitaxial structure 300 fills the groove 101, and includes, from bottom to top, a germanium silicon buffer layer 310, a boron-doped germanium silicon main layer 320, and a boron-doped cap layer 330, wherein the boron-doped germanium silicon main layer 320 includes, from bottom to top, a first boron-doped germanium silicon main layer 321, a silicon layer 322, and a second boron-doped germanium silicon main layer 323, and the silicon layer 322 is in contact with the lower surface of the gate structure 200.

[0088] Among them, the preparation method of the PMOS device can refer to the above-mentioned preparation method of the PMOS device, but is not limited to the above-mentioned preparation method. In this application, the above-mentioned preparation process is directly used to prepare the PMOS device, so the specific material, structure and preparation method of the PMOS device can refer to the above-mentioned embodiment, and will not be described in detail below.

[0089] As an example, the upper surface of the first boron-doped silicon germanium body layer 321 is lower than the lower surface of the gate structure 200 or is flush with the lower surface of the gate structure 200 .

[0090] As an example, the thickness of the SiGe buffer layer 310 includes The thickness of the first boron-doped silicon germanium main layer 321 includes The thickness of the silicon layer 322 includes The thickness of the second boron-doped silicon germanium main layer 323 includes The thickness of the boron-doped capping layer 330 includes

[0091] As an example, the doping concentration of germanium located on the upper side of the first boron-doped silicon germanium main layer 321 is greater than the doping concentration of germanium located on the lower side; the doping concentration of germanium located on the upper side of the second boron-doped silicon germanium main layer 323 is less than the doping concentration of germanium located on the lower side; the starting doping concentration of germanium in the second boron-doped silicon germanium main layer 323 is the ending doping concentration of germanium in the first boron-doped silicon germanium main layer 321.

[0092] As an example, the boron doping concentration in the first boron-doped silicon germanium body layer 321 includes 1E20 atoms / cm 3 ~9E20atoms / cm 3 The boron doping concentration in the second boron-doped silicon germanium main layer 323 includes 1E19atoms / cm 3 ~9E20atoms / cm 3 The boron doping concentration in the boron doped cap layer 330 includes 1E20atoms / cm 3 ~6E21atoms / cm 3 ; The starting doping concentration of boron in the second boron-doped silicon-germanium main layer 323 is the ending doping concentration of boron in the first boron-doped silicon-germanium main layer 321.

[0093] As an example, the silicon germanium buffer layer 310 includes a boron-doped silicon germanium buffer layer 310, and the boron doping concentration includes 1E18 atoms / cm 3 ~9E19atoms / cm 3 ; The boron-doped capping layer 330 includes a boron-doped silicon capping layer or a boron-doped germanium silicon capping layer.

[0094] As an example, the atomic proportion of germanium in the germanium silicon buffer layer 310 is 10% to 30%, and the atomic proportion of germanium includes a fixed atomic proportion of germanium or germanium located on the upper side that is greater than the atomic proportion of germanium located on the lower side; the atomic proportion of germanium in the first boron-doped germanium silicon main layer 321 is 30% to 50%, and the atomic proportion of germanium located on the upper side is greater than the atomic proportion of germanium located on the lower side; the atomic proportion of germanium in the second boron-doped germanium silicon main layer 323 is 20% to 50%, and the atomic proportion of germanium located on the upper side is less than the atomic proportion of germanium located on the lower side.

[0095] As an example, the cross-sectional morphology of the groove 101 includes a rectangle, a trapezoid, a U-shape, a Σ-shape, etc.

[0096] In summary, the present invention provides a PMOS device and a preparation method thereof, wherein an embedded epitaxial structure is formed in a groove on the side of a gate structure, wherein the embedded epitaxial structure includes, from bottom to top, a germanium silicon buffer layer, a boron-doped germanium silicon main layer and a boron-doped cap layer, and the boron-doped germanium silicon main layer includes, from bottom to top, a first boron-doped germanium silicon main layer, a silicon layer and a second boron-doped germanium silicon main layer, and the silicon layer is in contact with the lower surface of the gate structure.

[0097] The PMOS device of the present invention forms a silicon layer not doped with boron in the embedded epitaxial structure. The silicon layer can be used as an isolation layer to prevent boron from diffusing into the channel, thereby reducing the probability of leakage, and can be used as a buffer layer between the second boron-doped silicon germanium main layer and the first boron-doped silicon germanium main layer to improve device performance control.

[0098] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A PMOS device, characterized in that: The PMOS device comprises: Silicon substrate; A gate structure, wherein the gate structure is located on a surface of the silicon substrate; a groove, the groove being located in the silicon substrate at a side of the gate structure; An embedded epitaxial structure fills the groove, and includes, from bottom to top, a silicon germanium buffer layer, a boron-doped silicon germanium main layer and a boron-doped cap layer, wherein the boron-doped silicon germanium main layer includes, from bottom to top, a first boron-doped silicon germanium main layer, a silicon layer and a second boron-doped silicon germanium main layer, and the silicon layer is in contact with the lower surface of the gate structure.

2. The PMOS device according to claim 1, characterized in that: An upper surface of the first boron-doped silicon germanium main layer is lower than a lower surface of the gate structure or is flush with the lower surface of the gate structure.

3. The PMOS device according to claim 1, characterized in that: The thickness of the silicon germanium buffer layer includes The thickness of the first boron-doped silicon germanium main layer includes The thickness of the silicon layer includes The thickness of the second boron-doped silicon germanium main layer includes The thickness of the boron-doped capping layer includes 4. The PMOS device according to claim 1, characterized in that: The doping concentration of germanium located on the upper side of the first boron-doped silicon-germanium main layer is greater than the doping concentration of germanium located on the lower side; the doping concentration of germanium located on the upper side of the second boron-doped silicon-germanium main layer is less than the doping concentration of germanium located on the lower side; the starting doping concentration of germanium in the second boron-doped silicon-germanium main layer is the ending doping concentration of germanium in the first boron-doped silicon-germanium main layer.

5. The PMOS device according to claim 1, characterized in that: The boron doping concentration in the first boron-doped silicon germanium main layer includes 1E20 atoms / cm 3 ~9E20atoms / cm 3 The boron doping concentration in the second boron-doped silicon germanium main layer includes 1E19atoms / cm 3 ~9E20atoms / cm 3 The boron doping concentration in the boron doped capping layer includes 1E20atoms / cm 3 ~6E21atoms / cm 3 ; The starting doping concentration of boron in the second boron-doped silicon-germanium main layer is the ending doping concentration of boron in the first boron-doped silicon-germanium main layer.

6. The PMOS device according to claim 1, characterized in that: The germanium silicon buffer layer includes a boron-doped germanium silicon buffer layer, and the boron doping concentration includes 1E18 atoms / cm 3 ~9E19atoms / cm 3 ; The boron-doped capping layer includes a boron-doped silicon capping layer or a boron-doped germanium silicon capping layer.

7. The PMOS device according to claim 1, characterized in that: The atomic proportion of germanium in the germanium silicon buffer layer is 10% to 30%, and the atomic proportion of germanium includes that the atomic proportion of germanium is fixed or located on the upper side is greater than the atomic proportion of germanium located on the lower side; the atomic proportion of germanium in the first boron-doped germanium silicon main layer is 30% to 50%, and the atomic proportion of germanium located on the upper side is greater than the atomic proportion of germanium located on the lower side; the atomic proportion of germanium in the second boron-doped germanium silicon main layer is 20% to 50%, and the atomic proportion of germanium located on the upper side is less than the atomic proportion of germanium located on the lower side.

8. The PMOS device according to claim 1, characterized in that: The cross-sectional morphology of the groove includes a rectangle, a trapezoid, a U-shape or a Σ-shape.

9. A method for preparing a PMOS device, characterized in that: The following steps are involved: providing a silicon substrate; forming a gate structure on the surface of the silicon substrate; Patterning the silicon substrate to form a groove in the silicon substrate located on a side of the gate structure; An embedded epitaxial structure is formed to fill the groove, wherein the embedded epitaxial structure includes, from bottom to top, a silicon germanium buffer layer, a boron-doped silicon germanium main layer and a boron-doped cap layer, wherein the boron-doped silicon germanium main layer includes, from bottom to top, a first boron-doped silicon germanium main layer, a silicon layer and a second boron-doped silicon germanium main layer, and the silicon layer is in contact with the lower surface of the gate structure.

10. The method for preparing a PMOS device according to claim 9, characterized in that: The starting doping concentration of germanium in the second boron-doped silicon germanium main layer is the ending doping concentration of germanium in the first boron-doped silicon germanium main layer; the starting doping concentration of boron in the second boron-doped silicon germanium main layer is the ending doping concentration of boron in the first boron-doped silicon germanium main layer.

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