A power field effect tube device and a method for manufacturing the same

Abstract

A power field effect transistor device and a preparation method thereof. The present invention relates to a power semiconductor device. The present invention provides a contact hole groove above the first conductive type doped body region and a second conductive type heavily doped source region between the contact hole grooves, and a first conductive type contact heavily doped region is provided below the contact hole groove. The first conductive type contact heavily doped region and the second conductive type heavily doped source region are both connected to the upper surface metal through ohmic contact, thereby achieving a smaller cell size, lower on-resistance and better switch threshold uniformity.

Description

Technical Field

[0001] The invention relates to a power semiconductor device, in particular to the structure of a shielded gate trench field effect transistor device and a manufacturing method thereof. Background Art

[0002] The shielded gate trench field effect transistor has the characteristics of low on-resistance and fast switching speed. Figure 1 shown. Figure 1 The device 11 on the left is a schematic diagram of the structure of a traditional N-type shielded gate trench field effect transistor. The device structure includes: an N-type semiconductor 100; a series of cell trenches 101 located in the N-type semiconductor 100. The cell trench is filled with a gate electrode 110 located above and a shielded gate electrode 120 located below. Among them, the gate electrode 110 and the corresponding trench sidewall are isolated by a gate oxide layer; the shielded gate electrode 120 and the corresponding trench sidewall are isolated by a trench oxide layer; the gate electrode 110 and the shielded gate electrode 120 are isolated by an inter-electrode isolation oxide layer. The structure also includes a P-doped body region 103 and an N+ doped source region 104 located on the upper surface of the semiconductor between the cell trenches 101; in addition, between the cell trenches 101, there are also a series of contact hole trenches 102, and a P+ contact doping region 105 located below the source contact hole trench 102. The source contact hole trench 102 is covered with an upper surface metal layer, which is not drawn in the figure.

[0003] In order to further reduce the on-resistance of the shielded gate trench field effect transistor, it is necessary to reduce the cell size of the device and increase the cell density of the device. Figure 2 The top view of the cell trench 101 and the source contact hole trench 102 structure is shown. Among them, the minimum distance between the trenches (B) is limited by the trench width (C) and the minimum distance between the cell trench 101 and the source contact hole trench 102 (A). The cell trench 101 and the source contact hole trench 102 are formed by two photolithography processes, respectively. Limited by the precision limitation of the photolithography process, the alignment deviation of the two photolithography processes easily makes the distance between the cell trench 101 and the source contact hole trench 102 too close, resulting in the P+ contact doping region 105 formed under the source contact trench affecting the doping concentration of the channel region of the corresponding cell trench, thereby affecting the on-resistance and switching threshold of the device. Therefore, in the above structure, an appropriate safety distance (A) needs to be left between the cell trench 101 and the source contact hole trench 102, and this safety distance (A) limits the further reduction of the cell size.

[0004] Figure 1 The 12 devices on the left are schematic diagrams of the structure of an existing improved N-type shielded gate trench field effect transistor. Figure 1Compared with the structure, the pre-formed hard mask insulating layer 111 is used to form the source contact hole groove 102 in a self-aligned manner. This structure can solve the limitation of photolithography accuracy on the cell size. However, the following problems still exist in this structure: the morphology of the N+ doped source region 104 causes the contact resistance formed between it and the metal in the contact hole to be large; in addition, although the device structure can adjust the distance from the P+ contact doping region to the adjacent cell groove by increasing the etching angle and etching depth of the contact hole groove to avoid affecting the doping concentration in the channel region, as the cell size decreases, the corresponding contact hole groove opening becomes narrower, and the above method is difficult to implement. Therefore, it is difficult to avoid the P+ contact doping region 105 affecting the doping concentration in the channel region, thereby causing the on-resistance of the device (especially the on-resistance at a low switching threshold) to increase and the switching threshold uniformity to deteriorate. Summary of the invention

[0005] In order to overcome the above-mentioned problems, the present invention provides the following technical solution.

[0006] One of the purposes of the present invention is to provide a field effect transistor device, which includes a series of mutually parallel cellular grooves located on a second conductive type semiconductor, a first conductive type doped body region on the upper surface of the second conductive type semiconductor located between the cellular grooves, wherein the cellular grooves contain mutually isolated shielding gate electrodes, gate electrodes and an insulating filling layer located above the gate electrodes; a contact hole groove and a second conductive type heavily doped source region located between the contact hole grooves are provided above the first conductive type doped body region, a first conductive type contact heavily doped region is provided below the contact hole groove, and the first conductive type contact heavily doped region and the second conductive type heavily doped source region are both connected to the upper surface metal through ohmic contacts.

[0007] Furthermore, the contact hole trench is a discontinuous contact hole trench, and the second conductive type heavily doped source region is arranged between the discontinuous contact hole trenches.

[0008] Furthermore, the depth of the non-continuous contact hole trench is deeper than the second conductivity type heavily doped source region, and / or the first conductivity type contact heavily doped region expands outward from the contact hole trench to below the second conductivity type heavily doped source region.

[0009] Furthermore, the height of the upper surface of the gate electrode located next to the contact hole trench is lower than the height of the upper surface of the gate electrode located next to the second conductive type heavily doped source region, and the height of the entire gate electrode presents a periodic ups and downs shape.

[0010] Furthermore, the sidewalls of the non-continuous contact hole trench are vertical sidewalls, and the depth of the non-continuous contact hole trench is shallower than the height of the upper surface of the gate electrode in the adjacent cell trench.

[0011] Furthermore, the non-continuous contact hole trench has an inclined sidewall, which makes the non-continuous contact hole trench wider at the top and narrower at the bottom, and the depth of the non-continuous contact hole trench is deeper than the upper surface height of the gate electrode in the adjacent cell trench.

[0012] Furthermore, the discontinuous contact hole trench is a polygon for increasing the contact surface between the second conductivity type heavily doped source region and the side wall of the cell trench, and at least two sides or two contact points of the polygon are adjacent to the cell trenches on both sides thereof.

[0013] Furthermore, the discontinuous contact hole grooves located on both sides of the cell groove are arranged asymmetrically.

[0014] Furthermore, the discontinuous contact hole grooves include a left contact hole groove close to the left cell groove and a right contact hole groove close to the right cell groove, and the left contact hole grooves and the right contact hole grooves are alternately arranged along the cell groove direction.

[0015] Furthermore, the left contact hole trench and the right contact hole trench respectively extend toward the adjacent cell trench, and the distance D''' of the extended portion in the trench is between 0.2-0.5 um.

[0016] Furthermore, the contact hole trench is a continuous contact hole trench, the second conductive type heavily doped source region is arranged between the contact hole trench and the sidewall of the cell trench, and at least one of the continuous contact hole trenches is adjacent to the cell trenches on both sides thereof.

[0017] Furthermore, the insulating filling layer in the device is 3000A-12000A higher than the semiconductor, and the contact hole trench is located on the insulating filling layer with an opening larger than the opening on the semiconductor.

[0018] A method for preparing a field effect transistor, the method comprising the following steps: The first step is to form mutually parallel cell trenches on the second conductive semiconductor, a shielding gate electrode at the bottom of the cell trench and a thick oxide layer for isolating the shielding gate electrode from the trench, and then form an inter-electrode isolation layer located above the shielding gate electrode and a gate oxide layer located on the upper sidewall of the trench, and then form a gate electrode; The second step is to form a first conductivity type doped body region, then perform photolithography, and perform N-type ion implantation under the protection of photoresist to form a discontinuous second conductivity type heavily doped source region; The third step is to form an insulating filling layer material above the semiconductor; Step 4, removing the insulating filling layer material located above the semiconductor; The fifth step is to perform photolithography to form discontinuous contact holes and a first conductive type contact heavily doped region under the protection of a photoresist, and then form an upper surface metal layer, and finally form a device.

[0019] Furthermore, the preparation method comprises the following steps: The first step is to form mutually parallel cell trenches on the second conductive semiconductor, a shielding gate electrode at the bottom of the cell trench and a thick oxide layer for isolating the shielding gate electrode from the trench, and then form an inter-electrode isolation layer located above the shielding gate electrode and a gate oxide layer located on the upper sidewall of the trench, and then form a gate electrode; The second step is to form a first conductivity type doped body region, then perform photolithography, and perform second conductivity type ion implantation under the protection of photoresist to form a discontinuous second conductivity type heavily doped source region; The third step is to form an insulating filling layer material above the semiconductor; The fourth step is to perform photolithography to etch the insulating filling layer material between the grooves under the protection of the photoresist, wherein the spacing C'' of the photoresist at the top of the groove is not less than the distance B'' between the grooves; Step 5: etching the semiconductor to form a discontinuous contact hole, and then forming a first conductive type contact heavily doped region. The discontinuous contact hole is in a two-step shape, wherein the width C'' of the upper opening is wider than the distance B'' between the trenches, and the width of the lower opening is consistent with the distance B'' between the trenches; The sixth step is to form the upper surface metal layer and finally form the device.

[0020] Furthermore, the preparation method comprises the following steps: In the first step, a high-low structure gate electrode is formed by first filling polysilicon material, then etching back to a first height in the trench, then performing photolithography, and dry etching a portion of the polysilicon to a deeper second height under the protection of photoresist; and / or In the fifth step, one side of the discontinuous contact hole is adjacent to the trench where the lower gate electrode is located, and the depth of the contact hole is shallower than the height of the gate electrode in the trench, and the other side is adjacent to the second conductivity type heavily doped source region.

[0021] Compared with the existing device structure, the technical solution proposed by the present invention can achieve a smaller cell size, lower on-resistance and better switch threshold uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a schematic diagram of the structure of a traditional shielded gate trench field effect transistor device after removing the surface metal.

[0023] Figure 2The present invention is a top view of the structure of the trench and contact hole trench of a conventional shielded gate trench field effect transistor device.

[0024] Figure 3A FIG. 1 is a schematic structural diagram of a first embodiment of the device of the present invention.

[0025] Figure 3B It is a top view of the cell trench and contact hole trench structure in the first embodiment of the device of the present invention.

[0026] Figure 3C for Figure 3B Schematic diagram of the cross-section structure of the median tangent line L1.

[0027] Figure 4A FIG. 4 is a schematic structural diagram of another embodiment of the device of the present invention.

[0028] Figure 4B for Figure 4A Schematic diagram of the cross-section of the discontinuous contact hole groove structure in the mid-cell groove direction.

[0029] Figures 5A-5D It is a top view of the structure of the trench and contact hole trench of the device embodiment of the present invention.

[0030] Fig. 6A FIG. 4 is a schematic structural diagram of another embodiment of the device of the present invention.

[0031] Figure 6B FIG. 4 is a schematic structural diagram of another embodiment of the device of the present invention.

[0032] Figure 6C for Fig. 6A , Figure 6B Top view of the cell trench and contact hole trench structure of the device embodiment in FIG.

[0033] Fig. 7A FIG. 4 is a schematic structural diagram of another embodiment of the device of the present invention.

[0034] Figure 7B for Fig. 7A Top view of the cell trench and contact hole trench structure of the device embodiment in FIG.

[0035] Figure 7C A top view of the cell trench and contact hole trench structure of another embodiment of the device of the present invention.

[0036] FIG. 8A to FIG. 8E for Figure 4A The key steps of a method for manufacturing the device of the embodiment are shown in FIG.

[0037] FIG. 9A to FIG. 9B For the above Figure 6B The key steps of a method for manufacturing the device of the embodiment are shown in FIG.

[0038] FIG. 10A to FIG. 10B This is a key step in a method for manufacturing a device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0039] The following will explain the relevant technical background of the existing shielded gate trench field effect transistor. It should be noted that the corresponding position words such as "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", and "vertical" described in this document correspond to the relative positions of the reference diagram. The specific implementation does not limit the fixed direction. It should be noted that the devices in the drawings are not necessarily drawn to a specific scale. The straight lines shown as the boundaries of the doped regions and trenches in the drawings, as well as the sharp angles formed by the boundaries, are generally not straight lines and precise angles in actual applications.

[0040] The present invention is described in detail below in conjunction with the accompanying drawings and embodiments. It should be noted that in the following description of the shielded gate trench field effect transistor device and its manufacturing method of the present invention, the semiconductor substrate of the shielded gate trench field effect transistor device is considered to be composed of silicon (Si) material. However, the substrate can also be composed of any other material suitable for the manufacture of shielded gate trench field effect transistors, such as gallium nitride (GaN), silicon carbide (SiC), etc. In the following description, the conductivity type of the semiconductor region is divided into P type (second conductivity type) and N type (first conductivity type). A semiconductor region of P type conductivity type can be formed by doping one or more impurities into the original semiconductor region. These impurities can be but are not limited to: boron (B), aluminum (Al), gallium (Ga), etc. An N type conductive semiconductor region can also be formed by doping one or more impurities into the original semiconductor region. These impurities can be but are not limited to: phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), protons (H + ) etc. In the following description, heavily doped P-type conductive semiconductor regions are marked as P+ regions, and heavily doped N-type conductive semiconductor regions are marked as N+ regions. For example, in a silicon substrate, unless otherwise specified, the impurity concentration of a heavily doped region is generally 1 × 10 19 cm -3 Up to 1 × 10 22 cm -3 Those skilled in the art should know that the P-type (second conductivity type) and the N-type (first conductivity type) described in the present invention can be interchanged.

[0041] Figures 3A-3C Schematic diagram of the structure of the first embodiment of the device of the present invention. Figure 3B It is a top view of the structure of the cell trench 201 and the discontinuous contact hole trench 202. Figure 3C for Figure 3B Schematic diagram of the cross-section structure of the median tangent line L1.

[0042] The semiconductor field effect transistor device comprises: a series of mutually parallel cellular grooves 201 located on an N-type semiconductor 200; a P-doped body region 203 located between the cellular grooves and on the upper surface of the semiconductor; The cell trench has a gate electrode 210 and a shielding gate electrode (220) that are isolated from each other, and an insulating filling layer 211 is provided above the gate electrode 210 in the cell trench; The device also includes a series of non-continuous contact hole trenches 202 located between the series of cell trenches 201. There is a P+ contact doping region 205 below the contact hole trench 202. There is an N+ doping source region 204 between two adjacent contact hole trenches 202. The P+ contact doping region 205 and the N+ doping source region 204 are both connected to the upper surface metal through ohmic contacts.

[0043] Typically, the width of the cell groove 201 is between 0.3 um and 2 um, and the distance between adjacent cell grooves is between 0.2 um and 1.5 um.

[0044] Generally, the width of the upper surface of the non-continuous contact hole trench 202 is the width between the cell trenches 201, and the non-continuous contact hole trench 202 may be an inverted trapezoid with a larger upper portion and a smaller lower portion. The depth of the non-continuous contact hole trench 202 from the upper surface of the semiconductor is generally deeper than the height of the upper surface of the gate electrode 210, and is between 0.1 um and 1 um from the upper surface of the semiconductor.

[0045] The length of the non-continuous contact hole groove 202 along the cell groove direction is usually between 0.1 um and 1 um. The minimum distance (A') between two adjacent contact hole grooves 202 along the cell groove direction is usually between 0.05 um and 0.5 um.

[0046] like Figure 3C As shown, generally, the depth of the non-continuous contact hole trench 202 is deeper than the N+ doped source region 204. In one embodiment, the depth of the non-continuous contact hole trench 202 is 0.2-0.5 um, and the depth of the N+ doped source region 204 is 0.05-0.4 um.

[0047] The P+ contact doping region 205 located below the contact hole trench 202 has a doping source concentration of not less than 10 18 cm-3. The doping concentration of the P-doped body region 203 is usually 10 15 cm-3 to 10 18 cm-3, such as Figure 3CAs shown, generally, the P+ contact doping region 205 expands outward from the contact hole trench 202. Therefore, as the distance A' between adjacent non-continuous contact hole trenches 202 decreases, the P+ contact doping region 205 has a greater impact on the doping concentration of the P-doped body region 203 (ie, the channel region) below the N+ doped source region 204.

[0048] contrast Figure 2 and Figure 3B It can be seen from the top view of the trench structure that, compared with the conventional device, the channel structure of the device of the present invention is a discontinuous channel. Since the influence of the P+ contact doping region 205 below the contact hole trench 202 on the channel doping depends on the distance A' between adjacent discontinuous contact hole trenches 202, compared with the horizontal safety distance A in the conventional structure, the safety distance direction of the present invention changes from the horizontal direction to the vertical direction, so the distance B' between the trenches in the horizontal direction will not be limited, thereby achieving the purpose of reducing the cell size.

[0049] In one embodiment, the height of the upper surface of the gate electrode 210 located next to the contact hole trench 202 is lower than the height of the upper surface of the gate electrode 210 located next to the N+ doped source region 204. In this structure, in response to the period of the discontinuous contact hole trench 202, the height of the gate electrode 210 in the entire cell trench 201 presents periodic ups and downs. This structure is conducive to reducing gate capacitance and improving device switching performance.

[0050] Figure 4A , Figure 4B FIG. 1 is a schematic diagram of the structure of another embodiment of the device of the present invention. Figure 4B It is a schematic cross-sectional view of the non-continuous contact hole groove 202 structure along the direction of the cell groove 201.

[0051] Compared with the above-mentioned embodiment, this embodiment is different in that the sidewalls of the non-continuous contact hole trench 202 are vertical sidewalls. The depth of the non-continuous contact hole trench 202 is shallower than the upper surface height of the gate electrode 210 in the adjacent cell trench 201 .

[0052] The depth of the P+ contact doping region 205 below the non-continuous contact hole trench 202 is between 0.05 um and 0.4 um below the trench.

[0053] The N+ doped source region 204 between the non-continuous contact hole trenches 202 has a depth between 0.1 um and 0.8 um and is deeper than the top surface height of the adjacent gate electrode 210 .

[0054] Figure 5A A top view of a cell trench 201 and a discontinuous contact trench 202 structure of another embodiment of a device of the present invention is shown.

[0055] Compared with the above-mentioned embodiment, the difference of this embodiment is that the non-continuous contact hole trenches 202 and N+ doped source regions 204 at the left and right ends of the cell trench 201 are arranged differently, in a staggered arrangement. The lengths and periods of the contact hole trenches 202 and N+ doped source regions 204 at the two ends may be different. This asymmetric arrangement structure is conducive to more uniform current distribution when the device is turned on, thereby reducing the on-resistance and enhancing the reliability of the device.

[0056] In the above structure, the non-continuous contact hole trenches 202 are all quadrilateral. In fact, non-quadrilateral non-continuous contact hole trenches 202 can also be used.

[0057] Figure 5B A top view of a cell trench 201 and a discontinuous contact trench 202 structure of another embodiment of a device of the present invention is shown.

[0058] Compared with the above-mentioned embodiment, this embodiment is different in that the non-continuous contact hole trench 202 is hexagonal.

[0059] In this structure, there is a certain distance between the upper two sides and the lower two sides of the hexagonal trench 202 and the trench, which can improve the UIS capability of the device without affecting the channel resistance.

[0060] Figure 5C A top view of a cell trench 201 and a discontinuous contact trench 202 structure of another embodiment of a device of the present invention is shown.

[0061] Compared with the above-mentioned embodiment, this embodiment is different in that the non-continuous contact hole trench 202 is rhombus-shaped, and the left and right corners of the rhombus are adjacent to the cell trench 201 .

[0062] In this structure, there is a certain distance between the upper and lower sides of the hexagonal groove 202 and the groove, and the contact area between the N+ doped source region 204 and the cell groove 201 is larger. Therefore, the channel area is larger than that of the previous embodiment, and lower on-resistance can be achieved.

[0063] In one embodiment, the non-continuous contact hole trenches 202 are diamond-shaped and connected end to end.

[0064] Figure 5D A top view of a cell trench 201 and a contact hole trench 202 structure of another embodiment of the device of the present invention is shown.

[0065] Compared with the above-mentioned embodiment, this embodiment is different in that the contact hole trench 202 is a whole trench with periodic width variation, wherein the widest part of the contact hole trench 202 may be close to the adjacent cell trench 201 .

[0066] Fig. 6A , Figure 6BThe structural schematic diagrams of two other embodiments of the device of the present invention are respectively shown, and the changes are respectively Figure 3A , Figure 4A Embodiment device. Figure 6C for Fig. 6A , Figure 6B FIG. 2 is a top view of the cell trench 201 and contact hole trench 202 structures of the device embodiment.

[0067] Fig. 6A Devices and Figure 3A The device described in the example is compared to the Figure 6B Devices and Figure 4A The difference between the above devices is that: The insulating filling layer 211 in the device is 3000A-12000A higher than the semiconductor.

[0068] The discontinuous contact trench 202 structure includes a relatively large opening located on the insulating filling layer 211 and a relatively small opening located on the semiconductor.

[0069] Along the direction of the cell groove 201 , the width of the larger opening may be the same as the width of the smaller opening.

[0070] In the direction perpendicular to the cellular grooves 201 , the middle position of the larger opening is usually located in the middle between the cellular grooves 201 and is symmetrical on both sides. However, in fact, due to process limitations or other design considerations, it may also be located not in the middle and be asymmetrical on both sides.

[0071] In one embodiment, in the direction perpendicular to the cell groove 201 , the width of the larger opening is 0.3-1 um, and the width of the smaller opening is 0.1-0.5 um.

[0072] like Figure 6C As shown in the top view of the cell groove 201 and the contact hole groove 202 structure, compared with the traditional structure, the distance B'' between the cell grooves 201 in the horizontal direction is not affected by the contact hole groove width C'' and the left and right deviation of the contact hole groove lithography, so the purpose of reducing the cell size can be achieved.

[0073] Fig. 7A A schematic structural diagram of another embodiment of the device of the present invention is shown. Figure 7B It is a top view of the cell trench 201 and the contact hole trench 202 structure of the device embodiment.

[0074] Compared with the above-mentioned embodiment, this embodiment is different in that the non-continuous contact hole grooves 202 are alternately distributed left contact hole grooves and right contact hole grooves in the direction of the cell groove 201 .

[0075] There is an N+ doped source region 204 between the contact hole trench 202 and the adjacent semiconductor. The N+ doped source regions 204 are interconnected along the cell trench 201 and are distributed in an S shape.

[0076] In one embodiment, the depth of the gate electrode 210 in the cell trench 201 adjacent to the contact hole trench 202 is deeper than the depth of the contact hole trench 202 .

[0077] Compared with the previous embodiment, this structure has a higher channel density, which is beneficial to reducing the on-resistance.

[0078] like Figure 7B As shown, the width C''' of the left and right contact holes is usually smaller than the distance B''' between the cell grooves 201, which may limit the reduction of the cell size. Figure 7C An improvement scheme is presented to reduce the limitation of contact hole width on cell size.

[0079] Figure 7C It is a top view of the cell trench 201 and the contact hole trench 202 structure of another embodiment of the device of the present invention.

[0080] The structure and Figure 7B The difference of the embodiment shown is that the left and right contact holes are extended to the adjacent cell trench 201, and the distance D''' of the extended part in the trench is between 0.2-0.5 um. The extended part is located in the insulating filling layer 211 above the gate electrode 210 in the adjacent cell trench 201.

[0081] In some embodiments, the extended portions of the left and right grooves 202 at both ends of the cell groove 201 may be connected to each other.

[0082] FIG. 8A to FIG. 8E Shows the above Figure 4A The key steps of a method for manufacturing the device in the embodiment are: In the first step, mutually parallel cell trenches 201 are formed on the N-type semiconductor 200. The cell trench 201 has a shielding gate electrode 230 located at the bottom of the trench, wherein a thick oxide layer (231) is provided between the shielding gate electrode 230 and the trench. Then, an inter-electrode isolation layer 232 located above the shielding gate electrode and a gate oxide layer located on the upper sidewall of the trench are formed. After that, a gate electrode 210 is formed. The distance from the gate electrode to the upper surface of the semiconductor is between 0.2um and 0.7um, such as Fig. 8A shown.

[0083] In the second step, a P-doped body region 203 is formed, and then photolithography is performed, and N-type ion implantation is performed under the protection of photoresist to form a discontinuous N+ doped source region 204, such as Figure 8B As shown. Among them, Figure 8BThe left picture shows the contact hole trench area, and the right picture shows the non-contact hole trench area.

[0084] In the third step, an insulating filling layer material 211 is formed above the semiconductor, such as Figure 8C As shown. Figure 8C The left picture shows the contact hole trench area, and the right picture shows the non-contact hole trench area. The insulating filling layer material 211 may be an oxide layer, and is formed by a deposition method.

[0085] In the fourth step, chemical mechanical polishing is performed to remove the insulating filling layer material 211 located above the semiconductor. Fig.8D As shown. Fig.8D The left picture shows the contact hole trench area, and the right picture shows the non-contact hole trench area. In some embodiments, the chemical mechanical polishing may use a pre-formed nitride layer between the trenches as a stop layer.

[0086] The fifth step is to perform photolithography to form a discontinuous contact hole 202 and a P+ contact doping region 205 under the protection of a photoresist, and then form an upper surface metal layer 233, and finally form a device. Fig. 8E As shown. Fig.8D The left picture shows the contact hole trench area, and the right picture shows the non-contact hole trench area.

[0087] In one embodiment, the second step may be placed between the fourth step and the fifth step.

[0088] FIG. 9A to FIG. 9B Shows the above Figure 6B The key steps of a method for manufacturing a device in the embodiment are as follows. FIG. 8A to FIG. 8E The first three steps of the display are the same, the difference is: The fourth step is to perform photolithography to etch the insulating filling layer material 211 between the grooves under the protection of the photoresist. Fig. 9A As shown. Fig. 9A The left picture shows the contact hole groove area, and the right picture shows the non-contact hole groove area. The etching method may be dry etching, or dry etching may be performed first and then wet etching. Generally, the spacing C'' of the photoresist at the top of the groove is not less than the distance B'' between the grooves. In some embodiments, before performing photolithography, chemical mechanical grinding or reflow process may be performed first to make the upper surface of the insulating filling layer material 211 flat.

[0089] In the fifth step, the semiconductor is etched to form a discontinuous contact hole 202, and then a P+ contact doping region 205 is formed. Fig. 9B As shown. Fig. 9BThe left picture shows the contact hole groove area, and the right picture shows the non-contact hole groove area. As shown in the figure, the non-continuous contact hole 202 is a two-step shape, wherein the width C'' of the upper opening is wider than the distance B'' between the grooves, and the width of the lower opening is consistent with the distance B'' between the grooves.

[0090] The sixth step is to form the upper surface metal layer and finally form the device.

[0091] FIG. 10A to FIG. 10B The key steps of a manufacturing method of a device according to another embodiment of the present invention are shown. The structure of the contact hole trench area is shown in the figure. The key steps of the manufacturing method and FIG. 9A to FIG. 9B The manufacturing method of the device of the embodiment shown is different in that: In the first step, the gate electrode 210 is formed to have different height structures in the trench, such as Fig. 10A The steps of forming the gate electrode 210 of the high-low structure may be: first fill the polysilicon material, then etch back to the first height in the trench, then perform photolithography, and dry-etch a portion of the polysilicon to a deeper second height under the protection of the photoresist.

[0092] In the second step, the N+ type and P type ion implantation may be performed after etching back the polysilicon to the first height in the first step and before photolithography.

[0093] In the fourth step, the opening position of the photoresist after photolithography is located between adjacent trenches on one side and above the trench where the lower gate electrode 210 is located on the other side. The opening size C''' may be wider than the distance B''' between the trenches, such as Fig. 10B shown.

[0094] In the fifth step, the discontinuous contact hole 202 is adjacent to the trench where the lower gate electrode 210 is located on one side, and the depth of the contact hole is shallower than the height of the gate electrode in the trench, and is adjacent to the N+ doped source region 204 on the other side. In one embodiment, the arrangement of the discontinuous contact holes 202 may be as follows: Figure 7C Shown as top view.

[0095] Those skilled in the art should know that the above manufacturing steps only list key steps and do not show the complete steps of forming a device. Specific detailed manufacturing steps can be obtained based on common manufacturing process steps and common sense knowledge in the field and can be appropriately increased, decreased or changed.

[0096] In addition, those skilled in the art should know that the structural features and process steps mentioned in the above-mentioned embodiments of the present invention can be combined with each other to form more embodiment device structures and manufacturing processes.

Claims

1. A power field effect transistor device, comprising a series of mutually parallel cellular trenches located on a second conductive semiconductor, a first conductive type doped body region located on the upper surface of the second conductive semiconductor between the cellular trenches, wherein the cellular trenches contain mutually isolated shielding gate electrodes, gate electrodes, and an insulating filling layer located above the gate electrodes; characterized in that: A contact hole groove and a second conductive type heavily doped source region are provided above the first conductive type doped body region and between the contact hole grooves; a first conductive type heavily doped contact region is provided below the contact hole groove; and both the first conductive type heavily doped contact region and the second conductive type heavily doped source region are connected to the upper surface metal through ohmic contact.

2. The field effect transistor device according to claim 1, characterized in that: The contact hole trench is a discontinuous contact hole trench, and the second conductive type heavily doped source region is arranged between the discontinuous contact hole trenches; or The contact hole trench is a continuous contact hole trench, the second conductive type heavily doped source region (204) is arranged between the contact hole trench and the side wall of the cell trench, and at least one of the continuous contact hole trenches is adjacent to the cell trenches on both sides thereof.

3. The field effect transistor device according to claim 2, characterized in that: The depth of the non-continuous contact hole trench is deeper than the second conductivity type heavily doped source region, and / or the first conductivity type heavily doped contact region expands outward from the contact hole trench to below the second conductivity type heavily doped source region.

4. The field effect transistor device according to claim 2, characterized in that: The height of the upper surface of the gate electrode located next to the contact hole trench is lower than that of the upper surface of the gate electrode located next to the second conductive type heavily doped source region, and the height of the entire gate electrode presents a periodic ups and downs shape.

5. The field effect transistor device according to claim 2, characterized in that: The sidewalls of the non-continuous contact hole trench are vertical sidewalls, and the depth of the non-continuous contact hole trench is shallower than the upper surface height of the gate electrode in the adjacent cell trench; or The non-continuous contact hole groove has an inclined sidewall, which makes the non-continuous contact hole groove wider at the top and narrower at the bottom. The depth of the non-continuous contact hole groove is deeper than the upper surface height of the gate electrode in the adjacent cell groove.

6. The field effect transistor device according to claim 2, characterized in that: The discontinuous contact hole trench is a polygon used to increase the contact surface between the second conductive type heavily doped source region and the side wall of the cell trench, and at least two sides or two contact points of the polygon are adjacent to the cell trenches on both sides thereof.

7. The field effect transistor device according to claim 2, characterized in that: The discontinuous contact hole grooves located on both sides of the cell groove are arranged asymmetrically.

8. The field effect transistor device according to claim 2, characterized in that: The discontinuous contact hole grooves include a left contact hole groove close to the left cell groove and a right contact hole groove close to the right cell groove. The left contact hole grooves and the right contact hole grooves are alternately arranged in the direction of the cell grooves.

9. The field effect transistor device according to claim 8, characterized in that: The left contact hole groove and the right contact hole groove respectively extend toward the adjacent cell grooves, and the distance D''' of the extended part in the groove is between 0.2-0.5 um.

10. The field effect transistor device according to claim 1, characterized in that: The insulating filling layer in the device is 3000A-12000A higher than the semiconductor, and the contact hole trench is located on the insulating filling layer and the opening is larger than the opening on the semiconductor.

11. A method for preparing a power field effect transistor, characterized in that: The preparation method comprises the following steps: The first step is to form mutually parallel cell trenches on the second conductive semiconductor, a shielding gate electrode at the bottom of the cell trench and a thick oxide layer for isolating the shielding gate electrode from the trench, and then form an inter-electrode isolation layer located above the shielding gate electrode and a gate oxide layer located on the upper sidewall of the trench, and then form a gate electrode; The second step is to form a first conductivity type doped body region, then perform photolithography, and perform N-type ion implantation under the protection of photoresist to form a discontinuous second conductivity type heavily doped source region; The third step is to form an insulating filling layer material above the semiconductor; Step 4, removing the insulating filling layer material located above the semiconductor; The fifth step is to perform photolithography to form discontinuous contact holes and a first conductive type contact heavily doped region under the protection of a photoresist, and then form an upper surface metal layer, and finally form a device.

12. The method for preparing a power field effect transistor according to claim 11, characterized in that: The preparation method comprises the following steps: The first step is to form mutually parallel cell trenches on the second conductive semiconductor, a shielding gate electrode at the bottom of the cell trench and a thick oxide layer for isolating the shielding gate electrode from the trench, and then form an inter-electrode isolation layer located above the shielding gate electrode and a gate oxide layer located on the upper sidewall of the trench, and then form a gate electrode; The second step is to form a first conductivity type doped body region, then perform photolithography, and perform second conductivity type ion implantation under the protection of photoresist to form a discontinuous second conductivity type heavily doped source region; The third step is to form an insulating filling layer material above the semiconductor; The fourth step is to perform photolithography to etch the insulating filling layer material between the grooves under the protection of the photoresist, wherein the spacing C'' of the photoresist at the top of the groove is not less than the distance B'' between the grooves; Step 5: etching the semiconductor to form a discontinuous contact hole, and then forming a first conductive type contact heavily doped region. The discontinuous contact hole is in a two-step shape, wherein the width C'' of the upper opening is wider than the distance B'' between the trenches, and the width of the lower opening is consistent with the distance B'' between the trenches; The sixth step is to form the upper surface metal layer and finally form the device.

13. The method for preparing a power field effect transistor according to claim 11, characterized in that: The preparation method comprises the following steps: In the first step, a high-low structure gate electrode is formed by first filling polysilicon material, then etching back to a first height located in the trench, then performing photolithography, and dry etching a portion of the polysilicon to a deeper second height under the protection of photoresist; and / or In the fifth step, one side of the discontinuous contact hole is adjacent to the trench where the lower gate electrode is located, and the depth of the contact hole is shallower than the height of the gate electrode in the trench, and the other side is adjacent to the second conductivity type heavily doped source region.

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