Semiconductor device

Abstract

The invention relates to a semiconductor device. Provided is a semiconductor device having high reliability. The semiconductor device includes: a gate electrode; an oxide semiconductor layer having a polycrystalline structure; a gate insulating layer between the gate electrode and the oxide semiconductor layer; and a source electrode and a drain electrode on the oxide semiconductor layer, the oxide semiconductor layer including: a source region containing an impurity element and electrically connected to the source electrode; a drain region that contains an impurity element and is electrically connected to the drain electrode; a channel region between the source region and the drain region; and a first region that includes a first edge portion extending in a first direction from the source region toward the drain region and is adjacent to the channel region, the first region having a higher electrical resistivity than each of the source region and the drain region, and an etching rate of less than 3 nm / min when the oxide semiconductor layer is etched using an etching solution containing phosphoric acid as a main component at 40 DEG C.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device using an oxide semiconductor having a polycrystalline structure. Background Art

[0002] In recent years, instead of using silicon semiconductor films such as amorphous silicon, low-temperature polycrystalline silicon and single crystal silicon, the development of semiconductor devices including oxide semiconductor films has been continuously developed (for example, see Patent Documents 1 to 6). Like semiconductor devices including amorphous silicon films, semiconductor devices including oxide semiconductor films have a simple structure and can be formed by a low-temperature process. In addition, it is known that semiconductor devices including oxide semiconductor films have higher field effect mobility than semiconductor devices including amorphous silicon films.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-141338

[0006] Patent Document 2: Japanese Patent Application Publication No. 2014-099601

[0007] Patent Document 3: Japanese Patent Application Publication No. 2021-153196

[0008] Patent Document 4: Japanese Patent Application Publication No. 2018-006730

[0009] Patent Document 5: Japanese Patent Application Publication No. 2016-184771

[0010] Patent Document 6: Japanese Patent Application Publication No. 2021-108405 Summary of the invention

[0011] Problems to be solved by the invention

[0012] A semiconductor device is required to have not only high field effect mobility but also high reliability. One object of one embodiment of the present invention is to provide a semiconductor device having high reliability.

[0013] Means for solving problems

[0014] A semiconductor device according to one embodiment of the present invention includes: a gate electrode; an oxide semiconductor layer having a polycrystalline structure; a gate insulating layer between the gate electrode and the oxide semiconductor layer; a source electrode on the oxide semiconductor layer; and a drain electrode on the oxide semiconductor layer, wherein the oxide semiconductor layer includes: a source region containing an impurity element and electrically connected to the source electrode; a drain region containing an impurity element and electrically connected to the drain electrode; a channel region between the source region and the drain region; and a first region including a first edge extending along a first direction from the source region toward the drain region and adjacent to the channel region, the first region having a resistivity higher than that of the source region and the drain region, and an etching rate of the oxide semiconductor layer when the oxide semiconductor layer is etched using an etching solution containing phosphoric acid as a main component at 40° C. is less than 3 nm / min.

[0015] A semiconductor device according to one embodiment of the present invention includes: a gate electrode extending in a first direction; an oxide semiconductor layer having a polycrystalline structure, which includes a first edge portion and a second edge portion extending in a second direction intersecting the first direction; a gate insulating layer between the gate electrode and the oxide semiconductor layer; a source electrode on the oxide semiconductor layer; and a drain electrode on the oxide semiconductor layer, wherein the oxide semiconductor layer includes: a first region overlapping with the gate electrode when viewed from above; a source region adjacent to the first region and including an impurity element and electrically connected to the source electrode via a first contact hole; and a drain region adjacent to the first region and including an impurity element and electrically connected to the source electrode via a second contact hole. The invention relates to a semiconductor device comprising a semiconductor layer and a semiconductor material, wherein the semiconductor layer is electrically connected to the drain electrode; a second region surrounded by the source region and including the first portion of the first edge; a third region surrounded by the source region and including the first portion of the second edge; a fourth region surrounded by the drain region and including the second portion of the first edge; and a fifth region surrounded by the drain region and including the second portion of the second edge, wherein each of the first region, the second region, the third region, the fourth region and the fifth region has a higher resistivity than each of the source region and the drain region, and an etching rate of the oxide semiconductor layer when the oxide semiconductor layer is etched using an etching solution containing phosphoric acid as a main component at 40°C is less than 3 nm / min.

[0016] A semiconductor device according to an embodiment of the present invention includes: a gate electrode extending in a first direction; an oxide semiconductor layer having a polycrystalline structure, the oxide semiconductor layer including a first edge portion and a second edge portion extending in a second direction intersecting the first direction; a gate insulating layer between the gate electrode and the oxide semiconductor layer; a source electrode on the oxide semiconductor layer; and a drain electrode on the oxide semiconductor layer, the oxide semiconductor layer including: a first region overlapping the gate electrode in a plan view; a source region adjacent to the first region and including an impurity element and electrically connected to the source electrode via a first contact hole; a drain region adjacent to the first region and including an impurity element and electrically connected to the drain electrode via a second contact hole, the first region having a resistivity higher than that of the source region and the drain region, a first distance along the first direction from the first edge portion to the first contact hole in a plan view is greater than a second distance along the second direction from the first region to the first contact hole, and an etching rate of the oxide semiconductor layer when the oxide semiconductor layer is etched using an etching solution including phosphoric acid as a main component at 40° C. is less than 3 nm / min. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] [ Figure 1 ] is a schematic cross-sectional view showing the structure of a semiconductor device involved in one embodiment of the present invention.

[0018] [ Figure 2 ] is a schematic top view showing the structure of an oxide semiconductor layer of a semiconductor device involved in one embodiment of the present invention.

[0019] [ Figure 3A ] is a schematic cross-sectional view showing a method for forming a source region and a drain region in an oxide semiconductor layer of a semiconductor device according to one embodiment of the present invention.

[0020] [ Figure 3B ] is a schematic cross-sectional view showing a method for forming a source region and a drain region in an oxide semiconductor layer of a semiconductor device according to one embodiment of the present invention.

[0021] [ Figure 4 ] is a schematic top view showing the structure of an oxide semiconductor layer of a semiconductor device involved in a modified example of one embodiment of the present invention.

[0022] [ Figure 5 ] is a schematic cross-sectional view showing a method for forming a source region and a drain region in an oxide semiconductor layer of a semiconductor device involved in a modified example of one embodiment of the present invention.

[0023] [ Figure 6 ] is a schematic top view showing the structure of an oxide semiconductor layer of a semiconductor device involved in a modified example of one embodiment of the present invention.

[0024] [ Figure 7 ] is a schematic top view showing the structure of an oxide semiconductor layer of a semiconductor device involved in a modified example of one embodiment of the present invention.

[0025] [ Figure 8 ] is a schematic top view showing the structure of an oxide semiconductor layer of a semiconductor device involved in a modified example of one embodiment of the present invention.

[0026] [ Fig. 9 ] is a cross-sectional view showing the structure of a semiconductor device involved in a modified example of one embodiment of the present invention.

[0027] [ Fig.10 ] is a schematic top view showing the structure of an oxide semiconductor layer of a semiconductor device involved in one embodiment of the present invention.

[0028] [ Fig.11 ] is a schematic top view showing the structure of an oxide semiconductor layer of a semiconductor device involved in one embodiment of the present invention.

[0029] [ Fig.12 ] is a schematic top view showing the structure of an oxide semiconductor layer of a semiconductor device involved in a modified example of one embodiment of the present invention.

[0030] [ Fig.13 ] is a schematic top view showing the structure of an oxide semiconductor layer of a semiconductor device involved in one embodiment of the present invention.

[0031] [ Fig.14A ] is a schematic cross-sectional view showing the structure of a semiconductor device involved in one embodiment of the present invention.

[0032] [ Fig. 14B ] is a schematic cross-sectional view showing the structure of a semiconductor device involved in one embodiment of the present invention.

[0033] [ Fig.15A ] is a schematic cross-sectional view showing a method for manufacturing an oxide semiconductor layer of a semiconductor device involved in one embodiment of the present invention.

[0034] [ Fig. 15B ] is a schematic cross-sectional view showing a method for manufacturing an oxide semiconductor layer of a semiconductor device involved in one embodiment of the present invention.

[0035] [ Fig. 15C ] is a schematic cross-sectional view showing a method for manufacturing an oxide semiconductor layer of a semiconductor device involved in one embodiment of the present invention.

[0036] [ Fig.16 ] is a schematic cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0037] Description of Reference Numerals

[0038] 1, 10, 10A: semiconductor device, 100: substrate, 110: first insulating layer, 120: light shielding layer, 130: second insulating layer, 135: metal oxide layer, 140: oxide semiconductor layer, 141: channel region, 142: source region, 143: drain region, 145: oxide semiconductor film, 150: gate insulating layer, 160: gate electrode, 170: third insulating layer, 180: source electrode, 190: drain electrode, 210: base insulating layer, 220: light shielding layer, 240: silicon semiconductor layer, 250: gate insulating layer, 255: insulating layer, 260: gate electrode, 280: source electrode, 290: drain electrode, 310: source Line, 320: protective insulating layer, 330: first planarization layer, 340: connection electrode, 350: second planarization layer, 360: element electrode, A1: first region, A2: second region, A2-1: second-1 region, A2-2: second-2 region, A3: third region, A3-1: third-1 region, A3-2: third-2 region, CH1, CH2, CH3, CH4, CH5, CH6: contact hole, E1: first edge, E2: second edge, M1: first metal layer, M2: second metal layer, M3: third metal layer, M4: fourth metal layer, R1, R2: resist, TR1: first transistor, TR2: second transistor DETAILED DESCRIPTION

[0039] The following describes various embodiments of the present invention with reference to the accompanying drawings. The following disclosure is only an example. The configuration that can be easily thought of by those skilled in the art by appropriately changing the configuration of the embodiment while maintaining the main purpose of the invention is of course included in the scope of the present invention. With respect to the accompanying drawings, in order to make the description clearer, the width, film thickness and shape of the constituent elements are sometimes schematically indicated compared to the actual method. However, the illustrated shape is only an example and does not limit the interpretation of the present invention. In this specification and the accompanying drawings, for the constituent elements that are the same as the constituent elements described in the accompanying drawings that have appeared, there is a situation where the same figure mark is marked and the detailed description is appropriately omitted.

[0040] In this specification, etc., the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "above". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "below". Like this, for the convenience of explanation, the phrases "above" or "below" are used for explanation, and the up-and-down relationship between the substrate and the oxide semiconductor layer can also be configured in the opposite direction to that shown in the figure. In addition, as for the expression "oxide semiconductor layer on the substrate", it is only to explain the up-and-down relationship between the substrate and the oxide semiconductor layer, and other components can also be configured between the substrate and the oxide semiconductor layer. Above or below refers to the stacking order in a structure in which multiple layers are stacked. In the case of expressing "pixel electrode above the semiconductor device", it can also be a positional relationship in which the semiconductor device and the pixel electrode do not overlap when viewed from above. On the other hand, in the case of expressing "pixel electrode vertically above the semiconductor device", it indicates the positional relationship in which the semiconductor device and the pixel electrode overlap when viewed from above. It should be noted that viewing from above refers to viewing from a direction perpendicular to the surface of the substrate.

[0041] In this specification, unless otherwise specified, expressions such as “α includes A, B, or C”, “α includes any one of A, B, and C”, and “α includes one selected from the group consisting of A, B, and C” do not exclude the case where α includes a plurality of combinations of A to C. Furthermore, these expressions do not exclude the case where α includes other constituent elements.

[0042] In this specification, "semiconductor device" refers to all devices that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are included in one embodiment of a semiconductor device. The semiconductor device of the embodiment shown below can be, for example, a display device, an integrated circuit (IC) such as a microprocessor (MPU), or a transistor used in a memory circuit.

[0043] In this specification, etc., "display device" refers to a structure that uses an electro-optical layer to display an image. For example, the term display device sometimes refers to a display panel including an electro-optical layer, or sometimes refers to a structure on which other optical components (such as polarizing components, backlight sources, touch panels, etc.) are installed on a display unit. As long as there is no technical contradiction, the "electro-optical layer" can include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer.

[0044] In this specification and the like, the term "film" and the term "layer" can be used interchangeably as appropriate.

[0045] It should be noted that the following embodiments can be combined with each other as long as there is no technical contradiction.

[0046] <First embodiment>

[0047] Reference Figure 1 to Figure 3B A semiconductor device 10 according to an embodiment of the present invention will be described.

[0048] [1. Configuration of Semiconductor Device 10]

[0049] Figure 1 It is a schematic cross-sectional view showing the structure of a semiconductor device 10 according to one embodiment of the present invention.

[0050] like Figure 1 As shown, the semiconductor device 10 includes a substrate 100, a first insulating layer 110, a light shielding layer 120, a second insulating layer 130, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, a third insulating layer 170, a source electrode 180, and a drain electrode 190. The first insulating layer 110 is disposed on the substrate 100. The light shielding layer 120 is disposed on the first insulating layer 110. The second insulating layer 130 covers the upper surface and end surface of the light shielding layer 120 and is disposed on the first insulating layer 110. The oxide semiconductor layer 140 is disposed on the second insulating layer 130. The gate insulating layer 150 covers the upper surface and end surface of the oxide semiconductor layer 140 and is disposed on the second insulating layer 130. The gate electrode 160 overlaps with the oxide semiconductor layer 140 and is disposed on the gate insulating layer 150. The third insulating layer 170 covers the upper surface and end surface of the gate electrode 160 and is provided on the gate insulating layer 150. The source electrode 180 and the drain electrode 190 are provided on the third insulating layer 170. The source electrode 180 is connected to the oxide semiconductor layer 140 via a contact hole CH1 penetrating the gate insulating layer 150 and the third insulating layer 170. The drain electrode 190 is connected to the oxide semiconductor layer 140 via a contact hole CH2 penetrating the gate insulating layer 150 and the third insulating layer 170. The source electrode 180 and the drain electrode 190 are electrically connected to the oxide semiconductor layer 140.

[0051] The substrate 100 can support each layer constituting the semiconductor device 10. For example, as the substrate 100, a glass substrate, a quartz substrate, a sapphire substrate or other light-transmitting rigid substrate can be used. In addition, as the substrate 100, a silicon substrate or other non-light-transmitting rigid substrate can also be used. In addition, as the substrate 100, a polyimide resin substrate, an acrylic resin substrate, a siloxane resin substrate, a fluororesin substrate or other light-transmitting flexible substrate can be used. In order to improve the heat resistance of the substrate 100, impurities can be introduced into the flexible substrate.

[0052] The first insulating layer 110 can suppress diffusion of impurities from the substrate 100 or the outside. For example, silicon oxide (SiO x), silicon oxide nitride (SiO x N y ), aluminum oxide (AlO x ), or aluminum oxide nitride (AlO x N y ) or silicon nitride (SiN x ), silicon oxide nitride (SiN x O y ), aluminum nitride (AlN x ), or aluminum nitride (AlN x O y The first insulating layer 110 may have a single-layer structure or a stacked-layer structure.

[0053] Here, silicon oxide nitride (SiO x N y ) and aluminum oxide nitride (AlO x N y ) are each an oxide containing nitrogen (N) at a ratio (x>y) less than oxygen (O). x O y ) and aluminum nitride (AlN x O y ) is a nitride containing oxygen at a ratio less than nitrogen (x>y). It should be noted that for convenience of explanation, silicon oxide (SiO x ) and silicon oxide nitride (SiO x N y ) is referred to as "silicon oxide", and silicon nitride (SiN x ) and silicon oxide nitride (SiN x O y ) is referred to as "silicon nitride". Similarly, aluminum oxide (AlO x ) and aluminum oxide nitride (AlO x N y ) is referred to as "aluminum oxide", aluminum nitride (AlN x ) and aluminum nitride (AlN x O y ) is referred to as "aluminum nitride".

[0054] The light-shielding layer 120 can reflect or absorb light incident from the substrate 100 side. In other words, the light-shielding layer 120 can block light incident on the oxide semiconductor layer 140. For example, as the light-shielding layer 120, metals such as aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo) or tungsten (W), or alloys thereof or compounds thereof, etc. can be used. In addition, when the light-shielding layer 120 does not need to be conductive, the light-shielding layer 120 may not contain metal. When the light-shielding layer 120 does not contain metal, a black matrix made of black resin can be used as the light-shielding layer 120. The light-shielding layer 120 may have a single-layer structure or a stacked structure. For example, the light-shielding layer 120 may also have a stacked structure including a red filter, a green filter and a blue filter.

[0055] The second insulating layer 130 can suppress the diffusion of impurities from the light shielding layer 120. In addition, when the light shielding layer 120 has conductivity, the second insulating layer 130 can electrically insulate the light shielding layer 120 from the oxide semiconductor layer 140. For example, as the second insulating layer 130, the same oxide or nitride as the first insulating layer 110 can be used. The second insulating layer 130 can have a single-layer structure or a stacked structure. For example, the second insulating layer 130 can also have a stacked structure including a silicon oxide film and a silicon nitride film.

[0056] The detailed structure of the oxide semiconductor layer 140 is described later, but if the oxide semiconductor layer 140 is in contact with a nitride, oxygen defects are sometimes generated in the oxide semiconductor layer 140, or hydrogen is supplied to the oxide semiconductor layer 140. In this case, the conductivity of the oxide semiconductor layer 140 becomes higher, and the semiconductor characteristics of the oxide semiconductor layer 140 are lost. Therefore, in the second insulating layer 130 in contact with the oxide semiconductor layer 140, it is preferable to use an oxide. Specifically, when the second insulating layer 130 has a stacked structure including a silicon oxide film and a silicon nitride film, a silicon oxide film is provided on the silicon nitride film in such a manner that the silicon oxide film is in contact with the oxide semiconductor layer 140.

[0057] The gate insulating layer 150 is located between the oxide semiconductor layer 140 and the gate electrode 160, and can electrically insulate the oxide semiconductor layer 140 from the gate electrode 160. As the gate insulating layer 150, an oxide or a nitride similar to the first insulating layer 110 can be used. The gate insulating layer 150 may have a single layer structure or a stacked structure.

[0058] As described above, when the oxide semiconductor layer 140 is in contact with a nitride, hydrogen may be supplied to the oxide semiconductor layer 140. Therefore, an oxide is preferably used for the gate insulating layer 150 in contact with the oxide semiconductor layer 140. Specifically, as the gate insulating layer 150, silicon oxide can be used.

[0059] The gate electrode 160 functions as an electrode for forming a channel in the oxide semiconductor layer 140. For example, a metal such as copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or an alloy or compound thereof can be used as the gate electrode 160. The gate electrode 160 may have a single-layer structure or a stacked structure.

[0060] The third insulating layer 170 can suppress diffusion of impurities from the outside. For example, the third insulating layer 170 can be made of the same oxide or nitride as the first insulating layer 110. The third insulating layer 170 may have a single-layer structure or a stacked-layer structure.

[0061] The source electrode 180 and the drain electrode each function as an input electrode or an output electrode of the current flowing through the oxide semiconductor layer 140. For example, the same metal, alloy, or compound as the gate electrode can be used as the source electrode 180 and the drain electrode 190. The source electrode 180 and the drain electrode may have a single-layer structure or a stacked structure.

[0062] The semiconductor device 10 described above is a so-called top-gate transistor. The semiconductor device 10 can be variously deformed. For example, when the light shielding layer 120 is conductive, the semiconductor device 10 can be a structure in which the light shielding layer 120 functions as a gate electrode and the second insulating layer 130 functions as a gate insulating layer. In this case, the semiconductor device 10 is a so-called dual-gate transistor. In addition, when the light shielding layer 120 is conductive, the light shielding layer 120 can be a floating electrode or can be connected to the source electrode 180. In addition, the semiconductor device 10 can also be a so-called bottom-gate transistor in which the light shielding layer 120 functions as a main gate electrode.

[0063] [2. Configuration of Oxide Semiconductor Layer 140]

[0064] [2-1. Composition of Oxide Semiconductor Layer 140]

[0065] An oxide semiconductor containing two or more metal elements including indium (In) can be used as the oxide semiconductor layer 140. As metal elements other than indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), and lanthanide elements can be used.

[0066] The oxide semiconductor layer 140 is light-transmissive and has a polycrystalline structure including a plurality of crystal grains. In order to make the oxide semiconductor layer 140 have a polycrystalline structure, it is preferred to use an oxide semiconductor in which the ratio of indium to all metal elements is 50% or more in terms of atomic ratio. If the ratio of indium increases, the oxide semiconductor layer 140 is easily crystallized. In addition, as a metal element other than indium, gallium is preferably included. Gallium belongs to the same Group 13 element as indium. Therefore, the crystallinity of the oxide semiconductor layer 140 is hardly hindered by gallium.

[0067] The oxide semiconductor layer 140 has properties different from those of conventional oxide semiconductors having a polycrystalline structure, which will be described in detail later. Therefore, in order to distinguish the oxide semiconductor included in the oxide semiconductor layer 140 from conventional oxide semiconductors having a polycrystalline structure, the oxide semiconductor included in the oxide semiconductor layer 140 is referred to as Poly-OS (Poly-crystalline Oxide Semiconductor) for description below.

[0068] The Poly-OS included in the oxide semiconductor layer 140 can be formed by using a sputtering method and a heat treatment. Here, a method for forming the oxide semiconductor layer 140 is described.

[0069] First, an oxide semiconductor film is formed using a sputtering method. The formed oxide semiconductor film has an amorphous structure. Here, an amorphous structure refers to a structure in which there is no long-range ordered structure and no periodic lattice arrangement can be seen. For example, if an oxide semiconductor film having an amorphous structure is observed using an X-ray diffraction (XRD) method, no specific peak based on the crystal structure can be obtained in the diffraction pattern. It should be noted that an oxide semiconductor film having an amorphous structure sometimes has a short-range ordered structure in a tiny area. However, such an oxide semiconductor film does not show the characteristics of Poly-OS and can therefore be classified as an oxide semiconductor film having an amorphous structure.

[0070] The oxide semiconductor film having an amorphous structure is formed at a low temperature. For example, the temperature of the substrate for forming the oxide semiconductor film is below 150°C, preferably below 100°C, and more preferably below 50°C. If the temperature of the substrate is high, microcrystals are easily generated in the formed oxide semiconductor. In addition, the oxygen partial pressure in the chamber during film formation is above 1% and below 10%, preferably above 1% and below 5%, and more preferably above 2% and below 4%. If the oxygen partial pressure is high, microcrystals are generated in the oxide semiconductor film due to the excess oxygen contained in the oxide semiconductor. On the other hand, under the condition that the oxygen partial pressure is less than 1%, the oxygen composition in the oxide semiconductor film becomes uneven, forming an oxide semiconductor film containing a large number of microcrystals, or an oxide semiconductor film that does not crystallize even after heat treatment.

[0071] Next, the oxide semiconductor film formed by sputtering is subjected to heat treatment. The heat treatment is performed in the air, but the atmosphere for the heat treatment is not limited thereto. The temperature for the heat treatment is between 300°C and 500°C, preferably between 350°C and 450°C. In addition, the heat treatment time is between 15 minutes and 120 minutes, preferably between 30 minutes and 60 minutes. By performing the heat treatment, the oxide semiconductor film having an amorphous structure is crystallized to form an oxide semiconductor layer 140 containing Poly-OS.

[0072] The composition of the oxide semiconductor layer 140 is roughly consistent with the composition of the sputtering target. Therefore, the composition of the metal elements of the oxide semiconductor layer 140 can be determined based on the composition of the metal elements of the sputtering target. In addition, the composition of the oxide semiconductor layer 140 can also be determined using the XRD method. Specifically, based on the crystal structure and lattice constant of the oxide semiconductor layer 140 obtained by the XRD method, the composition of the metal elements of the oxide semiconductor layer 140 can be determined. In addition, the composition of the metal elements of the oxide semiconductor layer 140 can be determined using fluorescent X-ray analysis or electron probe microanalyzer (Electron Probe MicroAnalyzer: EPMA) analysis, etc. It should be noted that the oxygen contained in the oxide semiconductor layer 140 varies depending on the process conditions of the sputtering method, etc., so there is no limitation.

[0073] [2-2. Characteristics of Oxide Semiconductor Layer 140]

[0074] Next, the characteristics of the oxide semiconductor layer 140 including Poly-OS are described.

[0075] The oxide semiconductor layer 140 has excellent etching resistance. Specifically, with respect to the oxide semiconductor layer 140, the etching rate when etching is performed using an etching solution for wet etching is very small. This means that the oxide semiconductor layer 140 is hardly etched by the etching solution. When the oxide semiconductor layer 140 is etched using an etching solution containing phosphoric acid as a main component (hereinafter referred to as a "mixed acid etching solution") at 40°C, the etching rate is less than 3nm / min, less than 2nm / min, or less than 1nm / min. The proportion of phosphoric acid in the mixed acid etching solution is greater than 50%, greater than 60%, or greater than 70%. In addition to phosphoric acid, the mixed acid etching solution may also contain acetic acid and nitric acid. For an oxide semiconductor film that does not contain Poly-OS, such as an oxide semiconductor film having an amorphous structure before heat treatment, the etching rate when the oxide semiconductor film is etched using a mixed acid etching solution at 40°C is greater than 100nm / min. In addition, the etching rate when the oxide semiconductor layer 140 is etched using a 0.5% hydrofluoric acid solution at room temperature is less than 5 nm / min, less than 4 nm / min, or less than 3 nm / min. It should be noted that, for an oxide semiconductor film that does not include Poly-OS, the etching rate when the oxide semiconductor film is etched using a 0.5% hydrofluoric acid solution at room temperature is greater than 15 nm / min. Here, "40°C" refers to 40±5°C, which can be the temperature of the etching solution or the set temperature of the etching solution. In addition, "room temperature" refers to 25±5°C.

[0076] An embodiment of the oxide semiconductor layer 140 is shown in Table 1. Table 1 shows the etching rates of each sample produced in a mixed acid etching solution ("Mixed Acid AT-2F" manufactured by Rasa Industries, Ltd. in which the ratio of phosphoric acid in the mixed acid etching solution is 65%) and a 0.5% hydrofluoric acid solution. In addition, when etching each sample, the temperature of the mixed acid etching solution is 40°C, and the temperature of the 0.5% hydrofluoric acid solution is room temperature (22°C). In Table 1, sample 1 is an oxide semiconductor layer 140 including Poly-OS, sample 2 is an oxide semiconductor film having an amorphous structure before heat treatment, and sample 3 is an oxide semiconductor film including indium gallium zinc oxide (IGZO) in which the ratio of indium is less than 50%.

[0077] [Table 1]

[0078] Mixed acid etching solution 0.5% hydrofluoric acid solution Sample 1 <0.1nm / min <2nm / min Sample 2 111nm / min >18nm / min Sample 3 162nm / min -

[0079] As shown in Table 1, for Sample 1 (the oxide semiconductor layer 140 containing Poly-OS), it is hardly etched using a mixed acid etching solution, and even using a 0.5% hydrofluoric acid solution, it is etched at a maximum rate of only 2 nm / min. In the etching using a mixed acid etching solution, the etching rate of Sample 1 is less than 1 / 100 of the etching rate of Sample 2 (the oxide semiconductor film having an amorphous structure before heat treatment). In the etching using a 0.5% hydrofluoric acid solution, the etching rate of Sample 1 is less than about 1 / 10 of the etching rate of Sample 2. In addition, in the etching using a mixed acid etching solution, the etching rate of Sample 1 is less than 1 / 100 of the etching rate of Sample 3 (an oxide semiconductor film containing IGZO with an indium ratio of less than 50%). That is, Sample 1 has significantly better etching resistance than Samples 2 and 3.

[0080] Such excellent etching resistance of the oxide semiconductor layer 140 including Poly-OS is a property that cannot be obtained in the conventional oxide semiconductor having a polycrystalline structure manufactured by a process below 500° C. Although the detailed mechanism of the excellent etching resistance of the oxide semiconductor layer 140 including Poly-OS is not clear, it is believed that Poly-OS has a polycrystalline structure different from the conventional one.

[0081] As described above, the etching rate of the oxide semiconductor layer 140 including Poly-OS in the etching solution is very low. Therefore, it is very difficult to pattern the oxide semiconductor layer 140. Therefore, in the case of forming an island-shaped oxide semiconductor layer 140, the oxide semiconductor film having an amorphous structure before heat treatment is patterned into an island shape, and then heat treated to crystallize. Thus, an island-shaped oxide semiconductor layer 140 including Poly-OS can be formed.

[0082] [2-3. Structure of Oxide Semiconductor Layer 140]

[0083] Figure 2 It is a schematic plan view showing the structure of the oxide semiconductor layer 140 of the semiconductor device 10 according to one embodiment of the present invention. Figure 2 In FIG. 1 , for convenience of description, the gate electrode 160 , the source electrode 180 , and the drain electrode 190 located above the oxide semiconductor layer 140 are indicated by dotted lines.

[0084] The oxide semiconductor layer 140 is formed in an island shape. For example, the planar shape of the oxide semiconductor layer 140 is a quadrilateral, but is not limited thereto. The oxide semiconductor layer 140 is formed in an island shape and thus has one or more edges. Figure 2 As shown, when the planar shape of the oxide semiconductor layer 140 is a quadrangle, the oxide semiconductor layer 140 has four edge portions.

[0085] like Figure 2 As shown, the oxide semiconductor layer 140 includes a channel region 141, a source region 142, and a drain region 143. The channel region 141 is located between the source region 142 and the drain region 143. The channel region 141 overlaps with the gate electrode 160. The source region 142 overlaps with the source electrode 180. The drain region 143 overlaps with the drain electrode 190. The source electrode 180 is electrically connected to the source region 142 via the contact hole CH1, and the drain electrode 190 is electrically connected to the drain region 143 via the contact hole CH2. The channel region 141 has the properties of a semiconductor. Therefore, if a voltage is applied to the gate electrode 160, a channel serving as a current path is formed in the channel region 141. The source region 142 and the drain region 143 each have the properties of a conductor. Therefore, the carrier concentrations of the source region 142 and the drain region 143 are greater than the carrier concentration of the channel region 141. In other words, the channel region 141 has a higher resistivity (or lower conductivity) than each of the source region 142 and the drain region 143. For example, the sheet resistance of the source region 142 and the drain region 143 is 1000Ω / sq. or less, preferably 500Ω / sq. or less, and more preferably 250Ω / sq. or less. Hereinafter, for convenience of explanation, a region such as the channel region 141 having a higher resistivity than the source region 142 and the drain region 143 is referred to as a "high resistance region".

[0086] The oxide semiconductor layer 140 includes a first region A1, a second region A2, and a third region A3 as high resistance regions. The first region A1 is located between the source region 142 and the drain region 143. That is, the first region A1 is the channel region 141. The second region A2 includes a first edge E1 extending along the x-axis direction of the oxide semiconductor layer 140 and is adjacent to the first region A1. The third region A3 includes a second edge E2 extending along the x-axis direction of the oxide semiconductor layer 140 and is adjacent to the first region A1. The second edge E2 is located on the opposite side of the first edge E1. That is, the third region A3 is located on the opposite side of the second region A2 in a manner of sandwiching the first region A1. When viewed from above, the source region 142 and the drain region 143 are each surrounded by the first region A1 to the third region A3.

[0087] In a plan view, the gate electrode 160 extends in a manner overlapping the first region A1, the second region A2, and the third region A3, and covers the entire first region A1. In addition, the gate electrode 160 overlaps a portion of the source region 142 and a portion of the drain region 143. Therefore, the first width W1 of the first region A1 in the x-axis direction (equivalent to the channel length of the channel region 141) is smaller than the second width W2 of the gate electrode 160 in the x-axis direction.

[0088] [2-4. Formation of Source Region 142 and Drain Region 143]

[0089] Figure 3A and Figure 3B Each is a schematic cross-sectional view showing a method for forming a source region 142 and a drain region 143 in an oxide semiconductor layer 140 of a semiconductor device 10 according to an embodiment of the present invention. Specifically, Figure 3A and Figure 3B Each for their own reasons Figure 2 Sectional view taken along the Y1-Y2 line.

[0090] Figure 3A FIG. 1 shows an oxide semiconductor layer 140 formed on the second insulating layer 130 using the above-mentioned Poly-OS technology. Figure 3A The oxide semiconductor layer 140 has a predetermined shape and includes Poly-OS. Figure 3A In the method for forming the source region 142 and the drain region 143 shown in the figure, a resist R1 having a desired shape is formed on the oxide semiconductor layer 140. The resist R1 overlaps with the region (the first region A1, the second region A2, and the third region A3) for forming the high resistance region. On the other hand, the resist R1 does not overlap with the region for forming the source region 142 and the drain region 143.

[0091] Next, using the resist R1 as a mask, impurity elements are doped into the oxide semiconductor layer 140. In one example, boron (B) as an impurity element is doped into the oxide semiconductor layer 140 by ion implantation. It should be noted that other impurity elements such as phosphorus (P) may be doped into the oxide semiconductor layer 140 instead of boron. Thus, a source region 142 and a drain region 143 doped with impurity elements are formed in the oxide semiconductor layer 140. In the source region 142 and the drain region 143, oxygen vacancies are formed by doping with impurity elements, so that the source region 142 and the drain region 143 have low resistance. On the other hand, by being masked by the resist R1, a high resistance region that does not contain impurity elements is also formed. It should be noted that in the oxide semiconductor layer 140 containing Poly-OS, the source region 142 and the drain region doped with impurity elements sometimes have crystallinity, which is also one of the characteristics of Poly-OS. In this case, the crystal structure of each of the source region 142 and the drain region 143 is the same as the crystal structure of the channel region 141 .

[0092] Next, after the resist R1 is removed, silicon oxide is formed into a film to form the gate insulating layer 150. Then, the gate electrode 160 is formed on the gate insulating layer 150. At this time, the gate electrode 160 is patterned so as to overlap with the first region A1.

[0093] Figure 3B Shown in Figure 3A Different methods of forming the source region 142 and the drain region 143 . Figure 3B 2 shows a gate insulating layer 150 formed on the oxide semiconductor layer 140 including Poly-OS. Figure 3B In the method for forming the source region 142 and the drain region 143 shown, a resist R1 having a desired shape is formed on the gate insulating layer 150. The resist R1 overlaps with the region for forming the high resistance region. On the other hand, the resist R1 does not overlap with the region for forming the source region 142 and the drain region 143.

[0094] Next, using the resist R1 as a mask, an impurity element is doped into the oxide semiconductor layer 140 via the gate insulating layer 150. Thus, a source region 142 and a drain region 143 doped with the impurity element are formed in the oxide semiconductor layer 140.

[0095] Next, after the resist R1 is removed, the gate electrode 160 is formed on the gate insulating layer 150. At this time, the gate electrode 160 is patterned so as to overlap with the first region A1.

[0096] exist Figure 3A and Figure 3B In the method for forming the source region 142 and the drain region 143 shown in FIG. 1 , the doping of the impurity element into the oxide semiconductor layer 140 is performed not by using the gate electrode 160 as a mask but by using the resist R1 as a mask. Figure 2 As shown, the second width W2 of the gate electrode 160 is not limited to being consistent with the first width W1 of the first region A1. In addition, in order to make the gate electrode 160 overlap with the entire first region A1, the second width W2 is set to be larger than the first width W1. Therefore, the gate electrode 160 overlaps with the entire first region A1, and also overlaps with a portion of the source region 142 and a portion of the drain region 143. In addition, the gate electrode 160 also overlaps with a portion of the second region A2 and a portion of the third region A3.

[0097] In use Figure 3A or Figure 3BIn the semiconductor device 10 manufactured by the method for forming the source region 142 and the drain region 143 shown in FIG. 1 , the second region A2 including the first edge E1 and the third region A3 including the second edge E2 have the same degree of high resistance as the first region A1 corresponding to the channel region 141. Therefore, the second region A2 and the third region A3 do not become current paths such as the source region 142 and the drain region 143. That is, when a gate voltage above the threshold is applied to the gate electrode 160, current flows between the source electrode 180 and the drain electrode 190 via the channel region 141, the source region 142, and the drain region 143 of the oxide semiconductor layer 140. On the other hand, in the oxide semiconductor layer 140, almost no current flows in the second region A2 and the third region A3.

[0098] The second region A2 including the first edge E1 and the third region A3 including the second edge E2 are regions that are easily damaged by etching when forming the island-shaped oxide semiconductor layer 140 and are easily degraded by heat generated by the flow of current. In this embodiment, the heat generated in the second region A2 and the third region A3 is reduced, so the degradation caused by the heat generated in the second region A2 and the third region A3 can be suppressed. Therefore, in the case of making the second region A2 and the third region A3 have high resistance so that the current is not easy to flow, it is effective in suppressing the degradation of the second region A2 and the third region A3.

[0099] Furthermore, even if the second region A2 and the third region A3 deteriorate, since they are not regions where a current path is formed, the influence on the electrical characteristics of the semiconductor device 10 is small. Specifically, the shift of the threshold voltage is suppressed in the semiconductor device 10. Therefore, the semiconductor device 10 can have high reliability.

[0100] <Variation 1>

[0101] Reference Figure 4 and Figure 5 A modification of the present embodiment will be described. It should be noted that, below, descriptions of the same configurations as those described above may be omitted.

[0102] Figure 4 It is a schematic plan view showing the structure of an oxide semiconductor layer 140 of a semiconductor device 10 according to a modification of one embodiment of the present invention. Figure 4 In FIG. 1 , for convenience of description, the gate electrode 160 , the source electrode 180 , and the drain electrode 190 located above the oxide semiconductor layer 140 are indicated by dotted lines.

[0103] The shapes of the first to third regions A1 to A3, the source region 142, and the drain region 143 in the oxide semiconductor layer 140 are as shown in FIG. Figure 2 For explanation. Figure 4 In the oxide semiconductor layer 140 shown, the first width W1 of the first region A1 in the x-axis direction is substantially the same as the second width W2 of the gate electrode 160 in the x-axis direction. In addition, the gate electrode 160 overlaps not only the entire first region A1, but also the entire second region A2 and the entire third region A3. In a plan view, the boundaries between the first region A1 to the third region A3 and the source region 142 are substantially consistent with the edge of the gate electrode 160. Similarly, the boundaries between the first region A1 to the third region A3 and the drain region 143 are substantially consistent with the edge of the gate electrode 160.

[0104] In a plan view, the source electrode 180 overlaps with the source region 142, but does not overlap with the first region A1 to the third region A3. Similarly, the drain electrode 190 overlaps with the drain region 143, but does not overlap with the first region A1 to the third region A3. The source electrode 180 is in contact with the source region 142 via the contact hole CH1, and the drain electrode 190 is in contact with the drain region 143 via the contact hole CH2.

[0105] Figure 5 Schematic cross-sectional view showing a method for forming a source region 142 and a drain region 143 in an oxide semiconductor layer 140 of a semiconductor device 10 according to a modification of an embodiment of the present invention. Specifically, Figure 5 Reason Figure 4 Sectional view taken along the Y1-Y2 line.

[0106] Figure 5 2 shows a gate insulating layer 150 formed on the oxide semiconductor layer 140 including Poly-OS. Figure 5 In the formation method shown, a gate electrode 160 having a desired shape is formed on the gate insulating layer 150. The gate electrode 160 overlaps with the region (first region A1, second region A2, and third region A3) for forming the high resistance region. On the other hand, the gate electrode 160 does not overlap with the region for forming the source region 142 and the drain region 143.

[0107] Next, the impurity element is doped into the oxide semiconductor layer 140 via the gate insulating layer 150 using the gate electrode 160 as a mask. Thus, the source region 142 and the drain region 143 doped with the impurity element are formed in the oxide semiconductor layer 140 .

[0108] exist Figure 5 In the method for forming the source region 142 and the drain region 143 shown in FIG. 1 , the impurity element is doped into the oxide semiconductor layer 140 using the gate electrode 160 as a mask. Figure 4As shown, the second width W2 of the gate electrode 160 is substantially identical to the first width W1 of the first region A1. In addition, the gate electrode 160 does not overlap the source region 142 and the drain region 143, but overlaps the entire second region A2 and the entire third region A3.

[0109] In reference Figure 4 and Figure 5 The semiconductor device 10 described above can also achieve the same effects as described above.

[0110] <Variation 2>

[0111] Reference Figure 6 Another modification of the present embodiment will be described. It should be noted that, below, descriptions of the same configurations as those described above may be omitted.

[0112] Figure 6 It is a schematic plan view showing the structure of an oxide semiconductor layer 140 of a semiconductor device 10 according to a modification of one embodiment of the present invention. Figure 6 In FIG. 1 , for convenience of description, the gate electrode 160 , the source electrode 180 , and the drain electrode 190 located above the oxide semiconductor layer 140 are indicated by dotted lines.

[0113] The shapes of the first to third regions A1 to A3, the source region 142, and the drain region 143 in the oxide semiconductor layer 140 are as shown in FIG. Figure 2 For explanation. Figure 6 In the oxide semiconductor layer 140 shown, the first width W1 of the first region A1 in the x-axis direction is substantially the same as the second width W2 of the gate electrode 160 in the x-axis direction. The gate electrode 160 overlaps the entire first region A1, but the gate electrode 160 overlaps a portion of the second region A2 and a portion of the third region A3. That is, the gate electrode 160 extends along the y-axis direction with the second width W2, and overlaps the second region A2 and the third region A3.

[0114] In a plan view, the source electrode 180 overlaps with the second region A2, the third region A3, and the source region 142. The drain electrode 190 overlaps with the second region A2, the third region A3, and the drain region 143. However, the source electrode 180 and the drain electrode 190 are not in contact with the second region A2 and the third region A3. The source electrode 180 is in contact with the source region 142 via the contact hole CH1, and the drain electrode 190 is in contact with the drain region 143 via the contact hole CH2.

[0115] Figure 6 The shape of the gate electrode 160 shown in FIG. 1 can be formed, for example, as follows. Figure 5As described above, the gate electrode 160 is patterned so as to overlap with the region (the first region A1 to the third region) in the oxide semiconductor layer 140 for forming the high resistance region. Then, the oxide semiconductor layer 140 is doped with an impurity element using the gate electrode 160 as a mask. Then, a portion of the gate electrode 160 overlapping with the second region A2 and the third region A3 and the portion adjacent to the source region 142 and the drain region 143 is removed by etching. Thus, a gate electrode 160 is formed. Figure 6 The gate electrode 160 has the shape shown.

[0116] In reference Figure 6 The semiconductor device 10 described above can also achieve the same effects as described above.

[0117] <Variation 3>

[0118] Reference Figure 7 , another variation of the present embodiment will be described. It should be noted that, in the following, descriptions of the same configurations as those described above may be omitted.

[0119] Figure 7 It is a schematic plan view showing the structure of an oxide semiconductor layer 140 of a semiconductor device 10 according to a modification of one embodiment of the present invention. Figure 7 In FIG. 1 , for convenience of description, the gate electrode 160 , the source electrode 180 , and the drain electrode 190 located above the oxide semiconductor layer 140 are indicated by dotted lines.

[0120] The shapes of the first to third regions A1 to A3, the source region 142, and the drain region 143 in the oxide semiconductor layer 140 are as shown in FIG. Figure 2 For explanation. Figure 7 In the oxide semiconductor layer 140 shown, the gate electrode 160 has a second width W2 and a third width W3 in the x-axis direction and extends in the y-axis direction. The portion of the gate electrode 160 overlapping the first region A1 has the second width W2. The portion of the gate electrode 160 overlapping the second region A2 and the third region A3 has the third width W3. The second width W2 is substantially the same as the first width W1. On the other hand, the third width W3 is greater than the first width W1.

[0121] Figure 7 The shape of the gate electrode 160 shown in FIG. 1 can be formed, for example, as follows. Figure 5As described above, the gate electrode 160 is patterned so as to overlap with the region (the first region A1 to the third region) in the oxide semiconductor layer 140 for forming the high resistance region. Then, the impurity element is doped into the oxide semiconductor layer 140 using the gate electrode 160 as a mask. Then, a portion of the gate electrode 160 is removed by etching. At this time, the gate electrode 160 is etched so that the width of the portion overlapping with the second region A2 and the third region A3 is greater than the width of the portion overlapping with the first region A1. Thus, a gate electrode 160 is formed. Figure 7 The gate electrode 160 has the shape shown.

[0122] In reference Figure 7 The semiconductor device 10 described above can also achieve the same effects as described above.

[0123] <Variation 4>

[0124] Reference Figure 8 Another modification of the present embodiment will be described. It should be noted that, below, descriptions of the same configurations as those described above may be omitted.

[0125] Figure 8 It is a schematic plan view showing the structure of an oxide semiconductor layer 140 of a semiconductor device 10 according to a modification of one embodiment of the present invention. Figure 8 In FIG. 1 , for convenience of description, the gate electrode 160 , the source electrode 180 , and the drain electrode 190 located above the oxide semiconductor layer 140 are indicated by dotted lines.

[0126] The shapes of the first to third regions A1 to A3, the source region 142, and the drain region 143 in the oxide semiconductor layer 140 are as shown in FIG. Figure 2 For explanation. Figure 8 In the oxide semiconductor layer 140 shown, the gate electrode 160 has a second width W2 and a third width W3 in the x-axis direction and extends in the y-axis direction. The portion of the gate electrode 160 overlapping the first region A1 has the second width W2. The portion of the gate electrode 160 overlapping the second region A2 and the third region A3 has the third width W3. The second width W2 is substantially the same as the first width W1. On the other hand, the third width W3 is smaller than the first width W1.

[0127] Figure 8 The shape of the gate electrode 160 shown in FIG. 1 can be formed, for example, as follows. Figure 5As described above, the gate electrode 160 is patterned so as to overlap with the region (the first region A1 to the third region) in the oxide semiconductor layer 140 for forming the high resistance region. Then, the impurity element is doped into the oxide semiconductor layer 140 using the gate electrode 160 as a mask. Then, a portion of the gate electrode 160 is removed by etching. At this time, the gate electrode 160 is etched so that the width of the portion overlapping with the second region A2 and the third region A3 is smaller than the width of the portion overlapping with the first region A1. Thus, a gate electrode 160 is formed. Figure 8 The gate electrode 160 has the shape shown.

[0128] In reference Figure 8 The semiconductor device 10 described above can also achieve the same effects as described above.

[0129] <Variant 5>

[0130] Reference Fig. 9 Another modification of the present embodiment will be described. It should be noted that, below, descriptions of the same configurations as those described above may be omitted.

[0131] Fig. 9 It is a schematic plan view showing the structure of a semiconductor device 10A according to a modification of the one embodiment of the present invention.

[0132] like Fig. 9 As shown, the semiconductor device 10A includes a substrate 100, a first insulating layer 110, a light shielding layer 120, a second insulating layer 130, a metal oxide layer 135, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, a third insulating layer 170, a source electrode 180, and a drain electrode 190. In the semiconductor device 10A, a metal oxide layer 135 is provided below the oxide semiconductor layer 140 and in contact with the oxide semiconductor layer 140. The end surface of the metal oxide layer 135 is substantially consistent with the end surface of the oxide semiconductor layer 130. The gate insulating layer 150 covers the end surface of the metal oxide layer 135 and the upper surface and end surface of the oxide semiconductor layer 140, and is provided on the second insulating layer 130.

[0133] The metal oxide layer 135 can function as a buffer layer for improving the crystallinity of the oxide semiconductor layer 140. In the semiconductor device 10A including the oxide semiconductor layer 135 having improved crystallinity, the field effect mobility is further improved.

[0134] A metal oxide containing aluminum as a main component is used as the metal oxide layer 135. The ratio of aluminum contained in the metal oxide layer 135 may be 5% to 70%, 10% to 60%, or 30% to 50% of the entire metal oxide layer 135. The above ratio may be a mass ratio or a weight ratio.

[0135] The thickness of the metal oxide layer 135 is 1 nm to 10 nm, preferably 1 nm to 5 nm. Aluminum oxide is preferably used as the metal oxide layer 135. Aluminum oxide has a high barrier property to gases such as oxygen and hydrogen. Here, the so-called barrier property refers to the function of inhibiting the permeation of gases such as oxygen and hydrogen.

[0136] Note that a metal oxide containing a metal other than aluminum as a main component may be used as the metal oxide layer 135. For example, the metal oxide layer 135 may be indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO).

[0137] The metal oxide layer 135 can be formed using a sputtering method or an atomic layer deposition method (ALD method). In addition, the metal oxide layer 135 can be patterned using the oxide semiconductor layer 140 as a mask. As described above, the oxide semiconductor layer 140 containing Poly-OS has excellent etching resistance. Therefore, in the patterning of the metal oxide layer 135, even when the metal oxide layer 135 is etched, the oxide semiconductor layer 140 used as a mask is not etched. In the semiconductor device 10A, in the formation of the metal oxide layer 135, the oxide semiconductor layer 140 can be used as a mask, so that the photolithography process can be omitted.

[0138] In reference Fig. 9 The semiconductor device 10A described above can also achieve the same effect as described above. In addition, in the semiconductor device 10A, the oxide semiconductor layer 140 is formed using the metal oxide layer 135 as a buffer layer, so the crystallinity of the oxide semiconductor layer 140 including Poly-OS is improved, and as a result, the semiconductor device 10A has a higher field effect mobility.

[0139] <Second embodiment>

[0140] Reference Fig.10 A semiconductor device 10 according to an embodiment of the present invention will be described. In the following, description of the same configuration as that described in the first embodiment may be omitted.

[0141] Fig.10 It is a schematic plan view showing the structure of the oxide semiconductor layer 140 of the semiconductor device 10 according to one embodiment of the present invention. Fig.10 In FIG. 1 , for convenience of description, the gate electrode 160 , the source electrode 180 , and the drain electrode 190 located above the oxide semiconductor layer 140 are indicated by dotted lines.

[0142] Fig.10The oxide semiconductor layer 140 shown includes a high resistance region (a 1st region A1, a 2-1st region A2-1, a 2-2nd region A2-2, a 3-1st region A3-1, and a 3-2nd region A3-2), a source region 142, and a drain region 143. The 1st region A1 is located between the source region 142 and the drain region 143. The 2-1st region A2-1 includes a portion of the 1st edge portion E1 and is located in the source region 142. The 2-2nd region A2-2 includes a portion of the 1st edge portion E1 and is located in the drain region 143. The 3-1st region A3-1 includes a portion of the 2nd edge portion E2 and is located in the source region 142. The 3-2nd region A3-2 includes a portion of the 2nd edge portion E2 and is located in the drain region. In other words, the 2-1st region A2 - 1 and the 3-1st region A3 - 1 are surrounded by the source region 142 , and the 2-2nd region A2 - 2 and the 3-2nd region A3 - 2 are surrounded by the drain region 143 .

[0143] The gate electrode 160 overlaps the entire first region A1 and extends in the y-axis direction. The first width W1 of the first region A1 in the x-axis direction is substantially the same as the second width W2 of the gate electrode 160 in the x-axis direction. In the present embodiment, as the same layer as the gate electrode 160, a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4 are provided. That is, the gate electrode 160 and the first metal layer M1 to the fourth metal layer M4 can be formed in common in the same process. The first metal layer M1 to the fourth metal layer M4 have an island shape. The first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 overlap the entire 2-1 region A2-1, the entire 2-2 region A2-2, the entire 3-1 region A3-1, and the entire 3-2 region A3-2, respectively.

[0144] In a plan view, the 2-1 region A2-1 and the 3-1 region A3-1 are located between the gate electrode 160 and the source electrode 180. In addition, the 2-2 region A2-2 and the 3-2 region A3-2 are located between the gate electrode 160 and the drain electrode 190. The source electrode 180 is in contact with the source region 142 via the contact hole CH1, and the drain electrode 190 is in contact with the drain region 143 via the contact hole CH2.

[0145] The first to fourth metal layers M1 to M4 do not overlap the gate electrode 160 , the source electrode 180 , and the drain electrode 190 . Therefore, the first to fourth metal layers M1 to M4 are electrically floating but are hardly affected by any potential of the gate electrode 160 , the source electrode 180 , and the drain electrode 190 .

[0146] Fig.10The high resistance region, source region 142 and drain region 143 of the oxide semiconductor layer 140 shown can be formed by doping impurity elements using the gate electrode 160 and the first to fourth metal layers M1 to M4 as masks. It should be noted that the first to fourth metal layers M1 to M4 can be removed after ion implantation.

[0147] In reference Fig.10 In the semiconductor device 10 described, the high-resistance 2-1 region A2-1 and the 2-2 region A2-2 are provided so as to include the first edge E1, and the high-resistance 3-1 region A3-1 and the 3-2 region A3-2 are provided so as to include the second edge E2. Therefore, a channel region 141 is formed in the central portion of the first region A1 away from the first edge E1 and the second edge E2, and no current path is formed near the first edge E1 and the second edge E2. Therefore, in reference to Fig.10 The semiconductor device 10 described above can also achieve the same effects as those of the first embodiment.

[0148] <Third embodiment>

[0149] Reference Fig.11 A semiconductor device 10 according to an embodiment of the present invention will be described. In the following, description of the same configuration as that described in the first embodiment or the second embodiment may be omitted.

[0150] Fig.11 It is a schematic plan view showing the structure of the oxide semiconductor layer 140 of the semiconductor device 10 according to one embodiment of the present invention. Fig.10 In FIG. 1 , for convenience of description, the gate electrode 160 , the source electrode 180 , and the drain electrode 190 located above the oxide semiconductor layer 140 are indicated by dotted lines.

[0151] Fig.11 The oxide semiconductor layer 140 shown includes a high resistance region (first region A1), a source region 142, and a drain region 143. The first region A1 is located between the source region 142 and the drain region 143. In this embodiment, the second region A2 and the third region A3 having high resistance described in the first embodiment are not provided in the oxide semiconductor layer 140.

[0152] In a plan view, the source electrode 180 overlaps the oxide semiconductor layer 140 at a position approximately in the middle of the first edge E1 and the second edge E2, and is connected to the source region 142 via the contact hole CH1. The distance D11 along the y-axis direction from the first edge E1 to one contact hole CH1 is approximately the same as the distance D12 along the y-axis direction from the second edge E2 to another contact hole CH1. The distance D13 along the x-axis direction from the first region A1 to one contact hole CH1 is smaller than the distance D11 and the distance D12. In one example, the distance D11 and the distance D12 are more than twice the distance D13.

[0153] In a plan view, the drain electrode 190 overlaps the oxide semiconductor layer 140 at a position approximately in the middle of the first edge E1 and the second edge E2, and is connected to the drain region 143 via the contact hole CH2. The distance D21 along the y-axis direction from the first edge E1 to one contact hole CH1 is approximately the same as the distance D22 along the y-axis direction from the second edge E2 to another contact hole CH2. The distance D23 along the x-axis direction from the first region A1 to one contact hole CH2 is smaller than the distance D21 and the distance D22. In one example, the distances D21 and D22 are more than twice the distance D23.

[0154] In reference Fig.11 In the semiconductor device 10 described, when a gate voltage above the threshold is applied to the gate electrode 160, the electric lines of force between the source electrode 180 and the drain electrode 190 are concentrated in the central portion of the oxide semiconductor layer 140, while the electric lines of force are not easily extended to the vicinity of the first edge E1 and the vicinity of the second edge E2. Therefore, a channel region 141 is formed in the central portion of the first region A1 away from the first edge E1 and the second edge E2, and no current path is formed near the first edge E1 and the vicinity of the second edge E2. Therefore, in reference to Fig.11 The semiconductor device 10 described above can also achieve the same effects as those of the first embodiment.

[0155] <Modification>

[0156] Reference Fig.12 A modification of the present embodiment will be described. It should be noted that, below, descriptions of the same configurations as those described above may be omitted.

[0157] Fig.12 It is a schematic plan view showing the structure of an oxide semiconductor layer 140 of a semiconductor device 10 according to a modification of one embodiment of the present invention. Fig.12 In FIG. 1 , for convenience of description, the gate electrode 160 , the source electrode 180 , and the drain electrode 190 located above the oxide semiconductor layer 140 are indicated by dotted lines.

[0158] exist Fig.12 In the oxide semiconductor layer 140 shown in FIG. 1 , the source electrode 180 and the drain electrode 190 extend in the y-axis direction, and the source electrode 180 and the drain electrode 190 overlap with the first edge portion E1 and the second edge portion E2. Fig.11 Similarly to the structure shown, the source electrode 180 is in contact with the source region 142 via the contact hole CH1 formed at a position sufficiently far away from the first edge E1 and the second edge E2. In addition, the drain electrode 190 is also in contact with the drain region 143 via the contact hole CH2 formed at a position sufficiently far away from the first edge E1 and the second edge E2. Therefore, the channel region 141 is formed in the central portion of the first region A1 away from the first edge E1 and the second edge E2, and no current path is formed near the first edge E1 and the second edge E2.

[0159] In reference Fig.12 The semiconductor device 10 described above can also achieve the same effects as described above.

[0160] <Fourth embodiment>

[0161] Reference Figure 13 to Figure 15C A semiconductor device 10 according to an embodiment of the present invention will be described. In the following, descriptions of the same configurations as those described in the first to third embodiments may be omitted.

[0162] Fig.13 It is a schematic plan view showing the structure of the oxide semiconductor layer 140 of the semiconductor device 10 according to one embodiment of the present invention. Fig.13 In FIG. 1 , for convenience of description, the gate electrode 160 , the source electrode 180 , and the drain electrode 190 located above the oxide semiconductor layer 140 are indicated by dotted lines. Fig.14A and Fig. 14B 1 is a schematic cross-sectional view showing the structure of a semiconductor device 10 according to an embodiment of the present invention. Specifically, Fig.14A Reason Fig.13 A cross-sectional view of the semiconductor device 10 cut along the line Y3-Y4 in FIG. Fig. 14B Reason Fig.13 Sectional view taken along line Y5-Y6.

[0163] exist Fig.13 In the oxide semiconductor layer 140 shown in FIG. 1 , the film thickness of the second region A2 including the first edge portion E1 and the third region A3 including the second edge portion E2 vary. Specifically, as shown in FIG. Fig.14A and Fig. 14BAs shown, the film thickness of the second region A2 decreases from the first region A1 toward the first edge E1, and the film thickness of the third region A3 decreases from the first region A1 toward the second edge E2. For example, the width of the second region A2 and the width of the third region A3 in the y-axis direction are about 2 μm.

[0164] In a plan view, the source electrode 180 extends along the y-axis direction and overlaps with the second region A2, the third region A3, and the source region 142. The source electrode 180 is not in contact with the second region A2 and the third region A3, but is in contact with the source region 142 via the contact hole CH1. The drain electrode 190 extends along the y-axis direction in a plan view and overlaps with the second region A2, the third region A3, and the drain region 143. The drain electrode 190 is not in contact with the second region A2 and the third region A3, but is in contact with the drain region 143 via the contact hole CH2.

[0165] Here, refer to Figures 15A to 15C right Fig.13 An example of a method for manufacturing the oxide semiconductor layer 140 shown in FIG. 1 is described below.

[0166] Figures 15A to 15C It is a schematic cross-sectional view showing a method for manufacturing the oxide semiconductor layer 140 of the semiconductor device 10 according to one embodiment of the present invention.

[0167] First, the oxide semiconductor film 145 is formed on the second insulating layer 130. Then, a resist R2 patterned into a desired shape is formed on the oxide semiconductor film 145. Next, the oxide semiconductor film 145 is etched using the resist R2 as a mask. Thus, an island-shaped oxide semiconductor film 145 is formed.

[0168] Etching (or ashing) is continued. As a result, the volume of the resist R2 is reduced, and a region near the first edge E1 and a region near the second edge E2 of the oxide semiconductor film 145 are exposed from the resist R2, so that the surface layer of the oxide semiconductor film 145 can be removed by etching.

[0169] The etching time of the area near the first edge E1 in the oxide semiconductor film 145 is longer than the etching time of the area overlapping with the edge of the resist R2. Therefore, the film thickness of the area near the first edge E1 is smaller than the film thickness of the area overlapping with the edge of the resist R2. Similarly, the etching time of the area near the second edge E2 in the oxide semiconductor film 145 is longer than the etching time of the area overlapping with the edge of the resist R2. Therefore, the film thickness of the area near the second edge E2 is smaller than the film thickness of the area overlapping with the edge of the resist R2. On the other hand, the film thickness of the central portion of the oxide semiconductor film 145 hardly changes because the resist R2 remains overlapped even if etching is performed. Thus, an oxide semiconductor film 145 whose film thickness decreases toward the first edge E1 and the second edge E2 is formed.

[0170] Then, by heat treating the oxide semiconductor film 145 formed into the desired shape, the oxide semiconductor film 145 is crystallized to form an oxide semiconductor layer 140 including Poly-OS. If impurities are doped into the oxide semiconductor layer 140 using the gate electrode 160 as a mask, the impurity elements are doped into the region of the oxide semiconductor layer 140 that does not overlap with the gate electrode 160. Therefore, the impurity elements are also doped into the first edge E1 included in the second region A2 and the second edge E2 included in the third region A3. However, the film thickness near the first edge E1 and the film thickness near the second edge E2 are extremely small, and are not reduced in resistance like the source region 142 and the drain region 143. Therefore, no current path is formed near the first edge E1 and the second edge E2. Therefore, in reference to Fig.13 The semiconductor device 10 described above can also achieve the same effects as those of the first embodiment.

[0171] <Fifth embodiment>

[0172] Reference Fig.16 A semiconductor device 1 according to an embodiment of the present invention will be described. In the following, descriptions of the same configurations as those described in the first to fourth embodiments may be omitted.

[0173] Fig.16 It is a schematic cross-sectional view of a semiconductor device 1 according to an embodiment of the present invention.

[0174] The semiconductor device 1 includes a first transistor TR1 and a second transistor TR2 provided on a substrate 100. The first transistor TR1 has the same structure as the semiconductor device 10 described above, and includes an oxide semiconductor layer 140. The gate electrode 160 of the first transistor TR1 is electrically connected to a gate line. The source electrode 180 of the first transistor TR1 is electrically connected to a source line or a power supply line, etc. The drain electrode 190 of the first transistor TR1 is electrically connected to an element electrode 360.

[0175] The second transistor TR2 includes a substrate 100, a base insulating layer 210, a light shielding layer 220, a first insulating layer 110, a silicon semiconductor layer 240, a gate insulating layer 250, a gate electrode 260, a second insulating layer 130, a source electrode 280, and a drain electrode 290. The base insulating layer 210 is provided on the substrate 100. The light shielding layer 220 is provided on the base insulating layer 210. The first insulating layer 110 covers the upper surface and end surface of the light shielding layer 220 and is provided on the base insulating layer 210. The silicon semiconductor layer 240 is provided on the first insulating layer 110. The gate insulating layer 250 covers the upper surface and end surface of the silicon semiconductor layer 240 and is provided on the first insulating layer 110. The gate electrode 260 overlaps with the silicon semiconductor layer 240 and is provided on the gate insulating layer 250. The second insulating layer 130 covers the upper surface and end surface of the gate electrode 260 and is provided on the gate insulating layer 250. On the second insulating layer 130, an insulating layer (hereinafter, for convenience of explanation, described as "insulating layer 255") formed of the same layer as the gate insulating layer 150 of the first transistor TR1 is provided. A source electrode 280 and a drain electrode 290 are provided on the insulating layer 255. The source electrode 280 is connected to the silicon semiconductor layer 240 via a contact hole CH3 that penetrates the gate insulating layer 250, the second insulating layer 130, and the insulating layer 255. The drain electrode 290 is connected to the silicon semiconductor layer 240 via a contact hole CH4 that penetrates the gate insulating layer 250, the second insulating layer 130, and the insulating layer 255. The source electrode 280 and the drain electrode 190 are electrically connected to the silicon semiconductor layer 240. The gate electrode 260 is electrically connected to the gate line. The source electrode 280 is electrically connected to the source line 310.

[0176] The base insulating layer 210 of the second transistor TR2 has the same structure as the first insulating layer 110 of the first transistor TR1. The light shielding layer 220 of the second transistor TR2 has the same structure as the light shielding layer 120 of the first transistor TR1. The first insulating layer 110 of the second transistor TR2 has the same structure as the second insulating layer 130 of the first transistor TR1.

[0177] As the silicon semiconductor layer 240 of the second transistor TR2, a polycrystalline silicon semiconductor may be used, but the material of the silicon semiconductor layer 240 is not limited thereto. As the silicon semiconductor layer 240, other silicon-based semiconductors may also be used.

[0178] The gate insulating layer 250 of the second transistor TR2 has the same structure as the gate insulating layer 150 of the first transistor TR1. It should be noted that in the first transistor TR1, the insulating layer formed of the same layer as the gate insulating layer 250 is located below the light shielding layer 120 and has the same function as the first insulating layer 110.

[0179] The gate electrode 260 of the second transistor TR2 has the same structure as the gate electrode 160 of the first transistor TR1 . The gate electrode 260 may be electrically connected to the light shielding layer 220 .

[0180] The source electrode 280 and the drain electrode 290 of the second transistor TR2 have the same configurations as the source electrode 180 and the drain electrode 190 of the first transistor TR1 , respectively.

[0181] Hereinafter, components other than the above-described components included in the semiconductor device 1 will be described.

[0182] The connection electrode 340 is disposed on the first planarization layer 330 and is covered by the second planarization layer 350. The connection electrode 340 is connected to the drain electrode 190 of the first transistor TR1 via a contact hole CH5 that penetrates the protective insulating layer 320 and the first planarization layer 330. The connection electrode 340 is a transparent electrode formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but may also be a metal layer.

[0183] The element electrode 360 ​​is arranged on the second planarization layer 350, and is connected to the connection electrode 340 via the contact hole CH6 that penetrates the second planarization layer 350. The element electrode 360 ​​is a pixel electrode, a lower electrode, an anode or a cathode of various electronic devices. The element electrode 360 ​​is, for example, a transparent electrode formed of a transparent conductive material such as ITO or IZO. It should be noted that the element electrode 360 ​​may also be a metal electrode formed of a metal material such as silver or aluminum. In addition, the element electrode 360 ​​may also have a stacked structure of a transparent electrode and a metal electrode. For example, the element electrode 360 ​​may have a stacked structure in which a transparent electrode, a metal electrode and a transparent electrode are stacked in sequence, or may have a stacked structure of more than three layers.

[0184] The protective insulating layer 320 can cover and protect the first transistor TR1 and the second transistor TR2. As the protective insulating layer 320, an oxide or a nitride similar to the first insulating layer 110 can be used. The protective insulating layer 320 may have a single layer structure or a stacked structure.

[0185] As the first planarizing layer 330 and the second planarizing layer 350 , a transparent resin such as polyimide can be used.

[0186] The first transistor TR1 included in the semiconductor device 1 according to this embodiment has the same configuration as the semiconductor device 10 described in Embodiments 1 to 4. Therefore, degradation of the first edge portion E1 and the second edge portion E2 of the oxide semiconductor layer 140 of the first transistor TR1 can be suppressed, so that the semiconductor device 1 can have high reliability.

[0187] As the embodiments of the present invention, the embodiments and variations described above can be appropriately combined and implemented as long as they do not contradict each other. In addition, the solutions obtained by those skilled in the art by appropriately adding, deleting, or changing the design of the components based on the embodiments and variations, or the solutions obtained by adding, omitting, or changing the conditions of the processes as long as they have the gist of the present invention, are also included in the scope of the present invention.

[0188] Even if there are other effects different from the effects brought about by the above-mentioned embodiments, effects that are clear from the description of this specification or effects that can be easily predicted by those skilled in the art should of course be regarded as effects brought about by the present invention.

Claims

1. A semiconductor device comprising: a gate electrode; an oxide semiconductor layer having a polycrystalline structure; a gate insulating layer between the gate electrode and the oxide semiconductor layer; A source electrode on the oxide semiconductor layer; and a drain electrode on the oxide semiconductor layer, The oxide semiconductor layer comprises: a source region, comprising an impurity element and electrically connected to the source electrode; a drain region, which includes the impurity element and is electrically connected to the drain electrode; a channel region between the source region and the drain region; and a first region including a first edge portion extending along a first direction from the source region toward the drain region and adjacent to the channel region, The first region has a resistivity higher than that of each of the source region and the drain region. When the oxide semiconductor layer is etched at 40° C. using an etching solution containing phosphoric acid as a main component, the etching rate of the oxide semiconductor layer is less than 3 nm / min.

2. The semiconductor device according to claim 1, wherein: The gate electrode extends in a second direction intersecting the first direction, A width of the gate electrode in the first direction is greater than a width of the channel region in the first direction.

3. The semiconductor device according to claim 1, wherein: The gate electrode overlaps the entire first region.

4. The semiconductor device according to claim 1, wherein: The gate electrode includes a first portion overlapping the channel region when viewed from above, A first width of the first portion in the first direction is substantially the same as a width of the channel region in the first direction.

5. The semiconductor device according to claim 4, wherein: In the plan view, the gate electrode further includes a second portion overlapping the first region, A second width of the second portion in the first direction is greater than the first width.

6. The semiconductor device according to claim 4, wherein: In the plan view, the gate electrode further includes a second portion overlapping the first region, A second width of the second portion in the first direction is smaller than the first width.

7. The semiconductor device according to claim 1, wherein: The film thickness of the first region decreases from the channel region toward the first edge portion.

8. The semiconductor device according to claim 1, wherein: The source electrode is electrically connected to the source region via a first contact hole provided in the gate insulating layer. The drain electrode is electrically connected to the drain region via a second contact hole provided in the gate insulating layer.

9. The semiconductor device according to claim 1, wherein: The oxide semiconductor layer further includes a second region adjacent to the channel region, the second region including a second edge portion on the opposite side to the first edge portion, The second region has higher electrical conductivity than each of the source region and the drain region.

10. The semiconductor device according to claim 1, wherein The first region does not contain the impurity element.

11. A semiconductor device comprising a gate electrode extending in a first direction; an oxide semiconductor layer having a polycrystalline structure, the oxide semiconductor layer including a first edge portion and a second edge portion extending in a second direction intersecting the first direction; a gate insulating layer between the gate electrode and the oxide semiconductor layer; A source electrode on the oxide semiconductor layer; and a drain electrode on the oxide semiconductor layer, The oxide semiconductor layer comprises: A first region overlapping the gate electrode in a plan view; a source region adjacent to the first region and containing an impurity element and electrically connected to the source electrode via a first contact hole; a drain region adjacent to the first region and containing the impurity element and electrically connected to the drain electrode via a second contact hole; a second region surrounded by the source region and including a first portion of the first edge portion; a third region surrounded by the source region and including the first portion of the second edge portion; a fourth region surrounded by the drain region and including the second portion of the first edge portion; and a fifth region surrounded by the drain region and including a second portion of the second edge portion, Each of the first region, the second region, the third region, the fourth region, and the fifth region has a higher resistivity than each of the source region and the drain region. When the oxide semiconductor layer is etched at 40° C. using an etching solution containing phosphoric acid as a main component, the etching rate of the oxide semiconductor layer is less than 3 nm / min.

12. The semiconductor device according to claim 11, wherein In the plan view, each of the second region, the third region, the fourth region, and the fifth region overlaps with a metal layer formed of the same layer as the gate electrode.

13. The semiconductor device according to claim 11, wherein: Each of the first region, the second region, the third region, the fourth region, and the fifth region does not contain the impurity element.

14. A semiconductor device comprising a gate electrode extending in a first direction; an oxide semiconductor layer having a polycrystalline structure, the oxide semiconductor layer including a first edge portion and a second edge portion extending in a second direction intersecting the first direction; a gate insulating layer between the gate electrode and the oxide semiconductor layer; A source electrode on the oxide semiconductor layer; and a drain electrode on the oxide semiconductor layer, The oxide semiconductor layer comprises: A first region overlapping the gate electrode in a plan view; a source region adjacent to the first region and containing an impurity element and electrically connected to the source electrode via a first contact hole; and a drain region adjacent to the first region and containing the impurity element and electrically connected to the drain electrode via a second contact hole, The first region has a resistivity higher than that of each of the source region and the drain region. In the plan view, a first distance from the first edge to the first contact hole along the first direction is greater than a second distance from the first region to the first contact hole along the second direction, When the oxide semiconductor layer is etched at 40° C. using an etching solution containing phosphoric acid as a main component, the etching rate of the oxide semiconductor layer is less than 3 nm / min.

15. The semiconductor device according to claim 14, wherein: The first region does not contain the impurity element.

16. The semiconductor device according to any one of claims 1 to 15, wherein: The etching solution includes nitric acid and acetic acid.

17. The semiconductor device according to any one of claims 1 to 15, wherein: When the oxide semiconductor layer is etched using a 0.5% hydrofluoric acid solution at room temperature, an etching rate of the oxide semiconductor layer is less than 5 nm / min.

18. The semiconductor device according to any one of claims 1 to 15, wherein: The oxide semiconductor layer is formed by heat treating an oxide semiconductor film having an amorphous structure. When the oxide semiconductor film is etched using the etching solution at 40° C., an etching rate of the oxide semiconductor film is 100 nm / min or more.

19. The semiconductor device according to any one of claims 1 to 15, wherein: The oxide semiconductor layer contains a plurality of metal elements. One of the plurality of metal elements is indium, The atomic ratio of the indium to the plurality of metal elements is 50% or more.

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