Thin film transistor device, manufacturing method and display panel

Abstract

The present application is applicable to the field of display technology, and provides a thin film transistor device, a manufacturing method and a display panel. The thin film transistor device includes a first active layer, a first gate insulating layer, a gate, a second gate insulating layer, a second active layer, a first electrode and a second electrode. The first active layer, the first gate insulating layer, the gate, the second gate insulating layer and the second active layer are stacked in sequence on a substrate, and the first active layer is connected to the second active layer, the first electrode is connected to the first active layer, and the second electrode is connected to the second active layer. Due to the three-dimensional stacking of the first active layer and the second active layer on the upper and lower sides of the gate, the thin film transistor device is essentially folded in a three-dimensional space, and its orthographic projection area on the substrate is small. When applied to a display panel, it occupies less area in the non-opening area, which is conducive to ensuring a high aperture ratio and high resolution of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a thin film transistor device, a manufacturing method and a display panel. Background Art

[0002] In display panels, thin film transistor devices are used to control the on and off of pixels and provide pixel operating voltage. At present, people's demand for display is developing towards higher brightness, higher contrast, wider color gamut, faster refresh rate, and higher resolution. Therefore, this also puts higher requirements on the production and performance of thin film transistor devices. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a thin film transistor device, aiming to provide a solution for reducing the area of ​​the thin film transistor device and improving the resolution of the display panel.

[0004] The embodiment of the present application is implemented as follows: a thin film transistor device includes: a first active layer, a first gate insulating layer, a gate, a second gate insulating layer, a second active layer, a first electrode and a second electrode; the first active layer, the first gate insulating layer, the gate, the second gate insulating layer and the second active layer are stacked in sequence on a substrate, and the first active layer is connected to the second active layer; the first electrode is connected to the first active layer, and the second electrode is connected to the second active layer.

[0005] In one embodiment, the first active layer includes a first region and a fourth region, the orthographic projection of the first region on the substrate is located outside the orthographic projection of the gate on the substrate, and the orthographic projection of the fourth region on the substrate is located outside the orthographic projection of the first gate insulating layer on the substrate; the first region is used to connect to the first electrode, and the fourth region is used to connect to the second active layer;

[0006] Preferably, the orthographic projection of the fourth region on the substrate is located on a side of the orthographic projections of the first gate insulating layer and the second gate insulating layer on the substrate that is away from the first region; the thin film transistor device further comprises an interlayer insulating layer provided on the second active layer and the substrate;

[0007] Preferably, the first gate insulating layer and the second gate insulating layer are provided with a first via hole penetrating therethrough, the first via hole exposing the fourth region, and the second active layer is partially arranged in the first via hole and connected to the fourth region. The advantage is that the connection between the first active layer and the second active layer is convenient, and it is beneficial to the manufacture of other devices on the substrate.

[0008] In one embodiment, the first gate insulating layer includes a third region, the orthographic projection of the third region on the substrate is located outside the orthographic projection of the gate on the substrate, and the second gate insulating layer is connected to the third region. The advantage is that it is conducive to the connection between the first gate insulating layer and the second gate insulating layer.

[0009] In one embodiment, the first active layer includes a first semiconductor layer and a first conductor segment connected to each other, and the first electrode is connected to the first conductor segment;

[0010] Preferably, the first conductor segment comprises an atomic doping segment provided on one side of the first semiconductor layer;

[0011] Preferably, the atomic doping segment is an aluminum doped segment, a phosphorus doped segment or a boron doped segment;

[0012] Preferably, the first conductor segment comprises a metal layer disposed on a surface of the first semiconductor layer;

[0013] Preferably, the first conductor segment includes a metal layer disposed on the substrate, the metal layer includes a fifth region and a sixth region, the orthographic projection of the fifth region on the substrate is located within the orthographic projection of the gate on the substrate, the orthographic projection of the sixth region on the substrate is located outside the orthographic projection of the gate on the substrate, the first semiconductor layer is disposed on the fifth region, and the sixth region is connected to the first electrode. The advantage is that a solution for conductorization of multiple semiconductor materials is provided.

[0014] In one embodiment, the second active layer includes a second semiconductor layer and a second conductor segment connected to each other, and the second electrode is connected to the second conductor segment;

[0015] Preferably, the second conductor segment comprises an atomic doping segment provided on one side of the second semiconductor layer;

[0016] Preferably, the atomic doping segment is an aluminum doped segment, a phosphorus doped segment or a boron doped segment;

[0017] Preferably, the second conductor segment comprises a metal layer disposed on a surface of the second semiconductor layer;

[0018] Preferably, the second conductor segment comprises a metal layer provided on the second gate insulating layer and the second semiconductor layer, the metal layer comprises a fifth region, an orthographic projection of the fifth region on the substrate is located within an orthographic projection of the gate on the substrate, and the fifth region is provided on the second semiconductor layer;

[0019] Preferably, the metal layer further includes a sixth region connected to the fifth region, the orthographic projection of the sixth region on the substrate is located outside the orthographic projection of the second semiconductor layer on the substrate, and the sixth region is connected to the second electrode. The advantage is that a solution for conductorization of multiple semiconductor materials is provided.

[0020] In one embodiment, the first active layer includes an amorphous silicon semiconductor layer, a low temperature polycrystalline silicon semiconductor layer or a metal oxide semiconductor layer;

[0021] The second active layer includes an amorphous silicon semiconductor layer, a low temperature polysilicon semiconductor layer or a metal oxide semiconductor layer;

[0022] Preferably, the first active layer and the second active layer include semiconductor layers of the same material;

[0023] Preferably, the metal oxide semiconductor layer comprises a crystallized metal oxide semiconductor layer;

[0024] Preferably, the metal oxide semiconductor layer includes a first sublayer and a second sublayer, the first sublayer is located on a side of the second sublayer close to the gate, and the carrier mobility of the first sublayer is less than the carrier mobility of the second sublayer. The advantage is that the thin film transistor device is suitable for different types of devices and further improves the subthreshold swing.

[0025] In one embodiment, it further includes an interlayer insulating layer disposed on the second active layer, the first electrode and the second electrode are disposed on the interlayer insulating layer, a second via hole is disposed through the interlayer insulating layer, the first gate insulating layer and the second gate insulating layer, the first electrode is connected to the first active layer via the second via hole, the interlayer insulating layer is provided with a third via hole, and the second electrode is connected to the second active layer via the third via hole;

[0026] Preferably, it further comprises a planar layer disposed on the interlayer insulating layer, the first electrode and the second electrode are disposed on the planar layer, and the second via hole and the third via hole also penetrate the planar layer;

[0027] Alternatively, the first electrode is disposed on the first gate insulating layer, a second via hole is provided on the first gate insulating layer, and the first electrode is connected to the first active layer via the second via hole; the thin film transistor device further comprises an interlayer insulating layer disposed on the second active layer, the second electrode is disposed on the interlayer insulating layer, a third via hole is provided on the interlayer insulating layer, and the second electrode is connected to the second active layer via the third via hole. The advantage is that each electrode can be formed by the same photomask process, or it is conducive to reducing the height of the via hole.

[0028] Another object of the embodiment of the present application is to provide a method for manufacturing a thin film transistor device, comprising:

[0029] forming a first semiconductor layer on a substrate;

[0030] forming a first layer of gate insulating material on the first semiconductor layer;

[0031] forming a gate on the first layer of gate insulating material;

[0032] forming a second layer of gate insulating material on the gate to expose a portion of the first semiconductor layer;

[0033] A second semiconductor layer is formed on the second layer of gate insulating material, and the second semiconductor layer is connected to the first semiconductor layer.

[0034] In one embodiment, the method further includes the step of making a portion of the first semiconductor layer conductive, including:

[0035] The first semiconductor layer includes a first portion, an orthographic projection of the first portion on the substrate is located outside an orthographic projection of the gate on the substrate;

[0036] Using the gate as a barrier, atomic implantation is performed on the first portion of the first semiconductor layer; or, a metal layer is formed on a surface of a portion of the first semiconductor layer that is away from the substrate; or, a metal layer is formed on the substrate, wherein the metal layer includes a fifth region and a sixth region, the first semiconductor layer is formed on the fifth region and the substrate, an orthographic projection of the gate on the substrate overlaps with an orthographic projection of the fifth region on the substrate, and an orthographic projection of the sixth region on the substrate is outside an orthographic projection of the gate on the substrate;

[0037] Preferably, the method further comprises the step of making a part of the second semiconductor layer conductive, comprising:

[0038] A barrier layer is formed on the second semiconductor layer to expose a portion of the second semiconductor layer, and atoms are implanted into the second semiconductor layer using the barrier layer as a barrier; or a metal layer is formed on a surface of the second semiconductor layer that is away from the substrate; or a metal layer is formed on the second semiconductor layer and the patterned second gate insulating material, wherein the metal layer includes a fifth region; the fifth region is disposed on the second semiconductor layer, and an orthographic projection of the gate on the substrate overlaps with an orthographic projection of the fifth region on the substrate;

[0039] Preferably, the metal layer further includes a sixth region connected to the fifth region, and an orthographic projection of the sixth region on the substrate is located outside an orthographic projection of the second semiconductor layer on the substrate.

[0040] Another object of the embodiments of the present application is to provide a display panel, comprising a plurality of thin film transistor devices as described in the above embodiments or thin film transistor devices manufactured according to the manufacturing method of the thin film transistor device described in the above embodiments, and pixel units connected to the thin film transistor devices.

[0041] The thin film transistor device, manufacturing method and display panel provided by the embodiments of the present application have the following beneficial effects:

[0042] The thin film transistor device provided in the embodiment of the present application comprises a first active layer, a first gate insulating layer, a gate, a second gate insulating layer, a second active layer, a first electrode and a second electrode, wherein the first active layer, the first gate insulating layer, the gate, the second gate insulating layer and the second active layer are sequentially stacked on a substrate, and the first active layer is connected to the second active layer, the first electrode is connected to the first active layer, and the second electrode is connected to the second active layer. Due to the three-dimensional stacking of the first active layer and the second active layer on the upper and lower sides of the gate, the thin film transistor device is essentially folded in a three-dimensional space, the planar area occupied by the thin film transistor device on the substrate is small, the orthographic projection area of ​​the thin film transistor device on the substrate is small, and when the thin film transistor device is applied to a display panel, it occupies less area of ​​the non-opening area, which is conducive to ensuring a high aperture ratio and high resolution of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0044] Figure 1 is a cross-sectional view of a thin film transistor device provided in the first embodiment of the present application;

[0045] Figure 2 is a top view of a thin film transistor device provided in the first embodiment of the present application, wherein only the stacking relationship from the first active layer to the gate is shown;

[0046] Figure 3 is a top view of a thin film transistor device provided in the first embodiment of the present application, wherein only the stacking relationship from the gate to the second active layer is shown;

[0047] Figure 4is a cross-sectional view of a thin film transistor device provided in the first embodiment of the present application, wherein only a part of the film layer structure is shown;

[0048] Figure 5 is a cross-sectional view of a thin film transistor device provided in a second embodiment of the present application;

[0049] Figure 6 is a top view of a thin film transistor device provided in the second embodiment of the present application, wherein only the stacking relationship from the first active layer to the gate is shown;

[0050] Figure 7 is a top view of a thin film transistor device provided in the second embodiment of the present application, wherein only the stacking relationship from the gate to the second active layer is shown;

[0051] Figure 8 is a cross-sectional view of a thin film transistor device provided in a third embodiment of the present application;

[0052] Fig. 9 is a top view of a thin film transistor device provided in a fourth embodiment of the present application, wherein only the stacking relationship from the gate to the second active layer is shown;

[0053] Fig.10 is a cross-sectional view of a thin film transistor device provided in a fifth embodiment of the present application;

[0054] Fig.11 is a cross-sectional view of a thin film transistor device provided in a sixth embodiment of the present application;

[0055] Fig.12 is a flow chart of a method for manufacturing a thin film transistor device provided in an embodiment of the present application;

[0056] Fig.13 is a schematic diagram of step S1 of the method for manufacturing a thin film transistor device provided in the seventh embodiment of the present application;

[0057] Fig.14 is a schematic diagram of step S2 of the method for manufacturing a thin film transistor device provided in the seventh embodiment of the present application;

[0058] Fig.15 is a schematic diagram of step S3 of the method for manufacturing a thin film transistor device provided in the seventh embodiment of the present application;

[0059] Fig.16 and Fig.17 is a schematic diagram of step S4 of the method for manufacturing a thin film transistor device provided in the seventh embodiment of the present application;

[0060] Fig.18 is a schematic diagram of step S5 of the method for manufacturing a thin film transistor device provided in the seventh embodiment of the present application;

[0061] Fig.19 and Fig. 20 It is a schematic diagram of the step of partially conducting the second semiconductor layer in step S5 of the method for manufacturing a thin film transistor device provided in the seventh embodiment of the present application;

[0062] Fig.21 is a schematic diagram of step S6 of the method for manufacturing a thin film transistor device provided in the seventh embodiment of the present application;

[0063] Fig. 22 is a schematic diagram of step S1' of the method for manufacturing a thin film transistor device provided in the eighth embodiment of the present application;

[0064] Fig.23 It is a schematic diagram of the structure of a display panel provided in the ninth embodiment of the present application.

[0065] The meanings of the marks in the figure are:

[0066] 200-display panel, 99-pixel unit, 98-driving device, 97-switch device;

[0067] 100-Thin Film Transistor Device;

[0068] 10-substrate;

[0069] 11-gate;

[0070] 12-gate insulating layer;

[0071] 121-first gate insulating layer, 1213-third region;

[0072] 122- a second gate insulating layer;

[0073] 13-active layer;

[0074] 131-first active layer, 1311-first region, 1314-fourth region, 1315-first semiconductor layer, 1316-first conductor segment, 13165, 13165'-fifth region, 13166, 13166'-sixth region; 132-second active layer, 1322-second region, 1325-second semiconductor layer, 1326-second conductor segment;

[0075] 135-first sublayer, 136-second sublayer;

[0076] 141- a first electrode;

[0077] 142- second electrode;

[0078] 143 - third electrode;

[0079] 151 - buffer layer, 152 - light shielding layer, 153 - first insulating layer, 154 - interlayer insulating layer, 155 - planarizing layer;

[0080] 161 - first via hole, 162 - second via hole, 163 - third via hole, 164 - fourth via hole;

[0081] 81 - blocking layer, 71 - a first layer of gate insulating material, 72 - a second layer of gate insulating material. DETAILED DESCRIPTION

[0082] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0083] It should be noted that when a component is referred to as being "fixed to" or "disposed on" another component, it may be directly or indirectly fixed or disposed on the other component. When a component is referred to as being "connected to" another component, it may be directly or indirectly connected to the other component. The orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", etc. is based on the orientation or positional relationship shown in the accompanying drawings and is only for the convenience of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of this patent. The terms "first" and "second" are only used for the convenience of description and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features. "Multiple" means two or more, unless otherwise clearly and specifically defined.

[0084] In order to illustrate the technical solution described in this application, a detailed description is given below in conjunction with specific drawings and embodiments.

[0085] In the display panel, the thin film transistor device acts as a switching device and a driving device, providing a driving voltage to each pixel unit through various wirings, thereby controlling the opening of each pixel unit. The area where the thin film transistor device and wiring are set is the non-opening area, and the pixel unit for emitting light is set in the opening area. Within a certain area, the smaller the area of ​​the non-opening area, the more pixel units can be set on the entire display panel, that is, the higher the resolution of the display panel. Therefore, how to reduce the area of ​​the non-opening area has become an important improvement project in the direction of improving resolution.

[0086] See also Figure 1 As shown, the embodiment of the present application first provides a thin film transistor device 100, which can occupy a smaller area; see Fig.23As shown, the thin film transistor device 100 is applied to the display panel 200 , which is beneficial to reducing the area of ​​the non-opening region, thereby facilitating improving the resolution of the display panel 200 .

[0087] Specifically, see Figure 1 As shown, the thin film transistor device 100 includes a gate 11, a gate insulating layer 12, an active layer 13, a first electrode 141 and a second electrode 142. The active layer 13 includes a first active layer 131 and a second active layer 132, the gate insulating layer 12 includes a first gate insulating layer 121 and a second gate insulating layer 122, the first active layer 131 is disposed on the substrate 10, the first gate insulating layer 121 is disposed on the first active layer 131, the gate 11 is disposed on the first gate insulating layer 121, the second gate insulating layer 122 is disposed on the gate 11, the second active layer 132 is disposed on the second gate insulating layer 122 and connected to the first active layer 131, the first electrode 141 is connected to the first active layer 131, and the second electrode 142 is connected to the second active layer 132.

[0088] In this way, the first active layer 131, the first gate insulating layer 121, the gate 11, the second gate insulating layer 122 and the second active layer 132 are stacked in sequence in a direction perpendicular to the substrate 10, so that the active layer 13 and the gate insulating layer 12 are equivalent to being folded in a three-dimensional space after bypassing the gate 11.

[0089] The first active layer 131 includes a first region 1311 connected to the first electrode 141, and the second active layer 132 includes a second region 1322 connected to the second electrode 142. On the active layer 13, the portion between the first region 1311 and the second region 1322 is a conductive channel, and the distance between the first region 1311 and the second region 1322 is the length of the channel. It can be understood that the distance between the first region 1311 and the second region 1322 mentioned here does not refer to the straight-line distance between the two, but refers to the length of the curve consistent with the three-dimensional folding direction of the active layer 13. Figure 1 As shown, the channel of the active layer 13 is generally C-shaped. The first active layer 131 and the second active layer 132 are connected in series, and the length of the channel of the thin film transistor device 100 is the sum of the length of the channel on the first active layer 131 and the length of the channel on the second active layer 132.

[0090] Due to the three-dimensional stacking of the first active layer 131 and the second active layer 132 on the upper and lower sides of the gate 11, the thin film transistor device 100 provided in the embodiment of the present application is substantially folded in a three-dimensional space, and the thin film transistor device 100 occupies a small plane area on the substrate 10, that is, the orthographic projection area of ​​the thin film transistor device 100 on the substrate 10 is small. In this way, when the thin film transistor device 100 is applied to the display panel 200, it occupies less area of ​​the non-opening area, which is conducive to ensuring a high aperture ratio and high resolution of the display panel 200.

[0091] The type of the thin film transistor device 100 is not limited. Optionally, the first active layer 131 and the second active layer 132 are of the same type.

[0092] The thin film transistor device 100 may be an amorphous silicon thin film transistor, wherein the first active layer 131 and the second active layer 132 include an amorphous silicon semiconductor layer.

[0093] Alternatively, the thin film transistor device 100 is a low temperature polysilicon thin film transistor, and the first active layer 131 and the second active layer 132 thereof include a low temperature polysilicon semiconductor layer.

[0094] Alternatively, the thin film transistor device 100 is a metal oxide thin film transistor, and the first active layer 131 and the second active layer 132 thereof include metal oxide semiconductor layers.

[0095] In an optional embodiment, the thin film transistor device 100 is a metal oxide thin film transistor, and its first active layer 131 and the second active layer 132 are zinc oxide (ZnO) layers, or indium oxide (In2O3) layers, or tin oxide (SnO2) layers, or indium gallium zinc oxide (IGZO) layers, etc.

[0096] In an optional embodiment, the metal oxide semiconductor layer includes a crystallized metal oxide semiconductor layer. The crystallized metal oxide semiconductor layer refers to a semiconductor structure in which the atoms or molecules inside the metal oxide semiconductor material are regularly arranged and crystalline after being specifically treated. During the etching process of other film layers, the crystallized metal oxide semiconductor layer is less affected by the etching.

[0097] Compared with amorphous silicon thin film transistors, the metal oxide semiconductor layer of metal oxide thin film transistors has higher electron mobility. Compared with low-temperature polysilicon thin film transistors, the metal oxide semiconductor layer of metal oxide thin film transistors is easier to prepare. Metal oxide thin film transistors are used in the display panel 200 as driving thin film transistors, which can make the pixel unit 99 charge and discharge faster. As a result, the pixel unit 99 can respond and switch to a new state more quickly, the image smear, blur and jamming are reduced, and the display panel 200 has a clearer and smoother visual experience.

[0098] At the same time, the high electron mobility of the thin film transistor device 100 is accompanied by a low subthreshold swing. The reduction of the subthreshold swing will lead to insufficient grayscale expansion when the picture is displayed at a low grayscale, affecting the accuracy of the picture display.

[0099] The active layer 13 of the thin film transistor device 100 described above in the embodiment of the present application is substantially folded in a three-dimensional space, which can increase the length of the channel, thereby increasing its subthreshold swing. The thin film transistor device 100 can accurately output a corresponding small current under a relatively small gate 11 voltage, and can be applied to a display panel 200 to realize the expansion and accurate display of multiple low grayscale images.

[0100] In an alternative embodiment, see Figure 4 As shown, the metal oxide semiconductor layer may include a first sublayer 135 and a second sublayer 136, the first sublayer 135 is located on a side of the second sublayer 136 close to the gate 11, and the carrier mobility of the first sublayer 135 is less than the carrier mobility of the second sublayer 136. For example, in the thin film transistor device 100, the first active layer 131 may include the first sublayer 135 and the second sublayer 136, the first sublayer 135 is located on a side of the second sublayer 136 close to the gate 11; for another example, in the thin film transistor device 100, the second active layer 132 may include the first sublayer 135 and the second sublayer 136, the first sublayer 135 is located on a side of the second sublayer 136 close to the gate 11; or, in the thin film transistor device 100, the first active layer 131 and the second active layer 132 both include the first sublayer 135 and the second sublayer 136, as shown in FIG. Figure 4 shown.

[0101] The purpose of such a setting is that, since the carrier mobility of the first sublayer 135 is small and the first sublayer 135 is arranged close to the gate 11, when a voltage is applied to the gate 11, under the same electric field, the number of carriers induced in the metal oxide semiconductor layer becomes less, and thus, overall, the electron mobility of the thin film transistor device 100 is reduced, which can improve the subthreshold swing of the thin film transistor device 100.

[0102] First embodiment

[0103] See also Figures 1 to 3 As shown, the orthographic projection of the first region 1311 on the substrate 10 is outside the orthographic projection of the gate 11 on the substrate 10. At this time, regardless of the location and layer of the first electrode 141, the first region 1311 is easily connected to the first electrode 141.

[0104] like Figure 1 As shown, the first active layer 131 also includes a fourth region 1314, the orthographic projection of the fourth region 1314 on the substrate 10 is located outside the orthographic projection of the gate insulating layer 12 on the substrate 10, and the fourth region 1314 is not covered by the first gate insulating layer 121 and the second gate insulating layer 122, and thus can be used to connect with the second active layer 132. The orthographic projection of the gate insulating layer 12 on the substrate 10 refers to the common orthographic projection of the first gate insulating layer 121 and the second gate insulating layer 122. In this embodiment, the first gate insulating layer 121 and the second gate insulating layer 122 are patterned and removed on one side away from the first region 1311 to expose the fourth region 1314 of the first active layer 131.

[0105] Of course, it can be understood that, except for the fourth region 1314 , the first gate insulating layer 121 covers the other parts of the first active layer 131 .

[0106] In an optional embodiment, the first active layer 131 includes a crystallized metal oxide semiconductor layer. Therefore, during the etching process of the first gate insulating layer 121, over-etching of the first active layer 131 can be avoided, which is beneficial to ensure the size and area of ​​the fourth region 1314 and ensure effective overlap between the first active layer 131 and the second active layer 132.

[0107] In other embodiments, according to process or functional requirements, the second active layer 132 may also include a crystallized metal oxide semiconductor layer.

[0108] The orthographic projection of the gate 11 on the substrate 10 is located within the orthographic projection of the first gate insulating layer 121 on the substrate 10, and on the side corresponding to the fourth region 1314, the edge of the orthographic projection of the gate 11 on the substrate 10 is spaced from the edge of the orthographic projection of the first gate insulating layer 121 on the substrate 10. In other words, see Figure 1 and Figure 2 As shown, the first gate insulating layer 121 includes a third region 1213, and the orthographic projection of the third region 1213 on the substrate 10 is located between the orthographic projection of the gate 11 on the substrate 10 and the orthographic projection of the fourth region 1314 on the substrate 10. The third region 1213 is not covered by the gate 11, and the third region 1213 is used to connect to the second gate insulating layer 122.

[0109] See also Figure 1 and Figure 3 As shown, a portion of the second gate insulating layer 122 is located on the surface of the gate 11 , and another portion is disposed on the side of the gate 11 close to the fourth region 1314 and connected to the third region 1213 of the first gate insulating layer 121 .

[0110] See also Figure 1 and Figure 3 As shown, a portion of the second active layer 132 is disposed on the surface of the second gate insulating layer 122 , and another portion is disposed on the outer surface of the second gate insulating layer 122 and connected to the fourth region 1314 of the first active layer 131 .

[0111] See also Figure 2 and Figure 3 As shown, in the top view direction of the thin film transistor device 100, the orthographic projection shapes of the first active layer 131, the first gate insulating layer 121, the gate 11, the second gate insulating layer 122, and the second active layer 132 are not limited. The drawings of the embodiments of the present application are described by taking a substantially rectangular regular pattern as an example.

[0112] See also Figure 1 and Figure 2 As shown, the first region 1311 and the fourth region 1314 of the first active layer 131 are two opposite regions on the first active layer 131, that is, two regions as far apart as possible, so as to ensure that the length of the channel on the first active layer 131 can be maximized. For example, on the rectangular first active layer 131, the first region 1311 and the fourth region 1314 can be distributed generally along the direction of one side of the rectangle, or generally along the diagonal direction of the rectangle. In addition, considering the width-to-length ratio of the channel, the channels of the first active layer 131 and the second active layer 132 should have a larger width, and the first region 1311 and the fourth region 1314 can be distributed generally along the width direction of the rectangle.

[0113] Similarly, the orthographic projection of the second region 1322 on the substrate 10 is located on the opposite side of the fourth region 1314 of the first active layer 131, also to ensure that the length between the second region 1322 and the fourth region 1314 is as large as possible.

[0114] The layers where the first electrode 141 and the second electrode 142 are located are not limited as long as they can be connected to the active layer 13 .

[0115] In one embodiment, if Figure 1As shown, the thin film transistor device 100 further includes an interlayer insulating layer 154, which is disposed on the second active layer 132 and the substrate 10 to cover both the second active layer 132 and the gate insulating layer 12. The first electrode 141 and the second electrode 142 are disposed on the interlayer insulating layer 154, the first electrode 141 penetrates the interlayer insulating layer 154 and then connects to the first active layer 131, and the second electrode 142 penetrates the interlayer insulating layer 154 and then connects to the second active layer 132.

[0116] Specifically, the second via hole 162 penetrates the interlayer insulating layer 154 , the first gate insulating layer 121 , and the second gate insulating layer 122 , and avoids the gate 11 . The first electrode 141 is connected to the first region 1311 via the second via hole 162 .

[0117] Specifically, the third via hole 163 penetrates the interlayer insulating layer 154 , and the second electrode 142 is connected to the second region 1322 through the third via hole 163 .

[0118] At this time, the first electrode 141 and the second electrode 142 are in the same layer and are formed by the same photomask process, which can reduce the number of manufacturing steps and lower the manufacturing cost.

[0119] like Figure 1 As shown in FIG. 1 , the first active layer 131 includes a first semiconductor layer 1315 and a first conductor segment 1316. The first conductor segment 1316 is located in the first region 1311 and is used to connect to the first electrode 141. The first conductor segment 1316 is used to reduce the contact resistance between the first electrode 141 and the first semiconductor layer 1315.

[0120] Similarly, the second active layer 132 includes a second semiconductor layer 1325 and a second conductor segment 1326. The second conductor segment 1326 is located in the second region 1322 and is used to connect to the second electrode 142. The second conductor segment 1326 is used to reduce the contact resistance between the second electrode 142 and the second semiconductor layer 1325.

[0121] The first semiconductor layer 1315 and the second semiconductor layer 1325 are amorphous silicon semiconductor layers, low temperature polysilicon semiconductor layers or metal oxide semiconductor layers.

[0122] The first conductor segment 1316 may include an atomic doped segment disposed on one side of the first semiconductor layer 1315 , such as an Al (aluminum) doped segment, a P (phosphorus) doped segment, a B (boron) doped segment, and the like.

[0123] It should be noted that when performing atomic doping, the gate 11 can be used as a barrier. Since the first region 1311 and the fourth region 1314 (including the portion of the first semiconductor layer 1315 corresponding to the third region 1213) are not covered by the gate 11, atoms will be injected into the first region 1311 and the fourth region 1314. At this time, the fourth region 1314 is also conductive and cannot be used as a channel. Although this reduces the channel length between the first region 1311 and the second region 1322, the channel length can still be guaranteed based on the three-dimensional folding structure of the thin film transistor device 100.

[0124] In the orthographic projection direction of the substrate 10, the thickness of the atomic doping segment may be equal to the thickness of the first semiconductor layer 1315, or may be less than the thickness of the first semiconductor layer 1315. Figure 1 shown.

[0125] Alternatively, the first conductor segment 1316 may include a metal layer disposed on a portion of the surface of the first semiconductor layer 1315. The metal layer is an easily oxidizable metal layer, which can combine with oxygen atoms in the first semiconductor layer 1315, so that oxygen vacancies are generated in the portion of the first semiconductor layer 1315 corresponding to the metal layer, thereby enhancing conductivity and achieving conductorization.

[0126] Likewise, the second conductor segment 1326 may include an atomically doped segment disposed on one side of the second semiconductor layer 1325 , such as an Al (aluminum) doped segment, a P (phosphorus) doped segment, a B (boron) doped segment, and the like.

[0127] Alternatively, the second conductor segment 1326 may include a metal layer disposed on a portion of the surface of the second semiconductor layer 1325. The metal layer is an easily oxidizable metal layer, which can combine with oxygen atoms in the second semiconductor layer 1325, so that oxygen vacancies are generated in the portion of the second semiconductor layer 1325 corresponding to the metal layer, thereby enhancing conductivity and achieving conductorization.

[0128] Optionally, the first conductor segment 1316 and the second conductor segment 1326 are identical.

[0129] Please continue reading Figure 1 As shown, in one embodiment, the thin film transistor device 100 further includes a light shielding layer 152, which is disposed between the substrate 10 and the first active layer 131 and is insulated from the first active layer 131. The light shielding layer 152 is made of an opaque material to prevent light from irradiating the first active layer 131 from one side of the substrate 10 and generating an undesired photocurrent.

[0130] Optionally, the light shielding layer 152 is made of a metal material and is used to connect a fixed potential. Thus, the light shielding layer 152 can further provide an electromagnetic shielding function to prevent the thin film transistor device 100 from being subjected to electromagnetic interference.

[0131] Specific as Figure 1 As shown, a first insulating layer 153 is provided between the light shielding layer 152 and the first active layer 131, and the first insulating layer 153 is used to insulate and isolate the first active layer 131 from the light shielding layer 152. The material of the first insulating layer 153 can be at least one of silicon oxide and silicon nitride.

[0132] like Figure 1 As shown, in an optional embodiment, the fourth via hole 164 penetrates the interlayer insulating layer 154, the second gate insulating layer 122, the first gate insulating layer 121 and the first insulating layer 153, and the third electrode 143 is disposed on the interlayer insulating layer 154 and connected to the light shielding layer 152 via the fourth via hole 164. The third electrode 143 can be in the same layer as the first electrode 141 and the second electrode 142 and formed by a channel mask.

[0133] Please continue reading Figure 1 As shown, in one embodiment, the thin film transistor device 100 further includes a flat layer 155, the flat layer 155 is disposed on the interlayer insulating layer 154, and the first electrode 141, the second electrode 142 and the third electrode 143 are all disposed on the flat layer 155. In this way, the flat layer 155 provides a flat surface, which is conducive to the manufacture of the first electrode 141, the second electrode 142 and the third electrode 143, and the wiring arrangement. The second via 162, the third via 163 and the fourth via 164 are also disposed through the flat layer 155.

[0134] Second embodiment

[0135] See also Figures 5 to 7 As shown, the difference between the second embodiment and the aforementioned first embodiment is that the gate insulating layer 12 has a larger coverage area, and the first gate insulating layer 121 and the second gate insulating layer 122 are provided with a first via hole 161 penetrating therethrough, and the first via hole 161 is used to expose the fourth region 1314, and the second active layer 132 is partially disposed in the first via hole 161, so that the second active layer 132 is connected to the fourth region 1314 of the first active layer 131 via the first via hole 161. A portion of the second active layer 132 is also filled in the first via hole 161. Except for the first via hole 161, the first gate insulating layer 121 and the second gate insulating layer 122 fully cover the gate 11 and the first active layer 131.

[0136] That is, the first gate insulating layer 121 and the second gate insulating layer 122 are not completely removed at a side of the first active layer 131 away from the first region 1311 thereof. The interlayer insulating layer 154 may be partially formed on the second gate insulating layer 122 .

[0137] The purpose of such a configuration is that, on the side of the thin film transistor device 100 away from the first region 1311, since the first gate insulating layer 121 and the second gate insulating layer 122 are not completely removed, there will be no large step difference between the interlayer insulating layer 154 and the second gate insulating layer 122, which is more advantageous in the formation of the interlayer insulating layer 154 and the planarizing layer 155.

[0138] In addition, when the side of the thin film transistor device 100 away from the first region 1311 has other structures (please refer to Fig.23 When the switching device 97 shown in the figure is set, its multi-layer structure and / or circuit can be manufactured by using the first gate insulating layer 121 and the second gate insulating layer 122 that are not removed.

[0139] like Figure 6 As shown, the orthographic projection of the first via hole 161 on the substrate 10 can completely cover the orthographic projection of the fourth region 1314 on the substrate 10 to ensure that the fourth region 1314 is completely exposed and that the connection between the first active layer 131 and the second active layer 132 has sufficient channel width.

[0140] Third embodiment

[0141] See also Figure 8 As shown, the difference between the third embodiment and the aforementioned first embodiment is that the first conductor segment 1316 is different. In the third embodiment, the first conductor segment 1316 includes a metal layer disposed between the first semiconductor layer 1315 and the substrate 10, the metal layer includes a fifth region 13165 and a sixth region 13166 connected to each other, the orthographic projection of the fifth region 13165 on the substrate 10 overlaps with the orthographic projection of the gate 11 on the substrate 10, the first semiconductor layer 1315 is partially disposed on the fifth region 13165, the orthographic projection of the sixth region 13166 on the substrate 10 is located outside the orthographic projection of the gate 11 on the substrate 10, and the first electrode 141 is connected to the sixth region 13166.

[0142] The fifth region 13165 of the metal layer overlaps with the gate 11 in the orthographic projection direction of the substrate 10. When a voltage is applied to the gate 11, the common electric field generated between the gate 11 and the fifth region 13165 will change the distribution of carriers in the first semiconductor layer 1315, so that the portion of the first semiconductor layer 1315 corresponding to the fifth region 13165 exhibits conductive characteristics.

[0143] The material of the metal layer can be a molybdenum layer or a titanium-aluminum-titanium composite layer.

[0144] Fourth embodiment

[0145] See also Fig. 9 As shown, the difference between the fourth embodiment and the first embodiment is that the second conductor segment 1326 can also be set as a metal layer that partially overlaps with the gate 11. Fig. 9 As shown, the second conductor segment 1326 includes a metal layer disposed on the second semiconductor layer 1325 and the second gate insulating layer 122, the metal layer includes a fifth region 13165' and a sixth region 13166' connected to each other, the orthographic projection of the fifth region 13165' on the substrate 10 overlaps with the orthographic projection of the gate 11 on the substrate 10, the fifth region 13165' is disposed on the second semiconductor layer 1325, the orthographic projection of the sixth region 13166' on the substrate 10 is located outside the orthographic projection of the second semiconductor layer 1325 on the substrate 10, and the second electrode 142 is connected to the sixth region 13166'. The sixth region 13166' is disposed on the second gate insulating layer 122. Optionally, the orthographic projection of the sixth region 13166' on the substrate 10 is located within the orthographic projection of the gate 11 on the substrate 10, which is conducive to reducing the step difference between the fifth region 13165' and the sixth region 13166'; alternatively, it is also possible that the orthographic projection of the sixth region 13166' on the substrate 10 is located between the orthographic projection of the gate 11 on the substrate 10.

[0146] The sixth region 13166' is used to connect the fifth region 13165' and the second electrode 142. Therefore, in some embodiments, the sixth region 13166' may be eliminated so that the second electrode 142 is directly connected to the fifth region 13165'.

[0147] The fifth region 13165' of the metal layer overlaps with the gate 11 in the direction of the orthographic projection of the substrate 10. When a voltage is applied to the gate 11, the common electric field generated between the gate 11 and the fifth region 13165' will change the distribution of carriers in the second semiconductor layer 1325, so that the portion of the second semiconductor layer 1325 corresponding to the fifth region 13165' exhibits conductive characteristics.

[0148] The material of the metal layer can be a molybdenum layer or a titanium-aluminum-titanium composite layer.

[0149] Fifth embodiment

[0150] See also Fig.10As shown, the difference between the fifth embodiment and the aforementioned second embodiment is that the first conductor segment 1316 is different. In the fifth embodiment, the first conductor segment 1316 includes a metal layer disposed between the first semiconductor layer 1315 and the substrate 10, the metal layer includes a fifth region 13165 and a sixth region 13166 connected to each other, the orthographic projection of the fifth region 13165 on the substrate 10 overlaps with the orthographic projection of the gate 11 on the substrate 10, the first semiconductor layer 1315 is partially disposed on the fifth region 13165, the orthographic projection of the sixth region 13166 on the substrate 10 is located outside the orthographic projection of the gate 11 on the substrate 10, and the first electrode 141 is connected to the sixth region 13166.

[0151] The fifth region 13165 of the metal layer overlaps with the gate 11 in the orthographic projection direction of the substrate 10. When a voltage is applied to the gate 11, the common electric field generated between the gate 11 and the fifth region 13165 will change the distribution of carriers in the first semiconductor layer 1315, so that the portion of the first semiconductor layer 1315 corresponding to the fifth region 13165 exhibits conductive characteristics.

[0152] The material of the metal layer can be a molybdenum layer or a titanium-aluminum-titanium composite layer.

[0153] Sixth embodiment

[0154] See also Fig.11 As shown, the difference between the sixth embodiment and the first embodiment is that the first electrode 141 and the third electrode 143 are located in different layers. In the sixth embodiment, the first electrode 141 and the third electrode 143 are disposed on the first gate insulating layer 121 and in the same layer as the gate 11, and are formed by the same photomask and the same process as the gate 11.

[0155] The second via 162 penetrates the first gate insulating layer 121 , and the first electrode 141 is connected to the first region 1311 via the second via 162 ; the fourth via 164 penetrates the first gate insulating layer 121 and the first insulating layer 153 , and the third electrode 143 is connected to the light shielding layer 152 via the fourth via 164 .

[0156] It can be understood that the first electrode 141 and the third electrode 143 are arranged in the same layer as the gate 11, and the wiring used to connect the first electrode 141 and the third electrode 143 can be arranged in the same layer as the gate 11, or can be arranged in a different layer from the gate 11. For example, above the first electrode 141, a via hole penetrating the second gate insulating layer 122, the interlayer insulating layer 154, and the flat layer 155 can be continuously arranged to connect the first electrode 141 with the wiring located on the flat layer 155, and, above the third electrode 143, a via hole penetrating the second gate insulating layer 122, the interlayer insulating layer 154, and the flat layer 155 can be continuously arranged to connect the third electrode 143 with the wiring located on the flat layer 155.

[0157] See also Fig.12 As shown, an embodiment of the present application provides a method for manufacturing a thin film transistor device, comprising:

[0158] Step S1, such as Fig.13 As shown, a first semiconductor layer 1315 is formed on a substrate 10;

[0159] Step S2, such as Fig.14 As shown, a first layer of gate insulating material 71 is formed on the first semiconductor layer 1315;

[0160] Step S3, such as Fig.15 As shown, a gate 11 is formed on the first layer of gate insulating material 71;

[0161] Step S4, such as Fig.16 and Fig.17 As shown, a second layer of gate insulating material 72 is formed on the gate 11, and the first layer of gate insulating material 71 and the second layer of gate insulating material 72 are patterned to form a first gate insulating layer 121 and a second gate insulating layer 122, exposing the fourth region 1314 of the first semiconductor layer 1315;

[0162] Step S5, such as Fig.18 As shown, a second semiconductor layer 1325 is formed on the second gate insulating layer 122, and the second semiconductor layer 1325 is connected to the first semiconductor layer 1315;

[0163] And step S6, such as Fig.21 As shown, an interlayer insulating layer 154 and a planarization layer 155 are formed on the second semiconductor layer 1325 .

[0164] In step S1, a first semiconductor material layer is deposited on the substrate 10, and the first semiconductor material layer is patterned to obtain a first semiconductor layer 1315. Fig.13 As shown, the first semiconductor layer 1315 includes a first region 1311 and a fourth region 1314 that are spaced apart from each other;

[0165] In step S3 , the orthographic projection of the first region 1311 on the substrate 10 is located outside the orthographic projection of the gate 11 on the substrate 10 .

[0166] Among them, in step S4, if Fig.16 and Fig.17 As shown, after the first layer of gate insulating material 71 and the second layer of gate insulating material 72 are patterned to obtain the first gate insulating layer 121 and the second gate insulating layer 122, the first gate insulating layer 121 and the second gate insulating layer 122 allow the fourth region 1314 of the first active layer 131 to be exposed; the first gate insulating layer 121 and the second gate insulating layer 122 are connected to each other and cover the gate 11.

[0167] Among them, in step S5, if Fig.18 As shown, a second layer of semiconductor material is formed on the second gate insulating layer 122, and the second layer of semiconductor material is patterned to obtain a second semiconductor layer 1325. The second semiconductor layer 1325 is located on the surface of the second gate insulating layer 122 and the outer side away from the gate 11. The second semiconductor layer 1325 is connected to the fourth region 1314 of the first semiconductor layer 1315.

[0168] Seventh embodiment

[0169] In the seventh embodiment, see Fig.13 As shown, in step S1 , it also includes: forming a buffer layer 151 on the substrate 10 , forming a light shielding layer 152 on the buffer layer 151 , and forming a first insulating layer 153 on the light shielding layer 152 ; wherein the first semiconductor layer 1315 is formed on the first insulating layer 153 .

[0170] In one embodiment, the method for manufacturing the thin film transistor device further includes: a step of partially conducting the first semiconductor layer 1315 and the second semiconductor layer 1325. This includes: in step S3, as Fig.15 As shown, with the gate 11 as a barrier pattern, atoms are implanted into the first semiconductor layer 1315 to make the first region 1311 and the fourth region 1314 on the first semiconductor layer 1315 conductive, and a first conductor segment 1316 is obtained in the first region 1311; and Fig.19 As shown, in step S5, a barrier layer 81 is formed on the second semiconductor layer 1325 to expose the second region 1322 of the second semiconductor layer 1325. The barrier layer 81 is used as a barrier to perform atomic implantation on the second semiconductor layer 1325 to obtain a second conductor segment 1326 in the second region 1322. The barrier layer 81 is then removed. Fig. 20 shown.

[0171] Alternatively, the step of partially conducting the first semiconductor layer 1315 and the second semiconductor layer 1325 includes: forming a metal layer on a partial surface of the first semiconductor layer 1315, the metal layer being an easily oxidized metal layer, which can combine with oxygen atoms in the first semiconductor layer 1315, so that oxygen vacancies are generated in the portion of the first semiconductor layer 1315 corresponding to the metal layer, thereby enhancing the conductivity and achieving conductorization; and forming a metal layer on a partial surface of the second semiconductor layer 1325, the metal layer being an easily oxidized metal layer, which can combine with oxygen atoms in the second semiconductor layer 1325, so that oxygen vacancies are generated in the portion of the second semiconductor layer 1325 corresponding to the metal layer, thereby enhancing the conductivity and achieving conductorization.

[0172] In one embodiment, in step S4, refer to Fig.16 and Fig.17 As shown, the first layer of gate insulating material 71 and the second layer of gate insulating material 72 are removed near the fourth region 1314 to expose the fourth region 1314 of the first active layer 131 and part of the first insulating layer 153. In step S5, the second layer of semiconductor material is partially deposited on the first insulating layer 153 and then patterned.

[0173] Alternatively, in step S4, a first via 161 is formed on the first layer of gate insulating material 71 and the second layer of gate insulating material 72, and the first via 161 exposes the fourth region 1314 of the first active layer 131; in step S5, a second layer of semiconductor material is deposited in the second gate insulating layer 122 and its first via 161, and then patterned.

[0174] In one embodiment, if Fig.21 As shown, the method for manufacturing the thin film transistor device further includes:

[0175] Step S7, a third via hole 163 is formed on the interlayer insulating layer 154 and the planar layer 155, a second via hole 162 is formed on the planar layer 155, the interlayer insulating layer 154, the first gate insulating layer 121, and the second gate insulating layer 122, and a fourth via hole 164 is formed on the planar layer 155, the interlayer insulating layer 154, the first gate insulating layer 121, the second gate insulating layer 122, and the first insulating layer 153;

[0176] Then, a conductive metal layer is deposited on the flat layer 155 and patterned to obtain a first electrode 141, a second electrode 142 and a third electrode 143. The first electrode 141 is connected to the first conductor segment 1316 of the first active layer 131 via the second via 162, the second electrode 142 is connected to the second conductor segment 1326 via the third via 163, and the third electrode 143 is connected to the light shielding layer 152 via the fourth via 164.

[0177] Eighth embodiment

[0178] See also Fig. 22 As shown, in the method for manufacturing the thin film transistor device, the step of partially conducting the first semiconductor layer 1315 is implemented before step S1, which is defined as step S1', and the step of partially conducting the second semiconductor layer 1325 is implemented after step S5.

[0179] Specifically, in step S1′, before forming the first semiconductor layer 1315, a first conductor segment 1316 is formed on the substrate 10, the first conductor segment 1316 includes a metal layer, the metal layer includes a fifth region 13165 and a sixth region 13166 connected to each other, and the first semiconductor layer 1315 is partially disposed on the fifth region 13165. The first active layer 131 is formed by at least the first semiconductor layer 1315 and the first conductor segment 1316;

[0180] In step S3 , the obtained gate 11 overlaps with the fifth region 13165 of the metal layer in the orthographic projection direction of the substrate 10 , while the sixth region 13166 is staggered with the gate 11 in the orthographic projection direction of the substrate 10 .

[0181] The method further includes, after step S5, forming a second conductor segment 1326 on the second semiconductor layer 1325 and the second gate insulating layer 122, wherein the second conductor segment 1326 includes a metal layer, and the metal layer includes a fifth region 13165' and a sixth region 13166' connected to each other, wherein the fifth region 13165' is disposed on the second semiconductor layer 1325, and the sixth region 13166' is disposed on the second gate insulating layer 122. The second active layer 132 is formed by at least the second semiconductor layer 1325 and the second conductor segment 1326. The fifth region 13165' of the metal layer overlaps with the gate 11 in the orthographic projection direction of the substrate 10, while the sixth region 13166' is staggered with the gate 11 in the orthographic projection direction of the substrate 10, please refer to the aforementioned Fig. 9 shown.

[0182] Ninth embodiment

[0183] like Fig.23 As shown, a ninth embodiment of the present application provides a display panel 200 , which includes the thin film transistor device 100 as described in the above embodiments.

[0184] Specifically, the display panel 200 is provided with a plurality of pixel units 99 and a pixel driving circuit for driving each pixel unit 99 to work, and the pixel driving circuit includes a plurality of driving devices 98 and a plurality of switching devices 97. The driving device 98 and / or the switching device 97 adopts the thin film transistor device 100 described in the above embodiments. The specific structure of the pixel driving circuit is not limited.

[0185] In an optional embodiment, the driving device 98 is the thin film transistor device 100 described in the above embodiments. Further optionally, the thin film transistor device 100 is a metal oxide thin film transistor, an amorphous silicon thin film transistor or a low temperature polysilicon thin film transistor. In a specific embodiment, the thin film transistor device 100 is a metal oxide thin film transistor.

[0186] In an optional embodiment, the switch device 97 is the thin film transistor device 100 mentioned in the above embodiments. Further optionally, the thin film transistor device 100 is a metal oxide thin film transistor, an amorphous silicon thin film transistor or a low temperature polysilicon thin film transistor.

[0187] In an optional embodiment, the driving device 98 and the switching device 97 are both the thin film transistor device 100 described in the above embodiments. Based on the different working requirements of the driving device 98 and the switching device 97, the driving device 98 and the switching device 97 can have different structures and types.

[0188] Since the display panel 200 uses the thin film transistor device 100 as described in the above embodiments, the display panel 200 has the same technical effects as the above embodiments, which will not be described in detail here.

[0189] It can be understood that the thin film transistor device 100 is manufactured on the substrate 10. In the display panel 200, the substrate 10, the buffer layer 151, the shading layer 152, the first insulating layer 153, the first gate insulating layer 121, the second gate insulating layer 122, the interlayer insulating layer 154 and the flattening layer 155 can be shared to respectively serve as the substrate, buffer layer, shading layer, first insulating layer, first gate insulating layer, second gate insulating layer, interlayer insulating layer and flattening layer of the display panel 200.

[0190] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A thin film transistor device, characterized in that: include: A first active layer, a first gate insulating layer, a gate, a second gate insulating layer, a second active layer, a first electrode, and a second electrode; The first active layer, the first gate insulating layer, the gate, the second gate insulating layer, and the second active layer are sequentially stacked on the substrate, and the first active layer is connected to the second active layer; The first electrode is connected to the first active layer, and the second electrode is connected to the second active layer.

2. The thin film transistor device according to claim 1, characterized in that: The first active layer comprises a first region and a fourth region, the orthographic projection of the first region on the substrate is located outside the orthographic projection of the gate on the substrate, and the orthographic projection of the fourth region on the substrate is located outside the orthographic projection of the first gate insulating layer on the substrate; The first region is used to connect with the first electrode, and the fourth region is used to connect with the second active layer; Preferably, the orthographic projection of the fourth region on the substrate is located on a side of the orthographic projections of the first gate insulating layer and the second gate insulating layer on the substrate that is away from the first region; the thin film transistor device further comprises an interlayer insulating layer provided on the second active layer and the substrate; Preferably, a first via hole is provided through the first gate insulating layer and the second gate insulating layer, the first via hole exposes the fourth region, and the second active layer is partially disposed in the first via hole and connected to the fourth region.

3. The thin film transistor device according to claim 1, characterized in that: The first gate insulating layer includes a third region, an orthographic projection of the third region on the substrate is located outside an orthographic projection of the gate on the substrate, and the second gate insulating layer is connected to the third region.

4. The thin film transistor device according to claim 1, characterized in that: The first active layer includes a first semiconductor layer and a first conductor segment connected to each other, and the first electrode is connected to the first conductor segment; Preferably, the first conductor segment comprises an atomic doping segment provided on one side of the first semiconductor layer; Preferably, the atomic doping segment is an aluminum doped segment, a phosphorus doped segment or a boron doped segment; Preferably, the first conductor segment comprises a metal layer disposed on a surface of the first semiconductor layer; Preferably, the first conductor segment includes a metal layer arranged on the substrate, the metal layer includes a fifth region and a sixth region, the orthographic projection of the fifth region on the substrate is located within the orthographic projection of the gate on the substrate, and the orthographic projection of the sixth region on the substrate is located outside the orthographic projection of the gate on the substrate, the first semiconductor layer is arranged on the fifth region, and the sixth region is connected to the first electrode.

5. The thin film transistor device according to claim 1, characterized in that: The second active layer comprises a second semiconductor layer and a second conductor segment connected to each other, and the second electrode is connected to the second conductor segment; Preferably, the second conductor segment comprises an atomic doping segment provided on one side of the second semiconductor layer; Preferably, the atomic doping segment is an aluminum doped segment, a phosphorus doped segment or a boron doped segment; Preferably, the second conductor segment comprises a metal layer disposed on a surface of the second semiconductor layer; Preferably, the second conductor segment comprises a metal layer provided on the second gate insulating layer and the second semiconductor layer, the metal layer comprises a fifth region, an orthographic projection of the fifth region on the substrate is located within an orthographic projection of the gate on the substrate, and the fifth region is provided on the second semiconductor layer; Preferably, the metal layer further includes a sixth region connected to the fifth region, an orthographic projection of the sixth region on the substrate is located outside an orthographic projection of the second semiconductor layer on the substrate, and the sixth region is connected to the second electrode.

6. The thin film transistor device according to claim 1, characterized in that: The first active layer includes an amorphous silicon semiconductor layer, a low temperature polycrystalline silicon semiconductor layer or a metal oxide semiconductor layer; The second active layer includes an amorphous silicon semiconductor layer, a low temperature polysilicon semiconductor layer or a metal oxide semiconductor layer; Preferably, the first active layer and the second active layer include semiconductor layers of the same material; Preferably, the metal oxide semiconductor layer comprises a crystallized metal oxide semiconductor layer; Preferably, the metal oxide semiconductor layer includes a first sublayer and a second sublayer, the first sublayer is located on a side of the second sublayer close to the gate, and the carrier mobility of the first sublayer is smaller than the carrier mobility of the second sublayer.

7. The thin film transistor device according to any one of claims 1 to 6, characterized in that: It also includes an interlayer insulating layer disposed on the second active layer, the first electrode and the second electrode are disposed on the interlayer insulating layer, a second via hole is provided through the interlayer insulating layer, the first gate insulating layer and the second gate insulating layer, the first electrode is connected to the first active layer via the second via hole, the interlayer insulating layer is provided with a third via hole, and the second electrode is connected to the second active layer via the third via hole; Preferably, it further comprises a planar layer disposed on the interlayer insulating layer, the first electrode and the second electrode are disposed on the planar layer, and the second via hole and the third via hole also penetrate the planar layer; Alternatively, the first electrode is arranged on the first gate insulating layer, a second via hole is provided through the first gate insulating layer, and the first electrode is connected to the first active layer via the second via hole; the thin film transistor device also includes an interlayer insulating layer arranged on the second active layer, the second electrode is arranged on the interlayer insulating layer, a third via hole is provided through the interlayer insulating layer, and the second electrode is connected to the second active layer via the third via hole.

8. A method for manufacturing a thin film transistor device, characterized in that: include: forming a first semiconductor layer on a substrate; forming a first layer of gate insulating material on the first semiconductor layer; forming a gate on the first layer of gate insulating material; forming a second layer of gate insulating material on the gate to expose a portion of the first semiconductor layer; A second semiconductor layer is formed on the second layer of gate insulating material, and the second semiconductor layer is connected to the first semiconductor layer.

9. The method for manufacturing a thin film transistor device according to claim 8, characterized in that: The method further comprises the step of making a portion of the first semiconductor layer conductive, comprising: The first semiconductor layer includes a first portion, an orthographic projection of the first portion on the substrate is located outside an orthographic projection of the gate on the substrate; Using the gate as a barrier, atomic implantation is performed on the first portion of the first semiconductor layer; or, a metal layer is formed on a surface of a portion of the first semiconductor layer that is away from the substrate; or, a metal layer is formed on the substrate, wherein the metal layer includes a fifth region and a sixth region, the first semiconductor layer is formed on the fifth region and the substrate, an orthographic projection of the gate on the substrate overlaps with an orthographic projection of the fifth region on the substrate, and an orthographic projection of the sixth region on the substrate is outside an orthographic projection of the gate on the substrate; Preferably, the method further comprises the step of making a part of the second semiconductor layer conductive, comprising: A barrier layer is formed on the second semiconductor layer to expose a portion of the second semiconductor layer, and atoms are implanted into the second semiconductor layer using the barrier layer as a barrier; or a metal layer is formed on a surface of the second semiconductor layer that is away from the substrate; or a metal layer is formed on the second semiconductor layer and the patterned second gate insulating material, wherein the metal layer includes a fifth region; the fifth region is disposed on the second semiconductor layer, and an orthographic projection of the gate on the substrate overlaps with an orthographic projection of the fifth region on the substrate; Preferably, the metal layer further includes a sixth region connected to the fifth region, and an orthographic projection of the sixth region on the substrate is located outside an orthographic projection of the second semiconductor layer on the substrate.

10. A display panel, characterized in that: The invention comprises a plurality of thin film transistor devices according to any one of claims 1 to 7 or thin film transistor devices manufactured by the method for manufacturing a thin film transistor device according to claim 8 or 9, and pixel units connected to the thin film transistor devices.

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