A semiconductor structure and a method for manufacturing the same

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises a substrate, a channel layer and a barrier layer stacked in sequence; wherein the substrate comprises a plurality of P-type semiconductor regions arranged at intervals, the P-type semiconductor regions are in the shape of long strips and the extension direction is parallel to the channel length direction. The present disclosure provides a plurality of P-type semiconductor regions arranged at intervals and the extension direction is parallel to the channel length direction, which can transform a two-dimensional electron gas into a one-dimensional electron gas, and can slow down the drop of the transconductance curve at a large drain current, thereby improving the device transconductance flatness, and further improving the device linearity.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] High Electron Mobility Transistor (HEMT) is a heterojunction field effect transistor. Taking AlGaN / GaN heterostructure as an example, due to the presence of strong two-dimensional electron gas in AlGaN / GaN heterostructure, AlGaN / GaN HEMT is usually a depletion-mode device, making it difficult to realize an enhancement-mode device. However, the application of depletion-mode devices has certain limitations in many places. For example, in the application of power switching devices, enhancement-mode (normally off) switching devices are required. Enhancement-mode gallium nitride switching devices are mainly used in high-frequency devices, power switching devices, and digital circuits, and their research is of great significance.

[0003] At present, the linearity of common enhanced-mode GaN high electron mobility transistor devices is poor and cannot meet the actual engineering application requirements. Summary of the invention

[0004] In view of this, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, so as to further improve the linearity of an enhancement-mode gallium nitride high electron mobility transistor device.

[0005] According to one aspect of the present disclosure, an embodiment of the present disclosure provides a semiconductor structure, characterized in that it includes:

[0006] A substrate, a channel layer and a barrier layer stacked in sequence;

[0007] The substrate includes a plurality of P-type semiconductor regions arranged at intervals, and the P-type semiconductor regions are in the shape of long strips and their extension direction is parallel to the channel length direction.

[0008] As an optional embodiment, the thickness of the P-type semiconductor region is less than or equal to the thickness of the substrate.

[0009] As an optional embodiment, the positional relationship between the P-type semiconductor region and the substrate includes any one of the following positional relationships:

[0010] The P-type semiconductor region is located inside the substrate, and the substrate surrounds the upper surface, the lower surface and the sidewall of the P-type semiconductor region;

[0011] The P-type semiconductor region penetrates the substrate, and the substrate surrounds the sidewall of the P-type semiconductor region;

[0012] The P-type semiconductor region partially penetrates the substrate, and the substrate surrounds the lower surface and sidewalls of the P-type semiconductor region.

[0013] As an optional embodiment, along the channel width direction, the width variation of the plurality of P-type semiconductor regions includes at least one of the following variation modes: periodic variation, gradual increase, gradual decrease, increase first and then decrease, or decrease first and then increase.

[0014] As an optional embodiment, the semiconductor structure further comprises:

[0015] a dielectric layer, located on the barrier layer;

[0016] A source electrode, located on the barrier layer;

[0017] A drain electrode, located on the barrier layer;

[0018] The gate is located on the dielectric layer and between the source and the drain.

[0019] As an optional embodiment, along the channel length direction, an overlapping length of a projection of the P-type semiconductor region and the gate on the substrate is equal to a projection length of the gate.

[0020] As an optional embodiment, along the channel length direction, the overlapping length of the projections of the P-type semiconductor region and the gate on the substrate is smaller than the projection length of the gate and the overlapping projection is located on a side of the gate close to the drain.

[0021] As an optional embodiment, the width of the P-type semiconductor region below the side of the gate close to the drain is greater than the width of the P-type semiconductor region below the side of the gate close to the source.

[0022] As an optional embodiment, along the direction from the gate to the drain, the width of the P-type semiconductor region gradually decreases.

[0023] As an optional embodiment, along the direction from the gate to the drain, the P-type doping ion concentration of the P-type semiconductor region gradually decreases.

[0024] As an optional embodiment, the material of the dielectric layer includes at least one of silicon nitride, aluminum oxide, aluminum nitride and aluminum oxynitride.

[0025] As an optional embodiment, the thickness of the channel layer is less than 1 μm.

[0026] As an optional embodiment, the material of the substrate is semi-insulating SiC.

[0027] According to another aspect of the present disclosure, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, characterized in that it includes the following steps:

[0028] S1. providing a substrate;

[0029] S2, forming a plurality of P-type semiconductor regions arranged at intervals in the substrate;

[0030] S3, stacking a channel layer and a barrier layer in sequence on the substrate;

[0031] The P-type semiconductor region is in the shape of an elongated strip and its extension direction is parallel to the channel length direction.

[0032] As an optional embodiment, the method of forming a plurality of spaced-apart P-type semiconductor regions comprises ion implantation.

[0033] As an optional embodiment, the implanted ions in the ion implantation include at least one of aluminum ions, magnesium ions or zinc ions.

[0034] As an optional embodiment, the method for forming a plurality of spaced-apart P-type semiconductor regions includes etching grooves in the substrate and then selectively epitaxially growing P-type semiconductor material in the grooves.

[0035] As an optional embodiment, the method for manufacturing the semiconductor structure further comprises:

[0036] S4, forming a dielectric layer, a source electrode, a drain electrode, and a gate electrode on the dielectric layer and between the source electrode and the drain electrode.

[0037] The present disclosure provides a semiconductor structure, comprising a substrate, a channel layer and a barrier layer stacked in sequence; wherein the substrate comprises a plurality of P-type semiconductor regions arranged at intervals, the P-type semiconductor regions are in the shape of long strips and the extension direction is parallel to the channel length direction.

[0038] The P-type semiconductor region provided in the substrate of the present invention can realize the depletion of the two-dimensional electron gas between the channel layer and the barrier layer, and avoids the damage to the barrier layer caused by etching the P-type semiconductor layer after manufacturing the P-type semiconductor layer on the barrier layer.

[0039] The present invention provides a plurality of P-type semiconductor regions arranged at intervals and extending in a direction parallel to the channel length direction, which can convert a two-dimensional electron gas into a one-dimensional electron gas, thereby forming different threshold voltages in the channel layer at different positions, so that the device is gradually turned on along the channel width direction, which can slow down the decline of the transconductance curve when the drain current is large, thereby improving the transconductance flatness of the device and further improving the linearity of the device.

[0040] The semiconductor structure disclosed in the present invention is simple in structure, easy to control in process, low in cost, and the formed device has high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 Shown is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.

[0042] Figure 2 Shown is a schematic top view of a semiconductor structure provided by an embodiment of the present disclosure.

[0043] Figure 3a to Figure 3c Shown is a schematic side view of a semiconductor structure provided by some embodiments of the present disclosure.

[0044] Figures 4a to 4e Shown is a schematic top view of a semiconductor structure provided by some embodiments of the present disclosure.

[0045] Figure 5a to Figure 5b Shown is a schematic top view of a semiconductor structure provided by some embodiments of the present disclosure.

[0046] Figure 6 Shown is a schematic top view of a semiconductor structure provided by an embodiment of the present disclosure.

[0047] Figure 7 Shown is a schematic top view of a semiconductor structure provided by an embodiment of the present disclosure.

[0048] Figure 8 Shown is a schematic flow chart of a semiconductor structure manufacturing method provided in one embodiment of the present disclosure.

[0049] Figures 9 to 12 Shown is a schematic structural diagram of an intermediate structure of a semiconductor structure provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0051] In order to improve the linearity of an enhanced gallium nitride high electron mobility transistor device, the present disclosure provides a semiconductor structure, including a substrate, a channel layer and a barrier layer stacked in sequence; wherein the substrate includes a plurality of spaced P-type semiconductor regions, the P-type semiconductor regions are in the shape of long strips and the extension direction is parallel to the channel length direction. The present disclosure provides a plurality of spaced P-type semiconductor regions with the extension direction parallel to the channel length direction, which can transform a two-dimensional electron gas into a one-dimensional electron gas, thereby forming different threshold voltages in the channel layer at different positions, so that the device is gradually turned on along the channel width direction, which can slow down the decline of the transconductance curve when the drain current is large, thereby improving the transconductance flatness of the device, and further improving the linearity of the device.

[0052] Combine the following Figures 1 to 12 A semiconductor structure and a manufacturing method thereof mentioned in the present disclosure are further illustrated by way of example.

[0053] Figure 1 Shown is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. Figure 2 FIG. 1 is a schematic top view of a semiconductor structure provided by an embodiment of the present disclosure. Figure 1 As shown, the semiconductor structure includes: a substrate 10, a channel layer 20 and a barrier layer 30 stacked in sequence; wherein the substrate 10 includes a plurality of P-type semiconductor regions 11 arranged at intervals, and the P-type semiconductor regions 11 are long strips and extend in a direction parallel to the channel length direction (such as Figure 2 As shown in Figure 1 As shown, the semiconductor structure further includes: a dielectric layer 40 located on the barrier layer 30; a source 51 located on the barrier layer 30; a drain 52 located on the barrier layer 30; and a gate 53 located on the dielectric layer 40 and between the source 51 and the drain 52.

[0054] In this embodiment, the material of the substrate 10 is semi-insulating SiC. Semi-insulating SiC as a substrate is a preferred material for GaN heteroepitaxial growth. The lattice mismatch between SiC and GaN materials is only 3.4% and SiC has ultra-high thermal conductivity. The materials of the channel layer 20 and the barrier layer 30 include group III nitride materials, and a two-dimensional electron gas can be formed at the interface between the channel layer 20 and the barrier layer 30. In one optional scheme, the channel layer 20 is a GaN layer and the barrier layer 30 is an AlGaN layer. In other optional schemes, the material combination of the channel layer 20 and the barrier layer 30 can also be GaN / AlN, GaN / InN, GaN / InAlGaN, GaAs / AlGaAs, GaN / InAlN or InN / InAlN. The thickness of the channel layer 20 is less than 1μm. In one optional scheme, the thickness of the channel layer 20 is less than 300nm. In other optional schemes, the thickness of the channel layer 20 is less than 100nm. The thickness of the channel layer 20 may be reduced to increase the density of the two-dimensional electron gas.

[0055] In this embodiment, the material of the dielectric layer 40 includes at least one of silicon nitride, aluminum oxide, aluminum nitride and aluminum oxynitride. The material of the dielectric layer 40 has a strong charge binding ability. In the formed external electric field, the charge is not easily polarized, the polarized charge is small, and the polarized electric field is weak, which effectively avoids the short channel effect of the semiconductor structure. The dielectric layer 40 is provided to form a MIS gate structure, which can effectively reduce the gate leakage current, increase the gate voltage swing and the drain current swing, and further improve the linear performance of the device.

[0056] In one embodiment, Figure 3a to Figure 3c The figure shows a side view of a semiconductor structure provided by some embodiments of the present disclosure. The thickness of the P-type semiconductor region 11 is less than or equal to the thickness of the substrate 10, and the positional relationship between the P-type semiconductor region 11 and the substrate 10 includes any one of the following positional relationships: the P-type semiconductor region 11 is located inside the substrate 10, and the substrate 10 surrounds the upper surface, lower surface and sidewalls (such as Figure 3a As shown); the P-type semiconductor region 11 penetrates the substrate 10, and the substrate 10 surrounds the sidewalls of the P-type semiconductor region 11 (as shown Figure 3b The P-type semiconductor region 11 partially penetrates the substrate 10, and the substrate 10 surrounds the lower surface and sidewalls of the P-type semiconductor region 11 (as shown); Figure 3c When the P-type semiconductor region 11 is located inside the substrate 10, the crystal quality of the surface of the substrate 10 is better, which is conducive to the growth of the subsequent epitaxial layer; when the P-type semiconductor region 11 penetrates the substrate 10, the P-type semiconductor region 11 depletes the two-dimensional electron gas more thoroughly, further improving the linearity of the device.

[0057] In one embodiment, Figures 4a to 4e FIG. 1 is a schematic top view of a semiconductor structure provided by some embodiments of the present disclosure. Along the channel width direction, the width variation of the plurality of P-type semiconductor regions 11 includes at least one of the following variation modes: periodic variation (e.g. Figure 4a As shown), gradually increasing (as Figure 4b As shown), gradually decreases (as Figure 4c As shown), it increases first and then decreases (as shown Figure 4d as shown) or decreases first and then increases (as shown Figure 4e As shown in FIG. 1 , the present disclosure does not specifically limit the width variation of the plurality of P-type semiconductor regions 11. By changing the width of the plurality of P-type semiconductor regions 11, that is, changing the proportion and distribution of the plurality of P-type semiconductor regions 11 in the substrate 10, coupling of different gate control capabilities and threshold voltages is provided, thereby improving the linearity of the semiconductor device.

[0058] In one embodiment, Figure 5a to Figure 5b FIG. 1 is a schematic top view of a semiconductor structure provided by some embodiments of the present disclosure. Figure 5aAs shown, the length of the P-type semiconductor region 11 is greater than or equal to the length of the gate 53 along the channel length direction, and, along the channel length direction, the overlapping length of the projections of the P-type semiconductor region 11 and the gate 53 on the substrate 10 is equal to the projection length of the gate 53. Designing the length of the P-type semiconductor region 11 can adjust the two-dimensional electron gas depletion region between the channel layer 20 and the barrier layer 30, thereby adjusting the linearity of the semiconductor device. Designing the P-type semiconductor region 11 to be located below the gate 53 so that the device is gradually turned on along the channel width direction can slow down the decline of the transconductance curve when the drain current is large, thereby improving the device transconductance flatness, and further improving the device linearity. Figure 5b As shown, along the channel length direction, the overlapping length of the projections of the P-type semiconductor region 11 and the gate 53 on the substrate 10 is less than the projection length of the gate 53, and the overlapping projection is located on the side of the gate 53 close to the drain 52. The P-type semiconductor region 11 is located below the side of the gate 53 close to the drain 52, which can reduce the electric field peak on the side of the gate 53 close to the drain 52, thereby effectively improving the breakdown voltage of the semiconductor structure.

[0059] In one embodiment, Figure 6 FIG. 1 is a schematic top view of a semiconductor structure provided by an embodiment of the present disclosure. Figure 6 As shown, the width of the P-type semiconductor region 11 below the side of the gate 53 close to the drain 52 is greater than the width of the P-type semiconductor region 11 below the side of the gate 53 close to the source 51. The width of the P-type semiconductor region 11 below the side of the gate 53 close to the drain 52 is increased, that is, the width of the channel layer 20 below the side of the gate 53 close to the drain 52 is reduced, which reduces the peak electric field, avoids the breakdown caused by the peak electric field, and improves the device breakdown voltage.

[0060] In one embodiment, Figure 7 FIG. 1 is a schematic top view of a semiconductor structure provided by an embodiment of the present disclosure. Figure 7 As shown, along the direction from the gate 53 to the drain 52, the width of the P-type semiconductor region 11 gradually decreases. Along the direction from the gate 53 to the drain 52, the P-type doping ion concentration of the P-type semiconductor region 11 can also gradually decrease. The width or P-type doping ion concentration of the P-type semiconductor region 11 below the side of the gate 53 close to the drain 52 is the largest, that is, the depletion degree of the two-dimensional electron gas below the side of the gate 53 close to the drain 52 is the largest, which can effectively reduce the electric field peak of the side of the gate 53 close to the drain 52, thereby effectively improving the breakdown voltage of the semiconductor structure. Along the direction from the gate 53 to the drain 52, the width or P-type doping ion concentration of the P-type semiconductor region 11 gradually decreases, that is, the depletion effect on the two-dimensional electron gas is reduced, which not only maintains a low channel on-resistance, but also meets the requirements of modulating the electric field intensity and improving the breakdown voltage of the device.

[0061] An embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure. Figure 8 FIG. 1 is a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Figures 9 to 12 FIG. 1 is a schematic diagram of an intermediate structure of a semiconductor structure provided by an embodiment of the present disclosure. Figure 8 As shown, the method for manufacturing a semiconductor structure includes:

[0062] Step S1: Fig. 9 As shown, a substrate 10 is provided. The material of the substrate 10 is semi-insulating SiC. Semi-insulating SiC as a substrate is a preferred material for GaN heteroepitaxial growth. The lattice mismatch between SiC and GaN materials is only 3.4% and SiC has ultra-high thermal conductivity.

[0063] Step S2: Fig.10 As shown, a plurality of P-type semiconductor regions 11 are formed in the substrate 10. In an optional solution, a method for forming the plurality of P-type semiconductor regions 11 is provided by ion implantation, wherein the implanted ions include at least one of aluminum ions, magnesium ions or zinc ions. Fig.10 In another alternative, the method for forming a plurality of spaced apart P-type semiconductor regions 11 includes etching grooves in the substrate 10 and then selectively growing P-type semiconductor material in the grooves. Fig.11 As shown, by growing a P-type semiconductor material in the groove by an in-situ doping selective epitaxial process, a structure as shown in FIG. Fig.10 The intermediate structure shown in FIG. 1 is a schematic diagram of an embodiment of the present invention. The in-situ doping selective epitaxial process can make the impurity ions in the formed P-type semiconductor region 11 evenly distributed, and can well control the width of the formed P-type semiconductor region 11.

[0064] Step S3: Fig.12As shown, a channel layer 20 and a barrier layer 30 are sequentially stacked on a substrate 10, and a P-type semiconductor region 11 is in the shape of a long strip and the extension direction is parallel to the channel length direction. The growth of the channel layer 20 and the barrier layer 30 can be in-situ growth, or can be prepared by atomic layer deposition (ALD, Atomic layer deposition), chemical vapor deposition (CVD, Chemical Vapor Deposition), molecular beam epitaxy (MBE, Molecular Beam Epitaxy), plasma enhanced chemical vapor deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition), low pressure chemical vapor deposition (LPCVD, Low Pressure Chemical Vapor Deposition), metal organic chemical vapor deposition (MOCVD, Metal-Organic Chemical Vapor Deposition), or a combination thereof. Multiple P-type semiconductor regions arranged at intervals and extending in a direction parallel to the channel length direction can convert the two-dimensional electron gas into a one-dimensional electron gas, thereby forming different threshold voltages in the channel layer at different positions, so that the device is gradually turned on along the channel width direction, which can slow down the decline of the transconductance curve when the drain current is large, thereby improving the transconductance flatness of the device and further improving the linearity of the device.

[0065] Step S4: forming a dielectric layer 40, a source electrode 51, a drain electrode 52, and a gate electrode 53 on the dielectric layer 40 and between the source electrode 51 and the drain electrode 52, so as to form a gate electrode 53. Figure 1 The semiconductor structure shown.

[0066] In one embodiment, the thickness of the P-type semiconductor region 11 is less than or equal to the thickness of the substrate 10, and the positional relationship between the P-type semiconductor region 11 and the substrate 10 includes any one of the following positional relationships: the P-type semiconductor region 11 is located inside the substrate 10, and the substrate 10 surrounds the upper surface, the lower surface, and the sidewalls (such as Figure 3a As shown); the P-type semiconductor region 11 penetrates the substrate 10, and the substrate 10 surrounds the sidewalls of the P-type semiconductor region 11 (as shown Figure 3b The P-type semiconductor region 11 partially penetrates the substrate 10, and the substrate 10 surrounds the lower surface and sidewalls of the P-type semiconductor region 11 (as shown in FIG. Figure 3c When the P-type semiconductor region 11 is located inside the substrate 10, the crystal quality of the surface of the substrate 10 is better, which is conducive to the growth of the subsequent epitaxial layer; when the P-type semiconductor region 11 penetrates the substrate 10, the P-type semiconductor region 11 depletes the two-dimensional electron gas more thoroughly, further improving the linearity of the device.

[0067] In one embodiment, along the channel width direction, the width variation of the plurality of P-type semiconductor regions 11 includes at least one of the following variation modes: periodic variation (e.g. Figure 4a As shown), gradually increasing (as Figure 4b As shown), gradually decreases (as Figure 4c As shown), it increases first and then decreases (as shown Figure 4d as shown) or decreases first and then increases (as shown Figure 4e As shown in FIG. 1 , the present disclosure does not specifically limit the width variation of the plurality of P-type semiconductor regions 11. By changing the width of the plurality of P-type semiconductor regions 11, that is, changing the proportion and distribution of the plurality of P-type semiconductor regions 11 in the substrate 10, coupling of different gate control capabilities and threshold voltages is provided, thereby improving the linearity of the semiconductor device.

[0068] In one embodiment, Figure 5a As shown, the length of the P-type semiconductor region 11 is greater than or equal to the length of the gate 53 along the channel length direction, and, along the channel length direction, the overlapping length of the projections of the P-type semiconductor region 11 and the gate 53 on the substrate 10 is equal to the projection length of the gate 53. Designing the length of the P-type semiconductor region 11 can adjust the two-dimensional electron gas depletion region between the channel layer 20 and the barrier layer 30, thereby adjusting the linearity of the semiconductor device. Designing the P-type semiconductor region 11 to be located below the gate 53 so that the device is gradually turned on along the channel width direction can slow down the decline of the transconductance curve when the drain current is large, thereby improving the device transconductance flatness, and further improving the device linearity. Figure 5b As shown, along the channel length direction, the overlapping length of the projections of the P-type semiconductor region 11 and the gate 53 on the substrate 10 is less than the projection length of the gate 53, and the overlapping projection is located on the side of the gate 53 close to the drain 52. The P-type semiconductor region 11 is located below the side of the gate 53 close to the drain 52, which can reduce the electric field peak on the side of the gate 53 close to the drain 52, thereby effectively improving the breakdown voltage of the semiconductor structure.

[0069] In one embodiment, Figure 6 As shown, the width of the P-type semiconductor region 11 below the side of the gate 53 close to the drain 52 is greater than the width of the P-type semiconductor region 11 below the side of the gate 53 close to the source 51. The width of the P-type semiconductor region 11 below the side of the gate 53 close to the drain 52 is increased, that is, the width of the channel layer 20 below the side of the gate 53 close to the drain 52 is reduced, which reduces the peak electric field, avoids the breakdown caused by the peak electric field, and improves the device breakdown voltage.

[0070] In one embodiment, Figure 7As shown, along the direction from the gate 53 to the drain 52, the width of the P-type semiconductor region 11 gradually decreases. Along the direction from the gate 53 to the drain 52, the P-type doping ion concentration of the P-type semiconductor region 11 can also gradually decrease. The width or P-type doping ion concentration of the P-type semiconductor region 11 below the side of the gate 53 close to the drain 52 is the largest, that is, the depletion degree of the two-dimensional electron gas below the side of the gate 53 close to the drain 52 is the largest, which can effectively reduce the electric field peak of the side of the gate 53 close to the drain 52, thereby effectively improving the breakdown voltage of the semiconductor structure. Along the direction from the gate 53 to the drain 52, the width or P-type doping ion concentration of the P-type semiconductor region 11 gradually decreases, that is, the depletion effect on the two-dimensional electron gas is reduced, which not only maintains a low channel on-resistance, but also meets the requirements of modulating the electric field intensity and improving the breakdown voltage of the device.

[0071] The present disclosure provides a semiconductor structure, comprising a substrate, a channel layer and a barrier layer stacked in sequence; wherein the substrate comprises a plurality of P-type semiconductor regions arranged at intervals, the P-type semiconductor regions are in the shape of long strips and the extension direction is parallel to the channel length direction.

[0072] The P-type semiconductor region provided in the substrate of the present invention can realize the depletion of the two-dimensional electron gas between the channel layer and the barrier layer, and avoids the damage to the barrier layer caused by etching the P-type semiconductor layer after manufacturing the P-type semiconductor layer on the barrier layer.

[0073] The present invention provides a plurality of P-type semiconductor regions arranged at intervals and extending in a direction parallel to the channel length direction, which can convert a two-dimensional electron gas into a one-dimensional electron gas, thereby forming different threshold voltages in the channel layer at different positions, so that the device is gradually turned on along the channel width direction, which can slow down the decline of the transconductance curve when the drain current is large, thereby improving the transconductance flatness of the device and further improving the linearity of the device.

[0074] The semiconductor structure disclosed in the present invention is simple in structure, easy to control in process, low in cost, and the formed device has high reliability.

[0075] It should be understood that the term "including" and its variations used in the present disclosure are open inclusions, that is, "including but not limited to". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one other embodiment". In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0076] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: A substrate (10), a channel layer (20) and a barrier layer (30) stacked in sequence; The substrate (10) comprises a plurality of P-type semiconductor regions (11) arranged at intervals, and the P-type semiconductor regions (11) are in the shape of long strips and their extension direction is parallel to the channel length direction.

2. The semiconductor structure according to claim 1, characterized in that: The thickness of the P-type semiconductor region (11) is less than or equal to the thickness of the substrate (10).

3. The semiconductor structure according to claim 2, characterized in that: The positional relationship between the P-type semiconductor region (11) and the substrate (10) includes any one of the following positional relationships: The P-type semiconductor region (11) is located inside the substrate (10), and the substrate (10) surrounds the upper surface, the lower surface and the side wall of the P-type semiconductor region (11); The P-type semiconductor region (11) penetrates the substrate (10), and the substrate (10) surrounds the side wall of the P-type semiconductor region (11); The P-type semiconductor region (11) partially penetrates the substrate (10), and the substrate (10) surrounds the lower surface and side walls of the P-type semiconductor region (11).

4. The semiconductor structure according to claim 1, characterized in that: Along the channel width direction, the width variation of the plurality of P-type semiconductor regions (11) includes at least one of the following variation modes: periodic variation, gradual increase, gradual decrease, first increase and then decrease, or first decrease and then increase.

5. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: A dielectric layer (40) located on the barrier layer (30); A source electrode (51) located on the barrier layer (30); A drain electrode (52) located on the barrier layer (30); A gate electrode (53) is located on the dielectric layer (40) and between the source electrode (51) and the drain electrode (52).

6. The semiconductor structure according to claim 5, characterized in that: Along the channel length direction, the overlapping length of the projection of the P-type semiconductor region (11) and the gate (53) on the substrate (10) is equal to the projection length of the gate (53).

7. The semiconductor structure according to claim 5, characterized in that: Along the channel length direction, the overlapping length of the projections of the P-type semiconductor region (11) and the gate (53) on the substrate (10) is smaller than the projection length of the gate (53), and the overlapping projection is located on a side of the gate (53) close to the drain (52).

8. The semiconductor structure according to claim 5, characterized in that: The width of the P-type semiconductor region (11) below the side of the gate (53) close to the drain (52) is greater than the width of the P-type semiconductor region (11) below the side of the gate (53) close to the source (51).

9. The semiconductor structure according to claim 5, characterized in that: Along the direction from the gate (53) to the drain (52), the width of the P-type semiconductor region (11) gradually decreases.

10. The semiconductor structure according to claim 5, characterized in that: Along the direction from the gate (53) to the drain (52), the P-type doping ion concentration of the P-type semiconductor region (11) gradually decreases.

11. The semiconductor structure according to claim 5, characterized in that: The material of the dielectric layer (40) includes at least one of silicon nitride, aluminum oxide, aluminum nitride and aluminum oxynitride.

12. The semiconductor structure according to claim 1, characterized in that: The thickness of the channel layer (20) is less than 1 μm.

13. The semiconductor structure according to claim 1, characterized in that: The material of the substrate (10) is semi-insulating SiC.

14. A method for manufacturing a semiconductor structure, characterized in that: The following steps are involved: S1. providing a substrate (10); S2, forming a plurality of P-type semiconductor regions (11) arranged at intervals in the substrate (10); S3, sequentially stacking a channel layer (20) and a barrier layer (30) on the substrate (10); The P-type semiconductor region (11) is in the shape of a long strip and its extension direction is parallel to the channel length direction.

15. The method for manufacturing a semiconductor structure according to claim 14, characterized in that: The method for forming a plurality of spaced-apart P-type semiconductor regions (11) comprises ion implantation.

16. The method for manufacturing a semiconductor structure according to claim 15, characterized in that: The implanted ions of the ion implantation include at least one of aluminum ions, magnesium ions or zinc ions.

17. The method for manufacturing a semiconductor structure according to claim 14, characterized in that: The method for forming a plurality of spaced-apart P-type semiconductor regions (11) comprises etching grooves in the substrate (10) and then selectively epitaxially growing P-type semiconductor materials in the grooves.

18. The method for manufacturing a semiconductor structure according to claim 14, characterized in that: The method for manufacturing the semiconductor structure further comprises: S4, forming a dielectric layer (40), a source electrode (51), a drain electrode (52) and a gate electrode (53) located on the dielectric layer (40) and between the source electrode (51) and the drain electrode (52).

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