Semiconductor integrated device

Abstract

The embodiment of the invention provides a semiconductor integrated device which comprises a cell, the shape of the cell is a regular K polygon, and the value of K is 4 or 6 or 8; the cells are divided into K regular triangle structures by the diagonal lines of the cells, and each regular triangle structure comprises an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated with an HJD (High Junction Driver) or an MOSFET integrated with an SBD (Scheduling Bridge Driver); the number of the MOSFETs integrated with the HJD is n, and the number of the MOSFETs integrated with the SBD is m; wherein n and m are positive integers, and the sum of n and m is K. According to the embodiment of the invention, the technical problem that the reliability and the conduction capability of a traditional integrated Schottky diode device are limited is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a semiconductor integrated device. Background Art

[0002] Silicon carbide VDMOS devices have the advantages of high voltage resistance, low on-resistance, faster switching speed, higher operating temperature, heat dissipation capability and good radiation resistance, and have been widely used in power electronic circuits.

[0003] In order to obtain better device performance in practical application circuits, in 2016, the BJ Baliga team of North Carolina State University proposed a MOSFET integrated diode method to optimize the third quadrant characteristics of the device. Metal nickel Ni is used to form Schottky contacts, and the P-well region is used to shield the electric field of the Schottky contact region to reduce the leakage current of the device. Figure 1-1 This type is also called a split-source SBD integrated MOSFET, where SBD is the abbreviation for Schottky barrier diode.

[0004] In 2017, patent CN107275407B proposed a split-gate SiC VDMOS, which has a split gate in the middle of the gate ( Figure 1-2 A heterojunction diode HJD is integrated between the first polysilicon gate 2 and the second polysilicon gate 21. Figure 2 A P+ polysilicon layer 12, a P-type silicon carbide region 13 and a metal electrode 14 are formed in the middle, a groove is etched on the surface of the JFET, and P-type doping is performed at the bottom of the groove to form a P-type silicon carbide region 13, and then a Poly layer (a first polysilicon gate 2, a second polysilicon gate 21) is deposited in the groove to form a heterojunction diode HJD.

[0005] Among them, Figure 1-2 As shown, a first gate electrode 1, a second gate electrode 11, a P+ polysilicon layer 12, a P-type silicon carbide region 13, a metal electrode 14, a first polysilicon gate 2, a second polysilicon gate 21, a first metal source electrode 3, a second metal source electrode 31, a first gate dielectric layer 4, a second gate dielectric layer 41, a first P+ contact region 5, a second P+ contact region 51, a first N+ source region 6, a second N+ source region 61, a first Pbase region 7, a second Pbase region 71, an N- epitaxial layer 8, an N+ substrate 9, and a metal drain electrode 10.

[0006] In 2019, the University of Electronic Science and Technology of China applied for a patent for a split-gate 4H-SiC MOSFET device, patent number CN110534576 A, which achieves low reverse conduction voltage drop by integrating SBD in the middle of the gate, with a schottky contact in the middle, such as Figure 1-3 shown.

[0007] Figure 2 A cross-sectional view of a structure consisting of two adjacent halves of a conventional VDMOS device; Figure 3 for Figure 2 A top-down perspective view of two adjacent cells at the AA position shown. Figure 2 and Figure 3 In the figure, the vertical dashed line is the boundary of the cell. Figure 2 and Figure 3 As shown, substrate 2-1, drift region 2-2, channel contact region 2-31, channel region 2-32, source 2-32-1, JFET region 2-33, ohmic contact region 2-41, isolation region 2-42, gate 2-42-1, source metal 2-5. Figure 2 and Figure 3 The reason why the same area has different shapes is that Figure 3 For top-down perspective, some areas are perspective. Figure 2 In the embodiment, a single ohmic contact region 2-41 is a relatively wide strip. Figure 3 In the figure, the ohmic contact region 2-4 shows the narrower channel contact region 2-31 located thereunder due to perspective reasons. Figure 3 In the figure, visually, there are two narrow strips of ohmic contact regions 2-41 on both sides of the channel contact region 2-31.

[0008] In order to improve reliability, current devices with integrated Schottky diodes (such as Figure 1-1 and Figure 1-3 The devices shown in the figure are all integrated using strip cells in the layout, which sacrifices the channel density and limits the device conduction capability. In order to ensure the reverse low conduction characteristics of the device, a lot of chip area is sacrificed to make Schottky contacts, which requires extra costs.

[0009] Traditional VDMOS devices also use strip cell integration in the layout, such as Figure 2 shown.

[0010] Therefore, the conduction capability of conventional devices integrating Schottky diodes is limited, which is a technical problem that those skilled in the art urgently need to solve.

[0011] The above information disclosed in the background section is only for enhancing understanding of the background of the present application and therefore it may contain information that does not form the prior art known to a person of ordinary skill in the art. Summary of the invention

[0012] The embodiment of the present application provides a semiconductor integrated device to solve the technical problem that the conduction capability of a conventional device integrating a Schottky diode is limited, while ensuring the reliability of the semiconductor integrated device.

[0013] The embodiment of the present application provides a semiconductor integrated device, including a cell, wherein the shape of the cell is a regular K-gon, wherein the value of K is 4, 6, or 8; the diagonal of the cell divides the cell into K regular triangle structures, and one regular triangle structure includes a MOSFET integrated with an HJD or a MOSFET integrated with an SBD;

[0014] There are n MOSFETs with integrated HJD and m MOSFETs with integrated SBD.

[0015] Wherein, n and m are positive integers and the sum of n and m is K.

[0016] In implementation, the cell is a regular hexagonal cell, and the three diagonals of the regular hexagon of the cell divide the cell into six regular triangle structures;

[0017] Where n and m are positive integers and the sum of n and m is six, The value range is greater than or equal to Less than or equal to 2.

[0018] The embodiment of the present application adopts the above technical solution, which has the following technical effects:

[0019] In the prior art, a split-source SBD integrated MOSFET designed with a stripe cell arrangement is Figure 2 As shown. The present application chooses to integrate the heterojunction diode HJD and the Schottky diode SBD into the same cell, and the cell adopts a regular K-gon, such as a hexagonal cell arrangement of a regular hexagon. The cells with regular K-gons can increase the channel density, increase the conduction current, and solve the problem of insufficient conduction capability of devices with strip cell arrangement. At the same time, through the interlaced design of HJD and SBD, the device has a lower reverse low conduction voltage drop, and improves the reliability of the device, the chip area can be made smaller, and the cost can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0021] Figure 1-1 A schematic diagram of a split-source SBD integrated MOSFET proposed by the BJ Baliga team of North Carolina State University in 2016 in the background technology;

[0022] Figure 1-2 Schematic diagram of the split-gate SiC VDMOS of patent CN107275407B;

[0023] Figure 1-3 This is a schematic diagram of patent application CN 110534576 A;

[0024] Figure 2 A cross-sectional view of a structure consisting of two adjacent halves of a conventional VDMOS device;

[0025] Figure 3 for Figure 2 A top-down perspective view of two adjacent cells at the AA position shown;

[0026] Figure 4-1 A three-dimensional perspective schematic diagram of a cell of a semiconductor integrated device according to an embodiment of the present application;

[0027] Figure 4-2 for Figure 4-1 A perspective schematic diagram of a partially deleted JFET region 33;

[0028] Figure 5 for Figure 4-2 A cross-sectional view of a structure consisting of two halves of cells adjacent to each other at the OA position;

[0029] Figure 6 for Figure 4-2 A cross-sectional view of a structure consisting of two halves of cells adjacent to each other at the OB position;

[0030] Figure 7 for Figure 4-1 The cell shown has the source metal removed and Figure 5 A perspective diagram of a single cell in the XY direction showing the CC position shown;

[0031] Figure 8 for Figure 7 A partial enlarged view of

[0032] Fig. 9 for Figure 4-1 The cell shown has the source metal and the first gate removed and Figure 6 A perspective diagram of a single cell in the XY direction of the DD position shown;

[0033] Fig.10 for Fig. 9 A partial enlarged view of

[0034] Figure 11-1 A simulation device modeling diagram of a MOSFET with integrated SBD in the prior art;

[0035] Figure 11-2 A simulation device modeling diagram of a cell of a semiconductor integrated device according to an embodiment of the present application;

[0036] Fig.12 for Figure 11-1 and Figure 11-2 A graph showing the on-state current of the two devices as the source-drain voltage Vsd changes;

[0037] Fig.13 for Figure 11-1 and Figure 11-2 The curve diagram of the drain current of the two devices as the drain voltage changes;

[0038] Fig.14 for Fig.13 A graph with an index on the vertical axis.

[0039] Reference numerals:

[0040] Substrate 1, drift region 2,

[0041] Channel contact region 31, channel region 32, source 32-1,

[0042] JFET region 33, P-poly region 33-1, second P+ injection region 33-2,

[0043] Ohmic contact region 41, isolation region 42, first gate 42-1, second gate 42-2,

[0044] Schottky contact region 43,

[0045] Source Metal 5. DETAILED DESCRIPTION

[0046] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0047] Embodiment 1

[0048] like Figure 7 As shown, the semiconductor integrated device of the embodiment of the present application includes a cell, the shape of the cell is a regular K-gon, wherein the value of K is 4, 6, or 8; the diagonal of the cell divides the cell into K regular triangle structures, and one regular triangle structure includes a MOSFET integrated with HJD or a MOSFET integrated with SBD;

[0049] There are n MOSFETs with integrated HJD and m MOSFETs with integrated SBD.

[0050] Wherein, n and m are positive integers and the sum of n and m is K.

[0051] In implementation, such as Figure 7As shown, the cell is a regular hexagonal cell, and the three diagonals of the regular hexagonal cell divide the cell into six regular triangle structures;

[0052] There are n MOSFETs with integrated HJD and m MOSFETs with integrated SBD in the six equilateral triangle structures;

[0053] Where n and m are positive integers and the sum of n and m is six, The value range is greater than or equal to Less than or equal to 2.

[0054] In the prior art, a split-source SBD integrated MOSFET designed with a stripe cell arrangement is Figure 2 The present application selects to integrate the heterojunction diode HJD and the Schottky diode SBD in the same cell. The conduction capability of the heterojunction diode HJD is better than that of the Schottky diode SBD, so that the conduction capability of the semiconductor integrated device of the present application is better than that of the device with integrated Schottky diode in the prior art.

[0055] At the same time, the cells are arranged in hexagonal cells, which can improve the channel density, increase the conduction current, and solve the problem of insufficient conduction capacity of strip cell arrangement devices in the prior art.

[0056] At the same time, through the interlaced design of HJD and SBD, the device has a lower reverse low conduction voltage drop and improves the reliability of the device.

[0057] Specifically, SBD is the abbreviation of Schottky barrier diode; HJD is the abbreviation of heterojunction diode.

[0058] As a first optional method, m is 2, and the number of MOSFETs integrated with SBD is two;

[0059] n is 4, and the number of MOSFETs integrated with HJD is four.

[0060] That is, the area ratio of the MOSFET integrated with HJD and the MOSFET integrated with SBD is 2.

[0061] As a second optional method, m is 4, and the number of MOSFETs integrated with SBD is four;

[0062] n is 2, and there are two MOSFETs with integrated HJD. The two MOSFETs with integrated HJD are arranged in a regular hexagon in a vertex-to-vertex manner; four MOSFETs with integrated SBD are arranged in pairs at two intervals between the two MOSFETs with integrated HJD. That is, the area ratio of the MOSFET with integrated HJD to the MOSFET with integrated SBD is 1:2.

[0063] The accompanying drawings of the present application are illustrated in the first optional manner (two MOSFETs with integrated SBD and four MOSFETs with integrated HJD), and the arrangement is as follows: Figure 7 As shown:

[0064] The regular hexagon of the unit cell and its three diagonals are shown by dotted lines. Each MOSFET integrated with an SBD is an equilateral triangle, and each MOSFET integrated with an HJD is an equilateral triangle.

[0065] Two MOSFETs with integrated SBDs are arranged vertex to vertex in a regular hexagon;

[0066] Four HJD-integrated MOSFETs are arranged two by two at two intervals between two SBD-integrated MOSFETs.

[0067] by Figure 7 The two MOSFETs with integrated SBDs and the two MOSFETs with integrated SBDs arranged in a manner, the structure of a single cell is symmetrical and has high reliability. In addition, in the process of arranging multiple cells to form a semiconductor device, the arrangement is simple and can be easily prepared. In this way, the structure of each unit cell of the semiconductor integrated device of the embodiment of the present application is the same structure, and the arrangement is also a simple repetition, which makes the preparation of the semiconductor integrated device of the present application simple and quick.

[0068] The semiconductor integrated device of the embodiment of the present application:

[0069] First, each cell integrates two MOSFETs with integrated SBDs and four heterojunction diodes HJDs;

[0070] Secondly, the arrangement of two SBD-integrated MOSFETs and four HJD-integrated MOSFETs is defined as the two SBD-integrated MOSFETs are arranged vertex-to-vertex in a regular hexagon, and the four HJD-integrated MOSFETs are arranged in pairs at two intervals between the two SBD-integrated MOSFETs.

[0071] In the prior art, a split-source SBD integrated MOSFET designed with a stripe cell arrangement is Figure 2 As shown, the gates 2-42-1 of two adjacent cells are long strips. Figure 2 The middle gate 2-42-1 is a cross section.

[0072] This application is different. The semiconductor integrated device of this application chooses to integrate the heterojunction diode (HJD) and the Schottky diode (SBD) in the middle of the first gate 42-1 of the regular hexagonal frame of two adjacent cells, forming each unit cell with four MOSFETs integrated with HJD and two MOSFETs integrated with SBD; and the cell composed of four MOSFETs integrated with HJD and two MOSFETs integrated with SBD is a regular hexagonal cell. The regular hexagonal arrangement can improve the channel density and increase the conduction current. On the one hand, this application solves the problem of insufficient conduction capability of the strip cell arrangement device in the prior art; on the other hand, through the interlaced design of the MOSFET integrated with HJD and the MOSFET integrated with SBD, the semiconductor integrated device of this application has a lower reverse low conduction voltage drop, and improves the reliability of the device, the chip area can be made smaller, and the cost can be reduced.

[0073] It should be noted that if Figure 7 As shown, the regular hexagon is roughly a regular hexagon, and the MOSFET integrated with HJD and the MOSFET integrated with SBD are also roughly a regular triangle structure.

[0074] Adjacent HJD MOSFETs need to share a side, so that the HJD MOSFETs can be fine-tuned adaptively. It is just a roughly equilateral triangle structure. The place where the adjacent HJD MOSFETs are connected can be done according to the process.

[0075] In implementation, such as Figure 7 As shown, the two MOSFETs with integrated SBDs have the bottom sides of the Schottky contact regions as the two oppositely disposed bottom sides of the regular hexagon;

[0076] The bottom side of each HJD-integrated MOSFET having the HJD anode is located at the bottom side of the regular hexagon;

[0077] Among them, Figure 6 As shown, the HJD anode includes a P-poly region 33-1 and a second P+ injection region 33-2 formed sequentially from top to bottom.

[0078] In implementation, such as Figure 7 As shown, the cell is multiple;

[0079] Adjacent HJD-integrated MOSFETs in adjacent cells share a bottom edge of the HJD anode;

[0080] Each of the MOSFETs integrated with SBDs has a bottom edge of a Schottky contact region, that is, the bottom edges of the Schottky contact regions of adjacent MOSFETs integrated with SBDs in adjacent cells are not shared.

[0081] Adjacent HJD-integrated MOSFETs in adjacent cells share a bottom edge of the P-poly region of the HJD-integrated MOSFET, and the area occupied by all HJD-integrated MOSFETs in the semiconductor integrated device is smaller. The area of ​​the semiconductor integrated device with the same number of HJD-integrated MOSFETs can be made smaller.

[0082] In addition, combined with the feature that the bottom edges of the Schottky contact areas of the MOSFETs of adjacent integrated SBDs in adjacent cells are not shared, adjacent cells can be closely fitted together, thereby increasing the cell arrangement density of the semiconductor integrated device and making the area of ​​the semiconductor integrated device smaller.

[0083] In implementation, such as Figures 5 to 10 As shown, the semiconductor integrated device includes:

[0084] Substrate 1;

[0085] a drift region 2 located above the substrate;

[0086] A channel region 32 of a regular hexagonal frame is formed on the drift region 2;

[0087] A source electrode 32 - 1 of a regular hexagonal frame is formed on the channel region 32 ;

[0088] The JFET region 33 of a regular hexagonal frame is formed on the drift region 2 and is connected to the outer edge of the channel region 31; the JFET region has two first JFET frames and four second JFET frames; wherein the two first JFET frames are arranged opposite to each other and have flush top surfaces and serve as MOSFET frames for two integrated SBDs of the JFET region, and the four second JFET frames have downward steps and form a P-poly region 33-1 and a second P+ injection region 33-2 in sequence from top to bottom at the steps. The P-poly region 33-1 and the second P+ injection region 33-2 form a HJD anode.

[0089] The six sides of the channel region 32 of the regular hexagonal frame serve as the channel regions of two MOSFETs integrated with SBD and four MOSFETs integrated with HJD. In this way, the process of forming a channel region 32 of a regular hexagonal frame can form the channel regions of two MOSFETs integrated with SBD and four MOSFETs integrated with HJD at one time, the process is simple and easy to process, and the structure of the channel region 32 of the regular hexagonal frame is also relatively simple.

[0090] The six sides of the regular hexagonal source 32-1 serve as the sources of two SBD-integrated MOSFETs and four HJD-integrated MOSFETs. In this way, the process of forming a regular hexagonal source 32-1 can form the sources of two SBD-integrated MOSFETs and four HJD-integrated MOSFETs at one time, the process is simple and easy to process, and the structure of the regular hexagonal source 32-1 is also relatively simple.

[0091] The two first JFET frames are arranged opposite to each other and have the top surfaces flush and serve as frames for two integrated SBD MOSFETs in the JFET region. The four second JFET frames have downward steps and form a P-poly region 33-1 and a second P+ injection region 33-2 in sequence from top to bottom at the steps. This time, the corresponding layer structures are prepared for the structural requirements of the two integrated SBD MOSFETs and the four integrated HJD MOSFETs.

[0092] Figure 5 for Figure 4-2 A cross-sectional view of a structure consisting of two halves of cells adjacent to each other at the OA position; Figure 6 for Figure 4-2 A cross-sectional view of a structure consisting of two adjacent halves of a cell at the OB position. Figure 5 and Figure 6 In the figure, the vertical dotted line is the boundary of the cell.

[0093] In implementation, the semiconductor integrated device further includes:

[0094] A regular hexagonal channel contact region 31 is formed on the drift region 2 and is connected to the inner edge of the source 32 - 1 ;

[0095] A regular hexagonal ohmic contact region 41 covers the channel contact region 31 and partially covers the source electrode 32 - 1 ;

[0096] The isolation region 42 of a regular hexagonal frame is sleeve-connected to the outer edge of the ohmic contact region 41;

[0097] The first gate 42 - 1 of a regular hexagonal frame is disposed in the isolation region 42 and is completely surrounded by the isolation region 42 ;

[0098] Two Schottky contact regions 43 are formed at the first JFET frame and connected to the outside of the isolation region 42;

[0099] Source metal 5, formed on the ohmic contact region 41, the isolation region 42, the Schottky contact region 43 and the P-poly region 33-1;

[0100] A second gate 42-2 is formed on the middle portion of the HJD anode, wherein the first gate 42-1 and the second gate 42-2 are located in the same layer and connected;

[0101] A drain is formed on the back side of the substrate.

[0102] That is, each cell of the semiconductor integrated device is divided according to the two first JFET borders and four second JFET borders of the JFET area 33 of the regular hexagonal frame. The two relatively arranged first JFET borders and the structures located above and below them form two MOSFETs with integrated SBD, and the four second JFET borders and the structures located above and below them form four MOSFETs with integrated HJD.

[0103] In this way, the preparation process of the regular hexagonal channel contact area 31, the regular hexagonal ohmic contact area 41, and the regular hexagonal frame first gate 42-1 are simple, and their structures are also relatively simple, thereby making the preparation process of the semiconductor integrated device simple, the structure more compact, and saving chip area.

[0104] The first gate 42-1 and the second gate 42-2 are located in the same layer and connected, so that the first gate 42-1 and the second gate 42-2 can be formed by a single process and can maintain the same potential. That is, the gate of the MOSFET integrated with SBD (the second gate 42-2) and the gate of the MOSFET integrated with HJD (the first gate 42-1) are formed by a single process, and the preparation is simple.

[0105] Figure 7 for Figure 4-1 The cell shown has the source metal removed and Figure 5 A perspective diagram of a single cell in the XY direction showing the CC position shown; Figure 8 for Figure 7 A partial enlarged view of .

[0106] Fig. 9 for Figure 4-1 The cell shown has the source metal and the first gate removed and Figure 6 A perspective diagram of a single cell in the XY direction of the DD position shown; Fig.10 for Fig. 9 A partial enlarged view of .

[0107] Figure 4-1 , Figure 7 and Figure 8 In the same area Figure 4-1 The shape shows that Figure 7 and Figure 8 The reason why the shapes in are different is that Figure 7 and Figure 8Some areas are shown through for top-down perspective.

[0108] Figure 4-1 , Fig. 9 and Fig.10 In the same area Figure 4-1 The shape shows that Fig. 9 and Fig.10 The reason why the shapes in are different is that Fig. 9 and Fig.10 Some areas are shown through for top-down perspective.

[0109] The regular hexagonal ohmic contact region 41 is Figure 4-1 In the figure, it is shown as a wider bar. Figure 7 and Figure 8 In FIG. 4 , the regular hexagonal ohmic contact region 41 shows the narrower channel contact region 31 located thereunder due to perspective reasons. Figure 7 and Figure 8 In the figure, the ohmic contact region 41 is visually a regular hexagonal frame.

[0110] Fig.10 middle, Fig.10 The regular hexagonal frame between the middle channel region 32 and the isolation region 42 is Figure 5 The region where the first gate 42 - 1 and the source 32 - 1 overlap each other.

[0111] In the prior art, a split-source SBD integrated MOSFET designed with a stripe cell arrangement is Figure 2 As shown, two adjacent cells have a long strip-shaped gate 2-42-1 in common. The present application selects to integrate a heterojunction diode (HJD) and a Schottky diode (SBD) in the middle of the gates of two adjacent cells (corresponding to between the two first gates 42-1 of the respective regular hexagonal frames of the two adjacent cells, as shown in FIG. Figure 6 As shown in the figure, the cells are arranged in hexagonal cells, which can improve the channel density, increase the conduction current, and have a strong forward conduction capability, solving the problem of insufficient conduction capability of devices arranged in strip cells. Because the greater the channel density, the greater the conduction current under the same area, making the forward conduction capability of MOSFETs integrated with HJD and MOSFETs integrated with SBD stronger.

[0112] At the same time, through the interlaced design of HJD and SBD, the device has a lower reverse low conduction voltage drop and improves the reliability of the device. The chip area can be made smaller and the cost can be reduced.

[0113] The following is an explanation of the strong reverse conduction capability of MOSFETs with integrated HJD and MOSFETs with integrated SBD:

[0114] Because the hexagonal cell design is adopted, the reliability of the hexagonal cell is weaker than that of the strip cell, so the reliability will also be weaker after adding the SBD structure;

[0115] Therefore, it is necessary to introduce an area to shield the electric field at the SBD to improve the reliability of the device, but this will reduce the area of ​​the SBD, thereby reducing the reverse conduction voltage drop of the device. Therefore, the solution of introducing HJD to protect SBD can achieve both guaranteed reliability and low reverse conduction voltage drop (because HJD can also conduct).

[0116] In the middle of the gates of two adjacent cells (corresponding to the two first gates 42-1 of the respective regular hexagonal frames of the two adjacent cells, such as Figure 6 The SBD and HJD structures are integrated in the layout, and the two structures are arranged in an interlaced manner, which retains the advantages of low conduction of SBD and HJD. In addition, because the second P+ injection region 33-2 is located below the HJD, and the area is twice that of the MOSFET integrated with HJD (that is, the area of ​​the MOSFET integrated with HJD is twice that of the MOSFET integrated with SBD), the surge resistance and voltage withstand capability of the device can be improved, and the reliability of the device can be increased; the reasonable design of SBD can also reduce the reverse recovery loss of the device in power electronic applications.

[0117] The semiconductor integrated device of the present application has the following technical effects:

[0118] In the prior art, most SiC MOSFET devices with a single integrated SBD or integrated HJD MOSFET adopt a strip cell design. The semiconductor integrated device of the present application adopts a regular hexagonal cell arrangement design to improve the channel density and increase the on-current.

[0119] Compared with the SiC MOSFET device in the prior art that only integrates SBD, the semiconductor integrated device of the present application can achieve the aforementioned purpose of increasing channel density and increasing on-current, while improving the device's surge resistance and voltage resistance, increasing the device's reliability, and does not require additional design of the size of the JFET area to prevent the electric field in the Schottky contact area from being too high.

[0120] For the MOSFET device integrated with HJD in the prior art, although it has a low conduction voltage drop in the reverse direction, the MOSFET integrated with HJD can be regarded as a PiN diode in the reverse recovery process. During this process, minority carriers will be injected, increasing the reverse recovery loss of the device. Each cell of the semiconductor integrated device of the present application integrates one-third of the MOSFET integrated with SBD. During the reverse recovery process of the device, the injection of minority carriers will be greatly reduced, and the reverse recovery loss will be lower.

[0121] Figure 11-1A modeling diagram of a simulation device of a MOSFET with integrated SBD in the prior art (hereinafter referred to as device 1); Figure 11-2 for Figure 11-2 It is a simple combination structure of two SBDs and one HJD (hereinafter referred to as device 2). It is not the present application, but only a simplified version of the present application without MOS structure. The comparison between the two is to highlight the advantages of this combination. The advantages of the new structure are lower on-state voltage drop and higher voltage resistance (better reliability).

[0122] Fig.12 for Figure 11-1 and Figure 11-2 The on-state current of the two devices changes with the source-drain voltage Vsd. Fig.12 As shown, the horizontal axis is the source-drain voltage Vsd, in V; the vertical axis is the on-current of the integrated diode (SBD and HJD are both integrated diodes), in A. Fig.12 As shown, curve ① is a curve showing that the on-state current of the integrated diode of device 1 changes with the source-drain voltage Vsd; curve ② is a curve showing that the on-state current I of the integrated diode of device 2 changes with the source-drain voltage Vsd. total Curve ③ is the current I flowing through the Schottky terminal in the on-current of the integrated diode of device 2. SBD Curve ④ is the heterojunction current I in the on-current of the integrated diode of device 2. HJD Curve as the source-drain voltage Vsd changes.

[0123] Device 2 (turn-on voltage is about 1.3V) has a lower turn-on voltage than device 1 (turn-on voltage is about 1.45V). The component currents of device 2 are divided into the total current I total is the current I flowing through the Schottky terminal SBD and the heterojunction current I HJD The sum of I total =I SBD +I HJD It can be seen that the MOSFET with integrated HJD has a lower on-state voltage drop than the MOSFET with integrated SBD, but the current after conduction is smaller. However, for device 2, the combined current carrying capacity of the two is very similar to that of device 1.

[0124] Fig.13 for Figure 11-1 and Figure 11-2 The drain current of the two devices changes with the drain voltage. Fig.13 As shown in the figure, the horizontal axis is the drain voltage, in V; the vertical axis is the drain current, in A. Fig.13 As shown, curve ① is the curve of the drain current of device 1 changing with the drain voltage; curve ② is the curve of the drain current of device 2 changing with the drain voltage. Fig.13 As shown, due to the addition of the second P+ implantation region 33 - 2 , the withstand voltage of device 2 is improved compared with device 1 (ie, the breakdown voltage is higher), and the reverse leakage of device 2 is also lower.

[0125] Fig.14 for Fig.13 The vertical axis index of the graph; that is, relative to Fig.13 , Fig.14 The unit of the vertical axis becomes smaller. Fig.14 As shown, curve ① is the curve of the drain current of device 1 changing with the drain voltage; curve ② is the curve of the drain current of device 2 changing with the drain voltage. Fig.14 As shown, the reverse leakage of device 2 is also lower.

[0126] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0127] The present application is described with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, and the combination of the process and / or box in the flowchart and / or block diagram can be realized by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for realizing the function specified in one process or multiple processes in the flowchart and / or one box or multiple boxes in the block diagram.

[0128] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0129] These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce computer-implemented processing, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0130] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0131] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A semiconductor integrated device, characterized in that: The invention comprises a cell, wherein the shape of the cell is a regular K-gon, wherein the value of K is 4, 6 or 8; the diagonal of the cell divides the cell into K regular triangle structures, and one regular triangle structure comprises a MOSFET integrated with an HJD or a MOSFET integrated with an SBD; There are n MOSFETs with integrated HJD and m MOSFETs with integrated SBD. Wherein, n and m are positive integers and the sum of n and m is K.

2. The semiconductor integrated device according to claim 1, characterized in that: The cell is a regular hexagonal cell, and the three diagonals of the regular hexagonal cell divide the cell into six regular triangle structures; Where n and m are positive integers and the sum of n and m is six, The value range is greater than or equal to Less than or equal to 2.

3. The semiconductor integrated device according to claim 1, characterized in that: m is 2, and there are two MOSFETs with integrated SBD; n is 4, and the number of MOSFETs integrated with HJD is four.

4. The semiconductor integrated device according to claim 1, characterized in that: m is 4, and there are four MOSFETs with integrated SBD; n is 2, and the number of MOSFETs integrated with the HJD is two.

5. The semiconductor integrated device according to claim 3, characterized in that: Two MOSFETs of the integrated SBD are arranged in a regular hexagon in a vertex-to-vertex manner; The four MOSFETs integrated with HJD are arranged in pairs at two intervals between the two MOSFETs integrated with SBD; The two SBD-integrated MOSFETs have bottom sides of the Schottky contact regions as two oppositely disposed bottom sides of a regular hexagon; The bottom side of each HJD-integrated MOSFET having the HJD anode is located at the bottom side position of a regular hexagon.

6. The semiconductor integrated device according to claim 5, characterized in that: The number of cells is multiple; Adjacent MOSFETs with integrated HJDs in adjacent cells share a bottom edge with an HJD anode; Each of the SBD-integrated MOSFETs has a bottom side of a Schottky contact region.

7. The semiconductor integrated device according to claim 6, characterized in that: include: Substrate (1); a drift region (2) located above the substrate; A channel region (32) in the shape of a regular hexagonal frame is formed on the drift region (2); A source electrode (32-1) of a regular hexagonal frame is formed on the channel region (32); A JFET region (33) of a regular hexagonal frame is formed on the drift region (2) and is sleeve-connected to the outer edge of the channel region (32), the JFET region having two first JFET frames and four second JFET frames; wherein the two first JFET frames are arranged opposite to each other and have flush top surfaces and serve as MOSFET frames for two integrated SBDs of the JFET region; the four second JFET frames have downward steps and form HJD anodes at the steps, and serve as MOSFET frames for the integrated HJDs.

8. The semiconductor integrated device according to claim 7, characterized in that: Also includes: A regular hexagonal channel contact region (31) is formed on the drift region (2) and is sleeve-connected to the inner edge of the source (32-1); A regular hexagonal ohmic contact region (41) covers the channel contact region (31) and partially covers the source electrode (32-1); An isolation region (42) of a regular hexagonal frame is sleeve-connected to the outer edge of the ohmic contact region (41); A first gate (42-1) of a regular hexagonal frame is arranged in the isolation region (42) and is completely surrounded by the isolation region (42); Two Schottky contact regions (43) are formed on the first JFET frame and connected to the outside of the isolation region (42); A second grid (42-2) is formed on the middle portion of the HJD anode, wherein the first grid (42-1) and the second grid (42-2) are located in the same layer and connected; A source metal (5) is formed on the ohmic contact region (41), the isolation region (42), the Schottky contact region (43) and the HJD anode; A drain is formed on the back side of the substrate.

9. The semiconductor integrated device according to claim 8, characterized in that: A distance is maintained between the inner edge of the JFET region (33) and the outer edge of the source (32-1), and a portion of the channel region (32) is formed between the inner edge of the JFET region (33) and the outer edge of the source (32-1) to keep the source (32-1) facing the JFET region (33).

10. The semiconductor integrated device according to claim 9, characterized in that: A distance is maintained between the HJD anode and the inner edge of the JFET region (33), and the HJD anode is flush with the outer edge of the JFET region (33).

Images