Method for preparing gate structure, semiconductor device and electronic device

Abstract

The present invention relates to a method for preparing a gate structure, a semiconductor device and an electronic device, and relates to the field of integrated circuits. A method for preparing a gate structure comprises the following steps: providing a base structure; the base structure comprises a substrate, a gate dielectric layer is provided on the substrate, a dummy gate structure and a barrier layer are provided on the gate dielectric layer, and the barrier layer covers the dummy gate structure; performing a first dry etching process to remove the barrier layer located above the dummy gate structure to expose the dummy gate structure; performing a second dry etching process, by controlling the high etching selectivity of the dummy gate structure and the barrier layer during the second dry etching process, etching away all the dummy gate structures, forming a groove in the barrier layer, and exposing the gate dielectric layer in the groove; forming a metal gate in the groove. In the method for preparing the gate structure provided in the present application, both the barrier layer and the dummy gate structure adopt a dry etching process, so they can be completed on the same dry etching equipment, without the need to transfer different equipment, thereby improving production efficiency.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a method for preparing a gate structure, a semiconductor device and an electronic device. Background Art

[0002] At present, the manufacturing of CMOS integrated circuits uses the "silicon gate self-alignment" process, that is, the gate dielectric layer and the gate are formed first, and then the source and drain ion doping is performed. However, a high-temperature annealing process is performed later to activate the doping, but the gate undergoing such a step will cause device problems such as threshold voltage changes.

[0003] Conventional technology proposes a process of first forming a dummy gate, then etching away the dummy gate and filling a metal gate. However, a wet process or a combination of a wet process and a dry process is used when etching the dummy gate, which makes the process flow complicated. Summary of the invention

[0004] Based on this, it is necessary to provide a method for preparing a gate structure, a semiconductor device and an electronic device to address the problem of complex etching process of a dummy gate in the prior art.

[0005] In a first aspect, the present application provides a method for preparing a gate structure, comprising the following steps:

[0006] Providing a base structure; the base structure comprises a substrate, the substrate has a gate dielectric layer, the gate dielectric layer has a dummy gate structure and a barrier layer, the barrier layer covers the dummy gate structure;

[0007] Performing a first dry etching process to remove the barrier layer located above the dummy gate structure to expose the dummy gate structure;

[0008] Performing a second dry etching process, by controlling a high etching selectivity ratio between the dummy gate structure and the barrier layer during the second dry etching process, etching away all of the dummy gate structure, forming a trench in the barrier layer, wherein the trench exposes the gate dielectric layer;

[0009] A metal gate is formed in the trench.

[0010] In one embodiment, the formation process of the base structure includes:

[0011] providing a substrate;

[0012] forming a gate dielectric layer on the substrate;

[0013] forming a dummy gate structure on the gate dielectric layer;

[0014] A barrier layer is formed on the gate dielectric layer, wherein the barrier layer covers the dummy gate structure.

[0015] In one of the embodiments, the gate dielectric layer and the barrier layer are both made of silicon oxide, the dummy gate structure is made of polysilicon, and the high etching selectivity is a high etching selectivity of polysilicon relative to silicon oxide.

[0016] In one of the embodiments, in the second dry etching process, a mixed gas of xHBr / yO2 is used, wherein the ratio of x / y is (50-100):1.

[0017] In one of the embodiments, during the second dry etching process, the bias voltage is adjusted to 50V-200V.

[0018] In one embodiment, the first dry etching process and the second dry etching process are performed on the same etching machine, and the substrate structure is always located in the same chamber.

[0019] In one embodiment, the material of the metal gate includes at least one of aluminum, tungsten and copper.

[0020] In one embodiment, in the first dry etching process, carbon fluorine gas is used to etch the barrier layer.

[0021] In a second aspect, the present application also provides a semiconductor device, comprising a gate structure prepared by the preparation method.

[0022] In a third aspect, the present application also provides an electronic device, comprising the semiconductor device.

[0023] In the preparation method of the above-mentioned gate structure, the base structure includes a substrate, a gate dielectric layer is provided on the substrate, a dummy gate structure and a barrier layer are provided on the gate dielectric layer, and the barrier layer covers the dummy gate structure. The barrier layer is removed by a first dry etching process to expose the dummy gate structure, and the dummy gate structure is etched by a second dry etching process to form a groove, and then a metal gate is formed in the groove. In the conventional technology, a planarization process is used to remove the barrier layer, and a process combining wet etching and dry etching is used to etch the gate structure, which requires multiple equipment transfers, and the process is complicated, resulting in low production efficiency. In the preparation method of the gate structure provided in the present application, the barrier layer and the dummy gate structure are both processed by a dry etching process, so they can be completed on the same dry etching equipment, without the need to transfer different equipment, thereby improving production efficiency. In addition, the chemical polishing solution of the planarization process is generally expensive. The present application replaces the planarization process with dry etching to reduce costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 is a flow chart of a method for preparing a gate structure provided in an embodiment;

[0026] Figure 2 is a schematic diagram of a substrate structure provided in an embodiment;

[0027] Figure 3 is a schematic diagram of etching the barrier layer to expose the dummy gate structure in one embodiment;

[0028] Figure 4 is a schematic diagram of etching and removing the dummy gate structure in one embodiment;

[0029] Figure 5 is a schematic diagram of forming a metal gate in one embodiment;

[0030] Figure 6a Schematic diagram of grooves in some embodiments obtained under TEM;

[0031] Figure 6b Schematic diagram of grooves in some embodiments obtained under SEM;

[0032] Figure 7a Schematic diagram of the groove obtained in the conventional technology under TEM;

[0033] Figure 7b This is a schematic diagram of the groove in the traditional technology obtained under SEM.

[0034] Description of reference numerals:

[0035] 11. Substrate; 12. Gate dielectric layer; 13. Barrier layer; 14. Pseudo-gate structure; 15. Trench; 16. Metal gate. DETAILED DESCRIPTION

[0036] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0038] At present, the "silicon gate self-alignment" process is used in the manufacture of CMOS integrated circuits, that is, the gate dielectric layer and the gate are formed first, and then the ion doping of the source and drain is performed. Because the gate structure blocks the diffusion of ions into the channel region, the doping is gate-aligned. A high-temperature annealing process will be performed later to activate the doping, but the high-temperature annealing process of the gate will cause device problems such as threshold voltage changes.

[0039] Polysilicon pseudo-gate technology can solve the above problems. Similarly, after ion doping and high-temperature annealing, a protective oxide layer SiO2 is grown, and then polished through a planarization process to expose the polysilicon pseudo-gate. Subsequently, the polysilicon gate is removed through a mixed process of wet etching and dry etching, and the work function metal, i.e., the gate metal material, is used to fill the gate to form a metal gate.

[0040] However, when wet etching the polysilicon gate, wet etching is very sensitive to the doped polysilicon pseudo gate, and the etching rate will be greatly reduced; dry etching is required to be combined with wet etching, that is, dry etching is used to remove the doped polysilicon layer on the pseudo gate, and then wet etching is used to remove the remaining undoped polysilicon of the pseudo gate. This process is complicated, and because it is combined with isotropic wet etching, it is only suitable for the simultaneous removal of N-type pseudo gates and P-type pseudo gates.

[0041] See also Figure 1 The present invention provides a method for preparing a gate structure, comprising the following steps:

[0042] S11, such as Figure 2 As shown, a base structure is provided; the base structure includes a substrate 11 , a gate dielectric layer 12 is provided on the substrate 11 , a dummy gate structure 14 and a barrier layer 13 are provided on the gate dielectric layer 12 , and the barrier layer 13 covers the dummy gate structure 14 .

[0043] Exemplarily, the substrate 11 may be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate 11 may be a single-layer structure or a multi-layer structure. For example, the substrate 11 may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 11 may be a layered substrate 11 including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate 11 should not limit the scope of protection of the present disclosure. The substrate 11 may include a word line structure and a capacitor contact structure, etc., which are not closely related to the invention of this solution, so they are omitted.

[0044] Exemplarily, the substrate 11 further has a gate dielectric layer 12 , including but not limited to a silicon oxide layer (SiO 2 ), a silicon nitride layer (Si 3 N 4 ), an aluminum oxide (Al 2 O 3 ) or a silicon oxynitride layer (SiON).

[0045] Exemplarily, the barrier layer 13 is located on the gate dielectric layer 12, and covers the gate dielectric layer 12 and the dummy gate structure 14. The dummy gate structure 14 can play a placeholder role. Optionally, the material of the barrier layer 13 includes but is not limited to a silicon oxide layer (SiO2), a silicon nitride layer (Si3N4), an aluminum oxide (Al2O3) or a silicon oxynitride layer (SiON). Optionally, the material of the dummy gate structure 14 includes but is not limited to polysilicon.

[0046] S12, such as Figure 3 As shown, a first dry etching process is performed to remove the barrier layer 13 located above the dummy gate structure 14 to expose the dummy gate structure 14 .

[0047] Exemplarily, the barrier layer 13 is located on the dummy gate structure 14 , and after the barrier layer 13 is removed by etching, the dummy gate structure 14 can be exposed, which facilitates the subsequent etching of the dummy gate structure 14 .

[0048] In this step, a first dry etching process is used to remove the barrier layer 13. In conventional technology, a planarization process (CMP, Chemical Mechanical Planarization) is used to remove the barrier layer 13, and the substrate structure is placed in a planarization device for processing, and then transferred to an etching device for etching, which requires multiple transfers and has low production efficiency.

[0049] S13, such as Figure 4As shown, a second dry etching process is performed. By controlling the high etching selectivity of the dummy gate structure 14 and the barrier layer 13 during the second dry etching process, the entire dummy gate structure 14 is etched away to form a trench 15 in the barrier layer 13 , and the trench 15 exposes the gate dielectric layer 12 .

[0050] Exemplarily, a high etching selectivity refers to the ratio of the etching rate of a certain material to another material during the etching process. In this embodiment, the high etching selectivity refers to the high etching selectivity of the dummy gate structure 14 to the barrier layer 13, that is, the etching rate of the dummy gate structure 14 is greater than the etching rate of the barrier layer 13. By setting this selectivity, the etching power and process conditions can be effectively adjusted during the second dry etching process to ensure that while removing the dummy gate structure 14, the underlying barrier layer 13 will not be over-etched or damaged.

[0051] By increasing the etching power, the removal process of the dummy gate structure 14 can be accelerated. The high etching selectivity can ensure that the dummy gate structure 14 is effectively removed, avoiding the accumulation of harmful byproducts of the dummy gate structure 14 on the trench sidewalls. At the same time, the barrier layer 13 remains unaffected and has a complete protective effect.

[0052] For example, when the dummy gate structure 14 is completely removed, etching will continue to form a trench 15 , and the trench 15 will expose the gate dielectric layer 12 below, creating space for the subsequent deposition of the metal gate 16 .

[0053] Furthermore, both step S14 and step S13 use dry etching process, which means that the whole process does not need to replace equipment, avoiding time delay and additional cost expenditure caused by equipment replacement. By completing these two steps in the same equipment, production efficiency can be significantly improved, equipment downtime and operation complexity can be reduced. At the same time, the uniformity of this process can also ensure the stability and consistency of the etching process, help improve product quality, and shorten the overall production cycle. The choice of dry etching also ensures higher precision and good controllability in the etching process, so that each process step can be completed more accurately.

[0054] S14, such as Figure 5 As shown, a metal gate 16 is formed in the trench 15 .

[0055] Exemplarily, the groove 15 is formed and the gate dielectric layer 12 is exposed, and the metal gate 16 material can be deposited in the groove 15. In some feasible implementations, the metal gate 16 can be deposited by a deposition process, including but not limited to a chemical vapor deposition process (Chemical Vapor Deposition, CVD), an atomic layer deposition process (Atomic Layer Deposition, ALD), a high density plasma deposition (High Density Plasma, HDP) process, a plasma enhanced deposition process, and a spin-on dielectric layer (Spin-on Dielectric, SOD) process. One or more processes.

[0056] In the above-mentioned method for preparing the gate structure, the base structure includes a substrate 11, a gate dielectric layer 12 is provided on the substrate 11, a dummy gate structure 14 and a barrier layer 13 are provided on the gate dielectric layer 12, and the barrier layer 13 covers the dummy gate structure 14. The barrier layer 13 is removed by a first dry etching process to expose the dummy gate structure 14, and the dummy gate structure 14 is etched by a second dry etching process to form a groove 15, and then a metal gate 16 is formed in the groove 15. In the conventional technology, a planarization process is used to remove the barrier layer 13, and a process combining wet etching and dry etching is used to etch the gate structure, which requires multiple equipment transfers, and the process is complex, resulting in low production efficiency. In the method for preparing the gate structure provided in the present application, the barrier layer 13 and the dummy gate structure 14 are both processed by a dry etching process, so they can be completed on the same dry etching equipment, without the need to transfer different equipment, thereby improving production efficiency. In addition, the chemical polishing solution of the planarization process is generally expensive. The present application replaces the planarization process with dry etching to reduce costs.

[0057] In some embodiments, the first dry etching and the second dry etching include at least any one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), or high density plasma etching (HDP).

[0058] In some embodiments, the process of forming the base structure includes: providing a substrate 11; forming a gate dielectric layer 12 on the substrate 11; forming a dummy gate structure 14 on the gate dielectric layer 12; and forming a barrier layer 13 on the gate dielectric layer 12, wherein the barrier layer 13 covers the dummy gate structure 14.

[0059] Exemplarily, the surface of substrate 11 is cleaned and processed.

[0060] Exemplarily, the gate dielectric layer 12 may be a silicon oxide (SiO2) layer having good electrical insulation to isolate the gate electrode and the semiconductor channel and prevent a short circuit between the gate electrode and the source / drain. Further, the gate dielectric layer 12 may be formed of a material with a high-k dielectric constant. For example, the material of the gate dielectric layer 12 includes: aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3).

[0061] For example, a dummy gate structure 14 is formed on the gate dielectric layer 12 . The dummy gate structure 14 may be formed by a deposition process and patterned etching.

[0062] Exemplarily, a barrier layer 13 is formed on the gate dielectric layer 12 , and the barrier layer 13 covers both the gate dielectric layer 12 and the dummy gate structure 14 .

[0063] In some embodiments, the gate dielectric layer 12 and the barrier layer 13 are both made of silicon oxide, the dummy gate structure 14 is made of polysilicon, and the high etching selectivity is a high etching selectivity of polysilicon relative to silicon oxide.

[0064] When the gate dielectric layer 12 and the barrier layer 13 are both made of silicon oxide, and the dummy gate structure 14 is made of polysilicon, the etching selectivity is set to a high etching selectivity of polysilicon relative to silicon oxide. Specifically, this means that the etching rate of polysilicon is higher than the etching rate of silicon oxide. By setting this etching selectivity, during the etching process, the dummy gate structure 14 can be accurately removed while avoiding excessive etching of the gate dielectric layer 12 and the barrier layer 13.

[0065] In actual operation, as the etching intensity increases, the dummy gate structure 14 can be completely removed in a relatively short time because the etching rate of polysilicon is faster than that of silicon oxide, while the gate dielectric layer 12 and the barrier layer 13 are basically not affected due to the lower etching rate of silicon oxide, thereby maintaining their integrity. This optimization of the etching process not only improves the etching efficiency, but also ensures the selectivity of the process, so that other key layers will not be damaged during the etching process, ensuring the accuracy and integrity of the structure.

[0066] Therefore, by precisely controlling the etching selectivity, the safety of the etching process and the stability of production can be greatly improved while ensuring that the dummy gate structure 14 is completely removed, and defects or damage caused by incomplete or excessive etching can be reduced. This efficient etching strategy is of great significance for improving the manufacturing accuracy and yield of semiconductor devices.

[0067] like Figure 6a and 6b As shown, Figure 6aSchematic diagrams of the grooves 15 in some embodiments obtained under a TEM (Transmission Electron Microscope) are shown. Figure 6b Schematic diagrams of the grooves 15 in some embodiments obtained under a SEM (Scanning Electron Microscope) are shown. Figure 6a and 6b As shown, the use of a process with a high etching selectivity ratio of polysilicon to silicon oxide can achieve efficient removal of the polysilicon pseudo gate. In this process, the etching rate for polysilicon is significantly higher than that for silicon oxide, so the polysilicon pseudo gate structure is almost completely etched away, leaving only the silicon oxide gate dielectric layer.

[0068] The key to this process is the application of high etching selectivity, which enables the etchant to act on the polysilicon pseudo-gate layer first during the etching process, significantly reducing the etching rate of the silicon oxide gate dielectric layer, thereby effectively avoiding damage to the silicon oxide layer. This etching strategy not only ensures the complete removal of the pseudo-gate structure, but also greatly improves the process accuracy and prevents unnecessary damage to the gate oxide layer during the etching process.

[0069] therefore, Figure 6a and 6b The advantages of this highly selective etching process are clearly demonstrated, that is, by optimizing the etching selectivity, the polysilicon pseudo-gate can be completely removed while maintaining the integrity of the gate oxide layer, providing a good foundation for subsequent process steps. This method is particularly suitable for high-precision semiconductor manufacturing, ensuring the stability of the structure and the high quality of the device.

[0070] In traditional technology, such as Figure 7a As shown, Figure 7a A schematic diagram showing the deposition of etching byproducts on the sidewall of the trench 15 in the conventional process under TEM is shown. Figure 7b A schematic diagram of the deposition of etching byproducts on the sidewalls of the trench 15 in the conventional process under SEM (Scanning Electron Microscope) is shown. When etching the pseudo gate structure 14, etching byproducts will be left on the sidewalls of the formed trench 15 and will be deposited on the sidewalls of the barrier layer 13. The main components are SiBr4 and SiO2, which are not conducive to the subsequent filling of work function materials and affect the overall performance of the device.

[0071] In some embodiments, in the second dry etching process, a mixed gas of xHBr / yO2 is used, wherein the ratio of x / y is (50-100): 1. Optionally, the ratio of x / y in the mixed gas of xHBr / yO2 may be, but is not limited to, 50:1, 55:1, 60:1, 65:1, 70:1, 75:1, 80:1, 85:1, 90:1, 95:1 or 100:1, etc.

[0072] For example, HBr (hydrobromic acid) can be used to etch the polysilicon pseudo gate structure 14 because of its strong reactivity. O2 (oxygen) is mainly used to increase the oxidizing property in the etching reaction, to enhance the etching selectivity, to improve the etching accuracy, and to remove carbides or other residues produced by the reaction.

[0073] In the HBr / O2 mixed gas etching process, HBr is used as the main etching gas, and the gas consumption is relatively large. Oxygen (O2) is usually used to adjust the oxidizing property of the reaction and remove the product to enhance the etching selectivity. In this way, under the same etching conditions, the etching rate of the dummy gate structure 14 is greater than that of the sidewall barrier layer 13, and the second dry etching process can completely etch and remove the dummy gate structure 14 without leaving any impurities.

[0074] Setting the x / y ratio in the xHBr / yO2 mixed gas to (50-100): 1 can improve its etching selectivity and achieve a high etching selectivity ratio for the pseudo-gate structure. If the x / y ratio is too small, the HBr concentration is too small, and it is difficult to achieve the required etching selectivity. If the x / y ratio is too large, the HBr concentration is too high, which may lead to excessive etching and damage to the gate dielectric layer and barrier layer.

[0075] In some embodiments, during the second dry etching process, the bias voltage is adjusted to 50 V to 200 V. Optionally, the bias voltage may be, but is not limited to, 50 V, 80 V, 100 V, 120 V, or 150 V.

[0076] This embodiment uses a higher bias voltage to increase the etching rate. When the ratio of x / y in the xHBr / yO2 mixed gas is controlled to be (50-100):1, the bias voltage and the ratio of the mixed gas work together to achieve complete etching of the pseudo-gate structure without leaving impurities accumulated on the sidewalls of the trench and without damaging the barrier layer and the gate dielectric layer.

[0077] In some embodiments, the first dry etching process and the second dry etching process are performed on the same etching machine, and the substrate structure is always located in the same chamber. In this way, the substrate structure remains in the same chamber, avoiding the need to transfer the substrate to a different chamber during the etching process, which helps reduce contamination or errors that may be introduced during the transfer process, and can reduce operational complexity and improve production efficiency.

[0078] In addition, the process conditions for etching (such as gas composition, pressure, temperature, etc.) can be controlled more accurately, avoiding differences caused by transfer or process fluctuations between different chambers. And multiple treatments on the same equipment can save time in equipment switching, cleaning, gas switching, etc., thereby improving production efficiency and reducing costs. The substrate does not need to be frequently moved in and out of the etcher, which can reduce physical damage to the substrate surface caused by operation, handling, contact, etc.

[0079] In the conventional technology, since a planarization process, wet etching and other processes need to be combined, the substrate structure needs to switch between planarization equipment, wet etching equipment and the like, resulting in low production efficiency. However, the solution provided in this embodiment uses dry etching for both etching of the barrier layer 13 and etching of the dummy gate structure 14. Therefore, the first dry etching process and the second dry etching process can be controlled in the same chamber, which can improve production efficiency, reduce the risk of equipment line change and contamination, and ensure process stability.

[0080] In some embodiments, the material of the metal gate 16 includes at least one of aluminum, tungsten, and copper.

[0081] In some embodiments, in the first dry etching process, a carbon fluorine gas is used to etch the barrier layer 13. Exemplarily, the carbon fluorine gas may be CF4, C4F8, or CHF3. When the carbon fluorine gas is used to etch silicon oxide, the carbon fluorine gas generates active species (such as fluorine ions, fluorine radicals, etc.) through an ionization reaction. These active species react with the surface of silicon oxide to generate volatile gases (such as silicon hexafluoride SiF6), thereby achieving an etching effect.

[0082] The present application also provides a semiconductor device, comprising a gate structure prepared by the method for preparing a gate structure provided in any of the above embodiments.

[0083] The present application also provides an electronic device, including the semiconductor device in any of the above embodiments. The electronic device includes, for example, data storage devices, copiers, network devices, household appliances, instruments, mobile phones, computers and other devices with data storage functions. The electronic device may include a housing and a circuit board arranged in the housing, a memory or a data read-write circuit integrated on the circuit board. The structure of the memory can refer to the relevant description in some of the above embodiments. The electronic device may also include other necessary elements or components, which are not limited in the embodiments of the present disclosure.

[0084] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0085] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a gate structure, characterized in that: The following steps are involved: Providing a base structure; the base structure comprises a substrate, the substrate has a gate dielectric layer, the gate dielectric layer has a dummy gate structure and a barrier layer, the barrier layer covers the dummy gate structure; Performing a first dry etching process to remove the barrier layer located above the dummy gate structure to expose the dummy gate structure; Performing a second dry etching process, by controlling a high etching selectivity ratio between the dummy gate structure and the barrier layer during the second dry etching process, etching away all of the dummy gate structure, forming a trench in the barrier layer, wherein the trench exposes the gate dielectric layer; A metal gate is formed in the trench.

2. The method for preparing a gate structure according to claim 1, characterized in that: The formation process of the base structure includes: providing a substrate; forming a gate dielectric layer on the substrate; forming a dummy gate structure on the gate dielectric layer; A barrier layer is formed on the gate dielectric layer, wherein the barrier layer covers the dummy gate structure.

3. The method for preparing a gate structure according to claim 1, characterized in that: The gate dielectric layer and the barrier layer are both made of silicon oxide, the dummy gate structure is made of polysilicon, and the high etching selectivity is a high etching selectivity of polysilicon relative to silicon oxide.

4. The method for preparing a gate structure according to claim 1, characterized in that: In the second dry etching process, a mixed gas of xHBr / yO2 is used, wherein the ratio of x / y is (50-100):

1.

5. The method for preparing a gate structure according to claim 1 or 4, characterized in that: In the second dry etching process, the bias voltage is adjusted to 50V~200V.

6. The method for preparing a gate structure according to claim 1, characterized in that: The first dry etching process and the second dry etching process are performed on the same etching machine, and the substrate structure is always located in the same chamber.

7. The method for preparing a gate structure according to claim 1, characterized in that: The material of the metal gate includes at least one of aluminum, tungsten and copper.

8. The method for preparing a gate structure according to claim 1, characterized in that: In the first dry etching process, carbon fluorine gas is used to etch the barrier layer.

9. A semiconductor device, characterized in that: A gate structure prepared by the preparation method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: A semiconductor device comprising the semiconductor device according to claim 9.

Images