Semiconductor device and display device

Abstract

The invention relates to a semiconductor device and a display device. The present invention addresses the problem of improving the reliability of a semiconductor device including an oxide semiconductor while suppressing deterioration in characteristics. The semiconductor device includes: an oxide semiconductor layer having a polycrystalline structure over an insulating surface; a first gate insulating layer on the oxide semiconductor layer; an intermediate layer on the first gate insulating layer; a second gate insulating layer on the intermediate layer; and a gate wiring on the second gate insulating layer, the oxide semiconductor layer having a channel region and a conductive region, the first gate insulating layer overlapping the channel region and the conductive region, the intermediate layer and the second gate insulating layer overlapping the channel region and not overlapping the conductive region, and the gate wiring on the second gate insulating layer. The conductive region has a sheet resistance of 1000 [omega] / sq. Or less.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device. In particular, one embodiment of the present invention relates to a semiconductor device including an oxide semiconductor. Background Art

[0002] In recent years, oxide semiconductors have attracted attention as materials for semiconductor devices, replacing amorphous silicon, polycrystalline silicon, and single crystal silicon. In particular, as semiconductor devices including oxide semiconductors, the development of thin film transistors using oxide semiconductors as channels has been continuously advancing (for example, Patent Documents 1 to 6). Thin film transistors using oxide semiconductors as channels can be formed with simple structures and low-temperature processes in the same manner as semiconductor devices using amorphous silicon as channels. It is known that thin film transistors using oxide semiconductors as channels have higher field effect mobility than thin film transistors using amorphous silicon as channels.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-141338

[0006] Patent Document 2: Japanese Patent Application Publication No. 2014-099601

[0007] Patent Document 3: Japanese Patent Application Publication No. 2021-153196

[0008] Patent Document 4: Japanese Patent Application Publication No. 2018-006730

[0009] Patent Document 5: Japanese Patent Application Publication No. 2016-184771

[0010] Patent Document 6: Japanese Patent Application Publication No. 2021-108405 Summary of the invention

[0011] Problems to be solved by the invention

[0012] In the case of conventional thin film transistors using oxide semiconductors, impurity addition is sometimes used in the formation of source and drain regions. Specifically, by using ion implantation or the like to add impurity elements to a portion of an oxide semiconductor layer, oxygen defects can be intentionally generated inside the oxide semiconductor layer to achieve low resistance of the oxide semiconductor layer. Typically, impurities are added to the oxide semiconductor layer via a gate insulating layer.

[0013] In the case of forming the source region and the drain region by the above method, if the thickness of the gate insulating layer becomes thicker, it is necessary to increase the acceleration voltage during ion implantation by a corresponding amount. As a case where the thickness of the gate insulating layer becomes thicker, for example, the case of improving the gate resistance of the transistor (tolerance to high gate voltage) can be cited. However, if the acceleration voltage becomes higher, the burden on the ion implantation device becomes very large, and if the device performance is low, it is sometimes impossible to perform ion implantation with the necessary acceleration voltage. In this case, there may be concerns that the necessary amount of impurities cannot be added to the oxide semiconductor layer, and that the source region and drain region with sufficiently low resistance cannot be formed.

[0014] In response to the above problem, it is considered to use the gate electrode as a mask to half-etch the gate insulating layer to reduce the thickness of the portion of the gate insulating layer that overlaps the source region and the drain region. However, since the dry etching used in the half-etching of the gate insulating layer has poor in-plane uniformity, the thickness of the half-etched region sometimes varies from location to location, and the doping distribution during ion implantation may change. Such uneven doping distribution may cause uneven resistance values ​​in the source region and the drain region, as well as uneven conduction current of the thin film transistor.

[0015] One of the objects of the present invention is to improve the reliability of a semiconductor device including an oxide semiconductor while suppressing degradation of characteristics.

[0016] Means for solving problems

[0017] A semiconductor device according to one embodiment of the present invention includes: an oxide semiconductor layer having a polycrystalline structure on an insulating surface; a first gate insulating layer on the aforementioned oxide semiconductor layer; an intermediate layer on the aforementioned first gate insulating layer; a second gate insulating layer on the aforementioned intermediate layer; and a gate wiring on the aforementioned second gate insulating layer, wherein the aforementioned oxide semiconductor layer has a channel region and a conductive region, the aforementioned first gate insulating layer overlaps with the aforementioned channel region and the aforementioned conductive region, the aforementioned intermediate layer and the aforementioned second gate insulating layer overlap with the aforementioned channel region and do not overlap with the aforementioned conductive region, and the sheet resistance of the aforementioned conductive region is less than 1000Ω / sq.

[0018] A semiconductor device according to one embodiment of the present invention includes: an oxide semiconductor layer having a polycrystalline structure on an insulating surface; a first gate insulating layer on the oxide semiconductor layer; an intermediate layer on the first gate insulating layer; a second gate insulating layer on the intermediate layer; and a gate wiring on the second gate insulating layer, wherein the oxide semiconductor layer has a channel region and a conductive region, the first gate insulating layer overlaps with the channel region and the conductive region, the intermediate layer and the second gate insulating layer overlap with the channel region and do not overlap with the conductive region, and the etching rate of the oxide semiconductor layer when etching is performed at 40° C. using an etching solution containing phosphoric acid as a main component is less than 3 nm / min. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic cross-sectional view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0020] Figure 2 It is a schematic plan view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0021] Figure 3 This is a schematic enlarged cross-sectional view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0022] Figure 4 It is a flowchart showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0023] Figure 5 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0024] Figure 6 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0025] Figure 7 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0026] Figure 8 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0027] Fig. 9 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0028] Fig.10 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0029] Fig.11 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0030] Fig.12 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0031] Fig.13 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0032] Fig.14 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0033] Fig.15 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0034] Fig.16 It is a schematic cross-sectional view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0035] Fig.17 It is a schematic cross-sectional view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0036] Fig.18 It is a schematic plan view showing the overall structure of a display device according to one embodiment of the present invention.

[0037] Fig.19 It is a block diagram showing a circuit configuration of a display device according to one embodiment of the present invention.

[0038] Fig. 20 This is a circuit diagram showing the configuration of a pixel circuit of a display device according to one embodiment of the present invention.

[0039] Description of Reference Numerals

[0040] 10, 10a, 10b…semiconductor device; 20…display device; 21…pixel; 22…liquid crystal region; 24…sealing region; 26…terminal region; 100…substrate; 105…conductive layer; 110, 120…insulating layer; 125…metal oxide layer; 130…oxide semiconductor layer; 130a…channel region; 130b…conductive region; 140…first gate insulating layer; 142…metal oxide layer; 145…intermediate layer; 150, 152…second gate insulating layer; 152a, 152b…insulating layer; 160…gate wiring; 162…conductive layer; 165…anti- Etching mask; 170…insulating layer; 171, 173…contact hole; 180, 190…insulating layer; 200…source / drain wiring; 201…source wiring; 203…drain wiring; 300…array substrate; 301…pixel circuit; 302…source driving circuit; 303…gate driving circuit; 304…data signal line; 305…scanning signal line; 306…terminal portion; 307, 308…connecting wiring; 310…sealing portion; 311…liquid crystal element; 320…counter substrate; 330…flexible printed circuit (FPC) substrate; 340…IC chip; 350…holding capacitor DETAILED DESCRIPTION

[0041] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. The following disclosure is only an example. The configuration that can be easily thought of by those skilled in the art by appropriately changing the configuration of the embodiment while maintaining the gist of the invention is of course included in the scope of the present invention. With respect to the accompanying drawings, in order to make the description clearer, the width, thickness, shape, etc. of each part are sometimes schematically indicated compared to the actual method. However, the shape shown in the figure is only an example and does not limit the interpretation of the present invention. In this specification and each figure, the same figure mark is marked for the same elements as those previously described in relation to the figures that have appeared, and the detailed description is sometimes appropriately omitted.

[0042] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as up or above. Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as down or below. In this way, for the sake of convenience, the above or below phrases are used for explanation, but, for example, the up-and-down relationship between the substrate and the oxide semiconductor layer can also be configured in a manner opposite to that shown in the figure. In the following description, for example, the expression of the oxide semiconductor layer on the substrate is only used to illustrate the up-and-down relationship between the substrate and the oxide semiconductor layer as described above, and other components can also be configured between the substrate and the oxide semiconductor layer. Above or below refers to the stacking order in a structure with multiple layers stacked. In the case of the expression "the pixel electrode above the transistor", it can also be the positional relationship in which the transistor and the pixel electrode do not overlap when viewed from above. On the other hand, in the case of the expression "the pixel electrode vertically above the transistor", it refers to the positional relationship in which the transistor and the pixel electrode overlap when viewed from above.

[0043] A "display device" refers to a structure that uses an electro-optical layer to display an image. For example, a term such as a display device sometimes refers to a display panel that includes an electro-optical layer, or sometimes refers to a structure in which other optical components (for example, polarizing components, backlight sources, touch panels, etc.) are assembled on a display unit. As long as no technical contradiction arises, the "electro-optical layer" can include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer. Therefore, for the embodiments described later, a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer are exemplified as display devices for explanation, but the structure in this embodiment can be applied to a display device including the above-mentioned other electro-optical layers.

[0044] In this specification, unless otherwise specified, expressions such as “α includes A, B, or C”, “α includes any one of A, B, and C”, and “α includes one selected from the group consisting of A, B, and C” do not exclude the case where α includes a combination of multiple elements of A to C. In addition, the above expressions do not exclude the case where α includes other elements.

[0045] In this specification, the term "same" includes not only completely identical but also substantially identical. "Substantially identical" means that although not completely identical, they fall within a small range of differences that can be considered identical, for example, within an error range of ±5% (preferably ±3%).

[0046] <First embodiment>

[0047] A semiconductor device according to an embodiment of the present invention is described by taking a thin film transistor as an example. The semiconductor device according to the embodiment described below may be a thin film transistor used in an integrated circuit (IC) such as a microprocessor (MPU) or a memory circuit in addition to a thin film transistor used in a display device.

[0048] [Structure of semiconductor device]

[0049] The configuration of a semiconductor device 10 according to one embodiment of the present invention will be described. Figure 1 It is a schematic cross-sectional view showing the structure of a semiconductor device 10 according to one embodiment of the present invention. Figure 2 It is a schematic plan view showing the structure of a semiconductor device 10 according to one embodiment of the present invention. Figure 3 1 is a schematic enlarged cross-sectional view showing the structure of a semiconductor device 10 according to an embodiment of the present invention. Specifically, Figure 1 Corresponding to along Figure 2 This is a cross-sectional view taken along the dashed line AA' shown in FIG. Figure 3 Corresponding to Figure 1 FIG. 1 is an enlarged cross-sectional view of the vicinity of the end portion of the gate wiring 160 shown in FIG.

[0050] First, use Figure 1 The cross-sectional structure of the semiconductor device 10 is described. Figure 1 As shown, the semiconductor device 10 is provided on a substrate 100. The semiconductor device 10 includes a conductive layer 105, insulating layers 110 and 120, an oxide semiconductor layer 130, a first gate insulating layer 140, an intermediate layer 145, a second gate insulating layer 150, a gate wiring 160, insulating layers 170 to 190, a source wiring 201, and a drain wiring 203. When the source wiring 201 and the drain wiring 203 are not particularly distinguished, they are sometimes collectively referred to as a source / drain wiring 200.

[0051] The term "wiring" as used herein refers to a conductive layer that electrically connects elements, circuits, or elements and circuits. Wiring can also function as an electrode. For example, the portion of the gate wiring 160 that overlaps with the oxide semiconductor layer 130 functions as a gate electrode. In addition, the portions of the source wiring 201 and the drain wiring that are connected to the oxide semiconductor layer 130 function as a source electrode and a drain electrode, respectively.

[0052] The conductive layer 105 is provided on the substrate 100. The conductive layer 105 has a function as a light shielding film for the oxide semiconductor layer 130.

[0053] The insulating layers 110 and 120 are provided on the substrate 100 and the conductive layer 105. The insulating layer 110 has a function as a barrier film for shielding impurities diffusing from the substrate 100 to the oxide semiconductor layer 130. The insulating layer 120 functions as a base for the oxide semiconductor layer 130 disposed thereon.

[0054] The oxide semiconductor layer 130 is provided on the insulating layer 120. The oxide semiconductor layer 130 has a channel region 130a and a conductive region 130b arranged in a first direction. The channel region 130a is a region overlapping with the gate wiring 160 in the oxide semiconductor layer 130, and functions as a channel of the transistor. The conductive region 130b is a region called a source region or a drain region, and functions as a conductive layer connected to the source wiring 201 or the drain wiring 203. The conductive region 130b is a region having a lower resistance than the channel region 130a.

[0055] The first gate insulating layer 140 is provided on the oxide semiconductor layer 130. The first gate insulating layer 140 is a dielectric layer disposed between the oxide semiconductor layer 130 and the gate wiring 160. In this embodiment, a silicon oxide layer is used as the first gate insulating layer 140, but the present invention is not limited to this example.

[0056] The intermediate layer 145 is provided on the first gate insulating layer 140. The intermediate layer 145 functions as an etching stop layer when etching the second gate insulating layer 150. Therefore, the intermediate layer 145 can also be called an etching stop layer. As the intermediate layer 145, it is preferable to use a layer having an etching selectivity ratio of 10 or more (preferably 100 or more) relative to the second gate insulating layer 150. In this embodiment, as the intermediate layer 145, an oxide layer (for example, an aluminum oxide layer) or an oxide semiconductor layer (for example, IGZO) having aluminum as a main component is used, but it is not limited to this example.

[0057] The intermediate layer 145 can be set to any thickness as long as it functions as an etching stopper for the second gate insulating layer 150. When setting the thickness of the intermediate layer 145, it is sufficient to consider the thickness or etching rate of the second gate insulating layer 150, or the etchant (etching gas or etching solution) or etching conditions when etching the second gate insulating layer 150. However, the intermediate layer 145 functions as a part of the gate insulating layer of the semiconductor device 10, so it is ideal to make the thickness as thin as possible to suppress the influence on the electrical characteristics. In this embodiment, the thickness of the intermediate layer 145 is set to be greater than 5nm and less than 30nm (preferably greater than 10nm and less than 20nm).

[0058] As described later, the intermediate layer 145 is etched using the gate wiring 160 as a mask. Therefore, a portion of the first gate insulating layer 140 is not covered by the intermediate layer 145 and is exposed from the intermediate layer 145. In addition, the intermediate layer 145, the second gate insulating layer 150, and the gate wiring 160 have the same pattern shape. However, this example is not limited thereto, and the intermediate layer 145 may remain in a region that does not overlap with the gate wiring 160. In this case, the intermediate layer 145 inside the contact holes 171 and 173 described later is removed.

[0059] The second gate insulating layer 150 is provided on the intermediate layer 145. The second gate insulating layer 150 is a dielectric layer disposed between the intermediate layer 145 and the gate wiring 160. In this embodiment, a silicon oxide layer is used as the second gate insulating layer 150, but the present invention is not limited to this example.

[0060] The gate wiring 160 is opposite to the oxide semiconductor layer 130 via the first gate insulating layer 140, the intermediate layer 145, and the second gate insulating layer 150. That is, the first gate insulating layer 140, the intermediate layer 145, and the second gate insulating layer 150 are provided between the oxide semiconductor layer 130 and the gate wiring 160. The first gate insulating layer 140 is in contact with the oxide semiconductor layer 130. The intermediate layer 145 is in contact with the first gate insulating layer 140 and the second gate insulating layer 150. The second gate insulating layer 150 is in contact with the gate wiring 160. The gate wiring 160 has the function of serving as a top gate of the semiconductor device 10 and a light shielding film for the oxide semiconductor layer 130.

[0061] In this embodiment, the side surface of the gate wiring 160 is tilted, but the present invention is not limited to this example. By tilting the side surface of the gate wiring 160 to form a tapered shape, the generation of cracks in the insulating layer 170 formed on the gate wiring 160 and the poor coverage of the insulating layer 170 can be reduced.

[0062] The insulating layers 170 to 190 are provided on the first gate insulating layer 140 and the gate wiring 160. In this embodiment, the stacked structure composed of the insulating layers 170 to 190 is sometimes referred to as a passivation layer. The insulating layers 170 to 190 insulate the gate wiring 160 from the source / drain wiring 200. By providing the insulating layers 170 to 190, the parasitic capacitance between the gate wiring 160 and the source / drain wiring 200 can be reduced.

[0063] In this embodiment, a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer are used as the insulating layer 170, the insulating layer 180, and the insulating layer 190, respectively. The materials constituting the insulating layers 170 to 190 are not limited to this example, but as described later, it is desirable to have at least one insulating layer containing hydrogen. It should be noted that in this embodiment, by using a silicon oxide layer as the insulating layer 190, it functions as an etching stopper when patterning the source wiring 201 and the drain wiring 203.

[0064] like Figure 1 As shown, the insulating layer 170 constituting a portion of the passivation layer is in contact with the first gate insulating layer 140, the intermediate layer 145 (specifically, the side surface of the intermediate layer 145), the second gate insulating layer 150 (specifically, the side surface of the second gate insulating layer 150), and the gate wiring 160. Contact holes 171 and 173 reaching the oxide semiconductor layer 130 are provided in the insulating layers 170 to 190 and the first gate insulating layer 140.

[0065] The source wiring 201 is provided inside the contact hole 171 provided in the insulating layers 170 to 190 and the first gate insulating layer 140. The source wiring 201 is in contact with the oxide semiconductor layer 130 (specifically, the conductive region 130b) at the bottom of the contact hole 171. The drain wiring 203 is provided inside the contact hole 173 provided in the insulating layers 170 to 190 and the first gate insulating layer 140. The drain wiring 203 is in contact with the oxide semiconductor layer 130 (specifically, the conductive region 130b) at the bottom of the contact hole 173.

[0066] The operation of the semiconductor device 10 is mainly controlled by the gate voltage supplied to the gate wiring 160. An auxiliary voltage may also be supplied to the conductive layer 105. That is, the conductive layer 105 may also function as a gate wiring by supplying an auxiliary voltage. However, this example is not limited thereto, and the conductive layer 105 may also be used as a simple light shielding film. When the conductive layer 105 is used only as a light shielding film, the conductive layer 105 may be in a floating state without supplying a specific voltage.

[0067] In this embodiment, as the semiconductor device 10, a top-gate transistor having a gate wiring 160 above the oxide semiconductor layer 130 is exemplified, but the present invention is not limited to this configuration. For example, as the semiconductor device 10, a dual-gate transistor in which the conductive layer 105 is used as a gate wiring in addition to the gate wiring 160 can also be used. When the conductive layer 105 is used as a gate wiring, the insulating layers 110 and 120 function as gate insulating layers. However, the above configuration is only one embodiment, and the present invention is not limited to the above configuration.

[0068] Next, use Figure 2The planar structure of the semiconductor device 10 is described. Figure 2 As shown, the first direction (D1 direction) is the direction connecting the source wiring 201 and the drain wiring 203, corresponding to the direction of carrier migration. The length of the channel region 130a in the first direction in the oxide semiconductor layer 130 is the channel length (L), and the length of the channel region 130a in the second direction (D2 direction) is the channel width (W). It should be noted that the second direction is a direction intersecting the first direction. In this embodiment, the second direction represents a direction orthogonal to the first direction, but depending on the layout of the oxide semiconductor layer 130, the first direction and the second direction may not be orthogonal.

[0069] In this embodiment, the width of the conductive layer 105 in the first direction is wider than the width of the gate wiring 160. The reason for such a configuration is to effectively prevent external light from intruding into the channel region 130a. However, this example is not limited thereto, and the width of the conductive layer 105 may be the same as the width of the gate wiring 160.

[0070] Figure 2 2 illustrates a configuration in which the source / drain wiring 200 does not overlap with the conductive layer 105 and the gate wiring 160 in a plan view, but the present invention is not limited to this configuration. For example, the source / drain wiring 200 may overlap with at least one of the conductive layer 105 and the gate wiring 160 in a plan view. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0071] [Material of each layer of semiconductor device]

[0072] The substrate 100 can support each layer constituting the semiconductor device 10. As the substrate 100, for example, a glass substrate, a quartz substrate, or a sapphire substrate, etc., a rigid substrate having light transparency can be used. In addition, as the substrate, a silicon substrate, etc., a rigid substrate having no light transparency can also be used. In addition, as the substrate, a polyimide resin substrate, an acrylic resin substrate, a siloxane resin substrate, or a fluororesin substrate, etc., a flexible substrate having light transparency can be used. Impurities can also be introduced into the above-mentioned resin substrate in order to improve the heat resistance of the substrate 100. It should be noted that a substrate having a silicon oxide film or a silicon nitride film formed on the above-mentioned rigid substrate or flexible substrate can also be used as the substrate 100.

[0073] The conductive layer 105 can reflect or absorb external light. As described above, the conductive layer 105 has an area larger than the channel region 130a of the oxide semiconductor layer 130, and thus can shield the external light incident on the channel region 130a. As the conductive layer 105, for example, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W), or an alloy or compound thereof can be used. In addition, when conductivity is not required, a resin layer composed of a black resin or the like can be used instead of the conductive layer 105. The conductive layer 105 can be a single-layer structure or a stacked structure.

[0074] The insulating layers 110, 120, 170 to 190 have a function of preventing impurities from diffusing into the oxide semiconductor layer 130. The insulating layers 110, 120, 170 to 190 may have a single layer structure or a stacked structure. As the insulating layers 110, 120, 170 to 190, for example, silicon oxide (SiOx), silicon nitride oxide (SiOxNy), silicon nitride (SiNx), silicon nitride oxide (SiNxOy), aluminum oxide (AlOx), aluminum nitride oxide (AlOxNy), aluminum nitride oxide (AlNxOy), aluminum nitride (AlNx), etc. may be used. Here, silicon nitride oxide (SiOxNy) and aluminum nitride oxide (AlOxNy) are respectively a silicon compound and an aluminum compound containing nitrogen (N) at a ratio (x>y) less than oxygen (O). Silicon nitride oxide (SiNxOy) and aluminum nitride oxide (AlNxOy) are silicon compounds and aluminum compounds containing oxygen at a ratio (x>y) less than nitrogen. In this embodiment, silicon nitride (SiNx) is used as the insulating layers 110 and 180, and silicon oxide (SiOx) is used as the insulating layers 120, 170, and 190.

[0075] In this embodiment, the oxide semiconductor layer 130 has a polycrystalline structure. That is, the oxide semiconductor layer 130 of this embodiment is composed of an oxide semiconductor formed using the Poly-OS technology. The so-called Poly-OS technology refers to a technology for forming an oxide semiconductor layer having a polycrystalline structure. As the oxide semiconductor layer 130, a metal oxide having semiconductor properties can be used. For example, as the oxide semiconductor layer 130, an oxide semiconductor containing two or more metals including indium (In) can be used. As the oxide semiconductor layer 130, other elements other than the above can also be used. For example, as the oxide semiconductor layer 130, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium oxide (Zr), and lanthanide elements can also be used on the basis of indium.

[0076] The ratio of indium to the oxide semiconductor layer 130 as a whole is preferably 50% or more. If the ratio of indium increases, the oxide semiconductor layer 130 is easily crystallized. In addition, as a metal element other than indium, gallium is preferably included. Gallium and indium belong to the same Group 13 element. Therefore, the crystallinity of the oxide semiconductor layer 130 is hardly damaged by gallium.

[0077] In the oxide semiconductor layer 130 of this embodiment, the ratio of indium is 50% or more, so oxygen defects are easily formed. On the other hand, a crystalline oxide semiconductor is less likely to form oxygen defects than an amorphous oxide semiconductor. Therefore, the oxide semiconductor layer 130 has an advantage that oxygen defects are not easily formed even if the ratio of indium is 50% or more.

[0078] The first gate insulating layer 140 includes an insulating oxide. Specifically, as the first gate insulating layer 140, silicon oxide (SiOx), silicon nitride oxide (SiOxNy), aluminum oxide (AlOx), aluminum nitride oxide (AlOxNy), etc. can be used. The first gate insulating layer 140 preferably has a composition close to a stoichiometric ratio. In addition, the first gate insulating layer 140 preferably has few defects. For example, as the first gate insulating layer 140, an oxide in which no defects are observed when evaluated by an electron spin resonance method (ESR) can also be used.

[0079] As described later, in this embodiment, impurities are added (ion implantation) to the oxide semiconductor layer 130 via the first gate insulating layer 140. At this time, in order to control the acceleration voltage during ion implantation to be relatively low, the thickness of the first gate insulating layer 140 is preferably thin. On the other hand, assuming that the intermediate layer 145 located above the channel region 130a has a fixed charge, in order to suppress the adverse effects caused by the fixed charge, the intermediate layer 145 is as far away from the channel region 130a as possible. From this point of view, the thickness of the first gate insulating layer 140 is preferably as thick as possible. Taking the above into consideration, it can also be said that it is ideal to set the thickness of the first gate insulating layer 140 to be greater than 50nm and less than 150nm (preferably greater than 70nm and less than 100nm). In this embodiment, a silicon oxide layer with a thickness of 100nm is used as the first gate insulating layer 140.

[0080] The intermediate layer 145 can use an insulating oxide or oxide semiconductor. As described above, the intermediate layer 145 only needs to be a layer that functions as an etching stopper for the second gate insulating layer 150. The thickness of the intermediate layer 145 is preferably thinner than the thickness of the first gate insulating layer 140. In addition, the thickness of the intermediate layer 145 can be thinner than the thickness of the oxide semiconductor layer 130. As described above, the thickness of the intermediate layer 145 can be set to be greater than 5nm and less than 30nm (preferably greater than 10nm and less than 20nm).

[0081] When the intermediate layer 145 is an insulating layer (e.g., an aluminum oxide layer), the intermediate layer 145 is located between the oxide semiconductor layer 130 and the gate wiring 160, and thus functions as a part of the gate insulating layer. Therefore, when determining the device parameters of the semiconductor device 10, the thickness and dielectric constant of each of the first gate insulating layer 140, the intermediate layer 145, and the second gate insulating layer 150 need to be considered.

[0082] As a material constituting the intermediate layer 145, aluminum oxide (AlOx), aluminum nitride oxide (AlOxNy), or an oxide semiconductor (OS) can be used, but the present invention is not limited to these examples. As the oxide semiconductor, for example, a metal oxide such as IGZO can be used.

[0083] The second gate insulating layer 150 includes an insulating oxide. Specifically, as the second gate insulating layer 150, silicon oxide (SiOx), silicon nitride oxide (SiOxNy), silicon nitride (SiNx), etc. can be used. The second gate insulating layer 150 can use the same insulating layer as the first gate insulating layer 140. The thickness of the second gate insulating layer 150 can be set to be greater than 100nm and less than 250nm. In this embodiment, as the second gate insulating layer 150, a silicon oxide layer with a thickness of 200nm is used. It is ideal that the thickness of the second gate insulating layer 150 is 1.2 times or more (preferably 1.5 times or more) the thickness of the first gate insulating layer 140.

[0084] The gate wiring 160, the source wiring 201, and the drain wiring 203 are conductive. For example, copper (Cu), silver (Ag), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or alloys or compounds thereof can be used for the gate wiring 160, the source wiring 201, and the drain wiring 203. Each of the gate wiring 160, the source wiring 201, and the drain wiring 203 may have a single-layer structure or a stacked structure.

[0085] (Configuration near the end of the gate wiring)

[0086] use Figure 3 The structure near the end of the gate wiring 160 will be described. Figure 3 As shown, the oxide semiconductor layer 130 is divided into a channel region 130a and a conductive region 130b. The channel region 130a is a region of the oxide semiconductor layer 130 located vertically below the gate wiring 160, that is, a region overlapping the gate wiring 160. The conductive region 130b is a region of the oxide semiconductor layer 130 that does not overlap the gate wiring 160.

[0087] like Figure 3 As shown, the intermediate layer 145 overlaps with the second gate insulating layer 150 and the gate wiring 160, and has the same pattern shape as the second gate insulating layer 150 and the gate wiring 160. That is, the intermediate layer 145 and the second gate insulating layer 150 do not overlap with the conductive region 130b. In addition, in this embodiment, the thickness (T2) of the second gate insulating layer 150 is thicker than the thickness (T1) of the first gate insulating layer 140. In addition, the thickness (T3) of the intermediate layer 145 is thinner than the thickness (T1) of the first gate insulating layer 140 and the thickness (T2) of the second gate insulating layer 150.

[0088] Thus, in the semiconductor device 10 of the present embodiment, the first gate insulating layer 140, the intermediate layer 145, and the second gate insulating layer 150 are located between the oxide semiconductor layer 130 and the gate wiring 160. That is, the gate insulating layer of the semiconductor device 10 is composed of the first gate insulating layer 140, the intermediate layer 145, and the second gate insulating layer 150. In contrast, above the conductive region 130b, the first gate insulating layer 140 is arranged but the intermediate layer 145 and the second gate insulating layer 150 are not arranged. As a result, the thickness of the substantial gate insulating layer as a whole can be thickened, while the thickness of the gate insulating layer arranged above the conductive region 130b can be thinned.

[0089] As described above, according to the present embodiment, in the impurity addition process described later, impurities can be added to the conductive region 130b only via the first gate insulating layer 140. Therefore, for example, even if the acceleration voltage of the ion implantation device is not set high, the resistivity of the conductive region 130b can be sufficiently reduced. In addition, the thickness of the substantial gate insulating layer between the oxide semiconductor layer 130 and the gate wiring 160 can be thickened, so the resistance to the gate voltage of the semiconductor device 10 can be improved. As a result, it is possible to suppress characteristic degradation and improve the reliability of the semiconductor device 10 including the oxide semiconductor.

[0090] [Method for manufacturing semiconductor device]

[0091] Next, a method for manufacturing the semiconductor device 10 according to one embodiment of the present invention will be described. Figure 4 It is a flowchart showing a method for manufacturing the semiconductor device 10 according to one embodiment of the present invention. Figure 5 to Figure 15 It is a schematic cross-sectional view showing a method for manufacturing the semiconductor device 10 according to one embodiment of the present invention.

[0092] like Figure 4 and Figure 5 As shown, a conductive layer 105 is formed on the substrate 100 as a light shielding layer, and insulating layers 110 and 120 are formed on the conductive layer 105 ( Figure 4As the insulating layer 110, for example, a silicon nitride layer is formed. As the insulating layer 120, for example, a silicon oxide layer is formed. The insulating layers 110 and 120 are formed by a CVD (Chemical Vapor Deposition) method. In this specification, forming a film on a substrate by a sputtering method, a CVD method, or the like is referred to as "forming a thin film", which is used in the same meaning as the expression "forming a film as a thin film".

[0093] By using a silicon nitride layer as the insulating layer 110, the insulating layer 110 can block, for example, impurities diffusing from the substrate 100 side toward the oxide semiconductor layer 130. The silicon oxide layer used as the insulating layer 120 may include silicon oxide having a property of releasing oxygen by heat treatment.

[0094] In this embodiment, when the insulating layers 110 and 120 are formed, the film forming temperature is set to 350°C. In particular, the insulating layer 120 (i.e., the silicon oxide layer) can increase the oxygen content by setting the film forming temperature to a lower level. As described later, by increasing the amount of oxygen contained in the insulating layer 120, the amount of hydrogen diffused into the oxide semiconductor layer 130 can be reduced. It should be noted that the film forming temperature of the insulating layers 110 and 120 can be set to 250°C to 500°C (preferably 300°C to 450°C, more preferably 325°C to 400°C).

[0095] Then, if Figure 4 and Figure 6 As shown, a patterned oxide semiconductor layer 130 ( Figure 4 In the present embodiment, the process of forming the oxide semiconductor layer 130 is referred to as "OS patterning". That is, the oxide semiconductor layer 130 is formed by patterning the oxide semiconductor layer formed on the insulating layer 120. In the description of the present embodiment, when the "oxide semiconductor layer" is recorded without the reference numerals, it refers to the oxide semiconductor layer in the formed state (that is, the unprocessed state).

[0096] The oxide semiconductor layer may be etched by wet etching or dry etching. For example, an acidic etchant (oxalic acid or hydrofluoric acid) may be used for wet etching.

[0097] In this embodiment, the oxide semiconductor layer is formed by sputtering. In particular, the oxide semiconductor layer is formed by sputtering using a target formed of a crystalline oxide semiconductor. As described above, the oxide semiconductor layer is composed of a metal oxide with an indium ratio of 50% or more. The thickness of the formed oxide semiconductor layer is, for example, from 10 nm to 100 nm, from 15 nm to 70 nm, or from 15 nm to 40 nm. The oxide semiconductor layer of this embodiment is amorphous in the film-formed state. That is, the oxide semiconductor layer 130 before the heat treatment (OS annealing) described later (that is, the oxide semiconductor layer 130 just after patterning) is amorphous.

[0098] When the oxide semiconductor layer 130 is crystallized by the OS annealing described later, the oxide semiconductor layer 130 is preferably amorphous (a state in which the crystal component of the oxide semiconductor is small) from the formation based on the sputtering method to the implementation of the OS annealing. That is, the film formation conditions of the oxide semiconductor layer are preferably conditions in which the oxide semiconductor layer does not crystallize as much as possible immediately after the film formation. For example, in the case of forming an oxide semiconductor layer by sputtering, it is ideal to form the oxide semiconductor layer while controlling the temperature of the object to be formed (including the substrate 100 and the structure formed thereon). It should be noted that although the object to which the temperature control is actually applied is the object to be formed, since the structure formed on the substrate 100 is very thin, it can be regarded as essentially controlling the temperature of the substrate 100. Therefore, in the following description, the object to be formed is sometimes referred to as a "substrate".

[0099] When a thin film is formed (filmed) on a substrate by sputtering, ions generated in plasma and atoms rebounded by a sputtering target collide with an object to be formed (specifically, a structure formed on the substrate 100), so the temperature of the substrate rises during the thin film formation process. If the temperature of the substrate rises during the thin film formation process, the oxide semiconductor layer will contain microcrystals in the state just after the formation, and the subsequent crystallization by OS annealing will be hindered.

[0100] In order to control the temperature of the substrate when forming the oxide semiconductor layer (i.e., the film forming temperature), for example, the thin film formation can be performed while cooling the substrate. For example, the substrate can be cooled from the surface opposite to the formed surface in such a manner that the film forming temperature is below 100°C, below 70°C, below 50°C, or below 30°C. In particular, the film forming temperature of the oxide semiconductor layer of the present embodiment is preferably below 50°C. In the present embodiment, the formation of the oxide semiconductor layer is performed at a film forming temperature below 50°C, and the OS annealing described later is performed at a heating temperature above 400°C. Thus, in the present embodiment, the difference between the temperature when the oxide semiconductor layer is formed and the temperature when the oxide semiconductor layer 130 is OS annealed is preferably above 350°C. By forming the oxide semiconductor layer while cooling the substrate, an oxide semiconductor layer with a small amount of crystal components in the state just after formation can be obtained.

[0101] In addition, it is preferred that the oxygen partial pressure in the chamber during film formation is 1% to 10%, preferably 1% to 5%, and further preferably 2% to 4%. If the oxygen partial pressure is high, microcrystals are generated in the oxide semiconductor layer due to the excess oxygen contained in the oxide semiconductor. On the other hand, when the oxygen partial pressure is less than 1%, the composition of oxygen in the oxide semiconductor layer becomes uneven, and there is a possibility that an oxide semiconductor layer containing a large number of microcrystals or an oxide semiconductor layer that does not crystallize even after heat treatment may be formed.

[0102] Next, after the oxide semiconductor layer 130 is formed by patterning, the oxide semiconductor layer 130 is subjected to heat treatment (OS annealing) ( Figure 4 Step S1003). In the OS annealing, the oxide semiconductor layer 130 is heat-treated in an air atmosphere at a temperature of 250°C to 500°C (preferably 300°C to 500°C, and more preferably 350°C to 450°C), so that the amorphous oxide semiconductor layer 130 is crystallized. The heating atmosphere is not limited to the air atmosphere, and is preferably an oxidizing atmosphere (an atmosphere containing oxygen). In addition, the oxidizing atmosphere is more preferably a humid atmosphere (specifically, a humid air atmosphere). In addition, the treatment time of the heat treatment is 15 minutes to 120 minutes, or 30 minutes to 60 minutes after reaching the specified temperature. In this embodiment, the temperature of the OS annealing is set to 350°C.

[0103] In this embodiment, the substrate on which the oxide semiconductor layer 130 is formed is placed in a heating furnace having a heating medium (for example, a support plate) which is maintained at a set temperature in advance (250° C. to 500° C., 350° C. in this embodiment). The support plate as a heating medium has the function of supporting the substrate and heating the substrate and the film (including the oxide semiconductor layer 130) formed on the substrate. If the substrate on which the oxide semiconductor layer 130 is formed is placed on the support plate, the oxide semiconductor layer 130 is quickly heated. When the substrate is placed in the heating furnace, it is ideal to control the temperature drop of the support plate to within 15%, within 10%, or within 5% of the set temperature. That is, it is preferred to control the temperature of the support plate in such a way that the oxide semiconductor layer 130 reaches the set temperature in as short a time as possible.

[0104] As described above, in this embodiment, after the oxide semiconductor layer is patterned to form the oxide semiconductor layer 130, a crystallization process of the oxide semiconductor layer 130 is performed. This is because the etching resistance of the oxide semiconductor layer used in this embodiment is greatly improved by crystallization. That is, in this embodiment, the oxide semiconductor layer 130 after OS annealing shows very high etching resistance to the etchant (etching solution, etching gas), so the patterning of the oxide semiconductor layer is performed in advance before OS annealing. The etching resistance of the oxide semiconductor layer used in this embodiment will be described later.

[0105] Then, if Figure 4 and Figure 7 As shown, a first gate insulating layer 140 and a metal oxide layer 142 are formed ( Figure 4 Step S1004). As the first gate insulating layer 140, for example, a silicon oxide layer is formed. The first gate insulating layer 140 is formed by a CVD method. As the first gate insulating layer 140, it is ideal to form an insulating layer with as few defects as possible. In the present embodiment, the film forming temperature of the first gate insulating layer 140 is set to 350°C. The thickness of the first gate insulating layer 140 is, for example, not less than 50nm and not more than 150nm, not less than 60nm and not more than 150nm, or not less than 100nm and not more than 120nm. In the present embodiment, the thickness of the first gate insulating layer 140 is set to 100nm.

[0106] The metal oxide layer 142 is formed by a sputtering method. By using a sputtering method in the film formation of the metal oxide layer 142. Oxygen is injected into the first gate insulating layer 140 when the metal oxide layer 142 is formed. Therefore, a large amount of oxygen is contained in the first gate insulating layer 140 after the metal oxide layer 142 is formed. The thickness of the metal oxide layer 142 is, for example, 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 142. As described above, aluminum oxide has a high barrier property to gas, so during the heat treatment described later, it is possible to suppress the oxygen injected into the first gate insulating layer 140 from diffusing upward.

[0107] When the metal oxide layer 142 is formed by sputtering, the process gas used for sputtering may remain in the film of the metal oxide layer 142. For example, when Ar is used as the process gas for sputtering, Ar may remain in the film of the metal oxide layer 142. The remaining Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the metal oxide layer 142, etc.

[0108] Next, in a state where the metal oxide layer 142 is formed on the first gate insulating layer 140, a heat treatment (oxidation annealing) is performed to supply oxygen to the oxide semiconductor layer 130 ( Figure 4 In the process from forming the oxide semiconductor layer 130 to forming the first gate insulating layer 140 on the oxide semiconductor layer 130, oxygen defects may be generated on the upper surface and side surfaces of the oxide semiconductor layer 130. By oxidation annealing, oxygen released from the insulating layer 120 and the first gate insulating layer 140 is supplied to the oxide semiconductor layer 130, and the oxygen defects are repaired. The oxidation annealing can be performed at a temperature of 250°C to 500°C (preferably 300°C to 500°C, more preferably 350°C to 450°C). In this embodiment, the oxidation annealing is performed at a temperature of 350°C.

[0109] Oxygen released from the insulating layer 120 and the first gate insulating layer 140 by the oxidation annealing is supplied to the oxide semiconductor layer 130. Hydrogen may be released from the insulating layer 110 by the oxidation annealing, but most of the released hydrogen is captured by oxygen contained in the insulating layer 120 before reaching the oxide semiconductor layer 130.

[0110] As described above, oxygen can be supplied to the oxide semiconductor layer 130 by oxidation annealing. During oxidation annealing, the upward diffusion of oxygen injected into the first gate insulating layer 140 is blocked by the metal oxide layer 142, thereby suppressing its release into the atmosphere. Therefore, oxygen can be efficiently supplied to the oxide semiconductor layer 130 during oxidation annealing.

[0111] Then, if Figure 4 and Figure 8 As shown, after the oxidation annealing, the metal oxide layer 142 is etched to remove it ( Figure 4 The etching of the metal oxide layer 142 may be wet etching or dry etching. For example, diluted hydrofluoric acid (DHF) is used in wet etching.

[0112] Next, an intermediate layer 145, a second gate insulating layer 150, and a conductive layer 162 are formed on the first gate insulating layer 140 ( Figure 4 Step S1007). The intermediate layer 145 is formed by a CVD method or a sputtering method. In this embodiment, an aluminum oxide layer with a thickness of 10 nm is formed as the intermediate layer 145. The conductive layer 162 is formed by a sputtering method. In this embodiment, an alloy composed of molybdenum and tungsten is used as the conductive layer 162, but the present invention is not limited to this example. The conductive layer 162 is a conductive layer for forming the aforementioned gate wiring 160.

[0113] Then, if Figure 4 and Fig. 9 As shown, the conductive layer 162 is patterned to form a gate wiring 160 ( Figure 4 Specifically, a resist mask 165 is formed on the conductive layer 162, and the conductive layer 162 is etched using the resist mask 165 as a mask, thereby forming the gate wiring 160. In this embodiment, the conductive layer 162 is an alloy layer composed of molybdenum and tungsten, so the conductive layer 162 can be etched by dry etching using sulfur hexafluoride (SF6) as an etching gas.

[0114] Then, if Figure 4 and Fig.10 As shown, the second gate insulating layer 150 is etched using the resist mask 165 as a mask ( Figure 4 As described above, in this embodiment, the second gate insulating layer 150 is a silicon oxide layer, and the intermediate layer 145 is an aluminum oxide layer. Therefore, similarly to the formation of the gate wiring 160, the etching of the second gate insulating layer 150 can be performed by dry etching using sulfur hexafluoride (SF6) as an etching gas. That is, in this embodiment, the formation of the gate wiring 160 and the etching of the second gate insulating layer 150 can be performed continuously using the same etching gas.

[0115] In addition, the aluminum oxide layer configured as the intermediate layer 145 is hardly etched in dry etching using sulfur hexafluoride (SF6) as an etching gas. That is, in this embodiment, if the second gate insulating layer 150 is etched and the intermediate layer 145 is exposed, at this point in time, the intermediate layer 145 functions as an etching stopper layer and the etching stops.

[0116] Then, if Figure 4 and Fig.11 As shown, the intermediate layer 145 is etched using the resist mask 165 as a mask ( Figure 4 Step S1010). In the present embodiment, the intermediate layer 145 is an aluminum oxide layer, and thus the intermediate layer 145 can be etched using, for example, wet etching using diluted hydrofluoric acid (DHF). If the intermediate layer 145 is removed by etching, a portion of the first gate insulating layer 140 (the portion that does not overlap with the gate wiring 160) is exposed. In the present embodiment, the thickness of the intermediate layer 145 is 10 nm, and thus the intermediate layer 145 that is not masked by the resist mask 165 can be removed with almost no effect on the thickness of the first gate insulating layer 140. It should be noted that, in the present embodiment, the resist mask 165 is used as a mask, but the etching process of the intermediate layer 145 can also be performed using the gate wiring 160 as a mask after removing the resist mask 165.

[0117] Then, if Figure 4 and Fig.12 As shown, ion implantation is performed from above the gate wiring 160 and the intermediate layer 145 to add impurities ( Figure 4 As the impurity, phosphorus, boron, argon, etc. can be used. The purpose of adding impurities is to form oxygen defects in a part of the oxide semiconductor layer 130 to improve conductivity, so as the impurity, it is preferable to use an element with a large atomic radius.

[0118] This embodiment shows an example of adding impurities by ion implantation, but ion doping may also be used. In this embodiment, boron is added by ion implantation. The conditions for ion implantation in this embodiment are an acceleration voltage of 30 keV and a dose of 1×10 15 / cm 2 In this embodiment, only the first gate insulating layer 140 exists above the region where the conductive region 130 b is formed, so that even if the acceleration voltage is 30 keV, impurities can be added to the oxide semiconductor layer 130 at a sufficient concentration.

[0119] In this embodiment, an example of performing ion implantation with the resist mask 165 remaining is shown, but in the above-mentioned Fig.11When the resist mask 165 is removed by a process, ion implantation can also be performed using the gate wiring 160 as a mask. Figure 4 In the example of performing ion implantation after removing the intermediate layer 145 in step S1010, ion implantation can also be performed with the intermediate layer 145 remaining. However, the intermediate layer 145 also needs to be etched when forming the contact holes 171 and 173 described later, so it is ideal to remove it in advance before ion implantation.

[0120] like Fig.12 As shown, if ion implantation of impurities into the oxide semiconductor layer 130 is performed, a conductive region 130b is formed in the oxide semiconductor layer 130. At this time, the region in which the impurities are not implanted and maintains the original state functions as the channel region 130a. The concentration of the impurities added to the conductive region 130b is relatively higher than the concentration of the impurities added to the channel region 130a. Here, the "concentration of impurities" can be expressed as the number of impurities per unit volume. The so-called high concentration of impurities in the oxide semiconductor layer 130 means that the number of oxygen defects per unit volume is large, or the number of defects per unit volume is large.

[0121] In addition, the so-called high concentration of impurities in the oxide semiconductor layer 130 means that the conductivity of the conductive region 130b is higher than the conductivity of the channel region 130a. In other words, the resistivity of the conductive region 130b is lower than the resistivity of the channel region 130a. In other words, the sheet resistance of the conductive region 130b is lower than the sheet resistance of the channel region 130a.

[0122] As mentioned above, through Fig.12 The conductive region 130b formed in step S1011 shown in FIG. 1 functions as a source region and a drain region of the semiconductor device 10. If the oxide semiconductor layer 130 of the present embodiment has low resistance due to the introduction of oxygen defects, the resistance value is significantly reduced compared to the conventional oxide semiconductor layer. Specifically, the resistance value (sheet resistance) of the conductive region 130b in the oxide semiconductor layer 130 of the present embodiment is 1000Ω / sq. or less (preferably 500Ω / sq. or less, and more preferably 250Ω / sq. or less).

[0123] It should be noted that, in this embodiment, an example of configuring the conductive region 130b adjacent to the channel region 130a is shown, but the present invention is not limited to this example. For example, a so-called LDD region may be configured between the channel region 130a and the conductive region 130b. The so-called LDD region is a region having a lower conductivity than the channel region 130a and a higher conductivity than the conductive region 130b.

[0124] Then, if Figure 4 and Fig.13As shown, insulating layers 170 to 190 are formed on the first gate insulating layer 140 and the gate wiring 160 as passivation layers ( Figure 4 Step S1012). The insulating layers 170 to 190 are formed by a CVD method. In the present embodiment, as the insulating layers 170 to 190, a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer are formed, respectively. The film forming temperature of the insulating layers 170 to 190 is preferably set to be between 250°C and 500°C (preferably between 300°C and 450°C, and further preferably between 325°C and 400°C). In the present embodiment, the film forming temperature of the insulating layers 170 to 190 is set to 350°C. The thickness of the insulating layers 170 to 190 may be set to be between 30nm and 500nm. In the present embodiment, the thickness of the insulating layers 170 to 190 is set to 100nm, 300nm, and 30nm, respectively. However, the composition of the passivation layer is not limited to the above examples. For example, the passivation layer may be a single-layer structure or a two-layer structure, or may be a stacked structure of four or more layers. In addition, the insulating layer used for the passivation layer can be any insulating layer selected from silicon oxide (SiOx), silicon nitride (SiNx), silicon nitride oxide (SiOxNy), or silicon nitride oxide (SiOxNy).

[0125] The insulating layers 170 to 190 function as a passivation layer (protective layer) for preventing gas and moisture from entering from the outside. In addition, as described above, they also have the function of insulating and separating the gate wiring 160 from the source / drain wiring 200. In addition, in this embodiment, a silicon nitride layer is used as the insulating layer 180, so that the conductive region 130b of the oxide semiconductor layer 130 can be made less resistant.

[0126] When the silicon nitride layer is formed by the CVD method, ammonia is used as a raw material gas, so the insulating layer 180 contains a large amount of hydrogen. Therefore, by heating the insulating layer 180 when and after the insulating layer 180 is formed, hydrogen diffuses from the insulating layer 180. The diffused hydrogen reaches the oxide semiconductor layer 130 via the first gate insulating layer 140 and the insulating layer 170. At this time, hydrogen is captured by the oxygen vacancies in the conductive region 130b formed by the above-mentioned ion implantation, forming a donor energy level. As a result, the low resistance of the conductive region 130b is promoted.

[0127] Then, if Figure 4 and Fig.14 As shown, contact holes 171 and 173 are formed in the first gate insulating layer 140 and the insulating layers 170 to 190 ( Figure 4 The contact holes 171 and 173 expose a portion of the conductive region 130b.

[0128] Finally, if Figure 4 and Fig.15As shown in FIG. 1 , source / drain wiring 200 ( Figure 4 Step S1014). The above-described process completes Figure 1 The semiconductor device 10 is shown in FIG.

[0129] In the semiconductor device 10 manufactured by the manufacturing method of this embodiment, a field effect mobility of 20 cm-1 can be obtained within the range of 1 μm to 4 μm in the channel length L of the channel region 130 a and 2 μm to 25 μm in the channel width of the channel region 130 a. 2 / Vs or above, 25cm 2 / Vs or above, or 30cm 2 The so-called "field effect mobility" in this embodiment is the field effect mobility in the saturation region of the semiconductor device 10, which means the maximum value of the field effect mobility in the region where the potential difference (Vd) between the source wiring 201 and the drain wiring 203 is greater than the value (Vg-Vth) obtained by subtracting the threshold voltage (Vth) of the semiconductor device 10 from the voltage (Vg) supplied to the gate wiring 160.

[0130] (Etching Resistance of Oxide Semiconductor Layer)

[0131] As described above, the oxide semiconductor layer used in the semiconductor device 10 of this embodiment has excellent etching resistance. Specifically, the oxide semiconductor layer of this embodiment is hardly etched by an etchant (etching solution) for wet etching, and the etching rate is very low.

[0132] Specifically, when the oxide semiconductor layer of this embodiment is etched using an etching solution containing phosphoric acid as a main component (for example, a mixed acid etching solution, etc.) within a temperature range of not less than 35°C and not more than 45°C (for example, a range including an error of ±5°C for a set temperature of 40°C), the etching rate is less than 3nm / min, less than 2nm / min, or less than 1nm / min. The proportion of phosphoric acid in the etching solution is not less than 50%, not less than 60%, or not less than 70%. In addition to phosphoric acid, the etching solution may also contain nitric acid and acetic acid. In contrast, the etching rate of the oxide semiconductor layer with an amorphous structure of this embodiment (oxide semiconductor layer before OS annealing) when etched using the above-mentioned etching solution within a temperature range of not less than 35°C and not more than 45°C is not less than 100nm / min.

[0133] In addition, when the oxide semiconductor layer of this embodiment is etched using an etching solution containing hydrogen fluoride (for example, a hydrofluoric acid solution) at room temperature (here, "25°C ± 5°C"), the etching rate is less than 5 nm / min, less than 4 nm / min, or less than 3 nm / min. The proportion of hydrogen fluoride in the etching solution is 0.5%. In contrast, when the oxide semiconductor layer having an amorphous structure of this embodiment is etched using the above etching solution at room temperature, the etching rate is 15 nm / min or more.

[0134] Here, the etching rates of various oxide semiconductor layers are shown in Table 1. Table 1 shows the etching rates of each manufactured sample in a mixed acid etching solution and a 0.5% hydrofluoric acid solution. As a mixed acid etching solution, "Mixed Acid AT-2F (product name)" of Rasa Industries, LTD was used. The proportion of phosphoric acid in the mixed acid etching solution is about 65%. In addition, the temperature of the mixed acid etching solution when etching each sample is set to 40°C, and the temperature of the 0.5% hydrofluoric acid solution is set to 22°C. In Table 1, Sample 1 is an oxide semiconductor layer having a polycrystalline structure of the present embodiment, Sample 2 is an oxide semiconductor layer having an amorphous structure of the present embodiment, and Sample 3 is an oxide semiconductor layer of indium gallium zinc oxide (IGZO) containing less than 50% indium.

[0135] [Table 1]

[0136] Mixed acid etching solution 0.5% hydrofluoric acid solution Sample 1 <0.1nm / min <2nm / min Sample 2 111nm / min >18nm / min Sample 3 162nm / min -

[0137] As shown in Table 1, sample 1 is hardly etched even when using a mixed acid etching solution, and is only etched at about 2 nm / min even when using a 0.5% hydrofluoric acid solution. The etching rate of sample 1 is less than 1 / 100 of the etching rate of sample 2 in a mixed acid etching solution, and about 1 / 10 of the etching rate in a 0.5% hydrofluoric acid solution. In addition, the etching rate of sample 1 is less than 1 / 100 of the etching rate of sample 3 in a mixed acid etching solution. It can be seen that sample 1 has significantly superior etching resistance compared to samples 2 and 3.

[0138] The excellent etching resistance of the oxide semiconductor layer of this embodiment is a property that cannot be obtained by the oxide semiconductor layer with a polycrystalline structure in the past produced by a process below 500° C. The detailed mechanism has not yet been clarified, but such excellent etching resistance can be said to be evidence that the oxide semiconductor layer of this embodiment has a polycrystalline structure different from the past.

[0139] <Second embodiment>

[0140] In this embodiment, an example in which the configuration of the second gate insulating layer is different from that of the first embodiment is described. Specifically, in this embodiment, the second gate insulating layer 152 has a stacked structure. In the description of this embodiment, the same reference numerals are used in the drawings for the parts common to the first embodiment, and the description is focused on the parts different from the first embodiment.

[0141] The configuration of a semiconductor device 10 a according to one embodiment of the present invention will be described. Fig.16 Schematic cross-sectional view showing the structure of a semiconductor device 10a according to one embodiment of the present invention. Figure 1 The semiconductor device 10 shown in FIG. 1 is different in that the semiconductor device 10 a of the present embodiment has a stacked structure in which the second gate insulating layer 152 includes an insulating layer 152 a and an insulating layer 152 b .

[0142] In this embodiment, a silicon nitride layer is used as the insulating layer 152a, and a silicon oxide layer is used as the insulating layer 152b. However, the present invention is not limited to this example, and the position of the insulating layer 152a and the position of the insulating layer 152b may be interchanged.

[0143] In this embodiment, since the intermediate layer 145 composed of aluminum oxide is disposed between the insulating layer 152a composed of the silicon nitride layer and the oxide semiconductor layer 130, it is possible to prevent hydrogen released from the silicon nitride layer from diffusing toward the oxide semiconductor layer 130 (particularly the channel region 130a). That is, the intermediate layer 145 also functions as a barrier layer that prevents hydrogen from diffusing toward the channel region 130a.

[0144] The semiconductor device 10a of this embodiment achieves the same effects as the semiconductor device 10 described in Embodiment 1. That is, this embodiment can also improve the reliability of the semiconductor device 10a including an oxide semiconductor while suppressing characteristic degradation.

[0145] <Third Embodiment>

[0146] In the first and second embodiments, an example in which the oxide semiconductor layer 130 is provided in contact with the insulating layer 120 is described, but a metal oxide layer may be provided between the insulating layer 120 and the oxide semiconductor layer 130. In the description of this embodiment, the same reference numerals are used in the drawings for the parts common to the first embodiment, and the description will focus on the parts different from the first embodiment.

[0147] Fig.17 FIG. 1 is a schematic cross-sectional view showing the structure of a semiconductor device 10b according to an embodiment of the present invention. Figure 1The semiconductor device 10 shown in FIG. 1 is the same as that in FIG. 1 , but the semiconductor device 10 b of this embodiment has a metal oxide layer 125 disposed between the insulating layer 120 and the oxide semiconductor layer 130. In this embodiment, the metal oxide layer 125 uses a metal oxide having aluminum as a main component (specifically, an aluminum oxide (AlOx) layer). The metal oxide layer 125 can be formed, for example, by sputtering.

[0148] like Fig.17 As shown, in this embodiment, the metal oxide layer 125 has the same pattern shape as the oxide semiconductor layer 130. In this embodiment, the metal oxide layer 125 and the oxide semiconductor layer 130 are continuously stacked and then Figure 4 The steps S1002 and S1003 are performed to obtain a polycrystalline oxide semiconductor layer 130. Then, the metal oxide layer 125 is etched using the oxide semiconductor layer 130 as a mask, thereby forming the metal oxide layer 125 having the same pattern shape as the oxide semiconductor layer 130.

[0149] The thickness of the metal oxide layer 125 is, for example, 1 nm to 10 nm, 1 nm to 4 nm, or 1 nm to 3 nm. In this embodiment, the thickness of the metal oxide layer 125 is set to 3 nm. In this embodiment, the aluminum oxide layer used as the metal oxide layer 125 has a high barrier property to gas even if the thickness is 1 nm to 10 nm. Therefore, the metal oxide layer 125 of this embodiment blocks hydrogen and oxygen released from the insulating layer 120, and inhibits hydrogen and oxygen released from below from reaching the oxide semiconductor layer 130.

[0150] As described above, since the ratio of indium in the oxide semiconductor layer 130 of this embodiment is 50% or more, a semiconductor device with high mobility can be realized, but on the other hand, oxygen is easily reduced and oxygen defects are easily formed in the layer. Therefore, it is preferable to block hydrogen released from the insulating layer 120 by the metal oxide layer 125 in order to suppress the reduction reaction of the oxide semiconductor layer 130.

[0151] In addition, after the oxide semiconductor layer 130 is formed, more oxygen defects are formed on the upper side of the oxide semiconductor layer 130 than on the lower side during various manufacturing processes (patterning process, etc.). That is, the oxygen defects in the oxide semiconductor layer 130 exist in an uneven distribution in the thickness direction. In this case, if a sufficient amount of oxygen is supplied to repair the oxygen defects formed on the upper side of the oxide semiconductor layer 130, oxygen is excessively supplied on the lower side of the oxide semiconductor layer 130. As a result, defect energy levels different from those of the oxygen defects are formed due to the excessive supply of oxygen, sometimes causing phenomena such as changes in characteristics in reliability tests or a decrease in field effect mobility. Therefore, it can be said that the blocking of oxygen released from the insulating layer 120 by the metal oxide layer 125 is also preferred for suppressing the supply of excessive oxygen to the lower side of the oxide semiconductor layer 130.

[0152] Thus, in this embodiment, Figure 1 During the oxidation annealing shown in step S1005, oxygen can be supplied to the lower surface of the oxide semiconductor layer 130 having a small amount of oxygen defects, while oxygen can be supplied to the upper surface and side surfaces of the oxide semiconductor layer 130 having a relatively large amount of oxygen defects. Therefore, oxygen can be efficiently supplied to the oxide semiconductor layer 130 during the oxidation annealing, and the reliability of the semiconductor device 10 can be improved.

[0153] It should be noted that in this embodiment, the Figure 1 The example of the semiconductor device 10 shown in the embodiment is described, but it can also be applied to the second embodiment. Fig.16 The semiconductor device 10a is shown in FIG.

[0154] <Fourth Implementation Method>

[0155] In the fourth embodiment, a display device 20 using a semiconductor device according to an embodiment of the present invention is described. In the following embodiments, a case where the semiconductor device 10 described in the first embodiment is used as an element constituting a circuit of a liquid crystal display device is described. However, the present invention is not limited to this example, and the semiconductor device described in the second embodiment or the third embodiment may be used as an element constituting a circuit of a liquid crystal display device.

[0156] [Overview of Display Device]

[0157] Fig.18 FIG. 2 is a schematic top view showing the overall structure of a display device 20 according to an embodiment of the present invention. Fig.18As shown, the display device 20 has an array substrate 300, a sealing portion 310, an opposing substrate 320, a flexible printed circuit (FPC) substrate 330, and an IC chip 340. The array substrate 300 and the opposing substrate 320 are bonded together by the sealing portion 310. A plurality of pixels 21 are arranged in a matrix in the liquid crystal region 22 surrounded by the sealing portion 310. The liquid crystal region 22 is a region that overlaps with the liquid crystal element 311 described later when viewed from above. It should be noted that, with respect to the pixel 21, the letters "R", "G", and "B" correspond to pixels for red display, pixels for green display, and pixels for blue display, respectively.

[0158] The sealing area 24 provided with the sealing portion 310 is an area around the liquid crystal area 22. The flexible printed circuit substrate 330 is provided in the terminal area 26. The terminal area 26 is an area of ​​the array substrate 300 exposed from the opposing substrate 320 and is provided outside the sealing area 24. The so-called outside of the sealing area 24 means the area provided with the sealing portion 310 and the outside of the area surrounded by the sealing portion 310. The IC chip 340 is provided on the flexible printed circuit substrate 330. The IC chip 340 is provided for driving each pixel circuit 301 (see Fig.19 ) signal.

[0159] [Circuit Configuration of Display Device]

[0160] Fig.19 1 is a block diagram showing a circuit configuration of a display device 20 according to an embodiment of the present invention. Fig.19 As shown, Fig.18 21 shown in the figure, a plurality of pixel circuits 301 are arranged in a matrix shape corresponding to each pixel 21. A source driving circuit 302 is provided at a position adjacent to the liquid crystal region 22 in the Y direction (column direction) where the pixel circuit 301 is arranged. In addition, a gate driving circuit 303 is provided at a position adjacent to the liquid crystal region 22 in the X direction (row direction). The source driving circuit 302 and the gate driving circuit 303 are provided in the above-mentioned sealing region 24. However, the region where the source driving circuit 302 and the gate driving circuit 303 are provided is not limited to the sealing region 24, and may be any region as long as it is outside the region where the pixel circuit 301 is provided.

[0161] The data signal line 304 extends from the source driving circuit 302 in the Y direction and is connected to the plurality of pixel circuits 301 arranged in the Y direction. The scanning signal line 305 extends from the gate driving circuit 303 in the X direction and is connected to the plurality of pixel circuits 301 arranged in the X direction.

[0162] The terminal region 26 is provided with a terminal portion 306. The terminal portion 306 and the source driving circuit 302 are connected by a connection wiring 307. Similarly, the terminal portion 306 and the gate driving circuit 303 are connected by a connection wiring 308. By connecting the flexible printed circuit substrate 330 to the terminal portion 306, an external device is connected to the display device 20 via the flexible printed circuit substrate 330. Each pixel circuit 301 provided in the display device 20 is driven by a signal from an external device input through the flexible printed circuit substrate 330.

[0163] The semiconductor device 10 described in the first embodiment can be used as a switching element or a current control element included in the pixel circuit 301 , the source driver circuit 302 , and the gate driver circuit 303 .

[0164] [Pixel circuit of display device]

[0165] Fig. 20 2 is a circuit diagram showing the structure of a pixel circuit 301 of a display device 20 according to an embodiment of the present invention. Fig. 20 As shown, the pixel circuit 301 includes elements such as the semiconductor device 10, a storage capacitor 350, and a liquid crystal element 311.

[0166] The semiconductor device 10 includes a gate wiring 160, a source wiring 201, and a drain wiring 203. The gate wiring 160 is connected to a scanning signal line 305. However, the gate wiring 160 and the scanning signal line 305 may also be formed by an integral conductive layer. The source wiring 201 is connected to a data signal line 304. However, the source wiring 201 and the data signal line 304 may also be formed by an integral conductive layer.

[0167] The drain wiring 203 is connected to the storage capacitor 350 and the liquid crystal element 311. It should be noted that the roles of the source wiring 201 and the drain wiring 203 are sometimes exchanged by the relationship between the voltage supplied to the data signal line 304 and the voltage accumulated in the storage capacitor 350. That is, sometimes the source wiring 201 functions as a drain wiring, and the drain wiring 203 functions as a source wiring.

[0168] <Fifth Implementation>

[0169] In the fourth embodiment, it is described that each semiconductor device described in the first to third embodiments can be applied to a liquid crystal display device. However, the semiconductor device of each embodiment can also be applied to other display devices other than the liquid crystal display device. For example, the semiconductor device of each embodiment can also be applied to a self-luminous display device such as an organic EL display device, an electronic paper display device, etc.

[0170] As embodiments of the present invention, the embodiments described above (including variations of the embodiments) can be implemented in appropriate combination as long as there is no contradiction. In addition, solutions obtained by adding, deleting, or changing the design of components based on the embodiments, or solutions obtained by adding, omitting, or changing the conditions of processes by those skilled in the art are also included in the scope of the present invention as long as they have the gist of the present invention.

[0171] Even if there are other effects different from the effects brought about by the above-mentioned embodiments, the effects that can be clearly seen from the description of this specification or the effects that can be easily predicted by those skilled in the art should of course be interpreted as the effects brought about by the present invention.

Claims

1. A semiconductor device comprising: an oxide semiconductor layer having a polycrystalline structure on an insulating surface; a first gate insulating layer on the oxide semiconductor layer; an intermediate layer on the first gate insulating layer; a second gate insulating layer on the intermediate layer; and The gate wiring on the second gate insulating layer, The oxide semiconductor layer has a channel region and a conductive region, The first gate insulating layer overlaps with the channel region and the conductive region. The second gate insulating layer overlaps with the channel region and does not overlap with the conductive region. The conductive region has a sheet resistance of 1000 Ω / sq. or less.

2. A semiconductor device comprising: an oxide semiconductor layer having a polycrystalline structure on an insulating surface; a first gate insulating layer on the oxide semiconductor layer; an intermediate layer on the first gate insulating layer; a second gate insulating layer on the intermediate layer; and The gate wiring on the second gate insulating layer, The oxide semiconductor layer has a channel region and a conductive region, The first gate insulating layer overlaps with the channel region and the conductive region. The second gate insulating layer overlaps with the channel region and does not overlap with the conductive region. When the oxide semiconductor layer is etched at 40° C. using an etching solution containing phosphoric acid as a main component, the etching rate is less than 3 nm / min.

3. The semiconductor device according to claim 1 or 2, wherein: The intermediate layer is an oxide layer or an oxide semiconductor layer containing aluminum as a main component.

4. The semiconductor device according to claim 1 or 2, wherein: The intermediate layer overlaps the channel region and does not overlap the conductive region.

5. The semiconductor device according to claim 1 or 2, wherein: The thickness of the intermediate layer is thinner than that of the first gate insulating layer.

6. The semiconductor device according to claim 1 or 2, wherein: The second gate insulating layer is thicker than the first gate insulating layer.

7. The semiconductor device according to claim 1 or 2, wherein: The intermediate layer, the second gate insulating layer, and the gate wiring have the same pattern shape. 8 . The semiconductor device according to claim 1 , further comprising a metal oxide layer between the insulating surface and the oxide semiconductor layer.

9. The semiconductor device according to claim 8, wherein: The metal oxide layer is an oxide layer containing aluminum as a main component.

10. The semiconductor device according to claim 8, wherein The metal oxide layer has the same pattern shape as the oxide semiconductor layer.

11. The semiconductor device according to claim 1 or 2, wherein: The oxide semiconductor layer includes two or more metals including indium, and a ratio of indium in the two or more metals is 50% or more.

12. A display device comprising the semiconductor device according to claim 1 or 2 in each pixel.

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