Semiconductor structure and forming method thereof

Abstract

According to the semiconductor structure and the forming method thereof, a barrier layer is formed on the side wall of a first work function layer, a second work function layer is formed on the side wall of the barrier layer, the barrier layer isolates the second work function layer from the first work function layer, and elements in the second work function layer are not prone to penetrating through the barrier layer to be diffused into the first work function layer. Therefore, the problem of electrical parameter mismatch (Mismatch) between the first transistor and the second transistor is not easy to occur, when the semiconductor structure works, the first work function layer can well adjust the threshold voltage of the subsequently formed first transistor, and the second work function layer can well adjust the threshold voltage of the subsequently formed second transistor. And the electrical performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] In semiconductor manufacturing, with the development trend of ultra-large-scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to smaller feature sizes, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also shortened accordingly. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens, so the control ability of the gate structure over the channel becomes worse, and the difficulty of pinching off the channel by the gate voltage becomes increasingly greater, making the subthreshold leakage phenomenon, the so-called short channel effect (SCE), more likely to occur.

[0003] Therefore, in order to reduce the impact of the short channel effect, semiconductor technology has gradually begun to transition from planar MOSFET to more efficient three-dimensional transistors, such as fin field effect transistors (FinFET). In order to solve problems such as leakage current and power consumption, the gate material has also changed from traditional polysilicon gate to metal gate.

[0004] Threshold voltage tuning is one of the most challenging parts of metal gate technology. Layout-dependent effects (LDE) often cause different threshold voltages of different transistors in a semiconductor device. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to optimize the electrical performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first transistor region and a second transistor region adjacent to each other, the first transistor region being used to form a first transistor, the second transistor region being used to form a second transistor, and the second transistor having a doping type different from that of the first transistor; forming a first work function layer on the substrate, the first work function layer covering the first transistor region and exposing the second transistor region, the first work function layer being used to adjust a threshold voltage of the first transistor; forming a barrier layer on a side wall of the first work function layer; and forming a second work function layer on the first work function layer and the barrier layer, and on the substrate of the second transistor region, the second work function layer being used to adjust the threshold voltage of the second transistor.

[0007] Correspondingly, an embodiment of the present invention also provides a semiconductor structure, including: a substrate, the substrate including an adjacent first transistor region and a second transistor region, the first transistor region is used to form a first transistor, the second transistor region is used to form a second transistor, and the second transistor has a different doping type from the first transistor; a first work function layer, located on the substrate, the first work function layer covers the first transistor region and exposes the second transistor region, the first work function layer is used to adjust the threshold voltage of the first transistor; a barrier layer, located on the side wall of the first work function layer; a second work function layer, covering the first work function layer and the barrier layer, and the substrate of the second transistor region, the second work function layer is used to adjust the threshold voltage of the second transistor.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a barrier layer is formed on the side wall of the first work function layer, and a second work function layer is formed on the side wall of the barrier layer. The barrier layer isolates the second work function layer from the first work function layer, and elements in the second work function layer are not easy to diffuse into the first work function layer through the barrier layer, thereby reducing the probability of the occurrence of the metal boundary effect. Therefore, it is not easy for the first transistor and the second transistor to have an electrical parameter mismatch problem. When the semiconductor structure is working, the first work function layer can well adjust the threshold voltage of the first transistor formed subsequently, and the second work function layer can well adjust the threshold voltage of the second transistor formed subsequently, which is beneficial to improving the electrical performance of the semiconductor structure.

[0010] In an optional solution, the method for forming a semiconductor structure further includes: after providing a substrate and before forming the first work function layer, forming a gate dielectric layer on the substrate in the first transistor region and the second transistor region; in the step of forming the first work function layer, the first work function layer is formed on the gate dielectric layer; in the step of forming the second work function layer, the second work function layer is formed on the first work function layer and the gate dielectric layer exposed by the first work function layer. The barrier layer on the sidewall of the first work function layer increases the lateral spacing between the first work function layer in the first transistor region and the second work function layer in the second transistor region, so that the elements diffused from the second work function layer to the gate dielectric layer in the second transistor region are relatively spaced from the gate dielectric layer in the first transistor region, so that the elements in the gate dielectric layer in the second transistor region are not easily diffused into the gate dielectric layer in the first transistor region, reducing the probability of the occurrence of the metal boundary effect, so that the problem of electrical parameter mismatch is not easy to occur between the first transistor and the second transistor. When the semiconductor structure is working, the first work function layer can well adjust the threshold voltage of the first transistor formed subsequently, and the second work function layer can well adjust the threshold voltage of the second transistor formed subsequently, which is conducive to improving the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1 to 5 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0012] Figures 6 to 20 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure according to an embodiment of the invention. DETAILED DESCRIPTION

[0013] As can be seen from the background technology, the devices currently formed still have the problem of poor performance. The reasons for the poor performance of the devices are now analyzed in combination with a method for forming a semiconductor structure.

[0014] refer to Figures 1 to 5 , showing a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.

[0015] like Figure 1As shown, the steps of forming a semiconductor structure include: providing a substrate 2 and a fin 1 located on the substrate 2, the substrate 2 including an N-type transistor region II and a P-type transistor region I, the N-type transistor region II is used to form an NMOS transistor, and the P-type transistor region I is used to form a PMOS transistor; forming an isolation structure 3 on the substrate 2 where the fin 1 is exposed; forming a dummy gate structure (not shown in the figure) across the fin 1 on the substrate 2, the dummy gate structure covering part of the top wall and part of the side wall of the fin 1; forming an interlayer dielectric layer (not shown in the figure) on the substrate 2 where the dummy gate structure is exposed, the interlayer dielectric layer covering the side walls of the dummy gate structure; removing the dummy gate structure, forming a gate opening 4 in the interlayer dielectric layer, the gate opening 4 exposing the N-type transistor region II and the P-type transistor region I.

[0016] like Figure 2 As shown, a gate dielectric layer 5 is formed on the fin 1 and the isolation structure 3 exposed by the gate opening 4 .

[0017] like Figure 3 As shown, in the gate opening 4, a P-type work function layer 6 is formed on the gate dielectric layer 5 of the P-type transistor region I. The material of the P-type work function layer 6 includes TiN.

[0018] like Figure 4 As shown, an N-type work function layer 7 is formed on the P-type work function layer 6 and the gate dielectric layer 5 of the N-type transistor region II where the P-type work function layer 6 is exposed.

[0019] The material of the N-type work function layer 7 includes TiAl.

[0020] like Figure 5 As shown, a gate layer 8 covering the N-type work function layer 7 is formed on the N-type transistor region II and the P-type transistor region I exposed by the gate opening 4 , and the gate dielectric layer 5 , the P-type work function layer 6 , the N-type work function layer 7 and the gate layer 8 serve as a gate structure 10 .

[0021] In the above semiconductor structure, the NMOS transistor and the PMOS transistor share the same gate structure 10. At the junction of the N-type transistor region II and the P-type transistor region I, the N-type work function layer 7 is directly formed on the side wall of the P-type work function layer 6, and there will be an N / P interface (N / P Boundary Interface) between the N-type work function layer 7 and the P-type work function layer 6. The Al element in the N-type work function layer 7 will diffuse into the P-type work function layer 6 through the N / P interface, resulting in the simultaneous increase of the threshold voltages of the PMOS transistor and the NMOS transistor.

[0022] In addition, the N-type work function layer 7 is formed on the gate dielectric layer 5 of the N-type transistor region II, and the Al element in the N-type work function layer 7 will diffuse into the gate dielectric layer 5 of the N-type transistor region II. The Al element diffused into the gate dielectric layer 5 of the N-type transistor region II will diffuse into the gate dielectric layer 5 of the P-type transistor region I, thereby increasing the threshold voltages of the PMOS transistor and the NMOS transistor at the same time.

[0023] The two diffusion pathways of Al element in the N-type work function layer 7 are called Metal Boundary Effect (MBE), which will lead to the deterioration of electrical parameter mismatch between PMOS devices and NMOS devices, thereby affecting the electrical performance of the semiconductor structure.

[0024] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, wherein a barrier layer is formed on the side wall of the first work function layer, and a second work function layer is formed on the side wall of the barrier layer, the barrier layer isolates the second work function layer from the first work function layer, and elements in the second work function layer are not easy to diffuse into the first work function layer through the barrier layer, so that electrical parameter mismatch (Mismatch) is not easy to occur between the first transistor and the second transistor. When the semiconductor structure is working, the first work function layer can well adjust the threshold voltage of the subsequently formed first transistor, and the second work function layer can well adjust the threshold voltage of the subsequently formed second transistor, which is beneficial to improving the electrical performance of the semiconductor structure.

[0025] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0026] Figures 6 to 20 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure according to an embodiment of the invention.

[0027] refer to Figures 6 to 8 , providing a substrate, the substrate comprising adjacent first transistor region I and second transistor region II, the first transistor region I is used to form a first transistor, the second transistor region II is used to form a second transistor, and the second transistor has a different doping type from the first transistor.

[0028] In the present embodiment, the different doping types between the second transistor and the first transistor refer to that the doping ion type of the source-drain doping layer in the first transistor is different from the doping ion type of the source-drain doping layer in the second transistor.

[0029] Specifically, the first transistor region I is used to form a P-type transistor, and the second transistor region II is used to form an N-type transistor. As an example, the P-type transistor formed by the first transistor region I is a pull-up transistor of a static random access memory (SRAM), and the N-type transistor formed by the second transistor region II is a pull-down transistor of the static random access memory.

[0030] like Figure 6 As shown, the step of providing a base includes: providing a substrate 100 and a channel structure 101 located on the substrate 100 .

[0031] In this embodiment, the material of the substrate 100 is silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The substrate 100 can also be a silicon on insulator substrate 100 or a germanium on insulator substrate 100.

[0032] In this embodiment, the method for forming the semiconductor structure is used to form a fin field effect transistor (FinField-Effect Transistor, FinFET), and the channel structure 101 includes a fin. The material of the fin includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. In other embodiments, the method for forming the semiconductor structure is used to form a wrap-around gate transistor (Gate-All-Around, GAA), and the channel structure 101 may also include a plurality of channel layers spaced apart in a direction perpendicular to the surface of the substrate 100.

[0033] The step of providing a substrate further includes: forming an isolation structure 102 (eg, Figure 6 As shown in FIG. 1 , the isolation structure 102 covers part of the sidewall of the channel structure 101, and the top of the isolation structure 102 is lower than the top of the channel structure 101. The isolation structure 102 is used to electrically isolate adjacent channel structures 101 and adjacent devices.

[0034] The material of the isolation structure 102 is silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the isolation structure 102 is silicon oxide.

[0035] like Figure 7 As shown, a dummy gate structure 103 is formed on the substrate 100 across the channel structure 101, and the dummy gate structure 103 covers part of the top wall and part of the side wall of the channel structure 101; an interlayer dielectric layer 104 is formed on the substrate 100 where the dummy gate structure is exposed, and the interlayer dielectric layer 104 covers the side wall of the dummy gate structure 103.

[0036] The dummy gate structure 103 occupies a space position for a metal gate structure formed in a subsequent process. The dummy gate structure 103 includes a dummy gate oxide layer that conformally covers a portion of the top surface and a portion of the sidewall of the channel structure 101, and the dummy gate structure 103 also includes a dummy gate layer located on the dummy gate oxide layer.

[0037] In this embodiment, the dummy gate structure 103 is a stacked structure. In other embodiments, the dummy gate structure may also be a single-layer structure, that is, the dummy gate material structure only includes the dummy gate layer.

[0038] Specifically, the step of forming the dummy gate structure 103 includes: forming a dummy gate oxide material layer (not shown in the figure) conformally covering the channel structure 101, and then forming a dummy gate material layer (not shown in the figure) across the channel structure 101 on the dummy gate oxide material layer. Etching the dummy gate material layer and the dummy gate oxide material layer to form a dummy gate oxide layer and a dummy gate layer located on the dummy gate oxide layer, wherein the dummy gate oxide layer and the dummy gate layer cover a portion of the top and a portion of the sidewall of the channel structure 101.

[0039] In this embodiment, the material of the dummy gate oxide layer is silicon oxide. In other embodiments, the material of the dummy gate oxide layer may also be silicon oxynitride.

[0040] In this embodiment, the material of the dummy gate layer is polysilicon. In other embodiments, the material of the dummy gate layer may also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbon nitride oxide or amorphous carbon.

[0041] The interlayer dielectric layer 104 is used to isolate adjacent devices. The material of the interlayer dielectric layer 104 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride. In this embodiment, the material of the interlayer dielectric layer 104 is silicon oxide.

[0042] It should be noted that the method for forming the semiconductor structure further includes: forming a source-drain doping layer (not shown in the figure) in the channel structure 101 on both sides of the dummy gate structure after forming the dummy gate structure and before forming the interlayer dielectric layer 104. The dummy gate structure 103 will be replaced with a metal gate structure later, and when the semiconductor structure is working, the source-drain doping layer provides stress to the channel below the metal gate structure.

[0043] In this embodiment, the doping ion type of the source-drain doping layer of the first transistor is different from the doping ion type of the source-drain doping layer of the second transistor. Specifically, the doping ions of the source-drain doping layer of the first transistor include one or more of B, Ga and In, and the doping ions of the source-drain doping layer of the second transistor include one or more of P, As and Sb.

[0044] like Figure 8 As shown, after the interlayer dielectric layer 104 is formed, the dummy gate structure 103 is removed, and a gate opening 105 is formed in the interlayer dielectric layer 104 , wherein the gate opening 105 exposes the first transistor region I and the second transistor region II.

[0045] The gate opening 105 provides space for the subsequent formation of the metal gate structure. The gate opening 105 exposes the first transistor region I and the second transistor region II. Accordingly, the metal gate structure subsequently formed in the gate opening 105 is located on the first transistor region I and the second transistor region II.

[0046] In this embodiment, the extension direction of the gate opening 105 is perpendicular to the extension direction of the boundary between the first transistor region I and the second transistor region II. Accordingly, the extension direction of the metal gate structure subsequently formed in the gate opening 105 is perpendicular to the extension direction of the boundary between the first transistor region I and the second transistor region II.

[0047] refer to Figures 9 to 12 As shown, Fig. 9 yes Figure 8 A first work function layer 106 (such as Fig.12 As shown), the first work function layer 106 covers the first transistor region I and exposes the second transistor region II, and the first work function layer 106 is used to adjust the threshold voltage of the first transistor.

[0048] The first transistor is a P-type transistor, and the corresponding first work function layer 106 is used to adjust the threshold voltage of the P-type transistor.

[0049] In this embodiment, the step of forming the first work function layer 106 on the substrate includes: forming a first work function material layer 107 (such as Fig.11 As shown in the figure), the first work function material layer 107 covers the first transistor area I and the second transistor area II; a first mask layer (not shown in the figure) is formed on the first work function material layer 107, and the first mask layer covers the first transistor area I and exposes the second transistor area II; the first work function material layer 107 is etched using the first mask layer as a mask to form the first work function layer 106.

[0050] In this embodiment, the material of the first work function layer 106 is a P-type work function material. Specifically, the material of the first work function layer 106 is TiN or TaN.

[0051] In this embodiment, the first work function material layer 107 may be formed by a chemical vapor deposition process (CVD), a physical vapor deposition process (PVD) or an atomic layer deposition process (ALD).

[0052] It should be noted that in the step of forming the first work function material layer 107 , the first work function material layer 107 is formed on the bottom surface and sidewalls of the gate opening 105 , that is, the first work function material layer 107 is also formed on the sidewalls of the interlayer dielectric layer 104 .

[0053] like Fig.10 As shown, the method for forming the semiconductor structure further includes: after providing the substrate and before forming the first work function layer 106 , forming a gate dielectric layer 109 on the substrate of the first transistor region I and the second transistor region II.

[0054] The gate dielectric layer 109 is used to achieve electrical isolation between the channel structure 101 and a subsequently formed metal gate structure.

[0055] The step of forming the gate dielectric layer 109 includes: forming the gate dielectric layer 109 on the channel structure 101 and the substrate 100 where the channel structure 101 is exposed.

[0056] The material of the gate dielectric layer 109 is a gate dielectric material having a relative dielectric constant greater than that of silicon oxide. In this embodiment, the material of the gate dielectric layer 109 is HfO2. In other embodiments, the material of the gate dielectric layer may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2 or Al2O3.

[0057] In this embodiment, the gate dielectric layer 109 is formed by an atomic layer deposition process. In other embodiments, the gate dielectric layer may also be formed by a physical vapor deposition process.

[0058] In this embodiment, in the step of forming the gate dielectric layer 109 , the gate dielectric layer 109 is formed on the bottom surface and sidewalls of the gate opening 105 , that is, the gate dielectric layer 109 is also formed on the sidewalls of the interlayer dielectric layer 104 .

[0059] It should be noted that, in the step of forming the first work function layer 106 , the first work function layer 106 is also formed on the gate dielectric layer 109 on the side wall of the interlayer dielectric layer 104 .

[0060] The method for forming the semiconductor structure further includes: after forming the gate dielectric layer 109 and before forming the first work function layer 106, forming an anti-etching layer 110 (such as Fig.10 shown).

[0061] When etching the first work function material layer 107 to form the first work function layer 106, the anti-etching layer 110 can stop the etching and not easily cause etching damage to the gate dielectric layer 109. The anti-etching layer 110 also stops the etching in the subsequent step of forming a barrier layer, and is used to protect the gate dielectric layer 109 from being easily damaged by etching.

[0062] The anti-etching layer 110 is made of different materials from the first work function layer 106. In the step of etching the first work function material layer 107, the etching rate of the anti-etching layer 110 is lower than the etching rate of the first work function material layer 107. In this embodiment, the material of the anti-etching layer 110 is TaN.

[0063] In this embodiment, the anti-etching layer 110 is formed by an atomic layer deposition process or a chemical vapor deposition process.

[0064] In this embodiment, in the step of forming the anti-etching layer 110, the anti-etching layer 110 is formed on the bottom surface and sidewalls of the gate opening 105, that is, the anti-etching layer 110 is formed on the substrate of the first transistor region I and the second transistor region II, and on the sidewalls of the interlayer dielectric layer 104. Specifically, the anti-etching layer 110 is formed on the gate dielectric layer 109.

[0065] Continue to refer Fig.10 The method for forming the semiconductor structure further includes: after forming the gate dielectric layer 109 and before forming the anti-etching layer 110 , forming a barrier layer 111 covering the gate dielectric layer 109 .

[0066] Subsequently, a first work function layer 106 and a second work function layer 108 are formed on the barrier layer 111 . The barrier layer 111 is used to prevent elements in the first work function layer 106 and the second work function layer 108 from diffusing into the gate dielectric layer 109 .

[0067] In this embodiment, the material of the barrier layer 111 is TiN. In other embodiments, the material of the barrier layer can be Ta, Ti, ZrN, ZrTiN or other materials.

[0068] In this embodiment, the barrier layer 111 is formed by a physical vapor deposition process. In other embodiments, the barrier layer may be formed by a chemical vapor deposition process or an atomic layer deposition process.

[0069] In this embodiment, in the step of forming the barrier layer 111, the barrier layer 111 is formed on the bottom surface and sidewalls of the gate opening 105, that is, the barrier layer 111 is formed on the substrate of the first transistor region I and the second transistor region II, and on the sidewalls of the interlayer dielectric layer 104. Specifically, the barrier layer 111 is formed on the gate dielectric layer 109.

[0070] refer to Figures 13 to 16 ,in, Fig.15 yes Fig.14 A partial enlarged view of Fig.16 yes Fig.15 A barrier layer 112 (eg, Fig.15 shown).

[0071] A barrier layer 112 is formed on the side wall of the first work function layer 106, and a second work function layer is subsequently formed on the side wall of the barrier layer 112. The barrier layer 112 isolates the second work function layer from the first work function layer 106. Elements in the second work function layer are not easy to diffuse into the first work function layer 106 through the barrier layer 112, thereby reducing the probability of metal boundary effect. Therefore, electrical parameter mismatch is not easy to occur between the first transistor and the second transistor. When the semiconductor structure is working, the first work function layer 106 can well adjust the threshold voltage of the first transistor formed subsequently, and the second work function layer can well adjust the threshold voltage of the second transistor formed subsequently, which is beneficial to improving the electrical performance of the semiconductor structure.

[0072] In addition, the barrier layer 112 on the side wall of the first work function layer 106 increases the lateral spacing between the first work function layer 106 in the first transistor region I and the second work function layer in the second transistor region II, so that the lateral spacing between the elements diffused from the second work function layer to the gate dielectric layer in the second transistor region II and the gate dielectric layer 109 of the first transistor region I is larger, making it difficult for the elements of the gate dielectric layer 109 in the second transistor region II to diffuse into the gate dielectric layer 109 of the first transistor region I, reducing the probability of the metal boundary effect. Therefore, the problem of electrical parameter mismatch between the first transistor and the second transistor is unlikely to occur. When the semiconductor structure is working, the first work function layer 106 can well adjust the threshold voltage of the first transistor formed subsequently, and the second work function layer can well adjust the threshold voltage of the second transistor formed subsequently, which is beneficial to improving the electrical performance of the semiconductor structure.

[0073] In this embodiment, when the temperature exceeds 400° C., the diffusion coefficient of the elements in the second work function layer 108 in the barrier layer 112 is less than 5.6×10 -22 m 2 / s. Generally, the higher the temperature, the stronger the diffusion ability of the elements in the second work function layer 108. If the temperature exceeds 400°C, the diffusion coefficient of the elements in the second work function layer 108 in the barrier layer 112 is too high, for example, greater than 5.6×10 -22 m 2 / s, it is easy for elements in the second work function layer 108 to pass through the barrier layer 112 and enter the first work function layer 106, resulting in electrical parameter mismatch between the first transistor and the second transistor.

[0074] Specifically, the material of the barrier layer 112 includes TaN or W.

[0075] In this embodiment, the step of forming a barrier layer 112 on the sidewall of the first work function layer 106 includes: forming a barrier material layer 113 (such as a barrier material layer 114) on the first work function layer 106 and the substrate where the first work function layer 106 is exposed. Fig.13 As shown); removing the barrier material layer 113 on the top of the first work function layer 106 and on the substrate, and the remaining barrier material layer 113 located on the sidewall of the first work function layer 106 serves as the barrier layer 112.

[0076] In this embodiment, the barrier material layer 113 is formed by an atomic layer deposition process. The atomic layer deposition process includes performing multiple atomic layer deposition cycles, which makes it easy to accurately control the thickness of the barrier material layer 113, and is conducive to improving the thickness uniformity of the barrier material layer 113; in addition, the atomic layer deposition process has good gap filling performance and step coverage, which correspondingly improves the conformal coverage ability of the barrier material layer 113, so that the barrier material layer 113 can conformally cover the first work function layer 106 and the first work function layer 106 exposed on the anti-etching layer 110. In other embodiments, the barrier material layer can also be formed by a chemical vapor deposition process.

[0077] It should be noted that, with the lateral direction perpendicular to the sidewall of the first work function layer 106 as the lateral direction, the lateral dimension of the barrier layer 112 should not be too large or too small. If the lateral dimension of the barrier layer 112 is too large, it will take too much process time and material to form the barrier material layer 113, and it will take more time to etch the barrier material layer 113 to form the barrier layer 112, which is not conducive to improving the formation efficiency of the semiconductor structure. If the lateral dimension of the barrier layer 112 is too small, it is easy to cause the barrier layer 112 to fail to effectively block the elements in the second work function layer subsequently formed on the sidewall of the barrier layer 112 from diffusing into the first work function layer 106, and the metal boundary effect is likely to occur. The first work function layer 106 cannot well adjust the threshold voltage of the first transistor formed subsequently, so that there is a mismatch problem of electrical parameters between the first transistor and the second transistor, resulting in poor electrical performance of the semiconductor structure finally formed. In this embodiment, with the direction perpendicular to the sidewall of the first work function layer 106 as the lateral direction, the lateral dimension of the barrier layer 112 is 10 angstroms to 150 angstroms.

[0078] refer to Fig.17 and Fig.18 A second work function layer 108 is formed on the first work function layer 106, the barrier layer 112, and the substrate of the second transistor region II, and the second work function layer 108 is used to adjust the threshold voltage of the second transistor.

[0079] The second transistor is an N-type transistor, and the corresponding second work function layer 108 is used to adjust the threshold voltage of the N-type transistor.

[0080] In this embodiment, the second work function layer 108 may be formed by using a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

[0081] In this embodiment, the material of the second work function layer 108 is an N-type work function material. The material of the second work function layer 108 includes one or more of TiAL, TaAlN, and TiAlN.

[0082] It should be noted that, in the step of forming the second work function layer 108 , the second work function layer 108 is also formed on the sidewall of the interlayer dielectric layer 104 exposed by the gate opening 105 .

[0083] refer to Fig.19 and Fig. 20 , Fig. 20 yes Fig.19 As shown in the local enlarged view in FIG. 1 , the method for forming the semiconductor structure further includes: after forming the second work function layer 108 , forming a gate layer 114 in the gate opening 105 .

[0084] The gate layer 114 , the first work function layer 106 and the second work function layer 108 together serve as a metal gate structure.

[0085] In this embodiment, the material of the gate layer 114 is magnesium-tungsten alloy. In other embodiments, the material of the metal gate structure can also be W, Cu, Ag, Au, Pt, Ni or Ti.

[0086] Accordingly, an embodiment of the present invention further provides a semiconductor structure. Fig.19 and Fig. 20 , showing a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0087] The semiconductor structure includes: a substrate, the substrate includes a first transistor area I and a second transistor area II adjacent to each other, the first transistor area I is used to form a first transistor, the second transistor area II is used to form a second transistor, and the second transistor has a different doping type from the first transistor; a first work function layer 106, located on the substrate, the first work function layer 106 covers the first transistor area I and exposes the second transistor area II, the first work function layer 106 is used to adjust the threshold voltage of the first transistor; a barrier layer 112, located on the side wall of the first work function layer 106; a second work function layer 108, covering the first work function layer 106 and the barrier layer 112, as well as the substrate of the second transistor area II, the second work function layer 108 is used to adjust the threshold voltage of the second transistor.

[0088] The barrier layer 112 is located on the side wall of the first work function layer 106. The barrier layer 112 isolates the second work function layer 108 from the first work function layer 106. The elements in the second work function layer 108 are not easy to diffuse into the first work function layer 106 through the barrier layer 112, thereby reducing the probability of the metal boundary effect. Therefore, it is not easy for the first transistor and the second transistor to have an electrical parameter mismatch problem. When the semiconductor structure is working, the first work function layer 106 can well adjust the threshold voltage of the first transistor, and the second work function layer 108 can well adjust the threshold voltage of the second transistor, which is beneficial to improving the electrical performance of the semiconductor structure.

[0089] In the present embodiment, the different doping types between the second transistor and the first transistor refer to that the doping ion type of the source-drain doping layer in the first transistor is different from the doping ion type of the source-drain doping layer in the second transistor.

[0090] Specifically, the first transistor is a P-type transistor, which is a pull-up transistor of a static random access memory (SRAM), and the second transistor is an N-type transistor, which is a pull-down transistor of the static random access memory.

[0091] In this embodiment, the base includes: a substrate 100 and a channel structure 101 located on the substrate 100 .

[0092] In this embodiment, the material of the substrate 100 is silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The substrate 100 can also be a silicon on insulator substrate 100 or a germanium on insulator substrate 100.

[0093] In this embodiment, the semiconductor structure includes a fin field effect transistor (Fin Field-EffectTransistor, FinFET), and the channel structure 101 includes a fin. The material of the fin includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. In other embodiments, the semiconductor structure includes a wrap-around gate transistor (Gate-All-Around, GAA), and the channel structure 101 may also include a plurality of channel layers arranged at intervals in a direction perpendicular to the surface of the substrate 100.

[0094] The base also includes an isolation structure 102 located on the substrate 100 where the channel structure 101 is exposed, the isolation structure 102 covers part of the sidewall of the channel structure 101, and the top of the isolation structure 102 is lower than the top of the channel structure 101. The isolation structure 102 is used to electrically isolate adjacent channel structures 101 and adjacent devices.

[0095] The material of the isolation structure 102 is silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the isolation structure 102 is silicon oxide.

[0096] The semiconductor structure further includes an interlayer dielectric layer 104 (such as Figure 8 ), located on the substrate 100 and the channel structure 101, the interlayer dielectric layer 104 includes a gate opening 105 (as shown) exposing a portion of the substrate 100 and the channel structure 101. Figure 8 As shown), the gate opening 105 exposes the first transistor region I and the second transistor region II.

[0097] It should be noted that the extension direction of the gate opening 105 is perpendicular to the extension direction of the boundary between the first transistor region I and the second transistor region II.

[0098] The interlayer dielectric layer 104 is used to isolate adjacent devices. The material of the interlayer dielectric layer 104 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride. In this embodiment, the material of the interlayer dielectric layer 104 is silicon oxide.

[0099] It should be noted that, with the sidewall direction perpendicular to the first work function layer 106 as the lateral direction, the lateral dimension of the barrier layer 112 should not be too large or too small. If the lateral dimension of the barrier layer 112 is too large, it will take too much process time and material, which is not conducive to improving the formation efficiency of the semiconductor structure. If the lateral dimension of the barrier layer 112 is too small, the barrier layer 112 will not be able to well block the elements in the second work function layer 108 from diffusing into the first work function layer 106, and the first work function layer 106 will not be able to well adjust the threshold voltage of the first transistor, so that there is a mismatch in electrical parameters between the first transistor and the second transistor, resulting in poor electrical performance of the semiconductor structure. In this embodiment, with the sidewall direction perpendicular to the first work function layer 106 as the lateral direction, the lateral dimension of the barrier layer 112 is 10 angstroms to 150 angstroms.

[0100] In this embodiment, generally, the higher the temperature, the stronger the diffusion ability of the elements in the second work function layer 108. If the temperature exceeds 400°C, the diffusion coefficient of the elements in the second work function layer 108 in the barrier layer 112 is too high, for example, greater than 5.6×10 -22 m 2 / s, the elements in the second work function layer 108 may pass through the barrier layer 112 and enter the first work function layer 106, resulting in electrical parameter mismatch between the first transistor and the second transistor.

[0101] Specifically, the material of the barrier layer 112 includes TaN or W.

[0102] The semiconductor structure further includes: a gate dielectric layer 109 located on the substrate of the first transistor region I and the second transistor region II.

[0103] The gate dielectric layer 109 is used for electrical isolation.

[0104] Specifically, the gate dielectric layer 109 is formed on the substrate in the first transistor region I and the second transistor region II exposed by the gate opening 105 , and on the sidewalls of the interlayer dielectric layer 104 .

[0105] The material of the gate dielectric layer 109 is a gate dielectric material having a relative dielectric constant greater than that of silicon oxide. In this embodiment, the material of the gate dielectric layer 109 is HfO2. In other embodiments, the material of the gate dielectric layer may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2 or Al2O3.

[0106] The first transistor is a P-type transistor, and the corresponding first work function layer 106 is used to adjust the threshold voltage of the P-type transistor.

[0107] In this embodiment, the material of the first work function layer 106 is a P-type work function material. Specifically, the material of the first work function layer 106 is TiN or TaN.

[0108] It should be noted that the first work function layer 106 is located in the first transistor area I exposed by the gate opening 105. Correspondingly, the first work function layer 106 is located on the gate dielectric layer 109 of the first transistor area I, specifically, on the gate dielectric layer 109 on the substrate and on the gate dielectric layer 109 on the side wall of the interlayer dielectric layer 104.

[0109] In addition, the barrier layer 112 on the side wall of the first work function layer 106 increases the lateral spacing between the first work function layer 106 in the first transistor region I and the second work function layer 108 in the second transistor region II, so that the lateral spacing between the elements diffused from the second work function layer 108 to the gate dielectric layer in the second transistor region II and the gate dielectric layer of the first transistor region I is larger, making it difficult for the elements of the gate dielectric layer in the second transistor region II to diffuse into the gate dielectric layer of the first transistor region I, reducing the probability of the metal boundary effect. Therefore, the problem of electrical parameter mismatch is unlikely to occur between the first transistor and the second transistor. When the semiconductor structure is working, the first work function layer 106 can well adjust the threshold voltage of the first transistor, and the second work function layer 108 can well adjust the threshold voltage of the second transistor, which is beneficial to improving the electrical performance of the semiconductor structure.

[0110] The second transistor is an N-type transistor, and the corresponding second work function layer 108 is used to adjust the threshold voltage of the N-type transistor.

[0111] In this embodiment, the material of the second work function layer 108 is an N-type work function material. Specifically, the material of the second work function layer 108 includes one or more of TiAl, TaAlN, and TiAlN.

[0112] The second work function layer 108 is located on the first work function layer 106 of the first transistor region I and the gate dielectric layer 109 of the second transistor region II. Specifically, the second work function layer 108 is located on the gate dielectric layer 109 of the first transistor region I and the second transistor region II exposed by the gate opening 105.

[0113] It should be noted that the second work function layer 108 is also located on the side wall of the interlayer dielectric layer 104 exposed by the gate opening 105 .

[0114] The semiconductor structure further includes a gate layer 114 located on the first work function layer 106 and the second work function layer 108 of the gate opening 105 .

[0115] The gate layer 114 , the first work function layer 106 and the second work function layer 108 together serve as a metal gate structure.

[0116] In this embodiment, the material of the gate layer 114 is magnesium-tungsten alloy. In other embodiments, the material of the metal gate structure can also be W, Cu, Ag, Au, Pt, Ni or Ti.

[0117] The semiconductor structure further includes a blocking layer 111 located on the gate dielectric layer 109 .

[0118] The blocking layer 111 is used to block the elements in the first work function layer 106 and the second work function layer 108 from diffusing into the gate dielectric layer 109 .

[0119] In this embodiment, the material of the barrier layer 111 is TiN. In other embodiments, the material of the barrier layer can be Ta, Ti, ZrN, ZrTiN or other materials.

[0120] In this embodiment, the barrier layer 111 is located on the bottom surface and sidewalls of the gate opening 105 . Specifically, the barrier layer 111 is located on the substrates of the first transistor region I and the second transistor region II, and on the sidewalls of the interlayer dielectric layer 104 .

[0121] The semiconductor structure further includes an anti-etching layer 110 located between the first work function layer and the gate dielectric layer in the first transistor region, and between the second work function layer and the gate dielectric layer in the second transistor region.

[0122] The anti-etching layer 110 is used to stop etching in the step of forming the barrier layer 112 , and is also used to protect the gate dielectric layer 109 from being easily damaged by etching.

[0123] The material of the anti-etching layer 110 is different from that of the first work function layer 106. In this embodiment, the material of the anti-etching layer 110 is TaN.

[0124] Specifically, the anti-etching layer 110 is located between the first work function layer 106 and the barrier layer 111 of the first transistor region I, and between the second work function layer 108 and the barrier layer 111 of the second transistor region II.

[0125] The semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0126] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first transistor region and a second transistor region adjacent to each other, the first transistor region being used to form a first transistor, the second transistor region being used to form a second transistor, and the second transistor having a doping type different from that of the first transistor; forming a first work function layer on the substrate, wherein the first work function layer covers the first transistor region and exposes the second transistor region, and the first work function layer is used to adjust the threshold voltage of the first transistor; forming a barrier layer on the sidewalls of the first work function layer; A second work function layer is formed on the first work function layer, the barrier layer, and the substrate of the second transistor region, and the second work function layer is used to adjust the threshold voltage of the second transistor.

2. The method for forming a semiconductor structure according to claim 1, wherein: Taking the direction perpendicular to the sidewall of the first work function layer as the lateral direction, the lateral dimension of the barrier layer is 10 angstroms to 150 angstroms.

3. The method for forming a semiconductor structure according to claim 1, wherein: When the temperature exceeds 400°C, the diffusion coefficient of the elements in the second work function layer in the barrier layer is less than 5.6×10 -22 m 2 / s.

4. The method for forming a semiconductor structure according to claim 1, wherein: The material of the barrier layer includes TaN or W.

5. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a barrier layer on the sidewall of the first work function layer comprises: forming a barrier material layer on the first work function layer and the substrate where the first work function layer is exposed; The barrier material layer on the first work function layer and the substrate is removed, and the remaining barrier material layer on the side wall of the first work function layer serves as the barrier layer.

6. The method for forming a semiconductor structure according to claim 5, wherein: The barrier material layer is formed by an atomic layer deposition process or a chemical vapor deposition process.

7. The method for forming a semiconductor structure according to claim 5, wherein: The barrier material layer on the first work function layer and the substrate is removed by using a maskless etching process.

8. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming a semiconductor structure further comprises: after providing a substrate and before forming the first work function layer, forming a gate dielectric layer on the substrate in the first transistor region and the second transistor region; In the step of forming the first work function layer, the first work function layer is formed on the gate dielectric layer; In the step of forming the second work function layer, the second work function layer is formed on the first work function layer and the gate dielectric layer exposed by the first work function layer.

9. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the semiconductor structure further includes: after forming the gate dielectric layer and before forming the first work function layer, forming an anti-etching layer covering the gate dielectric layer, wherein the anti-etching layer serves as an etching stop in the step of forming the barrier layer.

10. The method for forming a semiconductor structure according to claim 1, wherein: The step of providing a substrate comprises: Providing a substrate and a channel structure on the substrate; forming a dummy gate structure across the channel structure on the substrate, wherein the dummy gate structure covers a portion of the top wall and a portion of the side wall of the channel structure; forming an interlayer dielectric layer on the substrate where the dummy gate structure is exposed, wherein the interlayer dielectric layer covers the side wall of the dummy gate structure; removing the dummy gate structure, forming a gate opening in the interlayer dielectric layer, wherein the gate opening exposes the first transistor region and the second transistor region; In the step of forming the first work function layer, the first work function layer is formed in the first transistor region exposed by the gate opening; In the step of forming the second work function layer, the second work function layer is formed in the first transistor region and the second transistor region exposed by the gate opening; The method for forming a semiconductor structure further includes: after forming the second work function layer, forming a gate layer in the gate opening.

11. The method for forming a semiconductor structure according to claim 10, wherein: An extension direction of the gate opening is perpendicular to an extension direction of a boundary between the first transistor region and the second transistor region.

12. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a first transistor region and a second transistor region adjacent to each other, the first transistor region being used to form a first transistor, the second transistor region being used to form a second transistor, and the second transistor having a doping type different from that of the first transistor; a first work function layer, located on the substrate, the first work function layer covering the first transistor region and exposing the second transistor region, the first work function layer being used to adjust a threshold voltage of the first transistor; A barrier layer, located on a side wall of the first work function layer; The second work function layer covers the first work function layer and the barrier layer, and the substrate of the second transistor region, and the second work function layer is used to adjust the threshold voltage of the second transistor.

13. The semiconductor structure according to claim 12, wherein: Taking the direction perpendicular to the sidewall of the first work function layer as the lateral direction, the lateral dimension of the barrier layer is 10 angstroms to 150 angstroms.

14. The semiconductor structure according to claim 12, wherein: When the temperature exceeds 400°C, the diffusion coefficient of the elements in the second work function layer in the barrier layer is less than 5.6×10 -22 m 2 / s.

15. The semiconductor structure according to claim 12, wherein: The materials of the barrier layer include: TaN or W.

16. The semiconductor structure according to claim 12, wherein: The base comprises: a substrate; a channel structure located on the substrate; an interlayer dielectric layer located on the substrate and the channel structure, wherein the interlayer dielectric layer comprises a gate opening exposing a portion of the substrate and the channel structure, and the gate opening exposes the first transistor region and the second transistor region; The first work function layer is located in the first transistor region exposed by the gate opening; The second work function layer is located in the first transistor region and the second transistor region exposed by the gate opening; The semiconductor structure further includes: a gate layer located on the first work function layer and the second work function layer of the gate opening.

17. The semiconductor structure according to claim 16, wherein: An extension direction of the gate opening is perpendicular to an extension direction of a boundary between the first transistor region and the second transistor region.

18. The semiconductor structure according to claim 12, wherein: The semiconductor structure also includes: A gate dielectric layer, located on the substrate in the first transistor region and the second transistor region; The first work function layer is located on the gate dielectric layer in the first transistor region; The second work function layer is located on the first work function layer in the first transistor region and the gate dielectric layer in the second transistor region.

19. The semiconductor structure according to claim 18, wherein: The semiconductor structure further includes an anti-etching layer located between the first work function layer and the gate dielectric layer in the first transistor region, and between the second work function layer and the gate dielectric layer in the second transistor region.

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