Method and structure for integrating CMOS (complementary metal oxide semiconductor) and self-aligned silicon germanium HBT (heterojunction bipolar transistor)

Abstract

The invention discloses a method and a structure for integrating a CMOS (Complementary Metal Oxide Semiconductor) and a self-aligned silicon germanium HBT (Heterojunction Bipolar Transistor). The method comprises the following steps: forming a plurality of shallow trench isolation regions on a silicon substrate; forming a polysilicon gate, gate silicon oxide and a lightly doped region in the CMOS active region; opening a base region window in the HBT region and forming a selective ion implantation region; forming a Si Ge base region; forming a sacrificial emitter region; etching to expose the surface of the outer side region of the Si Ge base region and form an outer base region; forming an emitter region window and exposing the Si Ge surface of the Si Ge base region below the emitter region window; and forming a silicon emitter region in the emitter region window, and photoetching and patterning the emitter region and the outer base region. In the invention, a novel sacrifice emitter region process is adopted, and a self-alignment method of lifting the outer base region and the emitter region is combined, so that the process complexity is effectively reduced, and the device process is compatible with the standard CMOS and other passive device processes.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor integrated circuits, and in particular relates to a method and structure for integrating CMOS and self-aligned silicon germanium HBT. Background Art

[0002] SiGe HBT (silicon germanium HBT) devices have the advantages of high frequency, low noise, and large gain and early voltage product, so they are widely used in the field of wireless communications; the Si Ge BiCMOS process formed by integrating it with the standard CMOS process has a relatively important application position in the field of analog RF. The SiGe BiCMOS process integrates HBT devices, MOSFETs and other passive devices at the same time, and all devices in the entire process share the thermal budget; therefore, how to form different devices and how to integrate more types of devices with different structures are important indicators of the completeness and scalability of the process. Summary of the invention

[0003] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is to provide a method and structure for integrating CMOS and self-aligned silicon germanium HBT.

[0004] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0005] A method for integrating CMOS and self-aligned silicon germanium HBT, comprising the following steps:

[0006] S1. etching a plurality of shallow trenches on a silicon substrate by photolithography, and filling each shallow trench with oxide to form a plurality of shallow trench isolation regions, wherein the plurality of shallow trench isolation regions separate the upper portion of the silicon substrate into a CMOS region and an HBT region, and separate the CMOS region into a CMOS active region and a substrate contact region, and separate the HBT region into a collector active region and a collector contact region;

[0007] S2, forming a polysilicon gate above the CMOS active area, and forming gate silicon oxide by oxidation on the surface of the polysilicon gate, and forming lightly doped areas by implantation in the CMOS active areas on both sides of the polysilicon gate;

[0008] S3, sequentially depositing a first silicon oxide layer and a first silicon nitride layer on a silicon substrate, opening a base window in the HBT region by photolithography etching the first silicon nitride layer and the first silicon oxide layer, then stripping off the remaining first silicon nitride layer, and implanting an N+ type selective ion implantation region in the base window;

[0009] S4, forming an epitaxial Si Ge layer on the silicon substrate in a non-selective manner, wherein the epitaxial Si Ge layer formed on the surface of the single crystal silicon is a single crystal Si Ge region, the single crystal Si Ge region forms a SiGe base region, and the epitaxial Si Ge layer formed on the surface of the first silicon oxide layer is a polycrystalline Si Ge region;

[0010] S5, depositing a second silicon oxide layer and a polysilicon sacrificial layer on the silicon substrate in sequence, and etching the polysilicon sacrificial layer to form a sacrificial emitter region above the selective ion implantation region;

[0011] S6, depositing a second silicon nitride layer to cover the sacrificial emitter region, photolithographically etching the second silicon nitride layer and the second silicon oxide layer to expose the SiGe surface in the outer region of the SiGe base region, and forming a P+ type doped external base region on the SiGe surface exposed in the SiGe base region by selective epitaxial SiGe;

[0012] S7, depositing a third silicon oxide layer on the silicon substrate, and performing chemical mechanical polishing on the third silicon oxide layer, using the second silicon nitride layer as a barrier layer;

[0013] S8, sequentially etching the second silicon nitride layer above the sacrificial emitter region, the sacrificial emitter region, and the second silicon oxide layer below the sacrificial emitter region to form an emitter region window, exposing the Si Ge surface of the SiGe base region below the emitter region window;

[0014] S9, forming an N+ type doped silicon emitter region in the emitter region window, and patterning the emitter region and the external base region by photolithography;

[0015] S10, completing the subsequent SiGe Bi CMOS process.

[0016] Furthermore, the width of the shallow trench is 0.2 μm to 1 μm, the depth of the shallow trench is 0.2 μm to 0.8 μm, the width of the collector active area is 0.2 μm to 2 μm, and the width of the collector contact area is 0.1 μm to 2 μm.

[0017] Furthermore, the implantation energy for forming the selective ion implantation region is 50KeV to 300KeV, and the implantation dose is 2e13cm -3 ~2e14cm -3 , the implanted impurities are arsenic or phosphorus.

[0018] Furthermore, the thickness of the epitaxial SiGe layer formed in a non-selective manner is 300A to 1000A, and the impurity in situ doped with boron forms a trapezoidal distribution with a peak concentration of 5e19cm -3 ~2e20cm -3 ;

[0019] Furthermore, the thickness of the second silicon oxide layer is 200A to 1000A, and the thickness of the polysilicon sacrificial layer is 2000A to 4000A.

[0020] Furthermore, the width of the sacrificial emitter region is 1 / 2 to 1 / 5 of the width of the collector active region.

[0021] Furthermore, the thickness of the second silicon nitride layer is 300A to 1500A; the in-situ impurity of the external base region is boron, and the doping concentration is 1e19cm -3 ~5e19cm -3 .

[0022] Furthermore, the thickness of the third silicon oxide layer is 1000A to 3000A; after chemical mechanical polishing, the residual thickness of the third silicon oxide layer in the CMOS region is 200A to 1500A.

[0023] Furthermore, the impurity of the silicon emitter region is phosphorus or arsenic, and the doping concentration is 5e19cm -3 ~1.5e20cm -3 .

[0024] The invention discloses a structure integrating CMOS and self-aligned silicon germanium HBT, which is manufactured by a method integrating CMOS and self-aligned silicon germanium HBT.

[0025] The present invention provides a self-aligned SiGe HBT structure and a manufacturing method thereof that are compatible with standard CMOS processes, which can be well compatible with existing process conditions and expand the overall adaptability and model library of the process. Compared with the self-aligned HBT process of other existing technical routes, the present invention first deposits a sacrificial emitter region, and then opens the emitter region window after the external base region is raised by epitaxy, which effectively reduces the process complexity and improves the robustness of the process. By adjusting the selective injection conditions, HBT devices with various breakdown voltages can also be manufactured. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0027] Figure 1 The flowchart is a method for integrating CMOS and self-aligned silicon germanium HBT according to an embodiment of the present invention. Figure 2 It is a schematic diagram of the structure after a shallow trench isolation region is formed on a silicon substrate.

[0028] Figure 3 It is a schematic diagram of the structure after forming polysilicon gate, gate silicon oxide and lightly doped region.

[0029] Figure 4 It is a schematic diagram of the structure after depositing the first silicon oxide layer and the first silicon nitride layer.

[0030] Figure 5 This is a schematic diagram of the structure after the base window is opened and implanted to form a selective ion implantation area.

[0031] Figure 6 Schematic diagram of the structure after forming the epitaxial Si Ge layer.

[0032] Figure 7 This is a schematic diagram of the structure after forming a second silicon oxide layer and a polysilicon sacrificial layer.

[0033] Figure 8 A schematic diagram of the structure after forming a sacrificial emitter region and depositing a second silicon nitride layer.

[0034] Fig. 9 This is a schematic diagram of the structure after the Si Ge surface in the outer area of ​​the Si Ge base region is exposed by photolithography.

[0035] Fig.10 A schematic diagram of the structure after forming an external base region, depositing a third silicon oxide layer and performing chemical mechanical polishing.

[0036] Fig.11 This is a schematic diagram of the structure after the emission area window is formed.

[0037] Fig.12 A schematic diagram of the structure after the silicon emitter region is formed by photolithography and patterning the emitter region and the external base region.

[0038] Fig.13 It is a schematic diagram of the structure after silicon nitride sidewalls and silicon oxide sidewalls are simultaneously formed in the CMOS area and the HBT area.

[0039] The accompanying drawings in the specification are as follows:

[0040] Silicon substrate-101; shallow trench isolation region-102; first silicon oxide layer-110; first silicon nitride layer-120; epitaxial Si Ge layer-130; second silicon oxide layer-140; polysilicon sacrificial layer-150; second silicon nitride layer-160; third silicon oxide layer-170;

[0041] Polysilicon gate-201; gate silicon oxide-202; lightly doped region-203; silicon nitride sidewalls-208, 308; silicon oxide sidewalls-209, 309; CMOS active region-210; substrate contact region-220;

[0042] Selective ion implantation region-301; base region window-302; Si Ge base region-303; sacrificial emitter region-304; external base region-305; emitter region window-306; silicon emitter region-307; emitter region single crystal silicon-3071; emitter region polycrystalline silicon-3072; collector region active region-310; collector region contact region-320. DETAILED DESCRIPTION

[0043] The following describes the implementation methods of the present invention through specific examples. The illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the present invention. The following embodiments and features in the embodiments may be combined with each other without conflict.

[0044] See also Figure 1 , Figure 1 This is a flow chart of an embodiment of a method for integrating CMOS and self-aligned silicon-germanium HBT according to the present invention. The method for integrating CMOS and self-aligned silicon-germanium HBT according to this embodiment comprises the following steps:

[0045] S1. Please refer to Figure 2 , multiple shallow trenches are etched on the silicon substrate 101 by photolithography, and oxide is filled in each shallow trench to form multiple shallow trench isolation regions 102. The width of the shallow trench is 0.2μm to 1μm, and the depth of the shallow trench is 0.2μm to 0.8μm. After the oxide is filled in each shallow trench, the oxide surface can be flattened by chemical mechanical polishing. Among the multiple shallow trench isolation regions 102, the middle shallow trench isolation region 102 separates the upper part of the silicon substrate 101 into a CMOS region on the right and an HBT region on the left. The two shallow trench isolation regions 102 on the right further separate the CMOS region into a CMOS active region 210 and a substrate contact region 220. The two shallow trench isolation regions 102 on the left further separate the HBT region into a collector active region 310 and a collector contact region 320. The width of the collector active region 310 is 0.2 μm to 2 μm, and the width of the collector contact region 320 is 0.1 μm to 2 μm.

[0046] S2. Please refer to Figure 3 First, a polysilicon gate 201 is formed above the CMOS active area 210. The polysilicon gate 201 can be obtained by depositing a polysilicon layer and then performing patterning etching. Then, a gate oxide silicon 202 is formed on the surface of the polysilicon gate 201 by rapid thermal oxidation; then, the CMOS active area 210 on both sides of the polysilicon gate 201 is implanted to form a lightly doped area 203, and the two lightly doped areas 203 serve as source / drain extension areas.

[0047] S3. Please refer to Figure 4 First, a first silicon oxide layer 110 and a first silicon nitride layer 120 are sequentially deposited on a silicon substrate 101 as protective layers. Figure 5 Then, the first silicon nitride layer 120 and the first silicon oxide layer 110 are etched by photolithography to open the base window 302 in the HBT region, and then the remaining first silicon nitride layer 120 is stripped off, and an N+ type selective ion implantation region 301 is implanted in the base window 302. The selective ion implantation region 301 is formed by medium energy and high dose N-type impurity implantation, the implantation energy is generally 50KeV to 300KeV, and the implantation dose is generally 2e13cm -3 ~2e14cm -3 , the implanted impurities can be arsenic or phosphorus.

[0048] S4. Please refer to Figure 6 , an epitaxial SiGe layer 130 is formed on the silicon substrate 101 in a non-selective manner. The epitaxial SiGe layer 130 formed on the surface of the single crystal silicon is a single crystal SiGe region, and the single crystal SiGe region forms a SiGe base region 303 (i.e., an intrinsic base region), and the epitaxial SiGe layer 130 formed on the surface of the first silicon oxide layer 110 is a polycrystalline SiGe region (the epitaxial SiGe layer 130 outside the SiGe base region 303 is the polycrystalline SiGe region). The thickness of the epitaxial SiGe layer 130 formed in a non-selective manner is 300A to 1000A, and the impurity in situ doped with the epitaxial SiGe layer 130 is boron, and forms a trapezoidal distribution with a peak concentration of 5e19cm -3 ~2e20cm -3 .

[0049] S5. Please refer to Figure 7 First, a high-quality oxide layer is deposited on the silicon substrate 101 as the second silicon oxide layer 140, and the thickness of the second silicon oxide layer 140 is 200A to 1000A. Then, a layer of polysilicon is deposited to form a polysilicon sacrificial layer 150, and the thickness of the polysilicon sacrificial layer 150 is 2000A to 4000A. Figure 8 After that, the polysilicon sacrificial layer 150 is etched and patterned, and the remaining polysilicon sacrificial layer 150 forms a sacrificial emitter region 304 above the selective ion implantation region 301 , and the width of the sacrificial emitter region 304 is 1 / 2 to 1 / 5 of the width of the collector active region 310 .

[0050] S6. Please continue reading Figure 8 First, a second silicon nitride layer 160 is deposited to cover the sacrificial emitter region 304. The thickness of the second silicon nitride layer 160 is 300A to 1500A. Fig. 9 Then, the second silicon nitride layer 160 and the second silicon oxide layer 140 are etched by photolithography to expose the Si Ge surface of the outer area of ​​the SiGe base region 303. Fig.10Then, a P+-type doped external base region 305 is formed on the SiGe surface exposed by the SiGe base region 303 by selective epitaxy. The in-situ impurity of the external base region 305 is boron with a doping concentration of 1e19 cm -3 ~5e19cm -3 By means of the above method, an elevated extrinsic base region 305 can be formed at the periphery of the intrinsic base region, so that the elevated extrinsic base region 305 is self-aligned with the emitter region.

[0051] S7. Please continue reading Fig.10 , depositing a third silicon oxide layer 170 on the silicon substrate 101, wherein the thickness of the third silicon oxide layer 170 is 1000A to 3000A. Chemical mechanical polishing is performed on the third silicon oxide layer 170, and the second silicon nitride layer 160 is used as a barrier layer for chemical mechanical polishing. After chemical mechanical polishing, the residual thickness of the third silicon oxide layer 170 in the CMOS region is 200A to 1500A.

[0052] S8, please refer to Fig.11 , the second silicon nitride layer 160 above the sacrificial emitter region 304 , the sacrificial emitter region 304 and the second silicon oxide layer 140 below the sacrificial emitter region 304 are etched in sequence to form an emitter region window 306 , exposing the SiGe surface of the SiGe base region 303 below the emitter region window 306 .

[0053] S9, please refer to Fig.12 , an N+-doped silicon emitter region 307 is formed in the emitter region window 306 by non-selective epitaxial silicon layer and patterned etching; the impurity of the silicon emitter region 307 is phosphorus or arsenic, and the doping concentration is 5e19cm -3 ~1.5e20cm -3 Since a non-selective growth method is adopted, when the epitaxial silicon layer is grown, single crystal silicon will be grown on the surface of the single crystal Si Ge, and polycrystalline silicon will be formed on the surface of the silicon nitride, that is, the silicon emitter region 307 includes the emitter region single crystal silicon 3071 and the emitter region polycrystalline silicon 3072. Afterwards, the emitter region and the external base region 305 are patterned by photolithography, and the third silicon oxide layer 170 outside the emitter region and the external base region 305 is firstly removed by photolithography, and then the second silicon nitride layer 160, the second silicon oxide layer 140 and the epitaxial Si Ge layer 130 not covering the third silicon oxide layer 170 are removed by etching.

[0054] S10, complete the subsequent Si Ge Bi CMOS process. Fig.13First, a gate spacer process is used to form silicon nitride sidewalls and silicon oxide sidewalls in the CMOS region and the HBT region simultaneously, wherein silicon nitride sidewalls 208 and silicon oxide sidewalls 209 are sequentially formed on the side of the gate silicon oxide 202 in the CMOS region, and silicon nitride sidewalls 308 and silicon oxide sidewalls 309 are sequentially formed on the side of the external base region 305 in the HBT region. Then, high doping implantation, rapid thermal annealing and metallization are performed in the source / drain contact region of the CMOS region until the entire Si Ge Bi CMOS process is completed; these processes are all existing technologies and will not be described in detail here.

[0055] The self-aligned Si Ge HBT manufacturing method of this embodiment is well compatible with the process conditions of the existing standard CMOS process, and expands the overall adaptability and model library of the process. Compared with the self-aligned HBT process of other existing technical routes, this embodiment first deposits the sacrificial emitter region 304, and then opens the emitter region window 306 after the external base region 305 is lifted by epitaxy, which effectively reduces the process complexity and improves the robustness of the process. The process of the embodiment is compatible with the original Bi CMOS process and is scalable. By adjusting the selective injection conditions, HBT devices with various breakdown voltages can also be manufactured.

[0056] The present invention also discloses a structure integrating CMOS and self-aligned silicon germanium HBT. The structure integrating CMOS and self-aligned silicon germanium HBT of the present invention can be manufactured by the method integrating CMOS and self-aligned silicon germanium HBT of any of the above embodiments.

[0057] The above embodiments only express the preferred implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for integrating CMOS and self-aligned silicon germanium HBT, characterized in that: The following steps are involved: S1. etching a plurality of shallow trenches on a silicon substrate by photolithography, and filling each shallow trench with oxide to form a plurality of shallow trench isolation regions, wherein the plurality of shallow trench isolation regions separate the upper portion of the silicon substrate into a CMOS region and an HBT region, and separate the CMOS region into a CMOS active region and a substrate contact region, and separate the HBT region into a collector active region and a collector contact region; S2, forming a polysilicon gate above the CMOS active area, and forming gate silicon oxide by oxidation on the surface of the polysilicon gate, and forming lightly doped areas by implantation in the CMOS active areas on both sides of the polysilicon gate; S3, sequentially depositing a first silicon oxide layer and a first silicon nitride layer on a silicon substrate, opening a base window in the HBT region by photolithography etching the first silicon nitride layer and the first silicon oxide layer, then stripping off the remaining first silicon nitride layer, and implanting an N+ type selective ion implantation region in the base window; S4, forming an epitaxial SiGe layer on the silicon substrate in a non-selective manner, wherein the epitaxial SiGe layer formed on the surface of the single crystal silicon is a single crystal SiGe region, the single crystal SiGe region forms a SiGe base region, and the epitaxial SiGe layer formed on the surface of the first silicon oxide layer is a polycrystalline SiGe region; S5, depositing a second silicon oxide layer and a polysilicon sacrificial layer on the silicon substrate in sequence, and etching the polysilicon sacrificial layer to form a sacrificial emitter region above the selective ion implantation region; S6, depositing a second silicon nitride layer to cover the sacrificial emitter region, photolithographically etching the second silicon nitride layer and the second silicon oxide layer to expose the SiGe surface in the outer region of the SiGe base region, and forming a P+ type doped external base region on the SiGe surface exposed in the SiGe base region by selective epitaxial SiGe; S7, depositing a third silicon oxide layer on the silicon substrate, and performing chemical mechanical polishing on the third silicon oxide layer, using the second silicon nitride layer as a barrier layer; S8, sequentially etching the second silicon nitride layer above the sacrificial emitter region, the sacrificial emitter region, and the second silicon oxide layer below the sacrificial emitter region to form an emitter region window, exposing the SiGe surface of the SiGe base region below the emitter region window; S9, forming an N+ type doped silicon emitter region in the emitter region window, and patterning the emitter region and the external base region by photolithography; S10, completing the subsequent SiGe BiCMOS process.

2. The method for integrating CMOS and self-aligned silicon germanium HBT according to claim 1, characterized in that: The width of the shallow trench is 0.2 μm to 1 μm, the depth of the shallow trench is 0.2 μm to 0.8 μm, the width of the collector active area is 0.2 μm to 2 μm, and the width of the collector contact area is 0.1 μm to 2 μm.

3. The method for integrating CMOS and self-aligned silicon germanium HBT according to claim 1, characterized in that: The injection energy for forming the selective ion injection area is 50KeV to 300KeV, and the injection dose is 2e13cm -3 ~2e14cm -3 , the implanted impurities are arsenic or phosphorus.

4. The method for integrating CMOS and self-aligned SiGe HBT according to claim 1, characterized in that: The thickness of the epitaxial SiGe layer formed in a non-selective manner is 300A to 1000A. The impurity doped in situ in the epitaxial SiGe layer is boron, and forms a trapezoidal distribution with a peak concentration of 5e19cm -3 ~2e20cm -3 .

5. The method for integrating CMOS and self-aligned SiGe HBT according to claim 1, characterized in that: The thickness of the second silicon oxide layer is 200A-1000A, and the thickness of the polysilicon sacrificial layer is 2000A-4000A.

6. The method for integrating CMOS and self-aligned silicon germanium HBT according to claim 1, characterized in that: The width of the sacrificial emitter region is 1 / 2 to 1 / 5 of the width of the collector active region.

7. The method for integrating CMOS and self-aligned silicon germanium HBT according to claim 1, characterized in that: The thickness of the second silicon nitride layer is 300A to 1500A; the in-situ impurity of the external base region is boron, and the doping concentration is 1e19cm -3 ~5e19cm -3 .

8. The method for integrating CMOS and self-aligned silicon germanium HBT according to claim 1, characterized in that: The thickness of the third silicon oxide layer is 1000A to 3000A; after chemical mechanical polishing, the residual thickness of the third silicon oxide layer in the CMOS region is 200A to 1500A.

9. The method for integrating CMOS and self-aligned silicon germanium HBT according to claim 1, characterized in that: The impurities in the silicon emitter region are phosphorus or arsenic, and the doping concentration is 5e19cm -3 ~1.5e20cm -3 .

10. A structure integrating CMOS and self-aligned silicon germanium HBT, characterized in that: The method for integrating CMOS and self-aligned silicon germanium HBT is used to manufacture the HBT.

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